A hybrid device driving circuit, control method and system

Abstract

The application belongs to the technical field of power electronics, and relates to a hybrid device driving circuit, a control method and a system. The driving circuit comprises an upper computer, an FPGA, a SiC MOSFET driving chip, a Si IGBT driving chip, a SiC MOSFET charging resistance adjusting module and a Si IGBT charging resistance adjusting module; the FPGA comprises a SiC conduction proportion adjusting module, a driving resistance control module and a delay module. The upper computer gives an instruction, the driving resistance switching signals PA and PB given by the FPGA are output to the charging resistance adjusting module, so that the states of eight driving resistance switching circuits of the SiC MOSFET and the Si IGBT are changed respectively. Meanwhile, the FPGA gives a conduction proportion adjusting signal, so that the conduction proportion of the SiC MOSFET is changed. The charging resistance multi-stage switching and the adjustable SiC conduction proportion can be realized by the method.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a hybrid device driving circuit, control method, and system. Background Technology

[0002] While Si devices are the mainstream power semiconductor devices, their material properties limit their ability to meet the demands of high-efficiency, high-density power electronic devices. Third-generation wide-bandgap semiconductor devices, such as SiC devices, possess high breakdown electric fields and high electron saturation velocities, making them suitable for high-frequency, high-voltage applications. However, their high cost and immature manufacturing processes restrict their widespread use in power electronic converters. Si / SiC hybrid devices combine the advantages of Si-based devices' high current stress with SiC-based devices' low switching losses, enabling them to meet the urgent needs of high-performance power electronic devices for high-frequency, high-reliability, high-current capacity, and low-cost high-voltage power electronic devices.

[0003] While Si / SiC hybrid devices theoretically offer significant combined advantages, they suffer from a prominent issue of uneven junction temperature distribution under real-world non-stationary operating conditions. Specifically, the heat concentration generated by SiC MOSFETs is much higher than that of the IGBTs primarily responsible for conduction, resulting in significantly larger junction temperature fluctuations in the MOSFETs compared to the IGBTs, which in turn leads to accelerated MOSFET aging. Simultaneously, Si / SiC hybrid devices contain two independent drive circuits. By rationally configuring and dynamically adjusting the drive resistors of these two circuits, the switching process of each device can be independently optimized. If flexible adjustment of the drive resistors can be achieved, a better balance can be struck between losses and current stress, thereby significantly improving the overall efficiency and operational reliability of the converter.

[0004] To address the aforementioned junction temperature imbalance issue, the junction temperature adjustment space of SiIGBTs can be fully utilized by adjusting the conduction ratio of SiC MOSFETs. However, systematic research on thermal management strategies for Si / SiC hybrid devices is still very limited. Regarding the issue of driving resistor adjustment for Si / SiC hybrid devices, existing driving circuit solutions for Si / SiC hybrid devices generally adopt a fixed resistor or simple step-by-step design approach, which cannot achieve real-time, multi-level adjustment of the driving resistor, and lacks a solution that can simultaneously achieve thermal balance control and electrical performance optimization. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes a hybrid device drive circuit with multi-level switching of charging resistors and adjustable SiC conduction ratio. This circuit possesses the following two core functions: 1) Online and multi-level adjustment of the charging resistor: Supports online adjustment of the charging resistor value in the drive circuit across multiple levels or continuously, thereby actively optimizing the switching trajectory and suppressing voltage and current overshoot; 2) Online and steplessly adjustable SiC conduction ratio: Enables flexible and continuous adjustment of the conduction time ratio of the SiC MOSFET within a switching cycle during device operation. This function allows for dynamic allocation of the current sharing ratio between the Si IGBT and SiC MOSFET, achieving active balanced control of the junction temperature distribution within the hybrid device.

[0006] The technical solution adopted by the present invention is as follows: Firstly, the present invention provides a hybrid device driving circuit, comprising: The host computer is connected to the input terminal of the FPGA and is used to transmit the original charging resistor and conduction ratio adjustment signals. The Field Programmable Gate Array (FPGA) has its input terminal connected to the output terminal of the host computer. It is used to receive and process the original signals from the host computer to generate a conduction ratio adjustment signal and a charging resistor adjustment signal. The SiC MOSFET driver chip has its input terminal connected to the first output terminal of the FPGA, and outputs a drive voltage to the SiC MOSFET charging resistor adjustment module. The Si IGBT driver chip has its input terminal connected to the second output terminal of the FPGA, and outputs a drive voltage to the Si IGBT charging resistor adjustment module. The SiC MOSFET charging resistance adjustment module has its input terminal connected to the output terminal of the SiC MOSFET driver chip and the third output terminal of the FPGA, and its output terminal connected to the gate of the SiC MOSFET, outputting a drive voltage to the SiC MOSFET to change the charging resistance of the SiC MOSFET. The Si IGBT charging resistance adjustment module has its input terminal connected to the output terminal of the Si IGBT driver chip and the fourth output terminal of the FPGA, and its output terminal connected to the gate of the Si IGBT to output a driving voltage to the Si IGBT, thereby changing the charging resistance of the Si IGBT.

[0007] Furthermore, the FPGA includes a SiC conduction ratio adjustment module, a drive resistor control module, and a delay module; The SiC conduction ratio adjustment module receives the output of the delay module and the original conduction ratio adjustment signal from the host computer, and outputs the DRV1 signal to the SiC MOSFET driver chip; The drive resistor control module receives the charging resistor adjustment signal from the host computer, outputs a PA signal to the SiC MOSFET charging resistor adjustment module, and outputs a PB signal to the Si IGBT charging resistor adjustment module. The delay module receives the original on-state ratio adjustment signal from the host computer, outputs the DRV2 signal to the Si IGBT driver chip, outputs a PWM wave to the SiC on-state ratio adjustment module, or outputs the DRV1 signal to the SiC MOSFET driver chip.

[0008] Furthermore, the SiC conduction ratio adjustment module has a built-in counter. When the rising edge of the PWM pulse signal of the next IGBT switching cycle arrives, the counter starts counting to t1, and the drive signal of the SiC MOSFET flips from high level to low level. At this time, the SiC MOSFET begins to enter the interrupt conduction stage. When the count reaches t2, the drive signal of the SiC MOSFET flips from low level to high level, and the interrupt conduction stage ends. The SiC MOSFET resumes to participate in conduction and current sharing, thereby generating PWM3 suitable for the SiC MOSFET. This PWM3 is then combined with the PWM2 corresponding to the IGBT to form a switching timing, realizing the dynamic adjustment of the SiC conduction ratio.

[0009] Furthermore, the calculation methods for t1 and t2 are as follows: The PWM pulse signal of the Si IGBT in one switching cycle is acquired, and the PWM pulse width T is calculated. cond Then calculate the interrupt conduction time ΔT. SiC : ; ; ; Where, r SiC This represents the SiC conduction ratio.

[0010] Furthermore, the drive resistor control module adopts an I / O expander, receives instructions from the host computer via the SPI bus, and outputs multiple parallel digital level signals, which serve as switching signals for the SiC MOSFET charging resistor adjustment module and the Si IGBT charging resistor adjustment module, respectively. The instructions transmitted by the host computer include the contents of 16 output pins. The instructions are input from pins 11-13, which specify output pins 1-8 and 21-28 as high or low level.

[0011] Furthermore, the SiC MOSFET charging resistor adjustment module and the Si IGBT charging resistor adjustment module each include at least two parallel drive resistor switching circuits; each drive resistor switching circuit includes: an optocoupler, a power relay, and a charging resistor; The input terminal of the optocoupler receives the switching signal output by the drive resistor control module, and its output terminal drives the coil of the power relay. The contact switch of the power relay is connected in series with the charging resistor to control whether the charging resistor is connected to the drive circuit.

[0012] Furthermore, the SiC MOSFET charging resistor is adjustable in a range of 10-80Ω with a step of 10Ω; the SiIGBT charging resistor is adjustable in a range of 5-40Ω with a step of 5Ω.

[0013] Furthermore, the delay module generates PWM1 and PWM2 respectively for MOSFET and IGBT. PWM1 is not delayed, while the delay module delays the rising edge of the PWM signal by T. on_d And the falling edge is T ahead of time off_d produce.

[0014] A second aspect of the present invention provides a control method for a hybrid device driving circuit, based on the hybrid device driving circuit described above, comprising: The host computer sends charging resistor adjustment signals and conduction ratio adjustment signals to the FPGA; The drive resistor control module generates a charging resistor switching signal based on the charging resistor adjustment signal, and controls the SiC MOSFET charging resistor adjustment module and the Si IGBT charging resistor adjustment module respectively to adjust the charging resistor value connected to the drive circuit. The delay module and the SiC turn-on ratio adjustment module generate the driving timing of the SiC MOSFET according to the turn-on ratio adjustment signal, wherein the proportion of the SiC MOSFET's on-time in one switching cycle is determined according to the turn-on ratio adjustment signal; The SiC MOSFET driver chip and the Si IGBT driver chip drive the corresponding SiC MOSFET and Si IGBT respectively by adjusting the charging resistor according to the generated driving timing sequence.

[0015] A third aspect of the present invention provides a hybrid device driving circuit system, based on the hybrid device driving circuit described above, comprising: The gate of the SiC MOSFET is connected to the output terminal of the SiC MOSFET charging resistor adjustment module. The gate of the Si IGBT is connected to the output terminal of the Si IGBT charging resistor adjustment module; The SiC MOSFET and the Si IGBT are connected in parallel to form a hybrid switch in a drain-collector and source-emitter configuration.

[0016] The beneficial effects of this invention are: (1) This invention proposes a novel Si / SiC hybrid device driving circuit, which has the functions of switching multiple charging resistors and varying SiC conduction ratio, and can selectively meet the needs of different scenarios such as thermal balance, low switching electrical stress, and low EMI.

[0017] (2) At the hardware level of the driving circuit proposed in this invention, multi-level and online adjustment of the charging resistors of SiC MOSFETs and Si IGBTs can be realized, and the resistance value can be adjusted by sending corresponding SPI commands to the host computer. This function can achieve a clear distinction in switching speed, thereby balancing different performance indicators such as switching losses, EMI, and electrical stress.

[0018] (3) At the software level of the driving circuit proposed in this invention, the on-state ratio of the SiC MOSFET can be adjusted online and steplessly, and its on-time can be changed by sending corresponding instructions from the host computer. This function can adapt to different optimization goals such as light load efficiency and thermal balance. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 The basic structure of the driving circuit of this invention; Figure 2 This is the operating logic of the switch timing generation module; Figure 3 These are two switching modes that the driving circuit of this invention can implement, wherein (a) is switching mode I and (b) is switching mode II; Figure 4 This is the operating logic of the SiC conduction ratio adjustment module and the delay module; Figure 5 It is a drive resistor control module; Figure 6These are the drive resistor switching circuits corresponding to the SiC MOSFET charging resistor adjustment module, where (a) is the drive resistor switching circuit numbered 1-4, and (b) is the drive resistor switching circuit numbered 5-8. Figure 7 It is a drive resistor switching circuit for SiC MOSFETs; Figure 8 It is the principle of driving signal generation. Detailed Implementation

[0021] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to embodiments and accompanying drawings. The content mentioned in the embodiments is not intended to limit the present invention.

[0022] like Figure 1 As shown, in order to achieve the functions of multi-level adjustable charging resistance and variable SiC conduction ratio, the present invention provides a hybrid device driving circuit, which mainly includes a host computer, a field-programmable gate array (FPGA), a SiC MOSFET driving chip, a Si IGBT driving chip, a SiC MOSFET charging resistance adjustment module, and a Si IGBT charging resistance adjustment module. The host computer is connected to the input terminal of the FPGA, transmitting the original charging resistance and conduction ratio adjustment signals. The FPGA is connected to the output terminal of the host computer, receiving and processing the original signals to generate the conduction ratio adjustment signal and the charging resistance adjustment signal. The SiC MOSFET driver chip is connected to the DRV1 output of the FPGA, outputting a drive voltage to the SiC MOSFET charging resistance adjustment module, providing a suitable drive voltage for the MOSFET. The Si IGBT driver chip is connected to the DRV2 output of the FPGA, outputting a drive voltage to the Si IGBT charging resistance adjustment module, providing a suitable drive voltage for the IGBT. The SiC MOSFET charging resistance adjustment module is connected to the output of the SiC MOSFET driver chip and the PA output of the FPGA, outputting a drive voltage to the MOSFET and changing the MOSFET's charging resistance according to PA. The Si IGBT charging resistance adjustment module is connected to the output of the Si IGBT driver chip and the PB output of the FPGA, outputting a drive voltage to the IGBT and changing the IGBT's charging resistance according to PB.

[0023] It should be further explained that the FPGA includes a SiC conduction ratio adjustment module, a drive resistor control module, and a delay module. The delay module receives the original conduction ratio adjustment signal from the host computer, outputs a DRV2 signal to the Si IGBT driver chip, and outputs a PWM wave to the SiC conduction ratio adjustment module or a DRV1 signal to the SiC MOSFET driver chip. Its function is to generate a basic PWM wave and a delayed PWM wave, and select the output based on the original signal. The SiC conduction ratio adjustment module receives the output from the delay module and the original conduction ratio adjustment signal from the host computer, and outputs a DRV1 signal to the SiC MOSFET driver chip. Its function is to generate and provide a variable conduction ratio signal DRV1 based on the original signal. The drive resistor control module receives the charging resistor adjustment signal from the host computer, outputs a PA signal to the SiC MOSFET charging resistor adjustment module, and outputs a PB signal to the Si IGBT charging resistor adjustment module. Its function is to generate and output charging resistor adjustment signals PA and PB based on the original signal.

[0024] The variable SiC turn-on ratio can adjust the junction temperature swing difference between SiC MOSFETs and Si IGBTs, thereby redistributing conduction losses and achieving junction temperature equalization. The designed drive circuit uses a SiC turn-on ratio adjustment module to regulate the turn-on ratio of the SiC MOSFET.

[0025] The switching timing of Si / SiC hybrid devices is jointly generated by the FPGA's delay module and the SiC turn-on ratio adjustment module. When using classic switching timing, it is generated by the delay module; when using switching timing with variable SiC turn-on ratio, the basic timing is generated by the delay module, then input to the SiC turn-on ratio adjustment module, which outputs the switching timing with variable SiC turn-on ratio.

[0026] like Figure 2 As shown, the FPGA's delay module generates PWM1 and PWM2, respectively, applicable to MOSFETs and IGBTs. PWM1 is not delayed, while the PWM2 signal is delayed by T from the rising edge of the PWM signal by the delay module. on_d And the falling edge is T ahead of time off_d produce.

[0027] like Figure 3 As shown, a SiC conduction ratio adjustment module is designed based on two commonly used switching modes. By combining PWM1 corresponding to the MOSFET and PWM2 corresponding to the IGBT, a hybrid device switching mode I is generated.

[0028] It should be further explained that the working principle of the SiC conduction ratio adjustment module is as follows: The PWM pulse signal of one switching cycle of the Si IGBT is acquired, and the PWM pulse width T is calculated. cond Then, calculate the interruption conduction time ΔT according to the following formula. SiC : (1) Where, r SiC This represents the SiC conduction ratio.

[0029] Therefore, we obtain ΔT SiC : (2) observe Figure 3 It can be observed that: (3) Where T1 is the on-time of the SiC MOSFET when the first segment of PWM is high, and T2 is the on-time of the SiC MOSFET when the second segment of PWM is high. Combining equations (2) and (3), we can obtain: (4) Right now: (5) Where t1 is the time from the rising edge of the IGBT's PWM pulse signal to the falling edge of the first stage of MOSFET conduction. t2 is the time from the rising edge of the second stage of MOSFET conduction to the falling edge of the IGBT's PWM pulse signal.

[0030] The SiC turn-on ratio adjustment module has a built-in counter. Therefore, when the rising edge of the PWM pulse signal of the next IGBT switching cycle arrives, the counter starts counting to t1, and the SiC MOSFET drive signal flips from high to low, at which point the SiC MOSFET enters the interrupt conduction phase. When the count reaches t2, the SiC MOSFET drive signal flips from low to high, the interrupt conduction phase ends, and the SiC MOSFET resumes its conduction and current sharing. This generates PWM3 suitable for the SiC MOSFET, which, combined with the PWM2 corresponding to the IGBT, forms a switching timing sequence, constituting switching mode II under different SiC turn-on ratios, thus realizing the dynamic adjustment of the SiC turn-on ratio.

[0031] The overall operating logic of the SiC on-state ratio adjustment module and the delay module is shown in Figure 4. The host computer specifies the switching mode. If switch mode I is selected, the delay module delays the PWM wave, generating PWM1 and PWM2 for the corresponding MOSFET and IGBT respectively. The two PWM waves constitute the switching timing sequence and are input to the driver chip. If switch mode II is selected, the delay module generates PWM2 for the corresponding IGBT, and the SiC on-state ratio adjustment module generates PWM3 for the corresponding MOSFET. Together, they constitute the switching timing sequence and are input to the driver chip.

[0032] The drive resistor has a significant impact on the dynamic characteristics of MOSFETs and IGBTs. Recommended values ​​for the drive resistor vary between different device models, and in practical applications, it often needs to be adjusted to meet diverse requirements. Therefore, the designed Si / SiC hybrid device drive circuit should have an adjustable charging resistor.

[0033] The driving resistor module designed in this invention is as follows: Figure 5 As shown, the host computer transmits SPI commands to the FPGA, which are processed by an isolator and then enter the drive resistor control module. This module then outputs variable resistor switching signals PA and PB. In one embodiment of this invention, the drive resistor control module uses an I / O expander MCP23S17.

[0034] To further clarify, the SPI commands transmitted by the host computer include the contents of 16 output pins. The commands are input from pins 11-13, specifying output pins 1-8 and 21-28 as high or low levels. Therefore, this module can control the pin output levels to control the closing of the relay in the drive resistor switching circuit, thus achieving the effect of connecting the resistor to the on-circuit and changing the charging resistance.

[0035] It should be further noted that the SiC MOSFET charging resistor adjustment module and the Si IGBT charging resistor adjustment module each contain 8 drive resistor switching circuits, as shown in Figure 6.

[0036] In one embodiment of the present invention, the SiC MOSFET charging resistor adjustment module and the Si IGBT charging resistor adjustment module are each composed of eight drive resistor switching circuits. Each circuit mainly includes I / O expanders, optocouplers, power relays, charging resistors, and other devices. The SiC MOSFET charging resistor adjustment module receives the signal PA output from the drive resistor control module in the FPGA from the left DR-OP, receives the drive voltage output from the SiC MOSFET driver chip from DRVP1, and outputs the drive voltage to the MOSFET through the output terminal G2. Its function is to change the state of the power relay inside each drive resistor switching circuit according to the level of signal PA, thereby determining whether different charging resistors are connected, and thus changing the charging resistance of the MOSFET. The Si IGBT charging resistor adjustment module receives the signal PB output from the drive resistor control module in the FPGA from the left DR-OP, receives the drive voltage output from the SiIGBT driver chip from DRVP2, and outputs the drive voltage to the IGBT through the output terminal. Its function is to change the state of the power relay inside each drive resistor switching circuit according to the level of signal PB, thereby determining whether different charging resistors are connected, and thus changing the charging resistance of the IGBT.

[0037] Figure 7 shows a drive resistor switching circuit for a SiC MOSFET. When the input signal DR-OP1 is high, a weak current is input to the left side, amplified by the optocoupler TLP187, causing a current from 4 to 3 to be generated on the right side. This drives the power relay APAN3124 to close, connecting DRVP1 to the charging resistor R6F1. When the input signal DR-OP1 is low, there is no current on the left side, and the power relay APAN3124 on the right side opens.

[0038] The resistance values ​​of the 16 charging resistor switching circuits in the SiC MOSFET charging resistor adjustment module and the Si IGBT charging resistor adjustment module are shown in Table 1.

[0039] Table 1: Charging resistor values ​​corresponding to the 16 drive resistor switching circuits ; The charging resistor adjustment module can change the charging resistance of the MOSFET and IGBT separately. For the MOSFET, the charging resistance adjustment range is 10-80 Ω in 10-degree increments. For the IGBT, the charging resistance adjustment range is 5-40 Ω in 5-degree increments. The discharge resistance of the MOSFET and IGBT cannot be adjusted by the proposed drive circuit and a fixed resistance value is used.

[0040] The present invention also provides a control method for a hybrid device driving circuit, comprising: The host computer sends charging resistor adjustment signals and conduction ratio adjustment signals to the FPGA; The drive resistor control module generates a charging resistor switching signal based on the charging resistor adjustment signal, and controls the SiC MOSFET charging resistor adjustment module and the Si IGBT charging resistor adjustment module respectively to adjust the charging resistor value connected to the drive circuit. The delay module and the SiC turn-on ratio adjustment module generate the driving timing of the SiC MOSFET according to the turn-on ratio adjustment signal, wherein the proportion of the SiC MOSFET's on-time in one switching cycle is determined according to the turn-on ratio adjustment signal; The SiC MOSFET driver chip and the Si IGBT driver chip drive the corresponding SiC MOSFET and Si IGBT respectively by adjusting the charging resistor according to the generated driving timing.

[0041] It should be further explained that the operator can transmit instructions to the FPGA via the host computer. The FPGA then outputs the corresponding variable resistor switching signal PA to the SiC MOSFET charging resistor adjustment module and the variable resistor switching signal PB to the Si IGBT charging resistor adjustment module, thereby changing the state of the eight drive resistor switching circuits of the SiC MOSFET and Si IGBT respectively. At the same time, the FPGA gives the conduction ratio adjustment signal to the SiC conduction ratio adjustment module, thereby changing the conduction ratio of the SiC MOSFET.

[0042] The charging resistor adjustment module provides a multi-level switchable drive resistor. Finally, the drive chip, combined with the switching timing of the MOSFET and IGBT, outputs a drive voltage through the charging resistor to drive the hybrid device. The drive signal generation principle is as follows: Figure 7 As shown.

[0043] In one embodiment of the present invention, taking a MOSFET as an example, when switching mode I is used, the generation circuit structure of the drive signal G2 of the gate driver chip 1EDI20N12AF is shown in Figure 8. When the device is turned on, the delay module outputs the MOSFET's switching timing DRV1 into the driver chip. When switching mode II is used, when the device is turned on, the SiC conduction ratio adjustment module outputs the MOSFET's switching timing DRV1 into the driver chip.

[0044] The driver chip generates a positive drive voltage at OUTP in conjunction with the PWM wave input from DRV1, and this positive voltage enters the SiC MOSFET charging resistor adjustment module from DRV1. This module is then equivalent to a resistor; the positive drive voltage charges G2 (the MOSFET gate) through the charging resistor. When the device is turned off, the driver chip generates a negative drive voltage at OUTN in conjunction with the PWM wave input from DRV1, and G2 discharges to OUTN through a fixed discharge resistor.

[0045] The principle of IGBT drive signal generation is basically the same as that of MOSFET. The difference is that, whether in switch mode I or switch mode II, the IGBT driver chip receives the PWM wave output by the delay module from DRV2.

[0046] The present invention also provides a hybrid device driving circuit system, based on the hybrid device driving circuit described in the above embodiments, comprising: The gate of the SiC MOSFET is connected to the output terminal of the SiC MOSFET charging resistor adjustment module. The gate of the Si IGBT is connected to the output terminal of the Si IGBT charging resistor adjustment module; The SiC MOSFET and the Si IGBT are connected in parallel to form a hybrid switch in a drain-collector and source-emitter configuration.

[0047] In summary, by adopting the technical solution of the present invention, multi-level switching of charging resistors and adjustable SiC conduction ratio can be achieved.

[0048] The above embodiments are preferred implementations of the present invention. In addition, the present invention can be implemented in other ways. Any obvious substitutions without departing from the concept of the present technical solution are within the protection scope of the present invention.

[0049] To facilitate understanding by those skilled in the art of the improvements of this invention over the prior art, some of the accompanying drawings and descriptions have been simplified, and for clarity, some other elements have been omitted from this application. Those skilled in the art should realize that these omitted elements may also constitute the content of this invention.

Claims

1. A hybrid device driving circuit, characterized in that, include: The host computer is connected to the input terminal of the FPGA and is used to transmit the original charging resistor and conduction ratio adjustment signals. The Field Programmable Gate Array (FPGA) has its input terminal connected to the output terminal of the host computer. It is used to receive and process the original signals from the host computer to generate a conduction ratio adjustment signal and a charging resistor adjustment signal. The SiC MOSFET driver chip has its input terminal connected to the first output terminal of the FPGA, and outputs a drive voltage to the SiC MOSFET charging resistor adjustment module. The Si IGBT driver chip has its input terminal connected to the second output terminal of the FPGA, and outputs a drive voltage to the Si IGBT charging resistor adjustment module. The SiC MOSFET charging resistance adjustment module has its input terminal connected to the output terminal of the SiC MOSFET driver chip and the third output terminal of the FPGA, and its output terminal connected to the gate of the SiC MOSFET, outputting a drive voltage to the SiC MOSFET to change the charging resistance of the SiC MOSFET. The Si IGBT charging resistance adjustment module has its input terminal connected to the output terminal of the Si IGBT driver chip and the fourth output terminal of the FPGA, and its output terminal connected to the gate of the Si IGBT to output a driving voltage to the Si IGBT, thereby changing the charging resistance of the Si IGBT.

2. The hybrid device driving circuit as described in claim 1, characterized in that, The FPGA includes a SiC conduction ratio adjustment module, a drive resistor control module, and a delay module; The SiC conduction ratio adjustment module receives the output of the delay module and the original conduction ratio adjustment signal from the host computer, and outputs the DRV1 signal to the SiC MOSFET driver chip; The drive resistor control module receives the charging resistor adjustment signal from the host computer, outputs a PA signal to the SiC MOSFET charging resistor adjustment module, and outputs a PB signal to the Si IGBT charging resistor adjustment module. The delay module receives the original on-state ratio adjustment signal from the host computer, outputs the DRV2 signal to the Si IGBT driver chip, outputs a PWM wave to the SiC on-state ratio adjustment module, or outputs the DRV1 signal to the SiC MOSFET driver chip.

3. The hybrid device driving circuit as described in claim 2, characterized in that, The SiC conduction ratio adjustment module has a built-in counter. When the rising edge of the PWM pulse signal of the next IGBT switching cycle arrives, the counter starts counting to t1. The drive signal of the SiC MOSFET flips from high level to low level, and the SiC MOSFET begins to enter the interrupt conduction stage. When the count reaches t2, the drive signal of the SiC MOSFET flips from low level to high level, the interrupt conduction stage ends, and the SiC MOSFET resumes to participate in conduction and current sharing. This generates PWM3 suitable for the SiC MOSFET, which is combined with the PWM2 corresponding to the IGBT to form a switching timing, realizing the dynamic adjustment of the SiC conduction ratio.

4. The hybrid device driving circuit as described in claim 3, characterized in that, The calculation methods for t1 and t2 are as follows: The PWM pulse signal of one switching cycle of the Si IGBT is acquired, and the PWM pulse width T is calculated. cond Then calculate the interrupt conduction time ΔT. SiC : ； ； ； Where, r SiC This represents the SiC conduction ratio.

5. A hybrid device driving circuit as described in claim 2, characterized in that, The drive resistor control module uses an I / O expander to receive instructions from the host computer via the SPI bus and outputs multiple parallel digital level signals, which serve as switching signals for the SiC MOSFET charging resistor adjustment module and the Si IGBT charging resistor adjustment module, respectively. The instructions transmitted by the host computer include the contents of 16 output pins. The instructions are input from pins 11-13, which specify output pins 1-8 and 21-28 as high or low level.

6. The hybrid device driving circuit as described in claim 5, characterized in that, The SiC MOSFET charging resistor adjustment module and the Si IGBT charging resistor adjustment module each include at least two parallel drive resistor switching circuits. Each drive resistor switching circuit includes: an optocoupler, a power relay, and a charging resistor; The input terminal of the optocoupler receives the switching signal output by the drive resistor control module, and its output terminal drives the coil of the power relay. The contact switch of the power relay is connected in series with the charging resistor to control whether the charging resistor is connected to the drive circuit.

7. A hybrid device driving circuit as described in claim 6, characterized in that, The SiC MOSFET charging resistor is adjustable from 10 to 80 Ω in 10 Ω increments; the Si IGBT charging resistor is adjustable from 5 to 40 Ω in 5 Ω increments.

8. A hybrid device driving circuit as described in claim 2, characterized in that, The delay module generates PWM1 and PWM2, respectively, applicable to MOSFET and IGBT. PWM1 is not delayed, while the PWM2 signal is delayed by the delay module by T on the rising edge of the PWM signal. on_d And the falling edge is T ahead of time off_d produce.

9. A control method for a hybrid device driving circuit, based on the hybrid device driving circuit as described in any one of claims 2 or 8, characterized in that, include: The host computer sends charging resistor adjustment signals and conduction ratio adjustment signals to the FPGA; The drive resistor control module generates a charging resistor switching signal based on the charging resistor adjustment signal, and controls the SiC MOSFET charging resistor adjustment module and the Si IGBT charging resistor adjustment module respectively to adjust the charging resistor value connected to the drive circuit. The delay module and the SiC turn-on ratio adjustment module generate the driving timing of the SiC MOSFET according to the turn-on ratio adjustment signal, wherein the proportion of the SiC MOSFET's on-time in one switching cycle is determined according to the turn-on ratio adjustment signal; The SiC MOSFET driver chip and the Si IGBT driver chip drive the corresponding SiC MOSFET and Si IGBT respectively by adjusting the charging resistor according to the generated driving timing sequence.

10. A hybrid device driving circuit system, based on the hybrid device driving circuit as described in any one of claims 1-8, characterized in that, include: The gate of the SiC MOSFET is connected to the output terminal of the SiC MOSFET charging resistor adjustment module. The gate of the Si IGBT is connected to the output terminal of the Si IGBT charging resistor adjustment module; The SiC MOSFET and the Si IGBT are connected in parallel to form a hybrid switch in a drain-collector and source-emitter configuration.

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