High-swing high-speed level-shifting circuit and shifter

Abstract

The application discloses a high-swing high-speed level shift circuit and a shifter, and the circuit comprises: a control circuit connected with a first power supply and the shifter circuit, an output stage circuit connected with a second power supply and the shifter circuit, and an overvoltage protection circuit connected with a third power supply and the shifter circuit; the control circuit is used for conducting the connection between the first power supply and the shifter circuit when the first power supply is powered on; the shifter circuit is used for sending a bit shift signal to the output stage circuit when the connection between the first power supply and the shifter circuit is conducted; the output stage circuit is used for outputting a voltage signal according to the bit shift signal; and the overvoltage protection circuit continuously conducts the connection between the third power supply and the shifter circuit, so that the control end of the shifter circuit is stabilized at the third power supply voltage, thereby solving the requirement of power supply of the overvoltage protection circuit on the power-on sequence in a multi-voltage domain, and the control circuit is disconnected when the first power supply is not powered on, thereby solving the clamping effect of a diode in the power-on process.

Description

Technical Field

[0001] This invention relates to the field of level conversion circuit technology, and in particular to a high-swing, high-speed level shifting circuit and shifter. Background Technology

[0002] Existing technology addresses the issue of high impedance at the control terminal of the output stage circuit when the high-swing, high-speed level shift circuit is disabled by adding a low-voltage power supply. However, the use of multiple power supplies introduces the problem of power-on sequence. The low-voltage power supply, acting as a protection power supply, is prioritized for power-on. However, the first power supply of the level shift circuit and the second power supply of the output stage circuit have a sequential power-on issue. When the second power supply powers on first, the low-voltage power supply's power-on logic stabilizes the voltage at the control terminal of the output stage circuit at a fixed value when the first power supply is on. When the second power supply powers on first, the low-voltage power supply cannot stabilize the voltage at the control terminal, resulting in high impedance at the output stage circuit. Furthermore, when the first power supply is not on, even if the low-voltage power supply is on, it cannot clamp the voltage at the control terminal to the low-voltage power supply voltage because the body diode of the high-swing, high-speed level shift circuit is forward-biased, clamping the voltage at the control terminal to the forward voltage drop of the diode. This can lead to overvoltage at the control terminal. Adding a diode to solve this problem introduces a forward voltage drop, which is unacceptable for high-swing applications. Summary of the Invention

[0003] The main objective of this invention is to propose a high-swing, high-speed level shifting circuit and shifter, which aims to address the requirements of power-on sequence for overvoltage protection circuits in multi-voltage domains and the clamping effect of the body diode.

[0004] To achieve the above objectives, the high-swing, high-speed level shifting circuit proposed in this invention includes: an overvoltage protection circuit, a shifting circuit, an output stage circuit, and a control circuit; The control circuit is connected to the first power supply and the shift circuit, the output stage circuit is connected to the second power supply and the shift circuit, and the overvoltage protection circuit is connected to the third power supply and the shift circuit. The control circuit is used to connect the first power supply and the shift circuit when the first power supply is powered on. The shift circuit is used to send a displacement signal to the output stage circuit when the first power supply and the shift circuit are connected. The output stage circuit is used to output a voltage signal according to the displacement signal; The overvoltage protection circuit is used to connect the third power supply and the shift circuit, so that the voltage at the control terminal of the shift circuit is the third power supply voltage.

[0005] In one embodiment, the overvoltage protection circuit includes: a voltage regulator circuit and an enable circuit; The voltage regulator circuit is connected to the third power supply, the shift circuit, and the enable circuit, and the enable circuit is connected to the first power supply or the second power supply. The enabling circuit is used to generate and send a conduction signal to the voltage regulator circuit when there is no output from the first power supply and / or the second power supply. The voltage regulator circuit is used to connect the third power supply and the level shifting circuit when the conduction signal is received, so that the voltage at the control terminal of the shifting circuit is the voltage of the third power supply.

[0006] In one embodiment, the control circuit includes: an on / off circuit and a drive circuit; The switching circuit is connected to the first power supply, the shifting circuit and the driving circuit, and the driving circuit is also connected to the third power supply and the first power supply; The driving circuit is used to generate and send a cutoff signal to the on / off circuit when the first power supply has no output. The on / off circuit is used to disconnect the connection between the second power supply and the shift circuit when the cutoff signal is received, so as to prevent the shift circuit from being unable to stabilize at the third power supply voltage.

[0007] In one embodiment, the voltage regulator circuit includes: a first PMOS transistor and a second PMOS transistor; The drain of the first PMOS transistor is connected to the third power supply, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and the enable circuit, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the drain of the second PMOS transistor is connected to the shift circuit.

[0008] In one embodiment, the enabling circuit includes: a first resistor, a first capacitor, and a first inverter; One end of the first resistor is connected to one end of the first capacitor, the gate of the second PMOS transistor, the gate of the third PMOS transistor, and the output terminal of the first inverter. The other end of the first resistor and the other end of the first capacitor are grounded. The input terminal of the inverter is connected to the second power supply.

[0009] In one embodiment, the switching circuit includes: a third PMOS transistor; The drain of the third PMOS transistor is connected to the first power supply, the gate of the third PMOS transistor is connected to the driving circuit, and the source of the third PMOS transistor is connected to the shift circuit.

[0010] In one embodiment, the driving circuit includes: a second resistor, a second capacitor, a fourth NMOS transistor, a second inverter, and a third inverter; One end of the second resistor is connected to the third power supply, and the other end of the second resistor is connected to the gate of the third PMOS transistor, one end of the second capacitor, and the drain of the fourth NMOS transistor. The other end of the second capacitor and the source of the fourth NMOS transistor are grounded. The gate of the fourth NMOS transistor is connected to the output of the second inverter. The input of the second inverter is connected to the output of the third inverter. The input of the third inverter is connected to the first power supply.

[0011] In one embodiment, the shift circuit includes: a first current source, a second current source, a fifth PMOS transistor, a sixth PMOS transistor, a third resistor, and a third capacitor; The source of the fifth PMOS transistor is connected to the source of the third PMOS transistor and the source of the sixth PMOS transistor. The gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor and the gate of the sixth PMOS transistor. The drain of the fifth PMOS transistor is connected to the first terminal of the first current source. The drain of the sixth PMOS transistor is connected to one end of the third resistor, one end of the third capacitor, and the output stage circuit. The other end of the third resistor is connected to the other end of the third capacitor, the first terminal of the second current source, and the drain of the second PMOS transistor. The second terminal of the first current source is grounded. The second terminal of the second current source is grounded.

[0012] In one embodiment, the output stage circuit includes: a seventh NMOS transistor and a third current source; The gate of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor, one end of the third resistor, and one end of the third capacitor. The drain of the seventh NMOS transistor is connected to the second power supply, and the source of the seventh NMOS transistor is connected to the first end of the third current source. The second end of the third current source is grounded.

[0013] The present invention also discloses a high-swing high-speed level shifter, which includes the high-swing high-speed level shifting circuit described above.

[0014] This invention discloses a high-swing, high-speed level shifting circuit and a high-swing, high-speed level shifter. The high-swing, high-speed level shifting circuit includes: an overvoltage protection circuit, a shifting circuit, an output stage circuit, and a control circuit. The control circuit is connected to a first power supply and the shifting circuit; the output stage circuit is connected to a second power supply and the shifting circuit; and the overvoltage protection circuit is connected to a third power supply and the shifting circuit. The control circuit is used to connect the first power supply and the shifting circuit when the first power supply is powered on. The shifting circuit is used to send a displacement signal to the output stage circuit when the first power supply and the shifting circuit are connected. The output stage circuit is used to output a voltage signal based on the displacement signal. The overvoltage protection circuit connects the third power supply and the shifting circuit, making the voltage at the control terminal of the shifting circuit the voltage of the third power supply. This solves the problem of power supply sequence requirements and potential leakage issues in the overvoltage protection circuit across multiple voltage domains. The control circuit is disconnected when the first power supply is not powered on, thus solving the clamping effect of the PMOS body diode during power-on. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is a circuit diagram of a first embodiment of the high-swing, high-speed level shifting circuit provided by the present invention; Figure 2 Another circuit diagram of the first embodiment of the high swing high speed level shifting circuit provided by the present invention; Figure 3 This is a schematic diagram of the structure of the first embodiment of the high swing high speed level shifting circuit provided by the present invention; Figure 4 This is a circuit diagram of a second embodiment of the high-swing, high-speed level shifting circuit provided by the present invention.

[0017] Explanation of icon numbers:

[0018] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0021] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0022] High swing high speed level shifting circuits such as Figure 1 As shown, in high-speed applications, in order to meet the requirements of high input bandwidth, it is necessary to minimize the parasitics of the signal channel nodes. Therefore, the seventh NMOS transistor Q7 in the output stage needs to use a high-speed low-voltage transistor. At the same time, in order to meet the requirements of high swing, the voltages of the first power supply 200 and the second power supply 600 are generally high. Although the voltage at point A is determined by the input voltage and the shift circuit during normal operation, which can prevent the seventh NMOS transistor Q7 from having an overvoltage problem, once the circuit is in the disabled state, point A will be in a high-impedance state, and the voltage at point A will become uncertain. At this time, it may cause an overvoltage problem in the voltage difference between the gate (G) and drain (D) of the seventh NMOS transistor Q7.

[0023] To address the issue of high impedance at point A when the circuit is disabled, a third power supply 700 is introduced as a protection power supply. Figure 2As shown, when the circuit is disabled, the logic controls the eighth NMOS transistor Q8 to conduct, clamping the voltage at point B to the third power supply 700. Since point A is in a high impedance state at this time, the voltage at point A is also the power supply voltage of the third power supply 700, thus solving the overvoltage problem when disabled.

[0024] However, the use of multiple power supplies brings about the issue of power-on sequence. The third power supply 700, as a protection power supply, is powered on first, but the first power supply 200 and the second power supply 600 have a power-on sequence issue. When the first power supply 200 is powered on first and the second power supply 600 is powered on later, because the protection enable logic is that the first power supply 200 is powered on first, the voltages of A and B are clamped to the third power supply 700. The second power supply 600 is powered on later, and the seventh NMOS transistor Q7 is not overvoltage. When the second power supply 600 is powered on first and the first power supply 200 is powered on later, the protection enable logic is that the first power supply 200 is powered on and the second power supply 600 is powered on first. At this time, the eighth NMOS transistor Q8 is cut off, the overvoltage protection circuit fails, and point A presents high resistance. The voltage difference between the gate (G) and drain (D) of the seventh NMOS transistor Q7 may be overvoltage. Similarly, if the protection enable logic is changed to the second power supply 600 being powered on, then when the first power supply 200 is powered on first and the second power supply 600 is powered on later, point A presents high resistance, and the voltage difference between the gate (G) and drain (D) of the seventh NMOS transistor Q7 may be overvoltage.

[0025] Furthermore, when the first power supply 200 is not powered on, even if the overvoltage protection circuit is activated, it cannot clamp the voltage at point A to the third power supply 700. This is because the body diode of the sixth PMOS transistor Q6 is forward-biased at this time, clamping the voltage at point A to the voltage of the diode's forward voltage drop. The voltage difference between the gate (G) and drain (D) of the seventh NMOS transistor Q7 may be excessive. To solve this problem, the first diode D6 can be added, such as... Figure 2 As shown. When the first power supply 200 is not powered on, the first diode D6 is reverse-biased and cut off, so that the voltage at point A is not clamped by the body diode of the sixth PMOS transistor Q6. And when working normally, the first diode D6 is forward-biased and the circuit function is still normal, but a forward voltage drop of the first diode D6 is introduced, which is unacceptable for high swing applications.

[0026] like Figure 3As shown, the present invention discloses a high-swing high-speed level shift circuit and a high-swing high-speed level shifter. The high-swing, high-speed level shifting circuit includes: an overvoltage protection circuit 500, a shifting circuit 400, an output stage circuit 300, and a control circuit 100. The control circuit 100 is connected to the first power supply 200 and the shifting circuit 400; the output stage circuit 300 is connected to the second power supply 600 and the shifting circuit 400; and the overvoltage protection circuit 500 is connected to the third power supply 700 and the shifting circuit 400. The control circuit 100 is used to connect the first power supply 200 and the shifting circuit 400 when the first power supply 200 is powered on. The shifting circuit 400 is used to send a displacement signal to the output stage circuit 300 when the first power supply 200 and the shifting circuit 400 are connected. The output stage circuit 300 is used to output a voltage signal according to the displacement signal. The overvoltage protection circuit 500 is used to connect the third power supply 700 and the shifting circuit 400, so that the voltage at the control terminal of the shifting circuit 400 is the third power supply voltage.

[0027] Understandably, this application incorporates a control circuit 100 to replace the first diode D6 to prevent the voltage at point A from being clamped by the body diode of the sixth PMOS transistor Q6. At the same time, this application improves the overvoltage protection circuit and solves the problem of power-on sequence caused by the use of multiple power supplies.

[0028] In this embodiment, the overvoltage protection circuit 500 connects the third power supply 700 and the shift circuit 400, making the voltage at the control terminal of the shift circuit 400 the voltage of the third power supply. The control terminal is the voltage at point B. This solves the requirements of the power supply sequence of the overvoltage protection circuit 500 in multiple voltage domains and the possible leakage problem. The control circuit 100 is disconnected when the first power supply 200 is not powered on, which solves the clamping effect of the body diode of the PMOS during the power-on process.

[0029] Figure 4 This is a circuit diagram of the second embodiment of the high-swing, high-speed level shifting circuit proposed in this invention.

[0030] Based on the first embodiment described above, a second embodiment of the high-swing, high-speed level shifting circuit of the present invention is proposed.

[0031] The overvoltage protection circuit 500 includes a voltage regulator circuit and an enable circuit. The voltage regulator circuit is connected to a third power supply 700, the shift circuit 400, and the enable circuit. The enable circuit is connected to a first power supply 200 or a second power supply 600. The enable circuit generates and sends a conduction signal to the voltage regulator circuit when the first power supply 200 and / or the second power supply 600 is not powered on. The voltage regulator circuit, upon receiving the conduction signal, connects the third power supply 700 and the shift circuit 400, making the voltage at the control terminal of the shift circuit 400 the voltage of the third power supply.

[0032] It is understood that the overvoltage protection circuit 500 includes the voltage regulator circuit and the enable circuit. The enable circuit is used to control the voltage at point C, so that the voltage regulator circuit is turned on or off. The enable circuit is connected to the first power supply 200 or the second power supply 600. Regardless of whether the first power supply 200 and the second power supply 600 are powered on or not, the enable circuit sends a turn-on signal to the voltage regulator circuit, the voltage regulator circuit is turned on, and the voltage at point B is clamped to the third power supply voltage.

[0033] The control circuit 100 includes an on / off circuit and a drive circuit; the on / off circuit is connected to the first power supply 200, the shift circuit 400, and the drive circuit, and the drive circuit is also connected to the third power supply 700 and the first power supply 200; the drive circuit is used to generate and send a cutoff signal to the on / off circuit when the first power supply 200 has no output; the on / off circuit is used to disconnect the connection between the second power supply 600 and the shift circuit 400 when the cutoff signal is received, to prevent the shift circuit 400 from failing to stabilize at the third power supply voltage.

[0034] It is understood that the control circuit 100 provides the voltage of the first power supply 200 to the shift circuit 400, including the following: when the first power supply 200 is powered on, the drive circuit sends a drive signal to the switching circuit, and the switching circuit connects the first power supply 200 and the shift circuit 400; when the first power supply 200 is not powered on, the drive circuit sends a cut-off signal to the switching circuit, and the switching circuit disconnects the first power supply 200 and the shift circuit 400.

[0035] The shift circuit 400 includes: a first current source A1, a second current source A2, a fifth PMOS transistor Q5, a sixth PMOS transistor Q6, a third resistor R3, and a third capacitor C3; the source of the fifth PMOS transistor Q5 is connected to the source of the third PMOS transistor Q3 and the source of the sixth PMOS transistor Q6, the gate of the fifth PMOS transistor Q5 is connected to the drain of the fifth PMOS transistor Q5 and the gate of the sixth PMOS transistor Q6, the drain of the fifth PMOS transistor Q5 is connected to the first terminal of the first current source A1, the drain of the sixth PMOS transistor Q6 is connected to one end of the third resistor R3, one end of the third capacitor C3, and the output stage circuit 300, the other end of the third resistor R3 is connected to the other end of the third capacitor C3, the first terminal of the second current source A2, and the drain of the second PMOS transistor Q2; the second terminal of the first current source A1 is grounded; the second terminal of the second current source A2 is grounded.

[0036] Understandably, in a PMOS, the source and drain are made of P-type semiconductor material, while the gate is made of metal or doped polysilicon. The gate is separated from the source and drain by a thin layer of silicon dioxide (SiO2) insulating material. When the gate voltage is lower than the source voltage by a certain value, the conductive path between the source and drain is "closed." Conversely, when the gate voltage is higher than the source voltage by a certain value, the path between the source and drain is open, putting the PMOS in the "on" state.

[0037] The output stage circuit 300 includes: a seventh NMOS transistor Q7 and a third current source A3; the gate of the seventh NMOS transistor Q7 is connected to the drain of the sixth PMOS transistor Q6, one end of the third resistor R3 and one end of the third capacitor C3, the drain of the seventh NMOS transistor Q7 is connected to the second power supply 600, and the source of the seventh NMOS transistor Q7 is connected to the first end of the third current source A3; the second end of the third current source A3 is grounded.

[0038] Understandably, the primary purpose of the shift circuit 400 and the output stage circuit 300 is to convert the level (or voltage range) of one circuit to the level of another circuit. High amplitude and high speed characteristics are emphasized during the level conversion process.

[0039] It should be noted that the first power supply 200 and the second power supply 600 are high-voltage power supplies. When the third power supply 700 is powered on, the first power supply 200 is powered on first. The enable circuit generates and sends a conduction signal to the voltage regulator circuit. The voltage at point C is low, the voltage regulator circuit is turned on, and the voltage at point B is stabilized at the third power supply voltage. At the same time, the drive circuit sends a drive signal to the switching circuit. The switching circuit connects the first power supply 200 and the shift circuit 400. The source voltages of the fifth PMOS transistor Q5 and the sixth PMOS transistor Q6 are higher than the gate voltages. The fifth PMOS transistor Q5 and the sixth PMOS transistor Q6 are turned on, controlling the seventh NMOS transistor to turn on. Because the voltage at point B has been regulated, there will be no overvoltage at the gate and source of the seventh NMOS transistor Q7. Subsequently, the second power supply 600 is powered on, and the high-swing high-speed level shift circuit works normally.

[0040] Specifically, when the third power supply 700 is powered on, and the second power supply 600 is powered on first, the enable circuit generates and sends a conduction signal to the voltage regulator circuit. The voltage at point C is low, the voltage regulator circuit is turned on, and the voltage at point B is stabilized at the third power supply voltage. At the same time, the drive circuit sends a cutoff signal to the switching circuit, the switching circuit disconnects the connection between the first power supply 200 and the shift circuit 400, and there is no voltage difference between the source voltage and gate voltage of the fifth PMOS transistor Q5 and the sixth PMOS transistor Q6, so the fifth PMOS transistor Q5 and the sixth PMOS transistor Q6 are turned off. Although the voltage at point B is the third power supply voltage, the body diode of the sixth PMOS transistor Q6 will not clamp due to the disconnection of the switching circuit. Subsequently, the first power supply 200 is powered on, and the driving circuit sends a driving signal to the switching circuit. The switching circuit connects the first power supply 200 and the shift circuit 400. The source voltages of the fifth PMOS transistor Q5 and the sixth PMOS transistor Q6 are higher than the gate voltage, and the fifth PMOS transistor Q5 and the sixth PMOS transistor Q6 are turned on, controlling the seventh NMOS transistor to turn on. The high-swing high-speed level shift circuit works normally.

[0041] In this embodiment, the overvoltage protection circuit 500 includes the voltage regulator circuit and the enabling circuit. The enabling circuit controls the voltage at point C, causing the voltage regulator circuit to turn on or off. The enabling circuit is connected to either the first power supply 200 or the second power supply 600. Regardless of whether the first power supply 200 or the second power supply 600 is powered on or off, the enabling circuit sends a conduction signal to the voltage regulator circuit, causing the voltage regulator circuit to turn on, and the voltage at point B is clamped to the third power supply voltage. The overvoltage protection circuit 500 solves the requirements of the power supply sequence and the potential leakage problem in the multi-voltage domain. The control circuit 100 provides a first power supply 200 to the shift circuit 400. When the first power supply 200 is powered on, the drive circuit sends a drive signal to the switching circuit, which connects the first power supply 200 and the shift circuit 400. When the first power supply 200 is not powered on, the drive circuit sends a cutoff signal to the switching circuit, which disconnects the first power supply 200 and the shift circuit 400. By controlling the switching of the first power supply 200, the control circuit 100 solves the clamping effect of the body diode of the sixth PMOS transistor Q6 during power-on, while also meeting the high swing and high speed requirements of the circuit.

[0042] Figure 4 This is a circuit diagram of the second embodiment of the high-swing, high-speed level shifting circuit proposed in this invention.

[0043] Based on the first and / or second embodiments described above, a third embodiment of the high-swing, high-speed level shifting circuit of the present invention is proposed.

[0044] The voltage regulator circuit includes: a first PMOS transistor Q1 and a second PMOS transistor Q2; the drain of the first PMOS transistor Q1 is connected to the third power supply 700, the gate of the first PMOS transistor Q1 is connected to the gate of the second PMOS transistor Q2 and the enable circuit, the source of the first PMOS transistor Q1 is connected to the source of the second PMOS transistor Q2, and the drain of the second PMOS transistor Q2 is connected to the shift circuit 400.

[0045] The enabling circuit includes: a first resistor R1, a first capacitor C1, and a first inverter D1; one end of the first resistor R1 is connected to one end of the first capacitor C1, the gate of the second PMOS transistor Q2, the gate of the third PMOS transistor Q3, and the output terminal of the first inverter D1; the other end of the first resistor R1 and the other end of the first capacitor C1 are grounded; and the input terminal of the first inverter D1 is connected to the second power supply 600.

[0046] Understandably, the input of the first inverter D1 is connected to the second power supply 600. When the second power supply 600 is powered on first, the enable signal is high voltage, which becomes low voltage after passing through the first inverter D1. The voltage at point C is low voltage. Because the body diode of the first PMOS transistor Q1 is conducting, the source voltages of the first PMOS transistor Q1 and the second PMOS transistor Q2 are higher than their gate voltages. The first PMOS transistor Q1 and the second PMOS transistor Q2 are conducting, and the voltage at point B is stabilized at the third power supply voltage. When the first power supply 200 is powered on first, the first resistor R1 and the first capacitor C1 are grounded, the voltage at point C is low voltage, the first PMOS transistor Q1 and the second PMOS transistor Q2 are conducting, and the voltage at point B is stabilized at the third power supply voltage. During normal operation, the second power supply 600 is high voltage, which is reversed to low voltage by the first inverter D1. The first PMOS transistor Q1 and the second PMOS transistor Q2 are conducting, and the voltage at point B is stabilized at the third power supply voltage.

[0047] Optionally, the same applies when the input terminal of the first inverter D1 is connected to the first power supply 200. The input terminal of the first inverter D1 is connected to the first power supply 200 or the second power supply 600 through a protection resistor.

[0048] It should be noted that the original eighth NMOS transistor Q8 was replaced with two PMOS transistors. To address the issue of uncertain voltage at point C due to different power supplies, a first resistor R1 and a first capacitor C1 were added to ground at point C. This ensures that even if the first power supply 200 is not powered on, the potential at point C is low, and the first PMOS transistor Q1 and the second PMOS transistor Q2 are turned on, clamping the voltage at point B to the third power supply voltage. Furthermore, to resolve the gate potential connection issue of the PMOS transistors (if the gate is connected to either the first power supply 200 or the second power supply 600, a large current will flow through the third power supply 700 via the body diode when that power supply is not powered on), the two PMOS transistors are connected in series, with their gates connected to the middle, forming a back-to-back connection. This means that the first PMOS transistor Q1 and the second PMOS transistor Q2 are only turned on when the voltage at point C is low; otherwise, regardless of the potential at point B, the first PMOS transistor Q1 and the second PMOS transistor Q2 will not be turned on.

[0049] The switching circuit includes a third PMOS transistor Q3; the drain of the third PMOS transistor Q3 is connected to the first power supply 200, the gate of the third PMOS transistor Q3 is connected to the driving circuit, and the source of the third PMOS transistor Q3 is connected to the shift circuit 400.

[0050] The driving circuit includes: a second resistor R2, a second capacitor C2, a fourth NMOS transistor Q4, a second inverter D2, and a third inverter D3; one end of the second resistor R2 is connected to the third power supply 700, and the other end of the second resistor R2 is connected to the gate of the third PMOS transistor Q3, one end of the second capacitor C2, and the drain of the fourth NMOS transistor Q4; the other end of the second capacitor C2 and the source of the fourth NMOS transistor Q4 are grounded; the gate of the fourth NMOS transistor Q4 is connected to the output terminal of the second inverter D2; the input terminal of the second inverter D2 is connected to the output terminal of the third inverter D3; and the input terminal of the third inverter D3 is connected to the first power supply 200.

[0051] Understandably, the third PMOS transistor Q3 is used to control the switching of the first power supply 200. During normal operation, the first power supply 200 is input to the gate of the fourth NMOS transistor Q4 through two inverters. The fourth NMOS transistor Q4 is turned on, and the voltage at point D is pulled down to ground. The third PMOS transistor Q3 is turned on, and the first power supply 200 supplies power to the subsequent shift circuit 400 through the third PMOS transistor Q3. The voltage drop of the third PMOS transistor Q3 can be reduced very little by increasing the width-to-length ratio of the third PMOS transistor Q3. When the first power supply 200 is not powered on, the voltage at point D is the third power supply voltage, the third PMOS transistor Q3 is turned off, the first power supply 200 is disconnected from the shift circuit 400, the sixth PMOS transistor Q6 is turned off, and the body diode of the sixth PMOS transistor Q6 is inverted and turned off, which solves the problem of the voltage at point A being clamped by the sixth PMOS transistor Q6. Furthermore, the loading of the control circuit 100 has little effect on the swing and parasitic influence at point A.

[0052] Optionally, reverse bias diodes can be added between all power supplies. As long as one power supply is powered on, the logic powered by the other power supplies can work normally, which can also solve the problem of power-on sequence.

[0053] In this embodiment, to address the power-on sequence requirements of the overvoltage protection circuit 500 in multiple voltage domains, as well as the clamping effect of the PMOS body diode during power-on, while also considering the high swing and high speed requirements of the circuit, the following overvoltage protection circuit 500 and control circuit 100 are proposed. The overvoltage protection circuit 500, through the connection of two back-to-back PMOS transistors, solves the power-on sequence requirements and potential leakage problems in the multi-voltage domain. The control circuit 100, by controlling the switching of the first power supply 200, solves the clamping effect of the PMOS body diode during power-on, while also considering the high swing and high speed requirements of the circuit.

[0054] The present invention also proposes a high-swing high-speed level shifter, which includes a high-swing high-speed level shifting circuit. The specific structure of the high-swing high-speed level shifting circuit is as described in the above embodiments. Since the present high-swing high-speed level shifter adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0055] The above description is merely an exemplary embodiment of the present invention and does not limit the scope of the present invention. Any equivalent structural transformations made based on the technical concept of the present invention and the contents of the specification and drawings of the present invention, or direct / indirect applications in other related technical fields, are included within the protection scope of the present invention.

Claims

1. A high-swing, high-speed level shifting circuit, characterized in that, include: Overvoltage protection circuit, shift circuit, output stage circuit and control circuit; The control circuit is connected to the first power supply and the shift circuit, the output stage circuit is connected to the second power supply and the shift circuit, and the overvoltage protection circuit is connected to the third power supply and the shift circuit. The control circuit is used to connect the first power supply and the shift circuit when the first power supply is powered on. The shift circuit is used to send a shift signal to the output stage circuit when the first power supply and the shift circuit are connected. The output stage circuit is used to output a voltage signal according to the shift signal; The overvoltage protection circuit is used to connect the third power supply and the shift circuit, so that the voltage at the control terminal of the shift circuit is the third power supply voltage. The overvoltage protection circuit includes: a voltage regulator circuit and an enable circuit; The voltage regulator circuit is connected to the third power supply, the shift circuit, and the enable circuit, and the enable circuit is connected to the first power supply or the second power supply. The enabling circuit is used to generate and send a conduction signal to the voltage regulator circuit when there is no output from the first power supply or the second power supply. The voltage regulator circuit is used to connect the third power supply and the shift circuit when the conduction signal is received, so that the voltage at the control terminal of the shift circuit is the voltage of the third power supply.

2. The high-swing, high-speed level shifting circuit as described in claim 1, characterized in that, The control circuit includes: an on / off circuit and a drive circuit; The switching circuit is connected to the first power supply, the shifting circuit and the driving circuit, and the driving circuit is also connected to the third power supply and the first power supply; The driving circuit is used to generate and send a cutoff signal to the on / off circuit when the first power supply has no output. The on / off circuit is used to disconnect the connection between the first power supply and the shift circuit when the cutoff signal is received, so that the voltage at the control terminal of the shift circuit is the third power supply voltage.

3. The high-swing, high-speed level shifting circuit as described in claim 2, characterized in that, The voltage regulator circuit includes: a first PMOS transistor and a second PMOS transistor; The drain of the first PMOS transistor is connected to the third power supply, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and the enable circuit, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the drain of the second PMOS transistor is connected to the shift circuit.

4. The high-swing, high-speed level shifting circuit as described in claim 3, characterized in that, The enabling circuit includes: a first resistor, a first capacitor, and a first inverter; One end of the first resistor is connected to one end of the first capacitor, the gate of the second PMOS transistor, the gate of the first PMOS transistor, and the output terminal of the first inverter. The other end of the first resistor and the other end of the first capacitor are grounded. The input terminal of the first inverter is connected to the second power supply or the first power supply.

5. The high-swing, high-speed level shifting circuit as described in claim 3, characterized in that, The switching circuit includes: a third PMOS transistor; The drain of the third PMOS transistor is connected to the first power supply, the gate of the third PMOS transistor is connected to the driving circuit, and the source of the third PMOS transistor is connected to the shift circuit.

6. The high-swing, high-speed level shifting circuit as described in claim 5, characterized in that, The driving circuit includes: a second resistor, a second capacitor, a fourth NMOS transistor, a second inverter, and a third inverter; One end of the second resistor is connected to the third power supply, and the other end of the second resistor is connected to the gate of the third PMOS transistor, one end of the second capacitor, and the drain of the fourth NMOS transistor. The other end of the second capacitor and the source of the fourth NMOS transistor are grounded. The gate of the fourth NMOS transistor is connected to the output of the second inverter. The input of the second inverter is connected to the output of the third inverter. The input of the third inverter is connected to the first power supply.

7. The high-swing, high-speed level shifting circuit as described in claim 6, characterized in that, The shift circuit includes: a first current source, a second current source, a fifth PMOS transistor, a sixth PMOS transistor, a third resistor, and a third capacitor; The source of the fifth PMOS transistor is connected to the source of the third PMOS transistor and the source of the sixth PMOS transistor. The gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor and the gate of the sixth PMOS transistor. The drain of the fifth PMOS transistor is connected to the first terminal of the first current source. The drain of the sixth PMOS transistor is connected to one end of the third resistor, one end of the third capacitor, and the output stage circuit. The other end of the third resistor is connected to the other end of the third capacitor, the first terminal of the second current source, and the drain of the second PMOS transistor. The second terminal of the first current source is grounded. The second terminal of the second current source is grounded.

8. The high-swing, high-speed level shifting circuit as described in claim 7, characterized in that, The output stage circuit includes: a seventh NMOS transistor and a third current source; The gate of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor, one end of the third resistor, and one end of the third capacitor. The drain of the seventh NMOS transistor is connected to the second power supply, and the source of the seventh NMOS transistor is connected to the first end of the third current source. The second end of the third current source is grounded.

9. A high-swing, high-speed level shifter, characterized in that, The high-swing high-speed level shifter includes the high-swing high-speed level shift circuit as described in any one of claims 1 to 8.

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