All-digital phase-locked loop and working method

Abstract

The application discloses a kind of all-digital phase-locked loop and working method, and phase-locked loop includes time digital converter, digital loop filter, digital controlled oscillator, digital time converter, phase accumulator and phase detector etc.Modular phase detection part is divided into integer phase detection and fractional phase detection, first integer phase operation is carried out, after fractional phase is compensated by DTC, reference phase and feedback phase are compared by TDC, to avoid using the divider of high complexity in traditional structure, and the introduction of DTC makes the measurement range of TDC greatly reduce, reduce the requirement to TDC performance and power consumption.The structure effectively reduces the design complexity and TDC performance bottleneck, while guaranteeing low phase noise and low stray, realizes accurate frequency synthesis.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit design technology, specifically to a fractional-division all-digital phase-locked loop based on DTC (Digital to Time Converter), TDC (Time to Digital Converter), and a counter. Background Technology

[0002] All-digital phase-locked loops (ADPLLs), as the core module of modern frequency synthesis technology, are widely used in electronic systems such as wireless communication, digital television broadcasting, and clock data recovery. Compared with traditional analog PLLs, all-digital PLLs have outstanding advantages such as strong process portability, superior resistance to power supply noise interference, and ease of integration with digital calibration algorithms. As semiconductor feature sizes continue to shrink and power supply voltages continue to decrease, analog circuit design faces greater challenges. All-digital PLLs, with their perfect compatibility with digital processes, have gradually become one of the mainstream choices for RF integrated circuit design. Especially in high-performance applications such as multi-core processor clock synchronization, RF transceivers, frequency synthesis, and satellite communications, all-digital PLLs need to simultaneously meet multiple technical specifications such as low phase noise, low spurious emissions, and high frequency resolution, which places higher demands on the design of the loop architecture.

[0003] As a key component of an all-digital phase-locked loop (PLL), the time-to-digital converter (TDC) quantizes the time difference into a numerical value, enabling precise measurement of fractional phase. To balance low quantization noise performance with the requirement of covering the entire feedback clock cycle in traditional ADPLL structures, the TDC often needs to possess both high resolution and a wide measurement range. However, high resolution demands a minimal basic delay for the TDC, while a wide measurement range requires cascading a large number of delay units, creating an inherent contradiction. To meet this requirement, complex structures with multi-stage cascading or time amplifiers are typically employed, inevitably leading to a significant increase in circuit power consumption. Traditional ADPLL structures require a divider in the TDC normalization section, further exacerbating the complexity and area overhead of the digital circuit. Therefore, how to effectively overcome the performance bottleneck of the TDC and achieve high-performance fractional-division frequency synthesis without significantly increasing system complexity and power consumption remains a crucial technical problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a fully digital phase-locked loop (PLL) that addresses the problems of high power consumption and hardware overhead caused by the high requirements for high-resolution and wide-range measurement range of the time-locked loop (TDC) and the high complexity of the normalization module in traditional ADPLL architectures. This invention significantly reduces the requirements for TDC performance and power consumption by separating integer phase detection from fractional phase detection, and by delegating fractional phase compensation to a Digital to Time Converter (DTC).

[0005] To achieve the above objectives, the present invention provides a fully digital phase-locked loop, comprising: The time-to-digital converter quantizes the time difference between the measured rising edges of REF_DLY and CKV into a digital value; A digital loop filter attenuates and filters the digital values ​​input from a time-to-digital converter. The Delta-sigma modulator jitters the NTW after it has been processed by the digital loop filter, reduces the frequency quantization compensation of the numerically controlled oscillator, and shapes the noise of the numerically controlled oscillator to a higher frequency. A numerically controlled oscillator adjusts the binary digital value fed into the Delta-sigma modulator and outputs a high-frequency oscillating sine wave. The variable phase accumulator counts the period of the CKV input from the numerically controlled oscillator to obtain the integer phase of the CKV. ; The reference phase accumulator accumulates the reference phase to obtain the reference phase. ; Digital phase detector, for integer phase and reference phase Perform the calculation to obtain the fractional phase. ; Digital time converter, converts the input fractional phase binary value It is converted into a delay T, which is used to delay the reference clock.

[0006] Furthermore, the time-to-digital converter includes the main circuit of the digital time converter, temperature code and binary code decoder.

[0007] Furthermore, the digital loop filter employs a proportional-integral digital filter or a high-order digital filter.

[0008] Furthermore, the adjustment of the numerically controlled oscillator includes three parts: coarse adjustment, intermediate adjustment, and fine adjustment. Their frequency compensation decreases sequentially, with the fine adjustment step size determining the quantization noise of the numerically controlled oscillator. The fine adjustment part is connected to a phase-locked loop, while the control words for coarse and intermediate adjustment are generated by algorithms.

[0009] Furthermore, the transfer function of the digital time converter is: ,in The total time delay of the digital-to-time converter output with k input codewords. This is the inherent offset time. Includes gain calibration using the LMS algorithm.

[0010] The operating method of this all-digital phase-locked loop is also provided, including: One output of the numerically controlled oscillator is connected to a variable phase accumulator, which performs calculations with the reference phase accumulator through a digital phase detector to generate a value, which is then input to a digital time converter and output to a time-to-digital converter. The other output is used as a feedback clock and is compared with the compensated reference clock in the time-to-digital converter. The digital phase difference is output to a digital loop filter by the time-to-digital converter, and after filtering by the digital loop filter, the frequency of the numerically controlled oscillator is modulated.

[0011] Subtract the integer phase from the feedback obtained by the variable phase accumulator from the reference phase accumulator to obtain the fractional phase difference. The reference clock REF is delayed in the digital time converter to obtain REF_DLY, which is aligned with the rising edge of CKV after locking.

[0012] REF_DLY and CKV are compared in phase using a time-to-digital converter. The comparison result is then filtered by a digital loop filter to adjust the output frequency of the digitally controlled oscillator until the frequency and phase are locked.

[0013] Furthermore, the reference phase includes an integer part and a fractional part, which are divided by phase detection. The integer phase detection is completed by a variable phase accumulator, a reference phase accumulator, and a digital phase detector, while the fractional phase detection is completed by a DTC and a TDC.

[0014] Furthermore, REF_DLY represents the reference phase, and CKV represents the feedback phase.

[0015] The beneficial effects of this invention are: (1) By adjusting the ADPLL structure, the integer phase effect is first eliminated by DPD, and then the fractional phase is processed by DTC and TDC. The integer phase detection and fractional phase detection are separated, avoiding the normalized division operation that must be performed on the fractional part in the traditional structure, which is uniformly compared in DPD, thus simplifying the complexity of digital circuits.

[0016] (2) By adding DTC to compensate for the fractional phase of the reference clock, the edge of the reference clock is delayed to be close to the feedback clock, which greatly reduces the measurement range of TDC and reduces the performance requirements and power consumption of TDC.

[0017] (3) By combining the advantages of DTC and TDC, this invention not only reduces the performance requirements of TDC in the traditional structure, but also avoids the loop from getting stuck in the limit loop of Bang-Bang modulation, avoids the use of a divider, reduces the implementation difficulty, saves area and power consumption, and can guarantee the output frequency and accuracy. Therefore, it can be widely used in multi-core processors, radio frequency transceivers and satellite communications. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the all-digital phase-locked loop structure proposed in this invention.

[0019] Figure 2 for Key waveform timing diagram.

[0020] Figure 3 for At that time, the key module outputs after the ADPLL lock proposed in this invention.

[0021] Figure 4 This is the s-domain model of ADPLL proposed in this invention.

[0022] Figure 5 The simulation results of the time-domain response of the ADPLL system of the present invention are shown. Detailed Implementation

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Note: Unless otherwise specified, the experimental methods in the following examples are conventional methods, performed according to the techniques or conditions described in the literature in this field or according to the product instructions. Unless otherwise specified, the materials and reagents used in the following examples are commercially available.

[0025] The loop of this invention contains a high-frequency feedback clock and a low-frequency reference clock output by a numerically controlled oscillator, forming two clock sources. The variable phase accumulator operates under the high-frequency clock, while the reference phase accumulator operates under the low-frequency reference clock. The two clocks have an arbitrary fractional frequency multiplication relationship, requiring cross-clock domain operation to process the two sets of data.

[0026] The fractional-order frequency division of this invention is mainly implemented through a digital-to-time converter and a time-to-digital converter module. By separating the integer phase and the fractional phase, and locking them, a digital phase detector obtains the fractional phase difference value to be compensated for each reference cycle. The reference clock is delayed by the corresponding value through the digital-to-time converter, and its rising edge is aligned with the feedback clock. At this time, the comparison result of the time difference between the two input signals by the time-to-digital converter is 0, and the output is sent to the digital loop filter. At this time, the digital loop filter no longer adjusts the frequency of the numerically controlled oscillator, and the loop is locked. Since the residual phase difference between the compensated reference clock and the feedback clock is limited to a very small range, only a narrow-range, low-complexity time-to-digital converter is needed to complete the precise measurement of this residual phase difference.

[0027] Time to Digital Converter (TDC) Digital Loop Filter (DLF) Digitally Controlled Oscillator (DCO) Delta-Sigma Modulator (DSM) Variable Phase Accumulator (VPA) Reference Phase Accumulator (RPA) Digital Phase Detector (DPD) Digital to Time Converter (DTC) LMS Least Mean Squares NTW digital modulation word CKV CNC oscillator output signal Example 1 like Figure 1 As shown, a fully digital phase-locked loop includes: The time-to-digital converter quantizes the time difference between the measured rising edges of REF_DLY and CKV into a digital value; A digital loop filter attenuates and filters the digital values ​​input from a time-to-digital converter. The Delta-sigma modulator jitters the digital modulation word NTW after it has been processed by the digital loop filter, reduces the frequency quantization compensation of the numerically controlled oscillator, and shapes the noise of the numerically controlled oscillator to a higher frequency. A numerically controlled oscillator adjusts the binary digital value fed into the Delta-sigma modulator and outputs a high-frequency oscillating sine wave. The variable phase accumulator counts the period of the CKV input from the numerically controlled oscillator to obtain the integer phase of the CKV. ; The reference phase accumulator accumulates the reference phase to obtain the reference phase. ; Digital phase detector, for integer phase and reference phase Perform the calculation to obtain the fractional phase. ; Digital time converter, converts the input fractional phase binary value It is converted into a delay T, which is used to delay the reference clock.

[0028] Furthermore, the time-to-digital converter includes the main circuit of the digital time converter, temperature code and binary code decoder.

[0029] Furthermore, the digital loop filter employs a proportional-integral digital filter or a high-order digital filter.

[0030] Furthermore, the adjustment of the numerically controlled oscillator includes three parts: coarse adjustment, intermediate adjustment, and fine adjustment. Their frequency compensation decreases sequentially, with the fine adjustment step size determining the quantization noise of the numerically controlled oscillator. The fine adjustment part is connected to a phase-locked loop, while the control words for coarse and intermediate adjustment are generated by algorithms.

[0031] Furthermore, the transfer function of the digital time converter is: ,in The total time delay of the digital-to-time converter output with k input codewords. For inherent offset time, For DTC gain, This is the input numeric codeword. It includes gain calibration, using the LMS algorithm.

[0032] The operating method of this all-digital phase-locked loop is also provided, including: Subtract the integer phase from the feedback obtained by the variable phase accumulator from the reference phase accumulator to obtain the fractional phase difference. The reference clock REF is delayed in the digital time converter to obtain REF_DLY, which is aligned with the rising edge of CKV after locking.

[0033] REF_DLY and CKV are compared in phase using a time-to-digital converter. The comparison result is then filtered by a digital loop filter to adjust the output frequency of the digitally controlled oscillator until the frequency and phase are locked.

[0034] Furthermore, the reference phase accumulated in the reference phase accumulator includes both an integer part and a fractional part.

[0035] Furthermore, REF_DLY represents the reference phase, and CKV represents the feedback phase.

[0036] like Figure 2 As shown, when the FCW (Frequency Command Word) is 2.25, the working waveform of the key node after locking using the all-digital phase-locked loop of the present invention can be seen. It can be seen that when the period of the reference signal REF is not an integer multiple of the period of the output signal CKV, the rising edges of the two original signals are not aligned in every period in the locked state. The ADPLL of the present invention obtains the delayed reference signal REF_DLY through the above calculation and compensation, and its rising edge is always aligned with CKV, proving that the TDC output is 0 after the loop is locked.

[0037] like Figure 3 As shown, the output values ​​of the key module, where FCW = As can be seen, under the global clock, RPA accumulates 2.25 per clock cycle, VPA accumulates the integer part of CKV, and the difference is obtained to obtain the compensation value for REF per cycle. After DTC compensation, REF_DLY is aligned with CKV, proving that the ADPLL phase detection method of the present invention is correct.

[0038] like Figure 4 As shown, the model of the all-digital phase-locked loop of the present invention includes the transfer functions of each module and the open-loop transfer function of the system: in, For DTC gain, For TDC gain, As a scaling factor, As the integrating factor, For reference clock frequency, For DCO gain, is the Laplace transform factor.

[0039] Feedback coefficient: Closed-loop transfer function: A is the open-loop transfer function, and F is the feedback coefficient.

[0040] like Figure 5As shown, the simulation results of the present invention using Simulink demonstrate that the loop is locked, proving that the proposed ADPLL structure and phase detection method are correct and conform to the response characteristics of a second-order system.

[0041] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A fully digital phase-locked loop, characterized in that, include: The time-to-digital converter quantizes the time difference between the measured rising edges of REF_DLY and CKV into a digital value; A digital loop filter attenuates and filters the digital values ​​input from a time-to-digital converter. The Delta-sigma modulator jitters the NTW after it has been processed by the digital loop filter, reduces the frequency quantization compensation of the numerically controlled oscillator, and shapes the noise of the numerically controlled oscillator to a higher frequency. The numerically controlled oscillator outputs a high-frequency oscillating sine wave based on the binary digital value fed in by the Delta-sigma modulator. The variable phase accumulator counts the period of the CKV input from the numerically controlled oscillator to obtain the integer phase of the CKV. ; The reference phase accumulator accumulates the reference phase to obtain the reference phase. ; Digital phase detector, for integer phase and reference phase Perform the calculation to obtain the fractional phase. ; Digital time converter, converts the input fractional phase binary value It is converted into a delay T, which is used to delay the reference clock.

2. The all-digital phase-locked loop according to claim 1, characterized in that, The time-to-digital converter includes the main circuit of the digital time converter, temperature code and binary code decoder.

3. The all-digital phase-locked loop according to claim 1, characterized in that, Digital loop filters employ proportional-integral digital filters or high-order digital filters.

4. The all-digital phase-locked loop according to claim 1, characterized in that, The adjustment of the numerically controlled oscillator includes three parts: coarse adjustment, intermediate adjustment and fine adjustment. The frequency compensation of the three parts decreases in that order. The fine adjustment step size determines the quantization noise of the numerically controlled oscillator. The fine adjustment part is connected to the phase-locked loop. The control words for coarse adjustment and intermediate adjustment are generated by the algorithm.

5. The all-digital phase-locked loop according to claim 1, characterized in that, The transfer function of the digital time converter is ,in The total time delay of the digital-to-time converter output with k input codewords. This is the inherent offset time.

6. The all-digital phase-locked loop according to claim 1, characterized in that, The digital time converter includes gain calibration using the LMS algorithm.

7. A method for implementing the all-digital phase-locked loop according to any one of claims 1-6, characterized in that: One output of the numerically controlled oscillator is connected to a variable phase accumulator, which performs calculations with the reference phase accumulator through a digital phase detector to generate a value, which is then input to a digital time converter and output to a time-to-digital converter. The other output is used as a feedback clock and is compared with the compensated reference clock in the time-to-digital converter. The digital phase difference is output to a digital loop filter by the time-to-digital converter, and after filtering by the digital loop filter, the frequency of the numerically controlled oscillator is modulated.

8. The method according to claim 7, characterized in that, include: Subtract the integer phase from the feedback obtained by the variable phase accumulator from the reference phase accumulator to obtain the fractional phase difference. The reference clock REF is delayed in the digital time converter to obtain REF_DLY, which is aligned with the rising edge of CKV after locking. REF_DLY and CKV are compared in phase by the time-to-digital converter. The comparison result is filtered by a digital loop filter to adjust the output frequency of the digitally controlled oscillator until the frequency and phase are locked.

9. The method according to claim 7, characterized in that, The reference phase accumulator includes an integer part and a fractional part, which are divided by phase detection. The integer phase detection is completed by a variable phase accumulator, a reference phase accumulator and a digital phase detector, while the fractional phase detection is completed by a DTC and a TDC.

10. The method according to claim 7, characterized in that, REF_DLY represents the reference phase, and CKV represents the feedback phase.

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