Pipelined analog-to-digital converter front-end circuit and related circuits and devices

Abstract

The application discloses a pipeline analog-to-digital converter front-end circuit and related circuits and devices thereof. The pipeline analog-to-digital converter front-end circuit comprises a charge-sharing sampling stage circuit, the charge-sharing sampling stage circuit comprises a first capacitor, a second capacitor and a mode switching circuit, the second end of the second capacitor is connected to the input end of the pipeline analog-to-digital converter, and the mode switching circuit is connected to the signal input end, the reset voltage end, the second end of the first capacitor and the first end of the second capacitor. In the first mode, the first capacitor performs input signal tracking, and the second capacitor and the connected pipeline analog-to-digital converter perform residual amplification work. In the second mode, the first capacitor keeps the tracked signal charge, and the path between the second capacitor and the reset voltage end is conducted to empty the charge of the second capacitor. In the third mode, the first capacitor and the second capacitor perform charge-sharing sampling. The pipeline analog-to-digital converter front-end circuit aims to improve the conversion efficiency of the pipeline analog-to-digital conversion circuit.

Description

Technical Field

[0001] This application relates to the field of wireless and communication technology, and in particular to a pipelined analog-to-digital converter front-end circuit and related circuits and devices. Background Technology

[0002] Pipeline analog-to-digital converters (ADCs) are in high demand in the wireless and communication technologies field. However, existing pipeline ADCs are limited by the structural characteristics of their traditional architecture, resulting in long input sampling and residual amplification operations, which in turn limits the conversion efficiency of pipeline ADCs. Summary of the Invention

[0003] The main objective of this application is to propose a front-end circuit for a pipelined analog-to-digital converter and related circuits and devices, which aims to improve the conversion efficiency of the pipelined analog-to-digital converter while ensuring high-precision and low-noise sampling and residual amplification.

[0004] To achieve the above objectives, the pipelined analog-to-digital converter front-end circuit provided in this application has a charge-shared sampling stage circuit and is applied to a pipelined analog-to-digital converter circuit, wherein the pipelined analog-to-digital converter circuit includes a pipelined analog-to-digital converter, and the charge-shared sampling stage circuit includes: A first capacitor having a first terminal and a second terminal, the first capacitor being used for input signal tracking through its first terminal; A second capacitor has a first terminal and a second terminal, the second terminal of which is used to connect to the input terminal of the pipelined analog-to-digital converter. A mode switching circuit is connected to a signal input terminal, a reset voltage terminal, a second terminal of the first capacitor, and a first terminal of the second capacitor. The mode switching circuit is configured to switch between a first mode, a second mode, and a third mode. In the first mode, the path between the second terminal of the first capacitor and the first terminal of the second capacitor is disconnected, and the path between the signal input terminal and the first terminal of the first capacitor is connected, so that the first capacitor performs input signal tracking, and the second capacitor performs residual amplification with the connected pipeline analog-to-digital converter. In the second mode, the path between the second terminal of the first capacitor and the first terminal of the second capacitor is disconnected, and the path between the signal input terminal and the first terminal of the first capacitor is disconnected, so that the first capacitor retains the tracked signal charge, and the path between the second capacitor and the reset voltage terminal is connected to clear the charge of the second capacitor. In the third mode, the mode switching circuit connects the path between the second terminal of the first capacitor and the first terminal of the second capacitor, so that the first capacitor and the second capacitor perform charge sharing sampling.

[0005] In one embodiment, the pipelined analog-to-digital converter front-end circuit further includes a sub-analog-to-digital converter and a reference switching circuit; The input terminal of the sub-analog-to-digital converter is connected to the signal input terminal through the mode switching circuit, the output terminal of the sub-analog-to-digital converter is connected to the control terminal of the reference switching circuit, and the first terminal of the second capacitor is connected to multiple reference voltage terminals through the reference switching circuit. In the first mode, the sub-analog-to-digital converter and the first capacitor synchronously track the input signal. The reference switching circuit connects the first terminal of the second capacitor to the corresponding reference voltage terminal according to the quantization result output by the sub-analog-to-digital converter. In the second mode, the sub-analog-to-digital converter performs the conversion. In the third mode, the sub-analog-to-digital converter performs the conversion.

[0006] In one embodiment, the mode switching circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch; the first switch is connected in series between the signal input terminal and a first terminal of the first capacitor; the second switch is connected in series between a first common-mode voltage terminal and a first terminal of the first capacitor; the third switch is connected in series between the first common-mode voltage terminal and a second terminal of the first capacitor; the fourth switch is connected in series between the second terminal of the first capacitor and a first terminal of the second capacitor; the fifth switch is connected in series between the reset voltage terminal and a first terminal of the second capacitor; and the sixth switch is connected in series between the input terminal of the sub-analog-to-digital converter and the signal input terminal. In the first mode, the mode switching circuit turns on the first switch, the third switch, and the sixth switch, while the second switch, the fourth switch, and the fifth switch are turned off. In the second mode, the second switch and the fifth switch are turned on, while the first switch, the third switch, the fourth switch, and the sixth switch are turned off. In the third mode, the mode switching circuit turns on the second and fourth switches, and turns off the first, third, fifth, and sixth switches.

[0007] In one embodiment, the capacitance value of the second capacitor is smaller than the capacitance value of the first capacitor; During the transition phase from the first mode to the second mode, the mode switching circuit is configured to sequentially disconnect the third switch and the first switch.

[0008] In one embodiment, the front-end circuit of the pipelined analog-to-digital converter further includes a noise cancellation unit, which includes an auto-zeroing capacitor connected in series between the residual amplifiers inside the pipelined analog-to-digital converter. The mode switching circuit also includes a seventh switch, which is connected in series between the second terminal of the second capacitor and the second reset voltage terminal. During the transition phase from the third mode to the first mode, the mode switching circuit disconnects the seventh switch to transfer the thermal noise generated by the charge-sharing sampling stage to the bottom plate of the automatic zeroing capacitor.

[0009] In one embodiment, the front-end circuit of the pipelined analog-to-digital converter further includes a zero-reset switch, the top plate of the automatic zero-reset capacitor is connected to the common-mode reference voltage terminal through the zero-reset switch, and the bottom plate of the automatic zero-reset capacitor is connected in series in the signal path of the amplification stage. In the first mode, the mode switching circuit disconnects the seventh switch and controls the zeroing switch to turn on, so as to physically clamp the top plate of the automatic zeroing capacitor to the common mode reference voltage terminal.

[0010] In one embodiment, the pipelined analog-to-digital converter front-end circuit further includes a substrate tracking circuit; The substrate tracking circuit includes a substrate tracking bootstrap circuit, a first tracking capacitor, and a second tracking capacitor. The ratio of the capacitance value of the first tracking capacitor to the capacitance value of the second capacitor is equal to the ratio of the capacitance value of the second tracking capacitor to the capacitance value of the second capacitor. The bottom plate of the first tracking capacitor can be selectively connected to the signal input terminal, and the top plate of the first tracking capacitor is connected to the input terminal of the substrate tracking bootstrap circuit; the bottom plate of the second tracking capacitor can be selectively connected to the first common-mode voltage terminal, and the top plate of the first tracking capacitor is connected to the input terminal of the substrate tracking bootstrap circuit. In one embodiment, the substrate tracking bootstrap circuit includes a bias capacitor and a bootstrap switch group; In the first mode or the second mode, the bootstrap switch group is configured to conduct the charging path between the bias capacitor and the preset bias voltage terminal, so that the bias capacitor stores the preset voltage difference; In the third mode, the bootstrap switch group is configured to disconnect the charging path and connect the bias capacitor in series between the top plate of the first tracking capacitor and the substrate of the fourth switch.

[0011] This application also provides a pipelined analog-to-digital converter circuit, characterized in that the pipelined analog-to-digital converter circuit includes: Multiple pipelined analog-to-digital converters; Multiple pipelined analog-to-digital converter front-end circuits as described above; In two adjacent pipelined analog-to-digital converters, the output of the first pipelined analog-to-digital converter is connected to the signal input of the charge-sharing sampling stage circuit in the front-end circuit of the pipelined analog-to-digital converter, and the input of the second pipelined analog-to-digital converter is connected to the second terminal of the second capacitor in the charge-sharing sampling stage circuit in the front-end circuit of the same pipelined analog-to-digital converter.

[0012] This application also provides a communication device, characterized in that the communication device includes a pipelined analog-to-digital converter front-end circuit as described above, or a pipelined analog-to-digital converter circuit as described above.

[0013] In summary, the pipelined analog-to-digital converter (ADC) front-end circuit provided in this application, through physical topology design and the synergistic effect of parallel timing mode switching circuitry, decouples and parallelizes the traditionally mutually restrictive input tracking, reset, and charge-sharing sampling operations with the residual amplification operation. Thus, parallel timing enables the various modules of the circuit to work synchronously, simultaneously performing residual amplification, automatic offset zeroing, and quantization operations while executing charge-sharing sampling. This improves the overall conversion efficiency of the pipelined ADC circuit while ensuring high-precision, low-noise sampling and residual amplification. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0015] Figure 1 A circuit diagram of an embodiment of the front-end circuit of the pipelined analog-to-digital converter provided in this application; Figure 2 A circuit diagram of an embodiment of the pipelined analog-to-digital converter front-end circuit in a first mode provided in this application; Figure 3 A circuit diagram of an embodiment of the pipelined analog-to-digital converter front-end circuit in the second mode provided in this application; Figure 4 A circuit diagram of an embodiment of the pipelined analog-to-digital converter front-end circuit in the third mode provided in this application; Figure 5A circuit diagram of a first embodiment of the substrate tracking circuit provided in this application; Figure 6 A circuit diagram of a second embodiment of the substrate tracking circuit provided in this application; Figure 7 A circuit diagram of the third embodiment of the substrate tracking circuit provided in this application; Figure 8 This is a circuit diagram of the fourth embodiment of the substrate tracking circuit provided in this application; Figure 9 The graph shows the relationship between SNDR and ΔVST (with and without STT). Figure 10 The graph shows the relationship between SFDR and ΔVST (with and without STT). Figure 11 The graph shows the relationship between SNDR and input frequency (with and without STT). Figure 12 The graph shows the relationship between SFDR and input frequency (with and without STT). Figure 13 The figure shows the PVT simulation results of SNDR at 2.5VΔVST and 1.1MHz input frequency; Figure 14 The figure shows the PVT simulation results of the SFDR at an input frequency of 2.5VΔVST and 1.1MHz. Figure 15 The image shows the Monte Carlo simulation results of SNDR. Figure 16 The image shows the Monte Carlo simulation results of SFDR.

[0016] Explanation of icon numbers: 10. Pipeline analog-to-digital converter front-end circuit; 20. Pipeline analog-to-digital converter circuit; 500. Pipeline analog-to-digital converter; C1, First capacitor; C2, Second capacitor; C3, Automatic zeroing capacitor; C4, First tracking capacitor; C5, Second tracking capacitor; S1, First switch; S2, Second switch; S3, Third switch; S4, Fourth switch; S5, Fifth switch; S6, Sixth switch; S7, Seventh switch; S8, Zeroing switch; ADC1, Sub-analog-to-digital converter.

[0017] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0020] Pipeline analog-to-digital converters (ADCs) are in high demand in the wireless and communication technologies field. However, existing pipeline ADCs are limited by the structural characteristics of their traditional architecture, resulting in long input sampling and residual amplification operations, which in turn limits the conversion efficiency of pipeline ADCs.

[0021] For example, the traditional bottom-plate sampling architecture limits the conversion rate and resolution. In traditional pipelined analog-to-digital converters, the bottom-plate sampling stage typically shares the same large-capacity sampling capacitor with the residual amplifier to suppress kT / C noise. This shared structure means that the sampling and residual amplification processes of the input signal must be performed independently and serially, thus limiting the conversion rate of the entire pipelined analog-to-digital converter.

[0022] To improve the conversion rate of pipelined analog-to-digital converter circuits, such as Figure 1As shown, the pipelined analog-to-digital converter (ADC) front-end circuit 10 provided in this application is applied to a pipelined ADC circuit 20, which includes a pipelined ADC 500. In one embodiment of this application, the pipelined ADC front-end circuit 10 includes a charge-shared sampling stage circuit, which includes a first capacitor C1, a second capacitor C2, and a mode switching circuit. The first capacitor C1 has a first terminal and a second terminal, and is used for input signal tracking through its first terminal. The second capacitor C2 has a first terminal and a second terminal, and its second terminal is used to connect to an input terminal of the pipelined ADC 500. The mode switching circuit connects the signal input terminal Vin, the reset voltage terminal VRS1, the second terminal of the first capacitor C1, and the first terminal of the second capacitor C2. The mode switching circuit is configured to switch between a first mode, a second mode, and a third mode.

[0023] In this context, the first capacitor C1 can be understood as the tracking capacitor, which is mainly used to effectively track the input signal and suppress thermal noise during the tracking process. The second capacitor C2 can be understood as the actual sampling capacitor in the analog-to-digital conversion capacitor network.

[0024] The mode switching circuit can be implemented using a switching network constructed from multiple metal-oxide-semiconductor transistors. Optionally, the mode switching circuit can integrate a timing logic control module or be externally connected to a dedicated clock generation and control circuit to generate multi-phase parallel operation timing control signals, thereby controlling the on and off states of each switch within the circuit to achieve automated switching from the first mode to the third mode. Optionally, the first mode, the second mode, and the third mode are cyclical and sequentially performed periodic operation stages to match the continuous data processing cycle of the pipelined analog-to-digital converter 500. The mode switching circuit is connected between the first capacitor C1 and the second capacitor C2, between the first capacitor C1 and the signal input terminal Vin, and between the second capacitor C2 and the reset voltage terminal VRS1.

[0025] like Figure 2As shown, in the first mode, the path between the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2 is disconnected, while the path between the signal input terminal Vin and the first terminal of the first capacitor C1 is connected. This allows the first capacitor C1 to track the input signal, and the second capacitor C2 performs residual amplification with the connected pipelined analog-to-digital converter 500. It is understandable that in the first mode (i.e., the tracking and residual amplification stage), the input signal tracking process of the first capacitor C1 is completely independent of the residual amplification process of the pipelined analog-to-digital converter 500. This allows the first capacitor C1 to perform signal tracking for a longer period, thereby alleviating the driving stress on the signal input terminal Vin. Simultaneously, the smaller second capacitor C2 does not need to perform active signal sampling but instead works in conjunction with the connected pipelined analog-to-digital converter 500 to perform residual amplification. This significantly reduces the reference load of the pipelined analog-to-digital converter 500 and further reduces reference voltage glitches. In other words, in the first mode, the input signal tracking process for the current sampling period and the residual amplification process for the previous sampling period are parallel. By changing the sampling and amplification operations from traditional serial execution to parallel execution, the time dependency between the two is eliminated, thereby improving the overall conversion rate of the pipeline analog-to-digital converter circuit 20 without sacrificing signal establishment accuracy.

[0026] Furthermore, it's worth mentioning that because the tracking process of the first capacitor C1 is completely independent of the residual amplification process of the pipelined analog-to-digital converter 500 in the first mode, the effective sampling time window of the first capacitor C1 is extended. Based on the physical mechanism of circuit setup accuracy, the increase in the sampling time window means that a larger setup time constant can be allowed while maintaining the same sampling accuracy, thereby directly reducing the unity-gain bandwidth requirement of the front-end driver amplifier. At the same time, the longer tracking time makes the voltage change rate of the input signal during charge storage smoother, effectively alleviating the slew rate pressure on the driver amplifier when handling large signal jumps.

[0027] like Figure 3As shown, in the second mode, the path between the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2 is disconnected, and the path between the signal input terminal Vin and the first terminal of the first capacitor C1 is also disconnected. This allows the first capacitor C1 to maintain the tracked signal charge, while the path between the second capacitor C2 and the reset voltage terminal VRS1 is connected to clear the charge of the second capacitor C2. It can be understood that in the second mode (i.e., the hold and reset phase), the path between the signal input terminal Vin and the first terminal of the first capacitor C1 is disconnected, causing the first capacitor C1 to end the tracking process and stably maintain the acquired signal charge. Simultaneously, the second terminal of the second capacitor C2 is disconnected from the pipelined analog-to-digital converter 500, and the path between the second capacitor C2 and the reset voltage terminal VRS1 is connected, entering the reset phase to clear the residual charge on the plates of the second capacitor C2, thereby effectively reducing the memory effect during continuous sampling.

[0028] like Figure 4 As shown, in the third mode, the path between the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2 is connected, enabling the first capacitor C1 and the second capacitor C2 to perform charge-sharing sampling. It can be understood that in the third mode (which can be understood as the charge-sharing sampling stage), the path between the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2 is connected, utilizing the signal charge held in the first capacitor C1 to perform passive charge sharing with the second capacitor C2 in its reset state, thereby completing the sampling action of the second capacitor C2.

[0029] In summary, the pipelined analog-to-digital converter front-end circuit 10 provided in this application, through physical topology design and the synergistic effect of parallel timing mode switching circuits, decouples and parallelizes the traditionally mutually restrictive input tracking, reset, and charge-sharing sampling operations with the residual amplification operation. Thus, by parallelizing the timing, the various modules of the circuit can work synchronously, simultaneously performing residual amplification, automatic offset zeroing, and quantization operations while executing charge-sharing sampling. This improves the overall conversion efficiency of the pipelined analog-to-digital converter circuit 20 while ensuring high-precision and low-noise sampling and residual amplification.

[0030] In one embodiment, such as Figure 1 As shown, the pipeline analog-to-digital converter front-end circuit 10 also includes a sub-analog-to-digital converter ADC1 and a reference switching circuit; the input terminal of the sub-analog-to-digital converter ADC1 is connected to the signal input terminal Vin through the mode switching circuit, the output terminal of the sub-analog-to-digital converter ADC1 is connected to the control terminal of the reference switching circuit, and the first terminal of the second capacitor C2 is connected to multiple reference voltage terminals through the reference switching circuit.

[0031] The sub-analog-to-digital converter (ADC1) can be understood as a coarse quantization unit in the pipelined analog-to-digital conversion stage. It is used to perform low-resolution fast quantization on the input analog signal to determine the voltage range of the current stage signal and output the corresponding digital quantization code. The reference switching circuit can be a multiplexer or switch array composed of multiple analog switches. Its main function is to select one or more matching reference voltages from multiple preset reference voltage terminals according to the digital quantization code output by the sub-analog-to-digital converter (ADC1), and apply the reference voltage to the corresponding plate of the connected analog-to-digital conversion capacitor network (i.e., the second capacitor C2 in this application) to generate the analog subtraction reference required for subsequent residual amplification.

[0032] like Figure 2 As shown, in the first mode, the mode switching circuit synchronously tracks the input signal with the sub-analog-to-digital converter ADC1 and the first capacitor C1. The reference switching circuit connects the first terminal of the second capacitor C2 to the corresponding reference voltage terminal based on the quantization result output by the sub-analog-to-digital converter ADC1. It is understandable that during this timing phase, the input tracking operation of the first capacitor C1 and the sub-analog-to-digital converter ADC1 operates completely independently in the time domain from the residual amplification operation of the previous signal cycle involving the second capacitor C2. Since the second capacitor C2 is directly connected to the reference voltage terminal selected based on the quantization result during residual amplification without performing active sampling, this reduces the reference load and further reduces reference signal glitches, improving setup accuracy.

[0033] like Figure 3 As shown, in the second mode, the mode switching circuit initiates high-order bit conversion for the sub-analog-to-digital converter (ADC1). It is understandable that as the first capacitor C1 finishes tracking and enters the hold-reset phase, ADC1 can independently and prematurely begin the conversion of the most significant bit (MSB) segment using the signal voltage captured in its own sampling network, without waiting for subsequent charge-sharing sampling operations to complete. This saves overall runtime.

[0034] like Figure 4 As shown, in the third mode, the sub-analog-to-digital converter ADC1 continuously performs low-order bit conversion. Understandably, during this stage, the first capacitor C1 and the second capacitor C2 are passively sharing charge to achieve accurate sampling of the analog signal, while the sub-analog-to-digital converter ADC1 synchronously remains in the low-signal bit (LSB) segment conversion state. Their operation does not interfere with each other, allowing the second capacitor C2 to immediately obtain the complete quantization result after completing a short period of charge-sharing sampling, seamlessly transitioning to the residual amplification stage of the next operating cycle.

[0035] It is worth mentioning that, unless otherwise specified, in Figures 1 to 8In the diagram, the red lines represent the signal transmission paths that are active or conducting when the circuit is in the first mode (i.e., the input signal tracking and residual amplification stage), the blue lines represent the signal transmission paths that are active or conducting when the circuit is in the third mode (i.e., the charge sharing sampling and bootstrap stage), and the gray (or light-colored) lines represent the circuit branches that are disconnected or inactive under that specific operating phase.

[0036] This embodiment utilizes a parallel operation timing mechanism, enabling the signal tracking, high-bit conversion, and low-bit conversion processes of the sub-analog-to-digital converter ADC1 to achieve a high degree of time overlap with the independent tracking, reset, and charge-sharing sampling operations of the first capacitor C1. This shortens the single-cycle time of the analog-to-digital conversion and allows each functional module to have more sufficient setup and conversion time. Consequently, without increasing the overall circuit design complexity, the conversion rate and quantization accuracy of the pipelined analog-to-digital converter circuit 20 are improved.

[0037] In one embodiment, such as Figure 1 As shown, the mode switching circuit includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, and a sixth switch S6. The first switch S1 is connected in series between the signal input terminal Vin and the first terminal of the first capacitor C1; the second switch S2 is connected in series between the first common-mode voltage terminal and the first terminal of the first capacitor C1; the third switch S3 is connected in series between the first common-mode voltage terminal and the second terminal of the first capacitor C1; the fourth switch S4 is connected in series between the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2; the fifth switch S5 is connected in series between the reset voltage terminal VRS1 and the first terminal of the second capacitor C2; and the sixth switch S6 is connected in series between the input terminal of the sub-analog-to-digital converter ADC1 and the signal input terminal Vin.

[0038] Optionally, the mode switching circuit further includes a control module, which is connected to the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6, respectively. This control module can generate multi-phase timing control signals containing non-overlapping phases based on the system global clock signal to control the switching actions of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6.

[0039] In this embodiment, the front-end circuit 10 of the pipelined analog-to-digital converter is described from the input side to the rear side along the analog signal transmission path. At the frontmost signal input terminal Vin, the signal path is divided into two parallel branches, a first branch and a second branch. The first branch is directly connected to the input terminal of the sub-analog-to-digital converter ADC1 through the sixth switch S6, providing it with an independent sampling path. The second branch passes through the first switch S1 and connects to the first terminal (i.e., the input-side plate) of the first capacitor C1. The second terminal (i.e., the output-side plate) of the first capacitor C1 and the first terminal of the second capacitor C2 are connected at the same intermediate node. Before and after this intermediate node, the second switch S2 and the third switch S3 are respectively bridged between the first common-mode voltage terminal and the two ends of the first capacitor C1 to construct a charge reference and transfer circuit. Immediately after the intermediate node, the fourth switch S4 is connected in series between the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2. At the first terminal of the second capacitor C2, the fifth switch S5 is bypassed and connected to the reset voltage terminal VRS1. Finally, the second end of the second capacitor C2 continues to extend backward and is connected to the residual amplification circuit of the pipeline analog-to-digital converter 500.

[0040] like Figure 2 As shown, in the first mode, the mode switching circuit turns on the first switch S1, the third switch S3, and the sixth switch S6, while the second switch S2, the fourth switch S4, and the fifth switch S5 are off. Understandably, at this time, the signal input terminal Vin, the first switch S1, the first capacitor C1, and the third switch S3 form a complete signal tracking loop, causing the first capacitor C1 to be connected between the input signal and the first common-mode voltage, initiating charge charging and tracking. Simultaneously, the conduction of the sixth switch S6 enables the sub-analog-to-digital converter ADC1 to synchronously capture the input signal. Since the fourth switch S4 is off, the front-end tracking network and the rear-end second capacitor C2 are completely physically isolated. At this time, the second capacitor C2 independently cooperates with the pipelined analog-to-digital converter 500 to perform interference-free residual amplification.

[0041] like Figure 3As shown, in the second mode, the mode switching circuit turns on the second switch S2 and the fifth switch S5, while the first switch S1, the third switch S3, the fourth switch S4, and the sixth switch S6 are off. It is understood that the off-center switching of the first switch S1, the third switch S3, and the sixth switch S6 cuts off the input of the external signal source, allowing the first capacitor C1 and the sub-analog-to-digital converter ADC1 to complete the sampling operation and freeze the signal charge in the internal network. Subsequently, the second switch S2 turns on, clamping the first terminal potential of the first capacitor C1 to the first common-mode voltage, preparing the potential for subsequent charge transfer. Simultaneously, in the subsequent network, the conduction of the fifth switch S5 directly shorts the first terminal of the second capacitor C2 to the reset voltage terminal VRS1, forcibly clearing the residual charge of the second capacitor C2 from the previous residual amplification cycle. Throughout the second mode, the fourth switch S4 remains off, ensuring that the charge retention process of the first capacitor C1 and the reset process of the second capacitor C2 do not interfere with each other.

[0042] like Figure 4 As shown, in the third mode, the mode switching circuit turns on the second switch S2 and the fourth switch S4, while the first switch S1, the third switch S3, the fifth switch S5, and the sixth switch S6 are off. It is understandable that the opening of the fifth switch S5 indicates the end of the reset phase, and immediately the fourth switch S4 turns on, opening the charge transfer path between the first capacitor C1 and the second capacitor C2. Since the first terminal of the first capacitor C1 is still clamped to the first common-mode voltage by the second switch S2, the signal charge held at the second terminal of the first capacitor C1 will naturally redistribute to the first terminal of the now-zeroed second capacitor C2; this is the passive charge-sharing sampling process. During this period, the sixth switch S6 remains off, allowing the sub-analog-to-digital converter ADC1 to continue performing its internal low-order quantization conversion without interfering with the charge-sharing process. Figure 4 In This is the first common-mode voltage terminal (i.e., the input common-mode voltage). In the charge-sharing sampling circuit, this... Its main function is to provide a stable, low-impedance DC reference potential for the relevant capacitor plates (such as the first terminal of the first capacitor C1).

[0043] In this embodiment, this application constructs a highly flexible charge routing network with physical isolation characteristics using six switches. The control module implements precise multi-phase timing control on these six switches, perfectly realizing the cyclic switching between the tracking, reset, and charge sharing states, and eliminating charge leakage and signal crosstalk between capacitors operating in different phases from the hardware level. Thus, by utilizing the idle time of each capacitor, reliable physical support is provided for the high-speed parallel operation of the entire pipeline analog-to-digital converter circuit 20.

[0044] In one embodiment, the capacitance of the second capacitor C2 is less than that of the first capacitor C1. It is understood that during the charge-sharing phase of the third mode, the final established node voltage depends on the capacitance ratio of the first capacitor C1 to the second capacitor C2. Designing the size of the second capacitor C2 (i.e., the actual sampling capacitor) to be smaller than, or even much smaller than, the first capacitor C1 (i.e., the tracking capacitor) maximizes the signal attenuation factor during charge sharing, bringing it as close to 1 as possible. This not only overcomes the severe input attenuation problem caused by charge redistribution in traditional passive charge-sharing architectures but also significantly improves signal transfer efficiency.

[0045] In this embodiment, during the transition from the first mode to the second mode, the mode switching circuit is configured to sequentially disconnect the third switch S3 and the first switch S1. It is understood that this timing sequence constitutes an improved bottom-plate sampling mechanism. Since the third switch S3 is connected to a constant first common-mode voltage terminal, when it is disconnected early, the reverse layer channel charge injected onto the plate of the first capacitor C1 is a constant value independent of the input signal. Subsequently, when the first switch S1, connected to the signal input terminal Vin, is disconnected, the nonlinear injected charge related to the input signal generated by the disconnection of the first switch S1 cannot enter the first capacitor C1 because the circuit of the first capacitor C1 has been cut off by the third switch S3. This specific switch-off timing effectively isolates input-dependent distortion from the physical path, ensuring extremely high linearity of the charge captured by the first capacitor C1.

[0046] It is important to note that if a smaller second capacitor C2 is used to improve transfer efficiency, once the first capacitor C1 is contaminated by nonlinear charge injection at the moment of sampling disconnection, the error signal will be amplified without attenuation and transmitted to the subsequent quantization circuit, leading to a deterioration in the overall linearity of the system. Conversely, if the bottom plate sampling timing ensures the purity of the charge, but the size of the second capacitor C2 is too large, severe signal attenuation will still occur during charge sharing, reducing the signal-to-noise ratio. Therefore, this embodiment captures high-fidelity linear signal charge from the source by sequentially disconnecting the third and first switches S1, and uses the smaller second capacitor C2 as a medium to ensure that this high-fidelity charge can be transferred efficiently and with low loss to the downstream pipelined analog-to-digital converter 500. The two complement each other, jointly achieving high linearity and high conversion efficiency. It is understandable that in the charge sharing stage of the third mode, the final node voltage depends on the capacitance ratio of the first capacitor C1 to the second capacitor C2. Ignoring the effects of parasitic capacitance, the voltage at the charge-sharing sampling node (located at the intermediate node between the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2) Satisfy the following formula:

[0047] in, The capacitance value of the first capacitor C1. The capacitance value of the second capacitor C2 is... For input common-mode voltage, The input signal voltage. Reset voltage (i.e., corresponding to) Figures 1 to 4 (Voltage of VRS1 and VRS2 in the middle). It is the attenuation factor and .

[0048] As can be seen from the derivation of the above formula, the voltage of the charge-sharing sampling node... It consists of two parts: one part has an attenuation factor Linear input differential components (i.e.) The other part is the common-mode voltage of the input. and reset voltage The relevant common-mode components. The size of the second capacitor C2 (i.e., the actual sampling capacitor) is designed to be smaller than, or even much smaller than, the first capacitor C1 (i.e., the tracking capacitor), so that the attenuation factor in the formula... It approaches 1 to the greatest extent possible. This design not only overcomes the significant input attenuation problem caused by charge redistribution in traditional passive charge-sharing architectures, but also shortens signal acquisition time and reduces the driving burden at the signal input, thereby improving signal transfer efficiency.

[0049] In this embodiment, by sequentially disconnecting the bottom plate sampling mechanism of the third switch S3 and the first switch S1 during the transition from the first mode to the second mode, the nonlinear layer channel charge injection related to the input signal is completely isolated from the physical path, improving the linear fidelity of the charge captured by the first capacitor C1. Furthermore, by designing the capacitance value of the second capacitor C2 to be smaller than or even much smaller than that of the first capacitor C1, passive charge sharing is achieved using an attenuation factor approaching 1. This not only effectively improves the inherent defects of severe input signal attenuation and decreased signal-to-noise ratio in traditional charge-sharing architectures, but also shortens the data acquisition time and reduces the slew rate and bandwidth pressure on the front-end input driver amplifier.

[0050] In one embodiment, such as Figures 1 to 4 As shown, the pipelined analog-to-digital converter front-end circuit 10 also includes a noise cancellation unit, which includes an auto-zero capacitor C3 connected in series between the amplification stages inside the pipelined analog-to-digital converter 500; the mode switching circuit also includes a seventh switch S7, which is connected in series between the second terminal of the second capacitor C2 and the second reset voltage terminal VRS2; during the transition phase from the third mode to the first mode, the mode switching circuit disconnects the seventh switch S7 so that the thermal noise generated by the charge-sharing sampling stage is transferred to the bottom plate of the auto-zero capacitor C3.

[0051] The noise cancellation unit achieves the cancellation of kT / C thermal noise through a five-stage quantized charge distribution and cancellation mechanism: The first stage is the tracking completion stage: When the third switch is opened in the first mode to end the input tracking of the first capacitor, a first kT / C thermal noise is introduced. The thermal noise in this stage satisfies the following formula: in, Let be the noise power of the first kT / C thermal noise, where k is the Boltzmann constant and T is the absolute temperature. Let be the capacitance value of the first capacitor. This formula shows that, because the capacitance value of the first capacitor is designed to be large, the noise power of the first kT / C thermal noise introduced across its terminals is significantly suppressed by the impedance stage; at the same time, the input bias voltage of the internal amplification stage of the pipelined analog-to-digital converter is amplified and stored as a reference on the bottom plate of the auto-zero capacitor.

[0052] The second stage is the reset completion stage: In the second mode, the charge of the second capacitor is reset to zero by turning on the fifth switch. At the instant the fifth switch is turned off, the second kT / C thermal noise is introduced to the first terminal of the second capacitor. The second kT / C thermal noise in this stage satisfies the following formula. in, The noise power of the second kT / C thermal noise. This is the capacitance value of the second capacitor.

[0053] The third stage is the charge-sharing sampling stage: In the third mode, the fourth switch is turned on, and the first capacitor and the second capacitor perform charge sharing. The noise charge captured by both is redistributed at the charge-sharing sampling node. At this time, the third kT / C thermal noise observed at the intermediate node is equivalent to the thermal noise of the first capacitor and the second capacitor connected in parallel. The third kT / C thermal noise in this stage satisfies the following formula: ,in This represents the noise power of the third kT / C thermal noise. This formula demonstrates that because the capacitance of the second capacitor is much smaller than that of the first capacitor, the noise power of the third kT / C thermal noise is extremely close to that of the aforementioned first kT / C thermal noise, and can still be maintained at an extremely low level.

[0054] The fourth stage is the switch-off and noise transmission stage: During the transition from the third mode to the first mode, the seventh switch is turned off. At this time, the fourth kT / C thermal noise observed at the second terminal of the second capacitor is amplified by the loop and directly transmitted and frozen to the bottom plate of the auto-zero capacitor. This fourth kT / C thermal noise is generated by the first capacitor and the second capacitor connected in series, as well as the feedback capacitor of the internal amplification stage of the pipeline analog-to-digital converter, satisfying the following formula: in, The noise power of the fourth kT / C thermal noise. This refers to the capacitance value of the feedback capacitor in the internal amplification stage of the pipelined analog-to-digital converter.

[0055] The fifth stage is the residual amplification and noise cancellation stage: When switching back to the first mode to activate residual amplification, the zero-reset switch is turned on, thereby physically clamping the top plate of the auto-zero capacitor to the common-mode reference voltage terminal; due to the high open-loop gain of the internal amplification stage (i.e., its second-stage amplifier) ​​of the pipelined analog-to-digital converter, the voltage of the top plate of the auto-zero capacitor is forced to zero, which causes the fourth kT / C thermal noise previously stored on the bottom plate of the auto-zero capacitor to be automatically canceled in the charge transfer path. Finally, the thermal noise transmitted to the amplified residual signal satisfies the following formula: in, To amplify the thermal noise equivalent voltage of the residual signal, For effective sampling capacitor (i.e., the second capacitor in this embodiment) ), The equivalent voltage of the third kT / C thermal noise. Residual thermal noise voltage introduced for amplifier auto-zeroing. This is the open-loop gain of the first stage amplifier within the pipelined analog-to-digital converter's internal amplification stage. From this formula, it can be intuitively seen that the fourth kT / C thermal noise generated and frozen in the previous stage has been canceled out by the equation. Ultimately, the thermal noise that truly participates in residual signal amplification and manifests in the system consists only of the extremely low-power third kT / C thermal noise. And the slight thermal noise introduced by the automatic zeroing capacitor itself. This fundamentally eliminates most of the thermal noise components generated by charge sharing and the reset stage.

[0056] Furthermore, since the second terminal of the second capacitor C2 becomes passively static after the seventh switch S7 is opened, this greatly relaxes the stringent constraints on the auto-zero bandwidth of the residual amplifier inside the pipelined analog-to-digital converter 500. This relaxation of bandwidth constraints allows for a further increase in the physical size of the auto-zero capacitor C3, thereby significantly reducing the thermal noise floor of the auto-zero capacitor C3 itself and more effectively filtering out broadband noise generated by other circuit modules in the noise cancellation path.

[0057] In this embodiment, by precisely coordinating the multi-phase switching timing with the auto-zero capacitor C3 positioned between amplification stages, the key thermal noise generated by charge-sharing sampling and reset operations is successfully captured, amplified, and frozen in the time domain. The loop feedback gain of the residual amplification stage is cleverly utilized to physically cancel this noise. This mechanism breaks through the physical bottleneck of traditional sampling circuits limited by kT / C thermal noise, achieving an ultra-low thermal noise floor without strictly limiting the input signal frequency and amplitude or requiring extremely high residual amplifier zero-zero bandwidth. Simultaneously, by relaxing the amplifier's bandwidth constraints, a larger auto-zero capacitor C3 can be used, providing superior broadband noise filtering performance and significantly improving the overall signal-to-noise ratio and dynamic range of the pipelined analog-to-digital converter circuit 20.

[0058] In one embodiment, such as Figures 1 to 4 As shown, the pipelined analog-to-digital converter 500 also includes a zero-reset switch S8. The top plate of the auto-zero capacitor C3 is connected to the common-mode reference voltage terminal through the zero-reset switch S8, and the bottom plate of the auto-zero capacitor C3 is connected in series in the signal path of the amplifier stage. In the first mode, the mode switching circuit opens the seventh switch S7 and controls the zero-reset switch S8 to turn on, so as to physically clamp the top plate of the auto-zero capacitor C3 to the common-mode reference voltage terminal.

[0059] In the first mode (i.e., the tracking and residual amplification stage), the entire circuit needs to perform input signal tracking for the current cycle and residual amplification and automatic zero-reset calibration for the previous sampling cycle in parallel. At this time, the seventh switch S7 is open, physically cutting off the connection path between the second terminal of the second capacitor C2 and the second reset voltage terminal VRS2, thereby completely isolating the reset potential and preventing it from causing crosstalk to the analog signal transmission in the subsequent amplification circuit, ensuring the integrity and purity of the residual amplification path.

[0060] Meanwhile, the mode switching circuit keeps the zero-reset switch S8 on, thereby physically clamping the top plate of the auto-zero capacitor C3 to a constant common-mode reference voltage. Since the bottom plate of the auto-zero capacitor C3 is connected in series in the signal path of the amplification stage (e.g., in series in the inter-stage signal path of a multi-stage residual amplifier), when the top plate is locked at the fixed common-mode reference voltage, the input bias voltage of the amplification stage inside the pipelined analog-to-digital converter 500 will be amplified by the preceding stage and precisely stored as charge on the bottom plate of the auto-zero capacitor C3. This physical clamping and charge capture operation operates completely independently of the input signal tracking process of the first capacitor C1 in the time domain, without interfering with each other. When the first mode ends and the switch to a subsequent mode begins, the zero-reset switch S8 opens, thereby safely freezing the captured input bias voltage charge in the auto-zero capacitor C3, providing a prerequisite for the subsequent inter-stage residual amplification stage to physically cancel this bias voltage using the amplifier's high open-loop gain.

[0061] In this embodiment, by utilizing the mode switching circuit to control the disconnection of the seventh switch S7 and the conduction of the zero-reset switch S8 in the first mode, complete physical isolation between the residual amplification path and the reset path is achieved, effectively preventing the decrease in interstage amplification accuracy caused by residual reset voltage or charge crosstalk. Simultaneously, by physically clamping the top plate of the auto-zero capacitor C3 to the common-mode reference voltage terminal, a high-fidelity voltage capture and static charge storage reference is constructed. This allows the input bias voltage of the residual amplifier to be frozen in parallel and precisely in the auto-zero capacitor C3 without occupying additional clock cycles, significantly improving the timing utilization and quantization accuracy of bias calibration. Furthermore, this physical clamping action provides a stable, low-impedance DC balanced operating point for the entire interstage amplification network, effectively suppressing common-mode potential transient disturbances during high-speed multi-phase switching, further ensuring the overall dynamic stability and conversion robustness of the pipelined analog-to-digital converter circuit 20.

[0062] In one embodiment, such as Figures 5 to 8 As shown, the front-end circuit 10 of the pipelined analog-to-digital converter also includes a substrate tracking circuit; the substrate tracking circuit includes a substrate tracking bootstrap circuit, a first tracking capacitor C4 and a second tracking capacitor C5, the ratio of the capacitance value of the first tracking capacitor C4 to the capacitance value of the first capacitor C1 is equal to the ratio of the capacitance value of the second tracking capacitor C5 to the capacitance value of the second capacitor C2; the bottom plate of the first tracking capacitor C4 is selectively connected to the signal input terminal Vin through a switching network, and the top plate is connected to the input terminal of the substrate tracking bootstrap circuit; the bottom plate of the second tracking capacitor C5 is selectively connected to the first common-mode voltage terminal through a switching network, and the top plate is connected to the input terminal of the substrate tracking bootstrap circuit.

[0063] Since the ratio of the first tracking capacitor C4 to the first capacitor C1 is exactly equal to the ratio of the second tracking capacitor C5 to the second capacitor C2, the first tracking capacitor C4 and the second tracking capacitor C5 essentially constitute a proportionally replicated network with electrical characteristics completely identical to those of the main charge-sharing sampling network (i.e., the network composed of the first capacitor C1 and the second capacitor C2). In the first mode (tracking stage), the bottom plate of the first tracking capacitor C4 is connected to the input signal through a switching network, and the bottom plate of the second tracking capacitor C5 is connected to the first common-mode voltage, thereby capturing signal charges that are precisely proportional to those of the main network on the plates of the replicated network. When the circuit enters the third mode (charge-sharing sampling stage), since the redistribution law of the charge is completely consistent with that of the main network, the replicated network can perfectly simulate and reproduce the transient voltage change trajectory of the main charge-sharing sampling node at its top plate without adding extra driving burden to the main signal path or diverting the actual signal charge of the main node. This provides a high-fidelity dynamic tracking reference that is synchronized with the main node voltage in real time for the substrate tracking bootstrap circuit.

[0064] In terms of topological connections, such as Figure 5 and Figure 6 As shown, the bottom plate of the first tracking capacitor C4 is selectively connected to the signal input terminal Vin through the first switch S1 network, and its top plate is connected to the input terminal of the substrate tracking bootstrap circuit; the bottom plate of the second tracking capacitor C5 is selectively connected to the first common-mode voltage terminal through the second switch S2 network, and its top plate is also connected to the input terminal of the substrate tracking bootstrap circuit. In specific multi-phase timing operation, when the circuit is in the first mode (tracking stage), the first switch S1 network is turned on so that the bottom plate of the first tracking capacitor C4 tracks the external input signal voltage in real time, and the second switch S2 network is turned on so that the bottom plate of the second tracking capacitor C5 is stably connected across the constant first common-mode voltage terminal. At this time, the substrate terminal of the fourth switch S4 is clamped to a fixed low-level voltage terminal through the substrate tracking bootstrap circuit. When the circuit enters the third mode (charge sharing sampling stage), both the first switch S1 network and the second switch S2 network are disconnected from the physical connection with the external voltage terminal. At this time, since the top plates of the first tracking capacitor C4 and the second tracking capacitor C5 converge at the input terminal of the substrate tracking bootstrap circuit, by utilizing the physical mechanism of charge redistribution at both ends of the replica network, a dynamic tracking voltage that fluctuates in real time and synchronously with the voltage of the main charge sharing sampling node will be generated at the top plate node. Thus, without intruding on or diverting the charge of the main signal path, a high-fidelity dynamic input trajectory is provided for the subsequent bootstrap control loop.

[0065] like Figure 5 and Figure 6The figures shown are schematic diagrams illustrating the topology and working principle of the substrate tracking circuit provided in the embodiments of this application during the tracking stage (i.e., the first mode) and the charge-sharing sampling stage (i.e., the third mode). Figure 5 In the tracking phase shown (the red highlighted path in the figure is in the on state), the proportionally replicated network composed of the first tracking capacitor C4 and the second tracking capacitor C5 has its bottom plate connected to the signal input terminal Vin and the first common-mode voltage terminal VCMI respectively through an on switch for signal tracking. At the same time, the top plates of both are pre-charged to the top plate bias voltage. During this period, the substrate terminal of the fourth switch S4 is safety clamped to a fixed low-level bias terminal to prevent breakdown. When the circuit switches to such... Figure 6 During the charge-sharing sampling phase shown (the blue highlighted path in the diagram is in the on state), the fourth switch S4 in the main circuit is turned on, and the etched network is disconnected from the external input signal. At this time, the bottom plates of the first tracking capacitor C4 and the second tracking capacitor C5 are jointly connected to the bottom plate bias voltage. The top plates of both are connected to the substrate of the fourth switch S4. Since the replica network and the main network (i.e., C1 and C2) maintain a strict proportional mapping in electrical characteristics, during the internal charge redistribution process, the top plate of the replica network can reproduce the dynamic voltage trajectory of the main circuit charge sharing node (i.e., the drain of the fourth switch S4) without damage and with high accuracy. This dynamic following voltage, combined with a preset bias network, is applied to the substrate of the fourth switch S4 in real time, thereby forcibly locking the drain-substrate voltage difference of the switch to a constant value, completely eliminating the nonlinear distortion caused by the parasitic capacitance of the PN junction fluctuating with the signal from the bottom layer of the physical topology.

[0066] In this embodiment, by utilizing a replicated capacitor network with a strictly proportional mapping relationship, lossless and high-precision tracking of the voltage trajectory of the main charge sharing node is achieved at the cost of minimal chip area and power consumption.

[0067] In one embodiment, such as Figure 7 and Figure 8 As shown, the substrate tracking bootstrap circuit includes a bias capacitor and a bootstrap switch group; in the first mode or the second mode, the bootstrap switch group is configured to conduct the charging path between the bias capacitor and the preset bias voltage terminal so that the bias capacitor stores the preset voltage difference; in the third mode, the bootstrap switch group is configured to disconnect the charging path and conduct the connection path between the bias capacitor connected in series with the top plate of the first tracking capacitor C4 and the substrate terminal of the fourth switch S4.

[0068] It is understandable that when the fourth switch S4 is turned on to perform charge-sharing sampling, the parasitic capacitance of the PN junction between its drain and the substrate will fluctuate nonlinearly with the change of the drain voltage (i.e., the node voltage modulated by the input signal), thereby degrading the sampling linearity of the system. This embodiment effectively overcomes this physical limitation by using a substrate tracking bootstrap circuit.

[0069] Its working mechanism is as follows: During the preparation period of the first or second mode (i.e., the tracking or reset phase), the bootstrap switch group charges the bias capacitor by connecting it to the preset bias voltage terminal, so that the two plates of the capacitor establish and store a constant DC preset voltage difference (e.g., denoted as ). When the circuit switches to the third mode (charge sharing sampling stage), the fourth switch S4 is turned on, and at the same time, the bootstrap switch group cuts off the charging circuit of the bias capacitor and places the bias capacitor between the replica network (the top plate of the first tracking capacitor C4) and the substrate end of the fourth switch S4.

[0070] In this connection state, since the voltage of the top plate of the replica network changes synchronously with the drain voltage of the master node, plus the constant preset voltage difference provided by the bias capacitor... This ensures that the voltage applied to the substrate of the fourth switch S4 always fluctuates strictly in the same direction and with the same amplitude as the fluctuations of its drain voltage. In other words, the drain-substrate voltage difference of the fourth switch S4... It is dynamically and forcibly locked to a constant value (i.e., the preset voltage drop). Based on the physical properties of semiconductors, a constant junction voltage drop means a constant depletion layer width, thereby completely solidifying the parasitic capacitance of the PN junction, which originally fluctuated wildly with the signal, into an extremely small constant.

[0071] In the timing loop control, in the first or second mode, the bootstrap switch group is configured to control the charging path between the bias capacitor and the preset bias voltage terminal. Specifically, the charging switch controls the first plate (top plate) of the bias capacitor to be connected to the high-level power supply terminal, and the second plate (bottom plate) to be connected to the ground level terminal, so that the bias capacitor is charged and frozen to a constant DC preset voltage difference before entering charge sharing. During this period, the substrate terminal of the fourth switch S4 is directly and physically connected to the fixed low-level common-mode bias terminal through the corresponding clamping switch to prevent the switching transistor from undergoing unexpected substrate breakdown at the moment of circuit switching. When the circuit enters the third mode (charge sharing sampling stage), the bootstrap switch group is configured to completely disconnect the above charging path and clamping path, so that the bias capacitor is in a floating bootstrap state, and simultaneously conduct the bootstrap connection path between the top plate of the first tracking capacitor C4 and the substrate terminal of the fourth switch S4. Specifically, the first plate of the bias capacitor is short-circuited with the top plate of the first tracking capacitor C4, and the second plate of the bias capacitor is short-circuited with the substrate terminal of the fourth switch S4. Because the voltage difference across the bias capacitor has the physical characteristic that it cannot change abruptly, the constant DC preset voltage difference stored inside it will be dynamically superimposed on the transient voltage of the top plate of the first tracking capacitor C4. This allows the voltage applied to the substrate of the fourth switch S4 to always strictly and in real time follow its drain voltage to fluctuate in the same direction and with the same amplitude, forcibly maintaining its drain-substrate voltage difference constant. This completely suppresses the nonlinear change of the parasitic capacitance of the PN junction, thereby ensuring the ultra-high sampling linearity of the pipeline analog-to-digital conversion circuit 20 as a whole.

[0072] In practical topologies, such as Figure 7 and Figure 8 As shown, in the timing loop control of the substrate tracking bootstrap circuit, To control the master control clock signal of the aforementioned second switch S2 (or its corresponding timing phase), To be consistent with the above A clock signal with strictly opposite phase (i.e., a complementary control signal). This is due to some analog switches in the bootstrap switch group (such as those used to control bias capacitors). In actual CMOS processes, the switching transistors in the charging path need to be implemented using full-transmission gates or transistors of specific conductivity types (such as NMOS or PMOS), thus introducing transistors with opposite phases. and It can ensure that the relevant switching transistors achieve synchronous, highly reliable on or off operation within the same operating phase.

[0073] like Figure 7 The diagram shown is a schematic representation of the transistor-level circuit state of the substrate tracking bootstrap circuit provided in this application embodiment during the tracking phase (i.e., the preparation period corresponding to the first or second mode described above). Figure 7The bold red lines visually represent the circuit loops that are in the conducting state during this stage. During this stage, the circuit is affected by relevant multi-phase clock signals (such as...). Under the control of (etc.), the charging network in the bootstrap switch group is turned on, causing the bias capacitor to... The upper plate is connected to a high-level power supply. The lower electrode plate is connected to the ground level terminal. Thus in Establish and store the preset DC bias voltage difference at both ends ( Simultaneously, the first tracking capacitor in the replicated network... (i.e., the first tracking capacitor C4 mentioned above) and the second tracking capacitor The bottom plates are connected to the input signal via conductive switches. and the first common-mode voltage This replicates the tracking state of the main circuit. Furthermore, the substrate end of the fourth switch S4... The clamping switch network is directly connected to a fixed low-level common-mode bias terminal. (Its voltage value is) This provides a safe initial static operating point for subsequent voltage bootstrapping, preventing substrate breakdown during mode switching.

[0074] like Figure 8 The diagram shows the transistor-level circuit state of the substrate tracking bootstrap circuit during the charge-sharing sampling phase (corresponding to the third mode described above). The bold blue lines in the diagram represent the bootstrap operating loop in the on-state during this phase. When the circuit switches to this mode, the corresponding control clock signal flips. Figure 7 The red charging and clamping circuit in the middle is completely cut off, and the bias capacitor is... It then enters a hovering state. Immediately afterwards, it is controlled by a bootstrap switch (such as...). The blue connected path controlled by (etc.) is turned on, connecting the floating bias capacitor. The top plate connected in series with the replica network (i.e. and (the common connection terminal) and the substrate terminal of the fourth switch S4 In this state, the top plate of the replicated network generates a transient voltage that follows the drain fluctuation of the master node due to internal charge sharing (as shown in the figure). ,in (for attenuation factor); due to the floating bias capacitor The internally stored DC voltage difference cannot change abruptly; this preset voltage difference is losslessly superimposed, resulting in the final output to the substrate. The bias voltage is dynamically bootstrapping to Through this precise dynamic level shifting, the substrate voltage of the fourth switch S4 perfectly follows the trajectory of its drain voltage, thereby realizing the technical effect of completely eliminating parasitic capacitance nonlinear fluctuations from the underlying hardware path.

[0075] In this embodiment, the substrate tracking circuit utilizes a scaled-down replica capacitor network for lossless voltage trajectory tracking and combines it with a bootstrap circuit to construct a dynamic constant-voltage bias loop. This structure eliminates the nonlinear variation of the switching parasitic capacitance Cj at the charge-sharing sampling node from the underlying physical mechanism, avoiding nonlinear attenuation of the differential-mode signal and instability of the common-mode operating point. Without the need for complex digital backend calibration, it achieves ultra-high sampling linearity and signal-to-noise ratio of the analog-to-digital converter circuit under high-frequency, large-signal input with extremely low hardware and power consumption.

[0076] It is worth noting that, from the perspective of physical structure and semiconductor manufacturing process, the bottom electrode plate generally refers to the conductive electrode plate (such as the bottom metal layer or polysilicon layer) that is physically closer to the semiconductor substrate in the vertical stack-up structure of the integrated circuit layout, and its parasitic capacitance with the substrate is relatively large; the top electrode plate refers to the conductive electrode plate that is relatively far from the substrate in the vertical structure, and its parasitic capacitance with the substrate is relatively small. From the perspective of circuit function and topology connection, based on the above-mentioned asymmetrical parasitic capacitance physical characteristics, in order to minimize the nonlinear interference and signal attenuation of parasitic capacitance on critical signal nodes (such as the input terminal of the residual amplifier, charge sharing nodes, and other high impedance sensitive nodes) during circuit network design, this application typically connects the top electrode plate with smaller parasitic capacitance to such sensitive nodes; while connecting the bottom electrode plate with larger parasitic capacitance to low impedance driving nodes (such as the external signal input terminal Vin, the reset voltage terminal VRS1, the common mode reference voltage terminal, etc.).

[0077] In summary, the pipelined analog-to-digital converter front-end circuit 10 disclosed in this application includes a charge-shared sampling stage circuit, a sub-analog-to-digital converter (ADC1) circuit, a residual amplifier circuit, and a substrate tracking circuit. The charge-shared sampling stage circuit includes a first capacitor C1, a second capacitor C2, and a mode switching circuit. The second terminal of the second capacitor C2 is used to connect to the input terminal of a pipelined analog-to-digital converter 500. The mode switching circuit connects to the signal input terminal Vin, the reset voltage terminal VRS1, the second terminal of the first capacitor C1, and the first terminal of the second capacitor C2. In the first mode, the first capacitor C1, the sub-analog-to-digital converter circuit, and the substrate tracking circuit track the input signal, while the second capacitor C2, in conjunction with the residual amplifier circuit, performs residual amplification. In the second mode, the first capacitor C1 and the substrate tracking circuit maintain the charge of the tracked signal, the path between the second capacitor C2 and the reset voltage terminal VRS1 is opened to clear the charge of the second capacitor C2, the sub-analog-to-digital converter circuit begins to perform analog-to-digital conversion on the tracked signal, and the residual amplifier stores the input offset. In the third mode, the mode switching circuit performs charge-sharing sampling with the first capacitor C1 and the second capacitor C2, the substrate tracking circuit modulates the parasitic capacitance of the charge-sharing sampling node, the sub-analog-to-digital converter circuit remains in the conversion state, and the residual amplifier performs kT / C noise cancellation. The pipelined analog-to-digital converter front-end circuit 10 disclosed in this application aims to improve the conversion efficiency of the pipelined analog-to-digital converter circuit 20 while ensuring high-precision and low-noise sampling and residual amplification.

[0078] To verify the effectiveness and technical advantages of the proposed charge-sharing sampling front-end circuit and pipelined analog-to-digital converter circuit, simulation tests were conducted, as follows: The proposed circuit has been implemented and verified in a 180nm CMOS process. It is powered by 1.8V and 5V, with a differential input voltage of 8.8Vpp and a sampling rate of 20MSPS. In terms of core circuit parameter configuration, the first capacitor (i.e., the tracking capacitor) is designed with a capacitance of 20pF, and the second capacitor is designed with a capacitance of 2.028pF.

[0079] like Figures 9 to 12 As shown, "W / STT" indicates the circuit test results using the substrate tracking technique described in this application, and "W / o STT" indicates the control circuit test results without the substrate tracking technique.

[0080] like Figure 9 and Figure 10As shown, the simulation results comparing the signal-to-noise ratio (SNDR) and spurious-free dynamic range (SFDR) of circuits employing the substrate tracking technology (W / STT) described in this application and those without (W / oSTT) are presented, respectively, as a function of a preset voltage drop (ΔVST). Considering the substrate breakdown effect of semiconductor devices in actual circuits, the design range of the preset voltage drop ΔVST is limited to less than or equal to 2.5V. The intuitive curve comparison shows that, under a ΔVST condition of 2.5V, the circuit employing the technology of this application achieves a high SNDR of 98.6dB and a high SFDR of 107.2dBc; compared to the control group without substrate tracking technology, its SNDR is significantly improved by 4dB, and its SFDR is significantly improved by 12dB, fully demonstrating the superior effect of this technology in suppressing parasitic capacitance nonlinearity and improving sampling linearity.

[0081] like Figure 11 and Figure 12 As shown, the simulation curves compare the SNDR and SFDR performance of circuits employing and without substrate tracking technology as the input signal frequency fluctuates. The simulation curves clearly demonstrate that as the input signal frequency gradually increases and approaches the Nyquist frequency, the circuit employing the substrate tracking technology of this application maintains extremely high performance stability, with its SNDR and SFDR remaining consistently at high levels of 95.5 dB and 99.1 dBc, respectively. In contrast, the conventional circuit without substrate tracking technology exhibits rapid and severe deterioration in its SNDR and SFDR under the same high-frequency input conditions. This further highlights the broadband distortion suppression advantage of the circuit in this application under high-frequency, large-signal input environments.

[0082] like Figure 13 and Figure 14 As shown, the simulation results of the pipelined analog-to-digital converter circuit provided in this application under extreme operating conditions of SNDR and SFDR under process, voltage, and temperature (PVT) fluctuations are presented at a preset voltage drop (ΔVST) of 2.5V and an input frequency of 1.1MHz. To verify the reliability of the circuit under different physical environments and manufacturing deviations, the simulation covers a variety of extreme PVT combinations. The simulation results show that even under the most severe operating conditions, the SNDR of the circuit in this application can still reach 93.3dB, and the SFDR can still reach 97.5dBc, demonstrating a strong resistance to manufacturing process deviations and drastic fluctuations in ambient temperature.

[0083] like Figure 15 and Figure 16As shown, the Monte Carlo statistical simulation results of SNDR and SFDR for the circuit of this application under the same test conditions are presented in histograms. Statistical analysis of a large number of random sampling points shows that the SNDR of this circuit remains stable above 95.5 dB and the SFDR remains stable above 106.5 dBc at all Monte Carlo simulation sampling points. This highly concentrated normal distribution result demonstrates that the charge-sharing sampling front-end circuit and substrate tracking mechanism proposed in this application not only have excellent theoretical performance but also exhibit extremely high yield and strong system robustness in actual mass production.

[0084] This application also provides a pipelined analog-to-digital converter (ADC) circuit 20, which includes the pipelined ADC front-end circuit 10 as described above. It should be noted that the specific embodiment of the pipelined ADC front-end circuit 10 is described above. Since this pipelined ADC circuit 20 adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought about by the technical solutions of the above embodiments.

[0085] In one embodiment of this application, the pipelined analog-to-digital converter circuit 20 includes multiple pipelined analog-to-digital converters (ADCs) and multiple pipelined ADC front-end circuits 10. In two adjacent pipelined ADCs 500, the output terminal of the preceding pipelined ADC 500 is connected to the signal input terminal Vin of the pipelined ADC front-end circuit 10, and the input terminal of the following pipelined ADC 500 is connected to the second terminal of the second capacitor C2 of the pipelined ADC front-end circuit 10.

[0086] When multiple pipelines work together, the pipelined analog-to-digital converter (ADC) front-end circuit 10 essentially acts as the load network between pipeline stages and the sampling network for the next stage. Thanks to the aforementioned parallel operation timing mechanism (i.e., the mode switching circuit switches between the first and third modes), when the current stage pipelined ADC 500 is in the residual amplification stage and outputs the residual signal, the current stage pipelined ADC front-end circuit 10 connected to its output is in the first mode (tracking stage), using its first capacitor C1 to independently track the residual signal; while when the current stage pipelined ADC front-end circuit 10 enters the third mode (charge-sharing sampling stage), it not only efficiently completes the high-precision signal acquisition with extremely low attenuation, but also seamlessly connects to the quantization and amplification cycle of the next pipelined ADC 500. This deep integration of cascaded topology and multi-phase parallel timing breaks the time bottleneck in traditional pipelined analog-to-digital converters 500, where the pre-amplifier and post-sampler stages must wait sequentially. This allows the circuit modules at each stage to overlap and operate synchronously, thereby achieving a significant leap in overall conversion rate at the system level.

[0087] Optionally, for the first-stage module in a multi-stage cascaded architecture, its first pipelined analog-to-digital converter front-end circuit 10 has its signal input terminal Vin directly connected to an external analog signal input source of the system (or connected to an external analog signal source via a pre-input buffer) to receive the raw analog voltage signal to be converted. This first-stage front-end circuit captures high-fidelity raw signal charge from the source using its internal bottom-plane sampling timing and substrate tracking technology, and transfers it to the first-stage pipelined analog-to-digital converter 500 with low loss using a small second capacitor C2 as a medium. Subsequently, each stage module completes quantization and residual amplification operations from high to low bits step by step through the aforementioned inter-stage transfer mechanism, and finally, the digital error correction and alignment logic circuits combine to output a complete high-resolution digital signal.

[0088] This application also provides a communication device, which includes a pipelined analog-to-digital converter front-end circuit 10 or a pipelined analog-to-digital converter circuit 20. It should be noted that the specific embodiments of the pipelined analog-to-digital converter front-end circuit 10 and the pipelined analog-to-digital converter circuit 20 are described above. Since this communication device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments.

[0089] The communication device can be any electronic device with wireless or wired signal transmission and reception capabilities, including but not limited to: cellular network base stations (such as macro base stations, micro base stations or pico base stations), mobile network terminals (such as smartphones, tablets or IoT nodes), wireless local area network access points (such as Wi-Fi routers), radar receiving systems, satellite communication earth station terminals, and software-defined radio (SDR) devices.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no technical conflict, the various technical features mentioned in the various embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A front-end circuit for a pipelined analog-to-digital converter, characterized in that, The pipelined analog-to-digital converter has a charge-shared sampling stage circuit at its front end and is applied to the pipelined analog-to-digital converter circuit. The pipelined analog-to-digital converter circuit includes a pipelined analog-to-digital converter, and the charge-shared sampling stage circuit includes: A first capacitor having a first terminal and a second terminal, the first capacitor being used for input signal tracking through its first terminal; A second capacitor has a first terminal and a second terminal, the second terminal of which is used to connect to the input terminal of the pipelined analog-to-digital converter. A mode switching circuit is connected to a signal input terminal, a reset voltage terminal, a second terminal of the first capacitor, and a first terminal of the second capacitor. The mode switching circuit is configured to switch between a first mode, a second mode, and a third mode. In the first mode, the path between the second terminal of the first capacitor and the first terminal of the second capacitor is disconnected, and the path between the signal input terminal and the first terminal of the first capacitor is connected, so that the first capacitor performs input signal tracking, and the second capacitor performs residual amplification with the connected pipeline analog-to-digital converter. In the second mode, the path between the second terminal of the first capacitor and the first terminal of the second capacitor is disconnected, and the path between the signal input terminal and the first terminal of the first capacitor is disconnected, so that the first capacitor retains the tracked signal charge, and the path between the second capacitor and the reset voltage terminal is connected to clear the charge of the second capacitor. In the third mode, the path between the second terminal of the first capacitor and the first terminal of the second capacitor is connected in the mode switching circuit, so that the first capacitor and the second capacitor perform charge sharing sampling.

2. The front-end circuit of the pipelined analog-to-digital converter as described in claim 1, characterized in that, The pipeline analog-to-digital converter front-end circuit also includes a sub-analog-to-digital converter and a reference switching circuit; The input terminal of the sub-analog-to-digital converter is connected to the signal input terminal through the mode switching circuit, the output terminal of the sub-analog-to-digital converter is connected to the control terminal of the reference switching circuit, and the first terminal of the second capacitor is connected to multiple reference voltage terminals through the reference switching circuit. In the first mode, the sub-analog-to-digital converter and the first capacitor synchronously track the input signal. The reference switching circuit connects the first terminal of the second capacitor to the corresponding reference voltage terminal according to the quantization result output by the sub-analog-to-digital converter. In the second mode, the sub-analog-to-digital converter performs the conversion. In the third mode, the sub-analog-to-digital converter performs the conversion.

3. The front-end circuit of the pipelined analog-to-digital converter as described in claim 2, characterized in that, The mode switching circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch; the first switch is connected in series between the signal input terminal and the first terminal of the first capacitor; the second switch is connected in series between the first common-mode voltage terminal and the first terminal of the first capacitor; the third switch is connected in series between the first common-mode voltage terminal and the second terminal of the first capacitor; the fourth switch is connected in series between the second terminal of the first capacitor and the first terminal of the second capacitor; the fifth switch is connected in series between the reset voltage terminal and the first terminal of the second capacitor; and the sixth switch is connected in series between the input terminal of the sub-analog-to-digital converter and the signal input terminal. In the first mode, the mode switching circuit turns on the first switch, the third switch, and the sixth switch, while the second switch, the fourth switch, and the fifth switch are turned off. In the second mode, the second switch and the fifth switch are turned on, while the first switch, the third switch, the fourth switch, and the sixth switch are turned off. In the third mode, the mode switching circuit turns on the second and fourth switches, and turns off the first, third, fifth, and sixth switches.

4. The front-end circuit of the pipelined analog-to-digital converter as described in claim 3, characterized in that, The capacitance value of the second capacitor is less than the capacitance value of the first capacitor; During the transition phase from the first mode to the second mode, the mode switching circuit is configured to sequentially disconnect the third switch and the first switch.

5. The front-end circuit of the pipelined analog-to-digital converter as described in claim 3, characterized in that, The pipelined analog-to-digital converter front-end circuit also includes a noise cancellation unit, which includes an automatic zeroing capacitor connected in series between the residual amplifiers inside the pipelined analog-to-digital converter. The mode switching circuit also includes a seventh switch, which is connected in series between the second terminal of the second capacitor and the second reset voltage terminal. During the transition phase from the third mode to the first mode, the mode switching circuit disconnects the seventh switch to transfer the thermal noise generated by the charge-sharing sampling stage to the bottom plate of the automatic zeroing capacitor.

6. The pipelined analog-to-digital converter front-end circuit according to claim 5, characterized in that, The pipelined analog-to-digital converter front-end circuit also includes a zero-reset switch. The top plate of the automatic zero-reset capacitor is connected to the common-mode reference voltage terminal through the zero-reset switch, and the bottom plate of the automatic zero-reset capacitor is connected in series in the signal path of the amplifier stage. In the first mode, the mode switching circuit disconnects the seventh switch and controls the zeroing switch to turn on, so as to physically clamp the top plate of the automatic zeroing capacitor to the common mode reference voltage terminal.

7. The front-end circuit of the pipelined analog-to-digital converter as described in claim 3, characterized in that, The pipeline analog-to-digital converter front-end circuit also includes a substrate tracking circuit. The substrate tracking circuit includes a substrate tracking bootstrap circuit, a first tracking capacitor, and a second tracking capacitor. The ratio of the capacitance value of the first tracking capacitor to the capacitance value of the second capacitor is equal to the ratio of the capacitance value of the second tracking capacitor to the capacitance value of the second capacitor. The bottom plate of the first tracking capacitor can be selectively connected to the signal input terminal, and the top plate of the first tracking capacitor is connected to the input terminal of the substrate tracking bootstrap circuit; the bottom plate of the second tracking capacitor can be selectively connected to the first common-mode voltage terminal, and the top plate of the first tracking capacitor is connected to the input terminal of the substrate tracking bootstrap circuit.

8. The front-end circuit of the pipelined analog-to-digital converter as described in claim 7, characterized in that, The substrate tracking bootstrap circuit includes a bias capacitor and a bootstrap switch group; In the first mode or the second mode, the bootstrap switch group is configured to conduct the charging path between the bias capacitor and the preset bias voltage terminal, so that the bias capacitor stores the preset voltage difference; In the third mode, the bootstrap switch group is configured to disconnect the charging path and connect the bias capacitor in series between the top plate of the first tracking capacitor and the substrate of the fourth switch.

9. A pipelined analog-to-digital converter circuit, characterized in that, The pipeline analog-to-digital conversion circuit includes: Multiple pipelined analog-to-digital converters; Multiple pipelined analog-to-digital converter front-end circuits as described in any one of claims 1 to 8; In two adjacent pipelined analog-to-digital converters, the output of the first pipelined analog-to-digital converter is connected to the signal input of the charge-sharing sampling stage circuit in the front-end circuit of the pipelined analog-to-digital converter, and the input of the second pipelined analog-to-digital converter is connected to the second terminal of the second capacitor in the charge-sharing sampling stage circuit in the front-end circuit of the same pipelined analog-to-digital converter.

10. A communication device, characterized in that, The communication device includes a pipelined analog-to-digital converter front-end circuit as described in any one of claims 1 to 8, or a pipelined analog-to-digital converter circuit as described in claim 9.

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