Semiconductor device and method of manufacturing the same, electronic device

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor device comprises the following steps: sequentially and alternately manufacturing an initial oxide layer and an initial sacrificial layer on one side of a substrate to obtain an initial stack structure; patterning to obtain a first initial hole and a second initial hole penetrating through the initial stack structure; epitaxially forming an epitaxial sacrificial column in each of the first initial hole and the second initial hole from the substrate upwards; laterally etching to remove the multilayer initial sacrificial layer until the epitaxial sacrificial column is exposed; laterally epitaxially forming a multilayer semiconductor layer based on the epitaxial sacrificial column to obtain a stack structure; removing the epitaxial sacrificial column at the first initial hole based on a patterning process, and forming a first through hole; laterally etching to remove a part of each of the multilayer semiconductor layers to form a multilayer first channel in communication with the first through hole; and sequentially manufacturing a gate insulating layer and a gate signal line which conformally cover and fill the first channel and the first through hole. The application achieves the effect of reducing the area of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a method for manufacturing the same, and an electronic device. Background Technology

[0002] Currently, some semiconductor devices utilize epitaxial processes to fabricate alternating Si and SiGe (silicon layer and silicon germanium layer) stacked structures on one side of a substrate. Then, the multiple SiGe layers are replaced with insulating layers, while the Si (silicon) layers are retained as the semiconductor layers of the transistor. Subsequently, the source, drain, and gate of the transistor are fabricated.

[0003] The lattice mismatch between Si and SiGe, i.e., the stress between them, limits the number of layers in the Si-SiGe stack, which restricts the area of ​​semiconductor devices from being further reduced. Summary of the Invention

[0004] This application addresses the shortcomings of existing methods by proposing a semiconductor device and its manufacturing method, as well as an electronic device, to solve the technical problem of limited layer number in Si-SiGe stacked structures in related technologies.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: An initial oxide layer and an initial sacrificial layer are sequentially and alternately fabricated on one side of the substrate to obtain an initial stacked structure; Patterning is used to obtain a first initial hole and a second initial hole that penetrate the initial stacked structure; Epitaxial sacrificial pillars are formed upward from the substrate, each filling the first initial hole and the second initial hole; Laterally etch away multiple layers of the initial sacrificial layer until the epitaxial sacrificial pillar is exposed; A multilayer semiconductor layer is formed by lateral epitaxy based on the epitaxial sacrificial pillar, resulting in a stacked structure; The epitaxial sacrificial pillar at the first initial hole of the stacked structure is removed by a patterning process, and a first through hole is formed; Lateral etching removes a portion of each of the multiple semiconductor layers to form a multi-layer first channel communicating with the first via. The gate insulating layer and gate signal line are sequentially manufactured to conformally cover and fill the first channel and the first via.

[0006] Optionally, after epitaxially forming epitaxial sacrificial pillars respectively filling the first initial hole and the second initial hole from the substrate upwards, and before laterally etching away multiple layers of the initial sacrificial layer until the epitaxial sacrificial pillars are exposed, the process includes: An initial second buffer layer and an initial first insulating layer are sequentially fabricated to conformally cover the initial stacked structure and the epitaxial sacrificial pillar, with the top of the epitaxial sacrificial pillar extending beyond the initial stacked structure. Auxiliary holes are patterned to penetrate the initial first insulating layer, the initial second buffer layer, and the periphery of the initial stacked structure; And, lateral etching to remove multiple layers of the initial sacrificial layer until the epitaxial sacrificial pillar is exposed, including: Based on the wet etching process, multiple layers of the initial sacrificial layer are removed through the auxiliary holes until the epitaxial sacrificial pillar is exposed.

[0007] Optionally, after removing the epitaxial sacrificial pillar at the first initial hole of the stacked structure based on a patterning process and forming the first via, and before laterally etching away a portion of each of the multiple semiconductor layers to form a multilayer first channel communicating with the first via, the method further includes: A first barrier layer is formed at the bottom of the first via, wherein the top surface of the first barrier layer is at least higher than the substrate and lower than the first channel.

[0008] Optionally, a first barrier layer is formed at the bottom of the first through-hole, comprising: An initial first barrier layer and an initial second barrier layer are sequentially deposited to conformally cover and fill the first through-hole; based on a patterning process, the initial first barrier layer and the initial second barrier layer are etched to obtain a first barrier layer conformally covering the first through-hole and a second barrier layer located at the bottom of the first through-hole. The surface of the second barrier layer is oxidized to obtain a third barrier layer. The first barrier layer includes the first barrier layer, the second barrier layer, and the third barrier layer.

[0009] Optionally, a gate insulating layer and a gate signal line are sequentially fabricated to conformally cover and fill the first channel and the first via, including: A conformal gate insulating layer and a first sub-gate are sequentially fabricated to cover and fill the first channel; A word line is manufactured to fill the first via; the gate signal line includes the electrically connected first sub-gate and the word line, and the word line includes multiple alternating and electrically connected second sub-gates and connecting lines.

[0010] Optionally, after sequentially fabricating a conformal gate insulating layer and gate signal line that cover and fill the first channel and the first via, the process includes: The epitaxial sacrificial pillar in the second initial hole is etched away to form a second through hole stopping on the substrate; A second barrier layer is manufactured to fill the bottom of the second via, the height of the second barrier layer being at least higher than the substrate and lower than the second channel; Lateral etching removes part of the semiconductor layer to form a second channel communicating with the second via, and the semiconductor layer is left as a channel region between the second channel and the first channel; A capacitor is fabricated in the second through-hole and the second channel.

[0011] Optionally, a capacitor is fabricated in the second via and the second channel, comprising: Fabricate a first electrode that conformally covers the second channel; A capacitor dielectric layer that fills the second through-hole and covers the first electrode and a second electrode are manufactured to obtain the capacitor.

[0012] Secondly, embodiments of this application provide a semiconductor device disposed on a substrate, comprising: A multilayer semiconductor layer and an oxide layer are alternately disposed on one side of the substrate, wherein the semiconductor layer is formed by homoepitaxial growth based on the substrate; Word lines penetrate the alternating layers of the semiconductor and oxide layers; A gate signal line includes the word line and multiple layers of first sub-gates. The word line includes multiple alternating and electrically connected second sub-gates and connecting lines. The second sub-gate layer is on the same layer as the semiconductor layer, and the first sub-gate is disposed around the periphery of the second sub-gate on the same layer. A multilayer gate insulating layer, wherein the gate insulating layer is on the same layer as the semiconductor layer, is disposed around the second sub-gate on the same layer, surrounds the first sub-gate on the same layer, and is surrounded by the semiconductor layer on the same layer.

[0013] Optionally, the semiconductor device further includes: The second electrode penetrates through multiple alternating layers of the semiconductor layer and the oxide layer; The capacitor dielectric layer includes a first capacitor dielectric layer and multiple layers of second capacitor dielectric layers, wherein the first capacitor dielectric layer is wound around the periphery of the second electrode, and the multiple layers of second capacitor dielectric layers are wound around the periphery of the first capacitor dielectric layer. The first electrode is a multilayer first electrode, which is co-layered with the corresponding semiconductor layer and is wrapped around the periphery of the first capacitor dielectric layer in the same layer, and encapsulates the second capacitor dielectric layer in the same layer.

[0014] Thirdly, embodiments of this application provide an electronic device, including: a semiconductor device manufactured using the manufacturing method of the first embodiment; or a semiconductor device including the second embodiment.

[0015] The beneficial technical effects of the technical solution provided in this application include: This application manufactures (e.g., deposits) an initial stacked structure including an overlapping initial oxide layer and an initial sacrificial layer on one side of a substrate, then homoepitaxially forms an epitaxial sacrificial pillar penetrating the initial stacked structure from the single crystal semiconductor substrate, and then laterally epitaxially forms a semiconductor layer replacing the initial sacrificial layer based on the epitaxial sacrificial pillar. As can be seen, since the semiconductor layer serving as the channel region in this application is homoepitaxially formed from a single-crystal semiconductor (e.g., single-crystal silicon) substrate, there is no need to use the Si-SiGe stacked structure manufactured by epitaxial processes in related technologies. Therefore, the semiconductor layer in this application does not have stress and defects caused by lattice mismatch between the Si (silicon) layer and the SiGe (silicon germanium) layer, resulting in a higher quality semiconductor layer. Moreover, it can block the path of stress and defects in the lower film layer in the stacked structure from being transferred to the upper semiconductor layer through the epitaxial process in a lattice mismatch manner. Theoretically, a larger number of semiconductor layers can be stacked, overcoming the problem that Si-SiGe stacks cannot achieve multi-layer stacking. This can improve the space utilization in the substrate or wafer height direction, thereby effectively reducing the area of ​​semiconductor devices, promoting the steady development of semiconductor devices from 2D to 3D, and improving the performance of semiconductor devices.

[0016] Moreover, since the semiconductor layer formed by homoepitaxial growth from a single-crystal semiconductor substrate has very little or no lattice mismatch, low stress, and few defects, it can be manufactured to a thicker target thickness, which is beneficial for adapting to a variety of designs, manufacturing processes, or customer needs.

[0017] In addition, the epitaxial sacrificial pillars ensure that the initial oxide layer does not collapse during the lateral epitaxial formation of the semiconductor layer.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic diagram of a semiconductor device manufacturing method provided in an embodiment of this application; Figure 2-24 This is a schematic diagram of the film structure after each step of a semiconductor device manufacturing method provided in this application embodiment is completed; Figure 25 A schematic diagram of the film structure of a semiconductor device provided in an embodiment of this application; Figure 26This is a top view schematic diagram of a semiconductor device (excluding the first buffer layer, the second buffer layer, and the first insulating layer) provided for an embodiment of this application.

[0020] Explanation of reference numerals in the attached figures 100-substrate; 110 - Initial stacked structure; 111 - Initial oxide layer; 112 - Initial sacrificial layer; 1101 - Stacked structure; 1111 - Oxide layer; 1121 - Sacrificial layer; 120 - First initial hole; 130 - Second initial hole; 140 - Auxiliary hole; 150-Extensional sacrificial column; 160 - Initial first buffer layer; 1601 - First buffer layer; 170 - Hard mask layer; 180 - Anti-reflective coating; 190 - Photoresist layer; 200 - Initial first insulating layer; 2001 - First insulating layer; 210 - First barrier layer; 211 - First isolation layer; 2111 - Initial first isolation layer; 212 - Second isolation layer; 2121 - Initial second isolation layer; 213 - Third isolation layer; 220-layer gap; 230 - First through hole; 240 - First channel; 250 - Second through hole; 260 - Second channel; 270 - Third through hole; 280 - Third channel; 290 - Semiconductor layer; 300 - Gate insulating layer; 310 - Gate signal line; 311 - First sub-gate; 3111 - Initial first sub-gate; 312 - Word line; 3121 - Second sub-gate; 3122 - Connector line; 320 - Capacitor; 321 - First electrode; 3211 - Initial first electrode; 322 - Capacitor dielectric layer; 3221 - First capacitor dielectric layer; 3222 - Second capacitor dielectric layer; 323 - Second electrode; 331 - First source / drain electrode; 332 - Second insulating layer; 340 - Second barrier layer. Detailed Implementation

[0021] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0022] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in the specification of this application means the presence of the stated features, steps, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" can be implemented as "A," or as "B," or as "A and B."

[0023] In this application, a semiconductor device refers to a component that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A semiconductor device has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0024] In related technologies, some semiconductor device manufacturing methods typically utilize Si or SiGe (silicon layer, silicon-germanium layer) to create stacked structures. The relevant process steps mainly include: A substrate is provided on which a stacked structure of alternating silicon-germanium layers and silicon layers is formed sequentially.

[0025] Lateral etching removes part of the silicon-germanium layer at the edge to create voids on both sides of the remaining silicon-germanium layer.

[0026] Insulating material is filled into the cavity to form sidewalls; source / drain electrodes are formed on both sides of the stacked structure.

[0027] Remove the silicon-germanium layer.

[0028] However, due to the lattice mismatch between Si and SiGe, i.e., the presence of stress between them, there is a critical thickness for growing a SiGe strained layer on a Si substrate. When the thickness of the SiGe strained layer exceeds the critical thickness, mismatched dislocations will be generated within the SiGe strained layer, causing stress relaxation and resulting in a deterioration in the quality of both the single-crystal Si and the SiGe strained layer.

[0029] Furthermore, not only does a single SiGe strained layer generate its own lattice mismatch defects when it exceeds the critical thickness, but these defects also accumulate with the propagation of Si-SiGe stacks. Each additional SiGe and Si layer inherits the lattice mismatch defects of all the SiGe and Si layers below it, and generates its own lattice mismatch defects according to the lattice mismatch defects of the previous SiGe strained layer. Therefore, the more layers a Si-SiGe stack structure has, the more quality defects are generated in the semiconductor device. This limits the height of the Si-SiGe stack structure in related technologies, making it impossible to achieve multi-layer stacking. This will limit the area of ​​semiconductor devices from being further reduced, thus restricting the development of semiconductor technology from 2D to 3D.

[0030] To address the technical problem that the stacking height is limited when using Si or SiGe to create a stacked structure, thus preventing further reduction in the area of ​​semiconductor devices, this application provides a method for manufacturing a semiconductor device.

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0032] Reference Figure 1 This application provides a method for manufacturing a semiconductor device, including the following steps S101-S108: S101: An initial oxide layer 111 and an initial sacrificial layer 112 are sequentially and alternately fabricated on one side of the substrate 100 to obtain an initial stacked structure 110, as shown in the figure. Figure 2 The diagram shows a schematic of the membrane structure.

[0033] S102: Patterning is used to obtain the first initial hole 120 and the second initial hole 130 that penetrate the initial stacked structure 110, resulting in... Figure 3 The diagram shows a schematic of the membrane structure.

[0034] S103: Epitaxial sacrificial pillars 150 are formed from the substrate 100 upwards, each filling the first initial hole 120 and the second initial hole 130, to obtain... Figure 4 The diagram shows a schematic of the membrane structure.

[0035] S104: Lateral etching removes multiple initial sacrificial layers 112 until the epitaxial sacrificial pillars 150 are exposed, resulting in... Figure 8 The diagram shows a schematic of the membrane structure.

[0036] S105: Based on the epitaxial sacrificial pillar 150, a multilayer semiconductor layer 290 is formed by lateral epitaxy to obtain a stacked structure 1101, resulting in the following... Figure 9 The diagram shows a schematic of the membrane structure.

[0037] S106: The epitaxial sacrificial pillar 150 at the first initial hole 120 of the stacked structure 1101 is removed using a patterning process, and a first through hole 230 is formed, resulting in... Figure 11 The diagram shows a schematic of the membrane structure.

[0038] S107: Lateral etching removes a portion of each of the multilayer semiconductor layers 290, forming a multilayer first channel 240 communicating with the first via 230, resulting in... Figure 14 The diagram shows a schematic of the membrane structure.

[0039] S108: Sequentially fabricate a gate insulating layer 300 and a gate signal line 310 that conformally cover and fill the first channel 240 and the first via 230, to obtain... Figure 17 The diagram shows a schematic of the membrane structure.

[0040] In this embodiment, an initial oxide layer 111 and an initial sacrificial layer 112 are alternately fabricated on one side of a substrate 100 as an initial stacked structure 110. An epitaxial sacrificial pillar 150 is first formed homogeneously from the substrate 100 upwards, and then a semiconductor layer 290 replacing the initial sacrificial layer 112 is formed laterally based on the epitaxial sacrificial pillar 150.

[0041] As can be seen, since the semiconductor layer 290 serving as the channel region in this application is homoepitaxially formed from a single-crystal semiconductor (e.g., single-crystal silicon) substrate, it does not require the use of Si-SiGe stacked structures manufactured based on epitaxial processes in related technologies. Therefore, the semiconductor layer in this application does not contain stress and defects caused by lattice mismatch between the Si (silicon) layer and the SiGe (silicon germanium) layer, resulting in a higher quality semiconductor layer. Moreover, it can block the path of stress and defects in the lower film layer in the stacked structure being transferred to the upper semiconductor layer through the epitaxial process in a lattice mismatch manner. Theoretically, it can stack a larger number of semiconductor layers, overcoming the problem that Si-SiGe stacks cannot achieve multi-layer stacking. It can improve the space utilization in the substrate or wafer height direction, thereby effectively reducing the area of ​​semiconductor devices, promoting the steady development of semiconductor devices from 2D to 3D, and improving the performance of semiconductor devices.

[0042] The initial sacrificial layer 112 is made of an insulating medium, including but not limited to nitrides such as silicon nitride (Si3N4). Si3N4 can be deposited using PECVD or LPCVD (Low Pressure Chemical Vapor Deposition) processes to obtain the initial sacrificial layer 112. Using silicon nitride as the initial sacrificial layer 112 is more cost-effective than using SiGe as the sacrificial layer 112, thus saving manufacturing costs.

[0043] Optionally, the material of the two epitaxial sacrificial pillars 150 includes, but is not limited to, silicon, which can be polycrystalline silicon or heavily doped monocrystalline silicon. When polycrystalline silicon or other materials are used for the epitaxial sacrificial pillars 150, they can be manufactured in the first initial hole 120 and the second initial hole 130 using a direct filling method.

[0044] In this application, both the epitaxial sacrificial pillar 150 and the semiconductor layer 290 are homoepitaxially formed from a single-crystal silicon substrate 100, thereby enabling the epitaxially formed semiconductor layer 290 to have higher crystal quality and lower defect density, thus improving the quality and performance of the semiconductor device.

[0045] Optionally, in this embodiment, the two epitaxial sacrificial pillars 150 define the positions of the transistor to be formed and the effective devices to be formed, respectively, so that the two epitaxial sacrificial pillars 150 define the positions and regions of the memory cells to be formed. Optionally, the effective device can be a capacitor 320, in which case the memory cell includes a transistor and a capacitor 320, which is a 1T1C structure; the effective device can also be another transistor, in which case the memory cell includes two transistors, which is a 2T0C structure.

[0046] Optionally, refer to Figure 2 In step S102 above, patterning to obtain the first initial hole 120 and the second initial hole 130 penetrating the initial stacked structure 110 includes: On one side of the initial stacked structure 110, a conformal cover initial first buffer layer 160, a hard mask layer 170, an anti-reflective coating 180, and a photoresist layer 190 are sequentially fabricated.

[0047] The photoresist layer 190 is exposed and developed to form a photoresist structure with a designed pattern.

[0048] Using the photoresist structure as a mask, the anti-reflective coating 180, the hard mask layer 170, and the initial first buffer layer 160 are etched to obtain the hard mask structure and the first buffer layer 1601.

[0049] The photoresist structure is stripped away.

[0050] Based on the hard mask structure and the first buffer layer 1601, the initial stacked structure 110 is etched to obtain the first initial hole 120 and the second initial hole 130.

[0051] Remove the hard mask structure.

[0052] Optionally, in step S103 above, when epitaxial sacrificial pillars 150 are formed from the substrate 100 upwards, each filling the first initial hole 120 and the second initial hole 130, the epitaxial sacrificial pillars 150 are epitaxially extended beyond the initial stacked structure 110 to obtain the following... Figure 4 The diagram shows a schematic of the membrane structure.

[0053] Optionally, in steps S103-S104 above, after epitaxially forming epitaxial sacrificial pillars 150 respectively filling the first initial via 120 and the second initial via 130 from the substrate 100 upwards, and before laterally etching away multiple layers of initial sacrificial layers 112 until the epitaxial sacrificial pillars 150 are exposed, the process includes: An initial second buffer layer (not shown in the figure) and an initial first insulating layer 200 are sequentially fabricated to conformally cover the initial stacked structure 110 and the epitaxial sacrificial pillar 150. The top of the epitaxial sacrificial pillar 150 extends beyond the initial stacked structure 110, resulting in the following: Figure 5 The diagram shows a schematic of the membrane structure.

[0054] Auxiliary holes 140 are patterned to penetrate the periphery of the initial first insulating layer 200, the initial second buffer layer, and the initial stacked structure 110, resulting in a stacked structure 1101, a second buffer layer, and a first insulating layer 2001 arranged alternately in sequence, as shown in the figure. Figure 6-7 The diagram shows a schematic of the membrane structure.

[0055] And, lateral etching to remove multiple initial sacrificial layers 112 until the epitaxial sacrificial pillars 150 are exposed, including: Based on a wet etching process, multiple layers of the initial sacrificial layer 112 are removed through auxiliary vias 140 until the epitaxial sacrificial pillar 150 is exposed, resulting in the following... Figure 8 The diagram shows a schematic of the membrane structure.

[0056] Optionally, in the above steps, an initial second buffer layer conformally covering the initial stacked structure 110 and the epitaxial sacrificial pillar 150 is fabricated by atomic layer deposition; an initial first insulating layer 200 conformally covering the initial second buffer layer is fabricated by chemical vapor deposition; and then the initial first insulating layer 200 is planarized by CMP (Chemical Mechanical Polishing).

[0057] The initial second buffer layer fabricated by ALD (Atomic Layer Deposition) has good quality but a slow deposition rate, while the initial first insulating layer 200 fabricated by CVD (Chemical Vapor Deposition) has relatively poor quality but a fast deposition rate. In this application, the thickness of the initial second buffer layer is less than the thickness of the initial first insulating layer 200. By employing these two deposition processes, this application ensures that the first buffer layer 1601 and the epitaxial sacrificial pillar 150 are encapsulated by a high-quality initial second buffer layer. The initial first insulating layer 200 is then deposited on the initial second buffer layer, which not only ensures the quality of the semiconductor device but also increases the processing speed and reduces processing costs.

[0058] Optionally, the auxiliary holes 140 patterned in the above steps that penetrate the periphery of the initial first insulating layer 200, the initial second buffer layer and the initial stacked structure 110 are the same as or substantially the same as the process of patterning the first initial hole 120 and the second initial hole 130 in step S102, and will not be described in detail here.

[0059] By patterning and etching away a portion of the outer peripheral wall of the initial stacked structure 110, the initial sacrificial layer 112 is formed into a sacrificial layer 1121, and the initial oxide layer 111 is formed into an oxide layer 1111, thereby exposing the end face of the sacrificial layer 1121, which facilitates the smooth contact of the lateral etching solution with the sacrificial layer 1121, thereby successfully removing the sacrificial layer 1121.

[0060] Since epitaxial sacrificial pillars 150 are formed from the substrate 100 upward in step S103, after all the multilayer sacrificial layers 1121 are removed, the multilayer oxide layers 1111 are connected to the epitaxial sacrificial pillars 150, thereby supporting the multilayer oxide layers 1111 through the epitaxial sacrificial pillars 150, preventing the multilayer oxide layers 1111 from collapsing, and ensuring that the width of the interlayer gap 220 for epitaxially forming the semiconductor layer 290 between two adjacent oxide layers 1111 remains consistent, thereby improving the quality and yield of the semiconductor device of this application.

[0061] In step S105 above, a multilayer semiconductor layer 290 is formed laterally based on the epitaxial sacrificial pillar 150, resulting in a stacked structure 1101. The semiconductor layer 290 is homoepitaxially formed from the silicon substrate 100, which makes the structure of the semiconductor layer 290 of this application more stable, thereby improving the quality of the semiconductor device.

[0062] Optionally, in steps S106-S107 above, after removing the epitaxial sacrificial pillar 150 at the first initial hole 120 of the stacked structure 1101 based on the patterning process and forming the first via 230, and before laterally etching away a portion of each of the multilayer semiconductor layers 290 to form the multilayer first channel 240 communicating with the first via 230, the method further includes: A first barrier layer 210 is formed at the bottom of the first via 230. The top surface of the first barrier layer 210 is at least higher than the substrate 100 and lower than the first channel 240, resulting in the following: Figure 13 The diagram shows a schematic of the membrane structure.

[0063] By creating a first barrier layer 210 at the bottom of the first via 230, it is possible to prevent the stacked layer structure 1101 from being etched into the substrate 100 during the lateral etching of the first channel 240.

[0064] Optionally, in the above steps, the Bosch process can be used to manufacture the first barrier layer 210 at the bottom of the first through-hole 230, including: By sequentially depositing an initial first barrier layer 2111 and an initial second barrier layer 2121 to cover and fill the first through-hole 230, the following is obtained: Figure 12 The diagram shows a schematic of the membrane structure.

[0065] Based on a patterning process, an initial first barrier layer 2111 and an initial second barrier layer 2121 are etched to obtain a first barrier layer 211 that conforms to the shape of the first through-hole 230 and a second barrier layer 212 located at the bottom of the first through-hole 230, resulting in... Figure 13 The diagram shows a schematic of the membrane structure.

[0066] The surface of the second barrier layer 212 is oxidized to obtain the third barrier layer 213. The first barrier layer 210 includes the first barrier layer 211, the second barrier layer 212, and the third barrier layer 213, resulting in the following: Figure 14 The diagram shows a schematic of the membrane structure.

[0067] Optionally, the material of the second barrier layer 212 includes, but is not limited to, polysilicon, and the third barrier layer 213 is a thin layer of silicon oxide formed by oxidizing the second barrier layer 212, which is the same material as the silicon oxide layer used to form the initial oxide layer 111 in step S101. The third barrier layer 213 serves as a passivation layer to prevent damage to the substrate 100 when etching the first channel 240.

[0068] Optionally, the third barrier layer 213 is in the same layer or substantially in the same layer as one of the oxide layers 1111, so that the oxide layer 1111 and the third barrier layer 213 form a complete film layer.

[0069] Optionally, after the oxidation to form the third barrier layer 213, and before the lateral etching to remove a portion of each of the multiple semiconductor layers 290 to form the multilayer first channel 240 communicating with the first via 230, the method further includes: Vapor phase etching removes the first barrier layer 211 from the sidewall of the first via 230, exposing the semiconductor layer 290, resulting in... Figure 14 The diagram shows a schematic of the membrane structure.

[0070] Optionally, in step S108, the gate insulating layer 300 and the gate signal line 310 are sequentially fabricated to conformally cover and fill the first channel 240 and the first via 230, including: The gate insulating layer 300 and the first sub-gate 311 are sequentially fabricated to conformally cover and fill the first channel 240, resulting in the following: Figure 15-16 The diagram shows a schematic of the membrane structure.

[0071] To manufacture the word line 312 that fills the first through hole 230, the following is obtained: Figure 17 The diagram shows a schematic of the membrane structure.

[0072] The gate signal line 310 includes a first sub-gate 311 and a word line 312 that are electrically connected. The word line 312 includes multiple alternating and electrically connected second sub-gates 3121 and connecting lines 3122. The second sub-gate 3121 is electrically connected to the first sub-gate 311 and together constitutes the gate of the semiconductor device of this application. The first sub-gate 311 is insulated from the corresponding semiconductor layer 290 through a gate insulating layer 300.

[0073] Optionally, in the above steps, the gate insulating layer 300 and the first sub-gate 311 that conformally cover and fill the first channel 240 are sequentially manufactured, including: Growing a conformal gate insulating layer 300 covering the first channel 240 yields, as shown in the figure. Figure 15 The diagram shows a schematic of the membrane structure.

[0074] The initial first sub-gate 3111 is deposited to cover and fill the first via 230 and the first channel 240 in a conformal manner, resulting in the following: Figure 16 The diagram shows a schematic of the membrane structure.

[0075] Remove the initial first sub-gate 3111 from the sidewall of the first through hole 230 to obtain the first sub-gate 311 filled in the first channel 240.

[0076] The second sub-gate 3121 and the connecting line 3122 are sequentially fabricated to cover and fill the first through-hole 230 in a conformal manner, resulting in the following: Figure 17 The diagram shows a schematic of the membrane structure.

[0077] Optionally, depending on the actual situation, CMP process can be used for planarization until the first insulating layer 2001 is exposed, so that the second sub-gate 3121 or the connecting line 3122 is flush with the surface of the first insulating layer 2001.

[0078] Optionally, the gate insulating layer 300 may be made of high-k (dielectric constant) materials, including but not limited to HfO2 (hafnium oxide), Al2O3 (aluminum oxide), HfAlO (hafnium aluminum oxide), and HfLaO (hafnium lanthanum oxide), where the dielectric constant of the high-k materials is greater than that of SiO (3.9). The gate insulating layer 300 may be grown using either ALD or CVD methods.

[0079] Optionally, the electrode material of the gate can be any one or more of the following different types of materials: For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals. It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials. Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; other materials that exhibit conductivity, etc. This application uses titanium nitride (TiN) as the material for the first sub-gate 311 and tungsten (W) as the material for the second sub-gate 3121 as an example for illustration.

[0080] Optionally, after sequentially fabricating the gate insulating layer 300 and the gate signal line 310 that conformally cover and fill the first channel 240 and the first via 230, the process includes: The epitaxial sacrificial pillar 150 in the second initial hole 130 is etched away to form a second through hole 250 that stops on the substrate 100.

[0081] A second barrier layer 340 is fabricated to fill the bottom of the second via 250. The height of the second barrier layer 340 is at least higher than the substrate 100 and lower than the second channel 260, resulting in the following: Figure 18 The diagram shows a schematic of the membrane structure.

[0082] Lateral etching removes a portion of the semiconductor layer 290, forming a second channel 260 communicating with the second via 250. A semiconductor layer 290, serving as a channel region, is left between the second channel 260 and the first channel 240, resulting in... Figure 18 The diagram shows a schematic of the membrane structure.

[0083] Capacitor 320 is manufactured in the second through hole 250 and the second channel 260, resulting in the following: Figure 20 The diagram shows a schematic of the membrane structure.

[0084] Optionally, the process for manufacturing the second via 250, the second barrier layer 340 and the second channel 260 is the same as the process for manufacturing the transistor in the preceding process, and will not be described again here.

[0085] Optionally, a capacitor 320 is fabricated in the second through-hole 250 and the second channel 260, including: Fabricating a first electrode 321 that conformally covers the second channel 260, resulting in... Figure 19 The diagram shows a schematic of the membrane structure.

[0086] By fabricating a capacitor dielectric layer 322 that fills the second through-hole 250 and covers the first electrode 321 and the second electrode 323, a capacitor 320 is obtained, as shown in the figure. Figure 20 The diagram shows a schematic of the membrane structure.

[0087] Optionally, fabricating a first electrode 321 that conformally covers the second channel 260 includes: By fabricating an initial first electrode 3211 that conformally covers the second channel 260 and the second through hole 250, as shown... Figure 19 The diagram shows a schematic of the membrane structure.

[0088] The initial first electrode 3211 is removed from the sidewall of the second through hole 250 to obtain the first electrode 321 that conformally covers the second channel 260.

[0089] By fabricating a capacitor dielectric layer 322 that fills the second through-hole 250 and covers the first electrode 321 and the second electrode 323, a capacitor 320 is obtained, as shown in the figure. Figure 20 The diagram shows a schematic of the membrane structure.

[0090] The structure and manufacturing method of the capacitor 320 of this application are the same as or similar to the structure and manufacturing method of conventional capacitors 320 in the art, and will not be described in detail here.

[0091] Optionally, in the embodiments of this application, when forming the capacitor 320, after depositing the first electrode 321, the capacitor dielectric layer 322, and the second electrode 323, planarization can be performed by CMP (Chemical Mechanical Polishing) as needed until the first insulating layer 2001 is exposed, so that the surfaces of the first electrode 321, the capacitor dielectric layer 322, the second electrode 323, and the first insulating layer 2001 are flush.

[0092] Optionally, the material of the capacitor dielectric layer 322 includes, but is not limited to, high-k (dielectric constant) materials such as HfO2 (hafnium oxide), Al2O3 (aluminum oxide), HfAlO (hafnium aluminum oxide), and HfLaO (hafnium lanthanum oxide). The material of the first electrode 321 includes, but is not limited to, TiN (titanium nitride), and the manufacturing method can be ALD growth or CVD growth. The material of the second electrode 323 includes, but is not limited to, Poly (polycrystalline silicon), and the manufacturing method can be ALD growth or CVD growth.

[0093] In this embodiment, the first electrode 321 is electrically connected to the channel region formed by the semiconductor layer 290 of the transistor, so that the capacitor 320 and the transistor form a memory cell with a 1T1C structure. The first electrode 321 serves as the second source and drain of the transistor. The second source and drain can be the drain of the transistor or the source of the transistor.

[0094] When the transistor is a PMOS transistor, after the gate of the transistor is turned on, electrons flow from the first electrode 321 to the first source-drain 331 of the transistor, and the first electrode 321 serves as the source of the transistor. When the transistor is an NMOS transistor, after the gate of the transistor is turned on, electrons flow from the first source-drain 331 to the first electrode 321 of the transistor, and the first electrode 321 serves as the drain of the transistor.

[0095] Optionally, after forming a multilayer semiconductor layer 290 laterally based on the epitaxial sacrificial pillar 150 to obtain the stacked structure 1101, the method further includes: In each semiconductor layer 290, a first source / drain electrode 331 is formed at the end of the first initial via 120 away from the second initial via 130 or at the end of the first via 230 away from the second via 250, to obtain... Figure 25 The diagram shows a schematic of the membrane structure.

[0096] Optionally, the first source / drain 331 can be manufactured before etching the first via 230; or the first source / drain 331 can be manufactured after manufacturing the gate of the transistor and before manufacturing the capacitor 320; the first source / drain 331 can also be manufactured simultaneously with the capacitor 320; or the first source / drain 331 can also be manufactured after the capacitor 320.

[0097] In this application, the first source / drain electrode 331 is manufactured after the capacitor 320 is manufactured, including: A third through-hole 270 is obtained by patterning a process that penetrates the first insulating layer 2001 (formed from the initial first insulating layer 200), the second buffer layer, the first buffer layer 1601 (formed from the initial first buffer layer 160), and the stacked structure 1101, resulting in the following: Figure 21-22 The diagram shows a schematic of the membrane structure.

[0098] A portion of each of the multilayer semiconductor layers 290 is removed laterally to form a multilayer third channel 280 communicating with the third via 270, resulting in... Figure 23 The diagram shows a schematic of the membrane structure.

[0099] A multilayer conductive material is fabricated to fill the third channel 280, serving as the first source / drain electrode 331, to obtain... Figure 24 The diagram shows a schematic of the membrane structure.

[0100] The second insulating layer 332 is deposited to fill the third via 270, resulting in the following: Figure 25 The diagram shows a schematic of the membrane structure.

[0101] Optionally, after depositing the second insulating layer 332, planarization can be performed by CMP (Chemical Mechanical Polishing) as needed until the first insulating layer 2001 is exposed, so that the surfaces of the second insulating layer 332 and the first insulating layer 2001 are flush.

[0102] Optionally, the material of the first source / drain electrode 331 includes a conductive material, which includes, but is not limited to, one or more combinations of TiN (titanium nitride), W (tungsten), Mo (molybdenum), Ni (nickel), TiAl (titanium aluminum alloy), and ITO (indium tin oxide).

[0103] Optionally, the material of the second insulating layer 332 includes, but is not limited to, nitrides such as silicon nitride (Si3N4) and oxides such as silicon oxide (SiO).

[0104] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned using a patterning process to fabricate the respective film layers.

[0105] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned using a patterning process to fabricate the respective film layers.

[0106] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.

[0107] In the description of the embodiments of this application, it should be understood that a "layer" refers to a thin film made of a certain material on a substrate 100 using a deposition or coating process. If the thin film does not require patterning during the entire fabrication process, the thin film can be called a layer. If the thin film requires patterning during the entire fabrication process, the "layer" after patterning includes at least one "pattern".

[0108] Based on the same inventive concept, this application also provides a semiconductor device. (See reference...) Figure 20 , Figure 25 as well as Figure 26 The semiconductor device of this application is disposed on the substrate 100 and includes a transistor.

[0109] The substrate 100 is used to carry the transistor. The transistor of this application includes a first source-drain 331, a second source-drain insulated from the first source-drain 331, a semiconductor layer 290 electrically connected to the first source-drain 331 and the second source-drain respectively, a gate signal line 310 for controlling the transistor to be turned on or off, and a gate insulating layer 300 located between the semiconductor layer 290 and the gate signal line 310. The semiconductor layer 290 and the gate signal line 310 are electrically isolated by the gate insulating layer 300.

[0110] The semiconductor layer 290 and the oxide layer 1111 are multi-layered, and the multi-layered semiconductor layer 290 and oxide layer 1111 are alternately disposed on one side of the substrate 100. The semiconductor layer 290 is formed based on the homoepitaxial layer of the substrate 100.

[0111] The gate signal line 310 includes a word line 312 and multiple layers of first sub-gates 311. The word line 312 passes through alternating layers of semiconductor layers 290 and oxide layers 1111. The word line 312 includes multiple alternating and electrically connected layers of second sub-gates 3121 and connecting lines 3122. The second sub-gate 3121 layer is on the same layer as the semiconductor layer 290, and the first sub-gate 311 is wound around the periphery of the second sub-gate 3121 on the same layer.

[0112] The gate insulating layer 300 is provided with multiple layers. The gate insulating layer 300 is on the same layer as the semiconductor layer 290, is disposed around the second sub-gate 3121 on the same layer, wraps around the first sub-gate 311 on the same layer, and is surrounded by the semiconductor layer 290 on the same layer.

[0113] The first source / drain 331 is located on one side of the gate signal line 310 and is distributed on the substrate 100 along the first direction with the gate signal line 310. The first source / drain 331 includes a second insulating layer 332 and a multilayer conductive material, which is wound around the periphery of the second insulating layer 332. The conductive material is on the same layer as the semiconductor layer 290.

[0114] Optionally, such as Figure 20-25As shown, the semiconductor device of this application also includes a capacitor 320 disposed on the substrate 100 along the first direction with the transistor.

[0115] Capacitor 320 includes a first electrode 321, a dielectric layer 322, and a second electrode 323. The second electrode 323 penetrates alternating layers of semiconductor 290 and oxide 1111.

[0116] The capacitor dielectric layer 322 includes a first capacitor dielectric layer 3221 and multiple layers of second capacitor dielectric layers 3222. The first capacitor dielectric layer 3221 is wound around the periphery of the second electrode 323, and the multiple layers of second capacitor dielectric layers 3222 are each wound around the periphery of the first capacitor dielectric layer 3221.

[0117] The first electrode 321 has multiple layers. The first electrode 321 and the corresponding semiconductor layer 290 are located in the same layer and are arranged around the periphery of the first capacitor dielectric layer 3221, and the second capacitor dielectric layer 3222 is wrapped in the same layer.

[0118] The first electrode 321 is electrically connected to the transistor, so that the first electrode 321 of this application serves as the second source and drain of the transistor.

[0119] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes: a semiconductor device manufactured using the semiconductor device manufacturing method described above; or, a semiconductor device as described above.

[0120] It should be noted that since the electronic devices in the embodiments of this application include semiconductor devices manufactured using the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, the electronic devices in the embodiments of this application also have the above-mentioned beneficial effects of the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, which will not be repeated here.

[0121] In some optional embodiments of this application, the electronic device includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include, for example, memory in a computer, and is not limited thereto.

[0122] By applying the embodiments of this application, at least the following beneficial effects can be achieved: In this embodiment, an epitaxial sacrificial pillar 150 is first formed homogeneously upward from the substrate 100, and then a semiconductor layer 290 replacing the initial sacrificial layer 112 is formed laterally based on the epitaxial sacrificial pillar 150. This embodiment does not require the use of Si / SiGe stacked structures manufactured using epitaxial processes in related technologies. Therefore, the semiconductor layer in this application does not contain stress and defects caused by lattice mismatch between the Si (silicon) layer and the SiGe (silicon-germanium) layer, resulting in higher quality semiconductor layers. Furthermore, it can block the path of stress and defects in the lower film layer of the stacked structure from being transferred to the upper semiconductor layer through lattice mismatch during the epitaxial process. Theoretically, this allows for the stacking of a larger number of semiconductor layers, overcoming the problem that Si-SiGe stacks cannot achieve multi-layer stacking. This improves space utilization in the substrate or wafer height direction, effectively reducing the area of ​​semiconductor devices and promoting the steady development of semiconductor devices from 2D to 3D, thus improving the performance of semiconductor devices.

[0123] By first epitaxially forming an epitaxial sacrificial pillar 150 upwards, and then laterally epitaxially forming a semiconductor layer 290 that replaces the initial sacrificial layer 112 based on the epitaxial sacrificial pillar 150, it can be ensured that the initial oxide layer 111 will not collapse when manufacturing the semiconductor layer 290, thus ensuring the structural stability of the semiconductor device during processing and improving the yield of the semiconductor device.

[0124] In this embodiment, both the epitaxial sacrificial pillar 150 and the semiconductor layer 290 are homoepitaxially formed from the substrate 100, thereby enabling the epitaxially formed semiconductor layer 290 to have high crystal quality and low defect density. The lattice mismatch between the semiconductor layer 290 and the substrate 100 is rare or has a very low probability, resulting in low stress and fewer defects. This allows for the fabrication of a thicker target thickness, which is beneficial for adapting to a variety of designs, manufacturing processes, or customer needs.

[0125] This application embodiment utilizes a barrier layer added to the bottom of both the transistor and the capacitor 320. When removing the epitaxial sacrificial pillar 150 and its respective covered initial channel region through the first via 230 and the second via 250, the barrier layer prevents the chemical solution from directly contacting the bottom substrate 100, thereby protecting the substrate 100 and avoiding the risk of semiconductor device collapse due to substrate loss. Compared to other solutions in related technologies, the process for fabricating the barrier layer in this application is mature and has low manufacturing cost.

[0126] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0127] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0128] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0129] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0130] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: An initial oxide layer and an initial sacrificial layer are sequentially and alternately fabricated on one side of the substrate to obtain an initial stacked structure; Patterning is used to obtain a first initial hole and a second initial hole that penetrate the initial stacked structure; Epitaxial sacrificial pillars are formed upward from the substrate, each filling the first initial hole and the second initial hole; Laterally etch away multiple layers of the initial sacrificial layer until the epitaxial sacrificial pillar is exposed; A multilayer semiconductor layer is formed by lateral epitaxy based on the epitaxial sacrificial pillar, resulting in a stacked structure; The epitaxial sacrificial pillar at the first initial hole of the stacked structure is removed by a patterning process, and a first through hole is formed; Lateral etching removes a portion of each of the multiple semiconductor layers to form a multi-layer first channel communicating with the first via. The gate insulating layer and gate signal line are sequentially manufactured to conformally cover and fill the first channel and the first via.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After epitaxially forming epitaxial sacrificial pillars that fill the first initial hole and the second initial hole respectively from the substrate upwards, and before laterally etching away multiple layers of the initial sacrificial layer until the epitaxial sacrificial pillars are exposed, the process includes: An initial second buffer layer and an initial first insulating layer are sequentially fabricated to conformally cover the initial stacked structure and the epitaxial sacrificial pillar, with the top of the epitaxial sacrificial pillar extending beyond the initial stacked structure. Auxiliary holes are patterned to penetrate the initial first insulating layer, the initial second buffer layer, and the periphery of the initial stacked structure; And, lateral etching to remove multiple layers of the initial sacrificial layer until the epitaxial sacrificial pillar is exposed, including: Based on the wet etching process, multiple layers of the initial sacrificial layer are removed through the auxiliary holes until the epitaxial sacrificial pillar is exposed.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After removing the epitaxial sacrificial pillar at the first initial hole of the stacked structure using a patterning process to form the first via, and before laterally etching away a portion of each of the multiple semiconductor layers to form a multilayer first channel communicating with the first via, the method further includes: A first barrier layer is formed at the bottom of the first via, wherein the top surface of the first barrier layer is at least higher than the substrate and lower than the first channel.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, A first barrier layer is formed at the bottom of the first through-hole, including: An initial first barrier layer and an initial second barrier layer are sequentially deposited to conformally cover and fill the first through-hole; based on a patterning process, the initial first barrier layer and the initial second barrier layer are etched to obtain a first barrier layer conformally covering the first through-hole and a second barrier layer located at the bottom of the first through-hole. The surface of the second barrier layer is oxidized to obtain a third barrier layer. The first barrier layer includes the first barrier layer, the second barrier layer, and the third barrier layer.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The gate insulating layer and gate signal line are sequentially fabricated to conformally cover and fill the first channel and the first via, including: A conformal gate insulating layer and a first sub-gate are sequentially fabricated to cover and fill the first channel; A word line is manufactured to fill the first via; the gate signal line includes the electrically connected first sub-gate and the word line, and the word line includes multiple alternating and electrically connected second sub-gates and connecting lines.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After sequentially fabricating a conformal gate insulating layer and gate signal line that cover and fill the first channel and the first via, the process includes: The epitaxial sacrificial pillar in the second initial hole is etched away to form a second through hole stopping on the substrate; A second barrier layer is manufactured to fill the bottom of the second via, the height of the second barrier layer being at least higher than the substrate and lower than the second channel; Lateral etching removes part of the semiconductor layer to form a second channel communicating with the second via, and the semiconductor layer is left as a channel region between the second channel and the first channel; A capacitor is fabricated in the second through-hole and the second channel.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, Fabricating a capacitor in the second via and the second channel includes: Fabricate a first electrode that conformally covers the second channel; A capacitor dielectric layer that fills the second through-hole and covers the first electrode and a second electrode are manufactured to obtain the capacitor.

8. A semiconductor device disposed on a substrate, characterized in that, include: A multilayer semiconductor layer and an oxide layer are alternately disposed on one side of the substrate, wherein the semiconductor layer is formed by homoepitaxial growth based on the substrate; Word lines penetrate the alternating layers of the semiconductor and oxide layers; A gate signal line includes the word line and multiple layers of first sub-gates. The word line includes multiple alternating and electrically connected second sub-gates and connecting lines. The second sub-gate layer is on the same layer as the semiconductor layer, and the first sub-gate is disposed around the periphery of the second sub-gate on the same layer. A multilayer gate insulating layer, wherein the gate insulating layer is on the same layer as the semiconductor layer, is disposed around the second sub-gate on the same layer, surrounds the first sub-gate on the same layer, and is surrounded by the semiconductor layer on the same layer.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes: The second electrode penetrates through multiple alternating layers of the semiconductor layer and the oxide layer; The capacitor dielectric layer includes a first capacitor dielectric layer and multiple layers of second capacitor dielectric layers. The first capacitor dielectric layer is wound around the periphery of the second electrode, and each of the multiple layers of second capacitor dielectric layers is wound around the periphery of the first capacitor dielectric layer. The first electrode is a multilayer first electrode, which is co-layered with the corresponding semiconductor layer and is disposed around the periphery of the first capacitor dielectric layer, and encapsulates the second capacitor dielectric layer of the same layer.

10. An electronic device, characterized in that, include: Semiconductor devices manufactured using the manufacturing method described in any one of claims 1 to 7; or, The semiconductor device as described in any one of claims 8 to 9.

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