Semiconductor device and method of manufacturing the same, electronic device

Abstract

The application provides a semiconductor device, a manufacturing method and an electronic device. The semiconductor device manufacturing method comprises: manufacturing a stack structure comprising a connection line region and a common bit line region connected along a first direction; forming a trench extending along a second direction through the stack structure in the common bit line region; based on lateral etching of the trench on a sacrifice layer, forming a plurality of first channels in communication with the trench; manufacturing a first barrier layer covering the side surface of the first channel; forming a first conductive layer covering the first barrier layer and a dielectric filling layer filling the first channel and the trench; forming a plurality of contact holes in the connection line region stopping at different sacrifice layers; removing the sacrifice layer exposed at the bottom of each contact hole to obtain a second channel in communication with the contact hole and expose the first barrier layer corresponding to each contact hole; and forming a connection line in the contact hole and the corresponding second channel. The application designs the first barrier layer to block damage to the first conductive layer during lateral etching, so that the common bit line meets the design requirements.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] This application proposes a semiconductor device and its manufacturing method, as well as an electronic device, which can solve the technical problem that the common bit line is easily damaged during the lateral etching process in related technologies.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: alternately manufacturing an isolation layer and a sacrificial layer on one side of a substrate to obtain a stacked structure, wherein the stacked structure includes a connection line region, a common bit line region, and a device region sequentially connected along a first direction; Based on the patterning process, a trench is formed in the common bit line region that penetrates the stacked structure and extends along the second direction, wherein the first direction intersects the second direction and is parallel to the substrate. The sacrificial layer is laterally etched based on the trench to form a plurality of first channels that are connected to the trench and spaced apart along a third direction perpendicular to the substrate; A first barrier layer is formed on the side of the first channel based on the trench; A first conductive layer covering the first barrier layer is formed based on the trench, and a dielectric filling layer is filled in the first channel and the trench, wherein the first barrier layer is electrically connected to the first conductive layer. Based on the patterning process, multiple contact holes are formed in the connecting line area, which are spaced apart along the second direction, penetrate the stacked structure along the third direction, and stop at different sacrificial layers. Remove the sacrificial layer exposed at the bottom of each contact hole to obtain a second channel communicating with the corresponding contact hole, thereby exposing the first barrier layer corresponding to the contact hole; A connecting line is formed between the contact hole and the corresponding second channel, such that the connecting line is electrically connected to the corresponding first barrier layer.

[0006] Optionally, a first barrier layer is formed based on the trench to cover the side of the first channel, comprising: A semiconductor barrier layer is formed covering the side of the first channel; A first metal layer is formed to cover the semiconductor barrier layer; Based on the annealing process, the first barrier layer covering the side of the first channel is obtained; Remove the remaining first metal layer.

[0007] Optionally, a semiconductor barrier layer is formed covering the side of the first channel, comprising: An initial semiconductor barrier layer is formed covering the inner wall of the trench and the first channel; An initial barrier layer is formed that fills the multi-layered first channel and conformally covers the inner wall of the trench; Remove the initial barrier layer on the inner wall of the trench and part of the initial barrier layer in the first channel to obtain a barrier layer located on the side of the first channel. Remove the initial semiconductor barrier layer that is not covered by the barrier layer to obtain the semiconductor barrier layer covering the side of the first channel.

[0008] Optionally, after removing the initial semiconductor barrier layer not covered by the barrier layer to obtain the semiconductor barrier layer covering the side of the first channel, and before forming the first metal layer covering the semiconductor barrier layer, the process includes: The barrier layer in the first channel is removed by etching.

[0009] Optionally, after alternately fabricating an isolation layer and a sacrificial layer on one side of the substrate to obtain a stacked structure, and based on a patterning process, forming a trench in the common bit line region that penetrates the stacked structure and extends along a second direction parallel to the substrate, the method further includes: Based on a patterning process, multiple device holes are formed in the device region that penetrate the stacked structure; A second metal layer is formed covering the plurality of device holes and the stacked structure; Based on the annealing process, a second barrier layer is obtained covering the bottom of the multiple device holes; Remove the remaining second metal layer; A sacrificial material is formed to fill the holes in the device.

[0010] Optionally, after forming the sacrificial material filling the device apertures, and before laterally etching the sacrificial layer based on the trenches to form a plurality of first channels communicating with the trenches and spaced apart in a third direction perpendicular to the substrate, the method includes: A third barrier layer is formed to cover the bottom of the trench.

[0011] Optionally, a first conductive layer covering the first barrier layer is formed based on the trench, and a dielectric filling layer is formed filling the first channel and the trench, including: An initial first conductive layer is formed to cover and fill the trench and the first channel; Remove the initial first conductive layer in the trench and part of the initial first conductive layer in the first channel to obtain the first conductive layer that fills the side of the first channel and covers the corresponding first barrier layer. A medium filling layer is formed to fill the trench and the first channel.

[0012] Optionally, based on a patterning process, a plurality of contact holes are formed in the connecting line region, spaced apart along the second direction and penetrating the stacked structure along the third direction and ending at different sacrificial layers, including: In the connecting line region, a plurality of stepped structures with different heights are formed along the second direction; An insulating layer is formed covering the multiple stepped structures; A plurality of contact holes are formed by a patterning process, which are spaced apart along the second direction and penetrate the insulating layer and the isolation layer along the third direction, with the bottom of each contact hole exposing the corresponding sacrificial layer.

[0013] Secondly, embodiments of this application provide a semiconductor device, including: A stacked structure disposed on a substrate, wherein interconnecting lines, common bit lines and storage structures are sequentially arranged and electrically connected along a first direction. The storage structure includes a multilayer storage array stacked along a third direction perpendicular to the substrate. The storage array includes at least one bit line extending along the first direction and a plurality of storage cells arranged in an array on both sides of the bit line. The common bit line extends along the second direction and includes multiple first conductive layers arranged along the first direction on both sides of the trench penetrating the stacked structure and stacked at intervals along the third direction. Each first conductive layer is electrically connected to a first barrier layer on the side away from the trench. The second direction intersects the first direction and is parallel to the substrate. The number of connecting lines is multiple and they are spaced apart along the second direction. Each connecting line includes a vertical portion that penetrates the stacked structure along the third direction and a horizontal portion that extends along the first direction. The horizontal portion is electrically connected to the first conductive layer of the corresponding layer through the corresponding first barrier layer.

[0014] Optionally, the connecting lines have a stepped structure, and the horizontal portions of the plurality of connecting lines arranged sequentially along the second direction are electrically connected to the first barrier layer of different layers.

[0015] Optionally, a second barrier layer is provided at the bottom of the storage structure.

[0016] Optionally, the trench is filled with a dielectric filling layer, and a third barrier layer is disposed between the dielectric filling layer and the substrate.

[0017] Thirdly, embodiments of this application provide an electronic device, comprising: a semiconductor device manufactured using the aforementioned semiconductor device manufacturing method; or, Semiconductor devices as described in the above embodiments.

[0018] The beneficial technical effects of the technical solution provided in this application include: by designing a conductive first barrier layer on the side of the first channel, the first barrier layer and the first conductive layer of the common bit line are electrically connected. When the sacrificial layer communicating with the contact hole is etched laterally, the first conductive layer can be avoided due to the barrier of the first barrier layer, thus ensuring that the first conductive layer meets the design requirements. Furthermore, since the connecting line is also electrically connected to the first barrier layer, the first barrier layer can be used to realize the electrical connection between the common bit line and the connecting line, thereby realizing the electrical connection between the connecting line in the connecting line area and the common bit line in the common bit line area, ensuring the normal operation of the semiconductor device.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0020] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic diagram of a semiconductor device manufacturing method provided in an embodiment of this application; Figures 2a-36 This is a schematic diagram of the film structure after each step of a semiconductor device manufacturing method is completed, as provided in an embodiment of this application. Figure 2b for Figure 2a A top-down view. Figure 12 for Figure 11 A magnified view of the selected area; Figure 37 This is a top view schematic diagram of a semiconductor device provided in an embodiment of this application. Explanation of reference numerals in the attached figures: 100-substrate; 110 - Layered structure; 111 - Isolation layer; 1111 - First isolation layer; 1112 - Second isolation layer; 1113 - Third isolation layer; 1114 - Fourth isolation layer; 1115 - Fifth isolation layer; 1116 - Sixth isolation layer; 112 - Sacrificial layer; 120 - Trench; 130 - First channel; 140 - First barrier layer; 150 - First conductive layer; 151 - Initial first conductive layer; 160 - Dielectric filling layer; 170 - Contact hole; 180 - Second channel; 190 - Connecting line; 191 - Vertical part; 192 - Horizontal part; 200 - Semiconductor barrier layer; 210 - First metal layer; 220 - Barrier layer; 201 - Initial semiconductor barrier layer; 221 - Initial barrier layer; 230 - Device via; 240 - Second metal layer; 250 - Second barrier layer; 260 - Sacrificial material; 270 - Third barrier layer; 280 - Third metal layer; 290 - Step structure; 300 - First photoresist structure; 310 - Second photoresist structure; 320 - Third photoresist structure; 330 - Insulating layer; 340 - Auxiliary groove; 350 - Common bit line; 360 - Memory cell; 361 - Bit line; 362 - Transistor; 363 - Capacitor. Detailed Implementation

[0021] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0022] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in the specification of this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" can be implemented as "A," or as "B," or as "A and B."

[0023] In related technologies, an isolation layer, such as oxide, and a sacrificial layer, such as nitride, are sequentially and alternately fabricated on a substrate as a stacked structure. Transistors and bit lines are then fabricated on this stacked structure, and finally, interconnects electrically connected to the bit lines are fabricated on the stacked structure. During interconnect fabrication, the nitride sacrificial layer is laterally etched using contact holes, and then filled with a conductive metallic material to form the interconnect.

[0024] Due to insufficient selectivity for the nitride sacrificial layer, excessive damage can easily occur to the conductive materials of the common bit line structure, such as titanium nitride (TIN), during lateral etching.

[0025] Furthermore, in transistor fabrication, after the device vias are formed, the silicon substrate is exposed, and sacrificial material must first be filled into the vias. During the subsequent etching of the sacrificial material, the inventors discovered that the exposed silicon interface suffers varying degrees of loss, causing damage to the silicon substrate.

[0026] To address the issue that the lateral etching process in related technologies can easily cause excessive damage to the common bit line structure, thus failing to meet the design requirements of the common bit line, this application provides a method for manufacturing a semiconductor device.

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0028] Some embodiments of this application provide a method for manufacturing a semiconductor device, and a schematic flowchart of the manufacturing method is shown below. Figure 1 As shown, the method includes steps S101 to S108.

[0029] S101: An isolation layer 111 and a sacrificial layer 112 are alternately fabricated on one side of a substrate 100 to obtain a stacked structure 110. The stacked structure 110 includes a connection line region, a common bit line region, and a device region connected sequentially along a first direction.

[0030] S102: Based on the patterning process, a trench 120 is formed in the common bit line region that penetrates the stacked structure 110 and extends along the second direction. The first direction and the second direction intersect and are both parallel to the substrate 100.

[0031] S103: Based on the trench 120, the sacrificial layer 112 is etched laterally to form a plurality of first channels 130 that are connected to the trench 120 and are spaced apart along a third direction perpendicular to the substrate 100.

[0032] S104: A first barrier layer 140 is formed based on the trench 120 to cover the side of the first channel 130.

[0033] S105: A first conductive layer 150 covering the first barrier layer 140 and a dielectric filling layer 160 filling the first channel 130 and the trench 120 are formed based on the trench 120, and the first barrier layer 140 is electrically connected to the first conductive layer 150.

[0034] S106: Based on a patterning process, multiple contact holes 170 are formed in the connection line area, which are spaced apart along the second direction, penetrate the stacked structure 110 along the third direction, and stop at different sacrificial layers 112.

[0035] S107: Remove the sacrificial layer 112 exposed at the bottom of each contact hole 170 to obtain a second channel 180 communicating with the contact hole 170, exposing the first barrier layer 140 corresponding to the contact hole 170.

[0036] S108: A connecting line 190 is formed in the contact hole 170 and the corresponding second channel 180, so that the connecting line 190 is electrically connected to the corresponding first barrier layer 140.

[0037] This application designs a conductive first barrier layer 140 on the side of the first channel 130, thereby electrically connecting the first barrier layer 140 and the first conductive layer 150 of the common bit line 350. When laterally etching the sacrificial layer 112 at the bottom of the contact hole 170, the first conductive layer 150 can be prevented from being etched due to the barrier of the first barrier layer 140, thus ensuring that the first conductive layer 150 meets the design requirements. Furthermore, since the connecting line 190 is also electrically connected to the first barrier layer 140, the first conductive layer 150 and the connecting line 190 can be electrically connected using the first barrier layer 140, thereby achieving the electrical connection between the connecting line 190 located in the connecting line region and the common bit line 350 located in the common bit line region, ensuring the normal operation of the semiconductor device.

[0038] like Figure 2a and Figure 2b As shown, the stacked structure 110 includes an isolation layer 111 and a sacrificial layer 112 alternately fabricated on one side of the substrate 100. The stacked structure 110 includes a connection line region, a common bit line region, and a device region sequentially connected along a first direction. Optionally, in some embodiments of this application, the substrate 100 is a silicon substrate 100, the material of the isolation layer 111 includes silicon oxide (SiO), and the material of the sacrificial layer 112 includes a nitride, such as silicon nitride (Si3N4).

[0039] Optionally, after alternately fabricating an isolation layer 111 and a sacrificial layer 112 on one side of the substrate 100 to obtain a stacked structure 110, a plurality of device vias 230 penetrating the stacked structure 110 are formed in the device region based on a patterning process, resulting in... Figure 3The diagram shows a film structure. Device aperture 230 is used to fabricate a memory cell 360 that includes at least transistor 362 or also includes capacitor 363.

[0040] Optionally, after forming a plurality of device holes 230 penetrating the stacked structure 110 in the device region, a second barrier layer 250 is formed covering the bottom of the device holes 230, including: A second metal layer 240 is formed covering multiple device holes 230 and the stacked structure 110, resulting in the following: Figure 4 The diagram shows a schematic of the membrane structure.

[0041] Based on the annealing process, a second barrier layer 250 is obtained covering the bottom of multiple device holes 230, resulting in... Figure 5 The diagram shows a schematic of the membrane structure.

[0042] Remove the remaining second metal layer 240 to obtain as follows Figure 6 The diagram shows a schematic of the membrane structure.

[0043] Optionally, after removing the remaining second metal layer 240, a sacrificial material 260 is formed to fill the plurality of device holes 230, resulting in... Figure 7 The diagram shows a schematic of the membrane structure.

[0044] After the device aperture 230 is formed, the silicon substrate 100 is exposed. During the etching process of the sacrificial material 260 when manufacturing the transistor 362, the exposed silicon interface will suffer varying degrees of loss. This application addresses this by covering the exposed silicon substrate 100 surface within the device aperture 230 with a second barrier layer 250. During the etching process of the sacrificial material 260, the second barrier layer 250 prevents etching of the silicon substrate 100, thereby ensuring the flatness of the silicon substrate 100 surface and guaranteeing the performance of the silicon substrate 100.

[0045] Optionally, after forming the sacrificial material 260 that fills the multiple device holes 230, a trench 120 extending through the stacked structure 110 and along the second direction is formed in the common bit line region based on a patterning process, resulting in... Figure 8 The diagram shows a schematic of the membrane structure.

[0046] Optionally, after forming a trench 120 that penetrates the laminated structure 110 and extends along the second direction in the common bit line region, a third barrier layer 270 covering the bottom of the trench 120 is formed, including: A third metal layer 280 is formed to cover the trench 120 and the stacked structure 110, resulting in the following: Figure 9 The diagram shows a schematic of the membrane structure.

[0047] Based on the annealing process, a third barrier layer 270 is obtained covering the bottom of the trench 120, resulting in... Figure 10The diagram shows a schematic of the membrane structure.

[0048] After removing the third metal layer 280 covering the sidewalls of trench 120 and the laminated structure 110, the following is obtained: Figure 11 and Figure 12 The diagram shows a schematic of the membrane structure.

[0049] Optionally, after removing the third metal layer 280 covering the sidewalls of the trench 120 and the stacked structure 110, the sacrificial layer 112 is etched laterally based on the trench 120 to form a plurality of first channels 130 that communicate with the trench 120 and are spaced apart along a third direction perpendicular to the substrate 100, resulting in... Figure 13 The diagram shows a schematic of the membrane structure.

[0050] By covering the bottom of the trench 120 with a third barrier layer 270, when the sacrificial layer 112 is laterally etched to form a plurality of first channels 130 spaced apart along the third direction, the third barrier layer 270 can prevent etching to the silicon substrate 100 due to its blocking effect, thereby ensuring the flatness of the surface of the silicon substrate 100 and ensuring the performance of the silicon substrate 100.

[0051] Optionally, after forming a plurality of first channels 130 that are in communication with the trench 120 and are spaced apart along a third direction perpendicular to the substrate 100, a first barrier layer 140 covering the sides of the first channels 130 is formed based on the trench 120.

[0052] A first barrier layer 140 is formed based on the trench 120 to cover the side of the first channel 130, including: A semiconductor barrier layer 200 is formed covering the sides of the first channel 130, including: An initial semiconductor barrier layer 201 is formed covering the inner walls of the trench 120 and the first channel 130, resulting in... Figure 14 The diagram shows a schematic of the membrane structure.

[0053] An initial barrier layer 221 is formed, filling the first channel 130 and conformally covering the inner wall of the trench 120, resulting in... Figure 15 The diagram shows a schematic of the membrane structure.

[0054] By removing the initial barrier layer 221 from the inner wall of the trench 120 and a portion of the initial barrier layer 221 within the first channel 130, a barrier layer 220 located on the side of the first channel 130 is obtained, as shown below. Figure 16 The diagram shown is a schematic of the membrane structure. Removing the initial semiconductor barrier layer 201 not covered by the barrier layer 220 yields a semiconductor barrier layer 200 covering the side of the first channel 130, resulting in... Figure 17 The diagram shows a schematic of the membrane structure.

[0055] The barrier layer 220 within the first channel 130 is removed by etching, forming a semiconductor barrier layer 200 covering the sides of the first channel 130, resulting in... Figure 18 The diagram shows a schematic of the membrane structure.

[0056] After fabricating the conformal covering trench 120 and the initial semiconductor layer of the multilayer first channel 130, a barrier layer 220 is fabricated covering the side of the first channel 130. This barrier layer 220 blocks the portion of the initial semiconductor barrier layer 201 located on the side of the first channel 130 near the via. When removing the conformal covering trench 120 and the initial semiconductor barrier layer 201 of the first channel 130, the barrier layer 220 prevents etching of the portion of the initial semiconductor barrier layer 201 covering the side of the first channel 130, thus allowing the semiconductor barrier layer 200 covering only the side of the first channel 130 to be successfully formed.

[0057] Optionally, the initial barrier layer 221 may be made of silicon oxide (SiO), which is a product of the natural oxidation of silicon. Therefore, it has a natural affinity for silicon-based materials, making it easy to form a high-quality interface. Furthermore, a high-quality silicon oxide layer typically has a very smooth surface, allowing for precise control of the silicon oxide layer thickness during subsequent etching, thereby precisely controlling the thickness of the semiconductor barrier layer.

[0058] Optionally, after forming the semiconductor barrier layer 200 covering the side of the first channel 130, the first barrier layer 140 formed on the side of the first channel 130 further includes: A first metal layer 210 is formed covering the semiconductor barrier layer 200 and the first channel 130, resulting in... Figure 19 The diagram shows a schematic of the membrane structure.

[0059] Based on the annealing process, a first barrier layer 140 is obtained covering the side of the first channel 130, resulting in... Figure 20 The diagram shows a schematic of the membrane structure.

[0060] After removing the remaining first metal layer 210, the following is obtained: Figure 21 The diagram shows a schematic of the membrane structure.

[0061] Optionally, the materials of the first barrier layer 140, the second barrier layer 250, and the third barrier layer 270 include conductive metal semiconductor compounds. For example, the metal semiconductor compound includes metal silicides, and the semiconductor barrier layer 200 on the side of the first channel 130 can react with the first metal layer 210 at high temperature to form metal silicides. Metal silicides typically have high hardness and good mechanical strength, which can prevent damage to the first conductive layer 150 during lateral etching. In addition, some metal silicides can effectively prevent the diffusion of metal atoms into the silicon substrate 100, which helps maintain the stability and reliability of the semiconductor device. Furthermore, using metal silicides as barrier layers is easy to integrate with existing silicon-based manufacturing processes without requiring significant changes to the production process, simplifying the production flow and reducing costs.

[0062] Metal silicides also possess relatively low resistivity, which allows them to significantly reduce contact resistance when used as contact materials in semiconductor devices, thereby improving device performance and reducing power consumption. Furthermore, compared to some traditional metals, some metal silicides have a smaller environmental impact, aligning with modern industrial requirements for green manufacturing. The metal silicides in this application include, but are not limited to, nickel silicide (NiSi), cobalt silicide (CoSi and CoSi2), tungsten silicide (WSix or WSi2), and chromium silicide (CrSi2).

[0063] Optionally, the semiconductor barrier layer 200 is made of polycrystalline silicon (poly) or monocrystalline silicon (Si). Since silicon (whether monocrystalline or polycrystalline) has high surface activity, it can react with various metals. High-temperature annealing allows metal atoms to diffuse under high temperatures, causing silicon and metal to react and form metal silicides. Furthermore, many metals have similar coefficients of thermal expansion to silicon, reducing stress caused by temperature changes and thus improving bonding strength and stability. However, silicon oxide (SiO) as the isolation layer 111 and silicon nitride (Si3N4) as the sacrificial layer 112 are typically dense amorphous materials, especially silicon oxide (SiO), which often exists as a naturally or artificially grown passivation layer. This dense structure hinders the diffusion of metal atoms, making it difficult to form metal-oxide or metal-nitride compounds. This difference in chemical properties allows metal silicides to be formed only on the sides of the first channel 130 as the first barrier layer 140, without forming metal silicides on the sidewalls of the first channel 130 and the via sidewalls.

[0064] Optionally, the first metal layer 210 of this application may be selected from different metals, thereby adjusting the work function of the metal silicide to optimize its interface characteristics with silicon, which is crucial for forming high-quality contacts.

[0065] In this application, the third barrier layer 270, the second barrier layer 250, and the first barrier layer 140 are metal silicides manufactured using the same process. Using the same process simplifies the entire manufacturing process; through standardized processes, production equipment can operate efficiently for longer periods, reducing downtime and maintenance costs. Furthermore, the first barrier layer 140 and the second barrier layer 250 manufactured using the same process conditions are more likely to maintain consistent characteristics and performance, thereby improving the overall quality of the product.

[0066] Optionally, after removing the remaining first metal layer 210 to obtain a first barrier layer 140 covering the sides of the first channel 130, a common bit line 350 filling the first channel 130 and the trench 120 is formed. The common bit line 350 includes a first conductive layer 150 covering the first barrier layer 140, and a dielectric filling layer 160 filling the first channel 130 and the trench 120. It includes: An initial first conductive layer 151 is formed to cover and fill the trench 120 and the first channel 130. The initial first conductive layer 151 located in the first channel 130 covers the corresponding first barrier layer 140, resulting in the following: Figure 22 The diagram shows a schematic of the membrane structure.

[0067] After removing the initial first conductive layer 151 in the trench 120 and a portion of the initial first conductive layer 151 in the first channel 130, a first conductive layer 150 is obtained that fills the side of the first channel 130 and covers the corresponding first barrier layer 140, resulting in the following: Figure 23 The diagram shows a schematic of the membrane structure.

[0068] A dielectric filling layer 160 is formed to fill the trench 120 and the multilayer first channel 130, thereby electrically connecting the first barrier layer 140 and the first conductive layer 150, resulting in... Figure 24 The diagram shows a schematic of the membrane structure.

[0069] Because a third barrier layer 270 is formed at the bottom of the trench 120 before the first conductive layer 150 is formed, when the portion of the initial first conductive layer 151 covering the conformal trench 120 is removed, the barrier effect of the third barrier layer 270 can prevent etching to the silicon substrate 100, thus avoiding damage to the silicon substrate 100 and improving the performance of the semiconductor device.

[0070] Optionally, after forming the filling trench 120 and the dielectric filling layer 160 of the multilayer first channel 130, a connecting line 190 is formed in the connecting line region.

[0071] Forming the connecting line 190 in the connecting line region includes: based on a patterning process, forming a plurality of contact holes 170 in the connecting line region that are spaced apart along the second direction, penetrate the stacked structure 110 along the third direction, and terminate at different sacrificial layers 112, including: Multiple stepped structures 290 with different heights are formed along the second direction.

[0072] Optionally, the stacked structure 110 of this application includes a stack of five isolation layers 111-sacrificial layers 112 and a top isolation layer 111 as an example, and along the third direction from bottom to top are the first isolation layer 1111 to the sixth isolation layer 1116.

[0073] Optionally, in the connecting line region, a plurality of stepped structures 290 with different heights along the second direction are manufactured, including: A first photoresist layer is fabricated on one side of the sixth isolation layer 1116; The first photoresist layer is exposed and developed to form a first photoresist structure 300, such that the first photoresist structure 300 covers half of the sixth isolation layer 1116, resulting in... Figure 25 The diagram shows a schematic of the membrane structure.

[0074] Based on the first photoresist structure 300, the sixth isolation layer 1116 at the top and the adjacent sacrificial layer 112 are etched to obtain the auxiliary trench 340 that stops at the fifth isolation layer 1115, resulting in... Figure 26 The diagram shows a schematic of the membrane structure.

[0075] The first photoresist structure 300 is stripped off.

[0076] A second photoresist layer is fabricated on one side of the sixth isolation layer 1116 and the fifth isolation layer 1115; The second photoresist layer is exposed and developed to form a second photoresist structure 310, such that the second photoresist structure 310 is distributed at both ends and covers half of the remaining portion of the sixth isolation layer 1116 and half of the exposed portion of the fifth isolation layer 1115, respectively, to obtain the following... Figure 27 The diagram shows a schematic of the membrane structure.

[0077] Based on the second photoresist structure 310, two etching processes are performed to obtain two auxiliary trenches 340 that stop at the fourth isolation layer 1114 and the third isolation layer 1113, respectively. The two auxiliary trenches 340 are connected to each other, resulting in... Figure 28 The diagram shows a schematic of the membrane structure.

[0078] The second photoresist structure 310 is retracted to obtain a third photoresist structure 320 distributed at both ends. The third photoresist structure 320 covers half of the remaining portion of the sixth isolation layer 1116 and half of the remaining portion of the fifth isolation layer 1115, respectively, resulting in the following... Figure 29 The diagram shows a schematic of the membrane structure.

[0079] Etching is performed based on the third photoresist structure 320 to obtain four auxiliary trenches 340 that stop at the fifth oxide layer, the fourth isolation layer 1114, the third isolation layer 1113, and the second isolation layer 1112, respectively. The four auxiliary trenches 340 are interconnected, resulting in... Figure 30 The diagram shows a schematic of the membrane structure.

[0080] After peeling off the third photoresist structure 320, multiple stepped structures 290 with different heights along the second direction are obtained, as shown below. Figure 31 The diagram shows a schematic of the membrane structure.

[0081] This application designs different photoresist structures and uses different photoresist structures as masks to etch the stacked structure sequentially, thereby obtaining four auxiliary trenches 340 that stop at different isolation layers 111, so that the connection line area forms a stepped structure 290.

[0082] Optionally, after obtaining multiple stepped structures 290 with different heights along the second direction, based on a patterning process, multiple contact holes 170 are formed in the connecting line region, spaced apart along the second direction and penetrating the stacked structure 110 along the third direction and ending at different sacrificial layers 112, further comprising: An insulating layer 330 is formed covering the stepped structure 290, resulting in... Figure 32 The diagram shows a schematic of the membrane structure.

[0083] Based on a patterning process, multiple contact holes 170 are formed in the connecting line area, spaced apart along the second direction and penetrating the insulating layer 330 and the isolation layer 111 along the third direction. This results in multiple contact holes 170 stopping at different sacrificial layers 112, with the bottom of each contact hole 170 exposing the corresponding sacrificial layer 112, resulting in... Figure 33 , 34 The diagram shows a schematic of the membrane structure.

[0084] Before forming the contact hole 170 for filling the connection line, a stepped structure 290 along the second direction is manufactured, and then an insulating layer 330 filling multiple auxiliary grooves 340 is formed. When the sacrificial layers 112 are laterally etched based on the contact hole 170 stopping at different sacrificial layers 112, the insulating layer 330 acts as a blocking structure for the sacrificial layers 112 located on both sides of the contact hole 170, so that during lateral etching, only the sacrificial layer 112 exposed at the bottom of the contact hole 170 can be etched, and the sacrificial layers 112 on both sides of the contact hole 170 will not be etched. After the corresponding sacrificial layer 112 is exposed at the bottom of each contact hole 170, forming the connecting line 190 in the connecting line area also includes: By removing the sacrificial layer 112 exposed at the bottom of each contact hole 170 through lateral etching, a second channel 180 communicating with the contact hole 170 is obtained, exposing the first barrier layer 140 corresponding to the contact hole 170, resulting in... Figure 35 The diagram shows a schematic of the membrane structure.

[0085] A connecting line 190 is formed within the contact hole 170 and the corresponding second channel 180, such that the connecting line 190 is electrically connected to the corresponding first barrier layer 140, resulting in... Figure 36 The diagram shows a schematic of the membrane structure.

[0086] The sacrificial layer 112 exposed at the bottom of each contact hole 170 is removed by lateral etching, thereby forming a second channel 180 communicating with the contact hole 170, and the second channels 180 arranged sequentially along the second direction form a stepped structure to expose the first barrier layer 140 corresponding to each contact hole 170.

[0087] A connecting line 190 is formed by filling the contact hole 170 and the second channel 180 with conductive material. The connecting line 190 includes a vertical portion 191 filled in the contact hole 170 and a horizontal portion 192 filled in the second channel. The horizontal portion 192 of the connecting line 190 arranged sequentially along the second direction also forms a stepped structure, thereby achieving the effect of electrically connecting the horizontal portion 192 arranged sequentially along the second direction with the first conductive layer 150 of the common bit line 350 through the corresponding first barrier layer 140.

[0088] Optionally, a memory structure is fabricated in the device region after a connection line 190 is formed between the contact hole 170 and the corresponding second channel 180, such that the connection line 190 is electrically connected to the corresponding first barrier layer 140.

[0089] Fabricating the memory structure in the device region includes: etching sacrificial material 260 based on a patterning process to expose a second barrier layer 250 at the bottom of the device aperture 230.

[0090] Since the bottom of the device hole 230 is covered by a second barrier layer 250, the silicon substrate 100 can be avoided during the etching of the sacrificial material 260, thus ensuring the performance of the silicon substrate 100.

[0091] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0092] In the description of the embodiments of this application, it should be understood that a "layer" refers to a thin film made of a certain material on a substrate 100 using a deposition or coating process. If the thin film does not require patterning during the entire fabrication process, the thin film can be called a layer. If the thin film requires patterning during the entire fabrication process, the "layer" after patterning includes at least one "pattern".

[0093] Based on the same inventive concept, some embodiments of this application provide a semiconductor device. (See also...) Figure 36 and Figure 37 The semiconductor device includes a stacked structure 110 disposed on a substrate 100, wherein a connection line region, a common bit line region, and a device region are sequentially connected along a first direction in the stacked structure 110. Connection lines 190, a common bit line 350, and a memory structure are sequentially arranged and electrically connected along the first direction on the stacked structure 110. Optionally, the connection lines 190 are fabricated in the connection line region, the common bit line 350 is fabricated in the common bit line region, and the memory structure is fabricated in the device region.

[0094] Reference Figure 37 The storage structure includes a multilayer storage array stacked along a third direction perpendicular to the substrate 100. The storage array includes at least one bit line 361 extending along a first direction and a plurality of storage cells 360 arranged in an array on both sides of the bit line 361.

[0095] Optionally, the memory cell 360 includes one or two transistors 362 arranged along the second direction. The memory cell 360 may include two electrically connected transistors 362 to form a 2T0C structure; or the memory cell 360 may include one transistor 362 and a capacitor 363 electrically connected thereto to form a 1T1C structure.

[0096] In practical applications, the memory structure can be a single-layer memory array or a multi-layer stacked memory array. The memory structure in this application includes multiple memory arrays stacked along a third direction. Each memory cell 360 includes a transistor 362 and a capacitor 363, forming a 1T1C structure. The capacitor 363 is electrically connected to the side of the transistor 362 away from the bit line 361.

[0097] Reference Figure 36 and Figure 37 The common bit line 350 extends along the second direction and includes multiple first conductive layers 150 arranged along the first direction on both sides of the trench 120 penetrating the stacked structure 110 and stacked at intervals along the third direction. Each first conductive layer 150 is electrically connected to a first barrier layer 140 on the side away from the trench 120. The second direction intersects the first direction and is parallel to the substrate 100.

[0098] Reference Figure 33 , Figure 36 and Figure 37 The number of connecting lines 190 is multiple and they are arranged at intervals along the second direction. The connecting lines 190 include a vertical portion 191 that penetrates the stacked structure 110 along the third direction and a horizontal portion 192 that extends along the first direction. The horizontal portion 192 is electrically connected to the corresponding first conductive layer 150 through the corresponding first barrier layer 140.

[0099] Reference Figure 34 and Figure 35 When the sacrificial layer 112 at the bottom of the contact hole 170 is etched laterally, the first conductive layer 150 can be avoided due to the obstruction of the first barrier layer 140. After the connection line 190 is manufactured, the first conductive layer 150 and the connection line 190 are electrically connected through the corresponding first barrier layer 140.

[0100] Optionally, refer to Figure 33 , Figure 36 and Figure 37 The connecting line 190 has a stepped structure 290, and the horizontal portions 192 of the multiple connecting lines 190 arranged sequentially along the second direction are electrically connected to the first barrier layer 140 of different layers.

[0101] Optionally, refer to Figure 8 A second barrier layer 250 is provided at the bottom of the storage structure. Optionally, a second barrier layer 250 is provided at the bottom of a row of storage cells 360 arranged at intervals along a third direction.

[0102] Optionally, refer to Figure 36 The trench 120 is filled with a dielectric filling layer 160, and a third barrier layer 270 is disposed between the dielectric filling layer 160 and the substrate 100.

[0103] Based on the same inventive concept, some embodiments of this application provide an electronic device, which includes any of the semiconductor devices provided in the above embodiments, or a semiconductor device manufactured according to the manufacturing method of the semiconductor device provided in the above format examples.

[0104] In some embodiments of this application, since the electronic device uses any of the semiconductor devices provided in the foregoing embodiments, the principle and technical effects are described in the foregoing embodiments and will not be repeated here.

[0105] Optionally, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or power bank.

[0106] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can incorporate any of the semiconductor devices provided in the above embodiments of this application into different devices according to actual application needs, thereby obtaining the electronic devices provided in some embodiments of this application.

[0107] Those skilled in the art will understand that the electronic devices provided in some embodiments of this application may be specifically designed and manufactured for a desired purpose, or may include known devices in general-purpose computers. These devices have any of the semiconductor devices provided in the various embodiments described above.

[0108] By applying the embodiments of this application, at least the following beneficial effects can be achieved: This application designs a conductive first barrier layer 140 on the side of the first channel 130, thereby electrically connecting the first barrier layer 140 and the first conductive layer 150 of the common bit line 350. When laterally etching the sacrificial layer 112 at the bottom of the contact hole 170, the first conductive layer 150 can be avoided due to the barrier of the first barrier layer 140, thus ensuring that the first conductive layer 150 meets the design requirements. Furthermore, since the connecting line 190 is also electrically connected to the first barrier layer 140, the first conductive layer 150 and the connecting line 190 can be electrically connected using the first barrier layer 140, realizing the electrical connection between the connecting line 190 manufactured in the connecting line region and the common bit line 350 manufactured in the common bit line region, ensuring the normal operation of the semiconductor device.

[0109] A second barrier layer 250 is fabricated at the bottom of the device hole 230. During the etching of the sacrificial material 260, the second barrier layer 250 can prevent etching of the silicon substrate 100, thereby ensuring the flatness of the surface of the silicon substrate 100 and ensuring the performance of the silicon substrate 100.

[0110] By fabricating a third barrier layer 270 at the bottom of the trench 120 before fabricating the first conductive layer 150, the third barrier layer 270 can prevent etching of the silicon substrate 100 and avoid damage to the silicon substrate 100 when etching away a portion of the initial first conductive layer 151 covering the conformal trench 120, thereby improving the performance of the semiconductor device.

[0111] The first barrier layer 140, the second barrier layer 250, and the third barrier layer 270 are all metal silicides manufactured using the same process. Using the same process simplifies the entire manufacturing process. Standardized processes allow production equipment to operate efficiently for longer periods, reducing downtime and maintenance costs. Furthermore, the first barrier layer 140 and the second barrier layer 250, manufactured using the same process conditions, are more likely to maintain consistent characteristics and performance, thereby improving the overall quality of the product.

[0112] By manufacturing stepped structures 290 that stop at different isolation layers 111 and an insulating layer 330 that fills multiple stepped structures 290, when the sacrificial layers 112 are laterally etched based on the contact holes 170 that stop at different sacrificial layers 112 along the second direction, the insulating layer 330 acts as a blocking structure for the sacrificial layers 112 located on both sides of the contact holes 170, so that only the sacrificial layers 112 exposed at the bottom of the contact holes 170 can be etched during lateral etching, thereby achieving the effect of electrically connecting the horizontal portions 192 of multiple connecting lines 190 arranged sequentially along the second direction with the first conductive layer 150 of the common bit line 350 at different layers.

[0113] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0114] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: An isolation layer and a sacrificial layer are alternately fabricated on one side of a substrate to obtain a stacked structure, the stacked structure including a connection line region, a common bit line region and a device region connected sequentially along a first direction; Based on the patterning process, a groove is formed in the common bit line region that penetrates the stacked structure and extends along the second direction; The first direction intersects the second direction and is parallel to the substrate; The sacrificial layer is laterally etched based on the trench to form a plurality of first channels that are connected to the trench and spaced apart along a third direction perpendicular to the substrate; A first barrier layer is formed based on the trench, covering the side of the first channel; A first conductive layer covering the first barrier layer is formed based on the trench, and a dielectric filling layer is filled in the first channel and the trench, wherein the first barrier layer is electrically connected to the first conductive layer. Based on the patterning process, multiple contact holes are formed in the connecting line area, which are spaced apart along the second direction, penetrate the stacked structure along the third direction, and stop at different sacrificial layers. Remove the sacrificial layer exposed at the bottom of each contact hole to obtain a second channel communicating with the contact hole, thereby exposing the first barrier layer corresponding to each contact hole; A connecting line is formed between the contact hole and the corresponding second channel, such that the connecting line is electrically connected to the corresponding first barrier layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, A first barrier layer is formed based on the trench to cover the side of the first channel, including: A semiconductor barrier layer is formed covering the side of the first channel; A first metal layer is formed to cover the semiconductor barrier layer; Based on the annealing process, the first barrier layer covering the side of the first channel is obtained; Remove the remaining first metal layer.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, Forming a semiconductor barrier layer covering the side of the first channel includes: An initial semiconductor barrier layer is formed covering the inner wall of the trench and the first channel; An initial barrier layer is formed to fill the first channel and conformally cover the inner wall of the trench; Remove the initial barrier layer on the inner wall of the trench and part of the initial barrier layer in the first channel to obtain a barrier layer located on the side of the first channel. Remove the initial semiconductor barrier layer that is not covered by the barrier layer to obtain the semiconductor barrier layer covering the side of the first channel.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, After removing the initial semiconductor barrier layer not covered by the barrier layer to obtain the semiconductor barrier layer covering the side of the first channel, and before forming the first metal layer covering the semiconductor barrier layer, the process includes: The barrier layer in the first channel is removed by etching.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After alternately fabricating an isolation layer and a sacrificial layer on one side of the substrate to obtain a stacked structure, and before forming a trench extending through the stacked structure and along a second direction parallel to the substrate in the common bit line region based on a patterning process, the method further includes: Based on a patterning process, multiple device holes are formed in the device region that penetrate the stacked structure; A second metal layer is formed to cover the device apertures and the stacked structure; Based on the annealing process, a second barrier layer is obtained covering the bottom of the multiple device holes. Remove the remaining second metal layer; A sacrificial material is formed to fill the holes in the device.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, After forming the sacrificial material filling the device apertures, before laterally etching the sacrificial layer based on the trenches to form a plurality of first channels communicating with the trenches and spaced apart along a third direction perpendicular to the substrate, the process includes: A third barrier layer is formed to cover the bottom of the trench.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, A first conductive layer covering the first barrier layer is formed based on the trench, and a dielectric filling layer is filled in the first channel and the trench, comprising: An initial first conductive layer is formed to cover and fill the trench and the first channel; Remove the initial first conductive layer in the trench and part of the initial first conductive layer in the first channel to obtain the first conductive layer that fills the side of the first channel and covers the corresponding first barrier layer. A medium filling layer is formed to fill the trench and the first channel.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Based on a patterning process, multiple contact holes are formed in the connecting line area, spaced apart along the second direction and penetrating the stacked structure along the third direction, ending at different sacrificial layers, including: In the connecting line region, a plurality of stepped structures with different heights are formed along the second direction; An insulating layer is formed covering the stepped structure; A plurality of contact holes are formed by a patterning process, which are spaced apart along the second direction and penetrate the insulating layer and the isolation layer along the third direction, with the bottom of each contact hole exposing the corresponding sacrificial layer.

9. A semiconductor device, characterized in that, The invention includes a stacked structure disposed on a substrate, wherein interconnecting lines, common bit lines, and a storage structure are fabricated on the stacked structure and are sequentially arranged and connected along a first direction. The storage structure includes a multilayer storage array stacked along a third direction perpendicular to the substrate. The storage array includes at least one bit line extending along the first direction and a plurality of storage cells arranged in an array on both sides of the bit line. The common bit line extends along the second direction and includes multiple first conductive layers arranged along the first direction on both sides of the trench penetrating the stacked structure and stacked at intervals along the third direction. Each first conductive layer is electrically connected to a first barrier layer on the side away from the trench. The second direction intersects the first direction and is parallel to the substrate. The number of connecting lines is multiple and they are spaced apart along the second direction. Each connecting line includes a vertical portion that penetrates the stacked structure along the third direction and a horizontal portion that extends along the first direction. The horizontal portion is electrically connected to the corresponding first conductive layer through the corresponding first barrier layer.

10. The semiconductor device according to claim 9, characterized in that, The connecting line has a stepped structure, and the horizontal portions of the plurality of connecting lines arranged sequentially along the second direction are electrically connected to the first barrier layer of different layers.

11. The semiconductor device according to claim 9, characterized in that, A second barrier layer is provided at the bottom of the storage structure.

12. The semiconductor device according to claim 9, characterized in that, The trench is filled with a dielectric filling layer, and a third barrier layer is disposed between the dielectric filling layer and the substrate.

13. An electronic device, characterized in that, include: Semiconductor devices manufactured using the manufacturing method described in any one of claims 1 to 8; or, The semiconductor device as described in any one of claims 9 to 12.

Images