Semiconductor memory device

Abstract

A semiconductor memory device is provided, including: a first semiconductor pattern extending in a first horizontal direction; a second semiconductor pattern having a horizontal width smaller than a horizontal width of the first semiconductor pattern in a second horizontal direction, spaced apart from the first semiconductor pattern in the second horizontal direction, and extending in the first horizontal direction, the second horizontal direction being substantially perpendicular to the first horizontal direction; a gate structure surrounding the first semiconductor pattern and the second semiconductor pattern, and extending in the second horizontal direction; a bit line connected to an end portion of the first semiconductor pattern in the first horizontal direction and extending in a vertical direction; and a capacitor structure connected to another end portion of the first semiconductor pattern in the first horizontal direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and more specifically, to a three-dimensional semiconductor memory device. Background Technology

[0002] With the increasing demand for smaller size, more multifunctionality, and higher performance in electronic products, there is a need for high-capacity semiconductor memory devices, necessitating increased integration to provide these high-capacity devices. While the integration density of two-dimensional semiconductor memory devices has increased, it remains limited, as it is primarily determined by the area occupied by a single memory cell. Summary of the Invention

[0003] The disclosed concept provides a three-dimensional semiconductor memory device with improved operational reliability.

[0004] According to an aspect of the disclosed concept, a semiconductor memory device is provided, comprising: a first semiconductor pattern extending in a first horizontal direction; a second semiconductor pattern having a horizontal width in a second horizontal direction that is smaller than the horizontal width of the first semiconductor pattern, being spaced apart from the first semiconductor pattern in the second horizontal direction, and extending in the first horizontal direction, the second horizontal direction being substantially orthogonal to the first horizontal direction; a gate structure surrounding the first semiconductor pattern and the second semiconductor pattern and extending in the second horizontal direction; a bit line connected to an end of the first semiconductor pattern in the first horizontal direction and extending in a vertical direction; and a capacitor structure connected to another end of the first semiconductor pattern in the first horizontal direction, wherein the second semiconductor pattern is spaced apart from each of the bit line and the capacitor structure.

[0005] According to aspects of the disclosed concept, a semiconductor memory device is provided, comprising: a plurality of first semiconductor patterns, each extending in a first horizontal direction and arranged spaced apart from each other in each of a second horizontal direction and a vertical direction, the second horizontal direction being substantially orthogonal to the first horizontal direction; a plurality of second semiconductor patterns, each extending in the first horizontal direction, each second semiconductor pattern having a horizontal width in the second horizontal direction smaller than the horizontal width of each of the plurality of first semiconductor patterns, arranged spaced apart from each other in each of the second horizontal direction and vertical direction, and alternately arranged spaced apart from the plurality of first semiconductor patterns in the second horizontal direction; and a plurality of gate structures surrounding the plurality of first semiconductor patterns and the plurality of second semiconductor patterns. Each gate structure extends in a second horizontal direction and is arranged spaced apart from each other in a vertical direction; an interlayer insulating layer surrounds a plurality of first semiconductor patterns, a plurality of second semiconductor patterns, and a plurality of gate structures; a plurality of bit lines are connected to the ends of the first semiconductor patterns arranged spaced apart from each other in the vertical direction in the first horizontal direction, each bit line extending in the vertical direction and spaced apart from each other in the second horizontal direction; a line trench filling insulating layer surrounds the plurality of bit lines; a plurality of capacitor structures are connected to the other ends of the plurality of first semiconductor patterns in the first horizontal direction; and a capacitor trench filling insulating layer surrounds the plurality of capacitor structures, wherein the plurality of second semiconductor patterns are spaced apart from the plurality of bit lines and the plurality of capacitor structures.

[0006] According to an aspect of the disclosed concept, a semiconductor memory device is provided, comprising: a plurality of first semiconductor patterns, each extending in a first horizontal direction and arranged spaced apart from each other in each of a second horizontal and a vertical direction, the second horizontal direction being substantially orthogonal to the first horizontal direction; a plurality of second semiconductor patterns extending in the first horizontal direction, each second semiconductor pattern having a horizontal width in the second horizontal direction smaller than the horizontal width of each of the plurality of first semiconductor patterns, arranged spaced apart from each other in each of the second horizontal and vertical directions, and alternately arranged spaced apart from the plurality of first semiconductor patterns in the second horizontal direction; and a plurality of gate structures surrounding the plurality of first semiconductor patterns and the plurality of second semiconductor patterns, each gate structure extending in the second horizontal direction. The plurality of first semiconductor patterns, a plurality of second semiconductor patterns, and a plurality of gate structures are arranged at intervals in the vertical direction; an interlayer insulating layer surrounds a plurality of first semiconductor patterns, a plurality of second semiconductor patterns, and a plurality of gate structures; a plurality of bit lines are connected to the ends of the first semiconductor patterns arranged at intervals in the vertical direction in a first horizontal direction, each bit line extending in the vertical direction and arranged at intervals in the second horizontal direction; a line trench filling insulating layer surrounds the plurality of bit lines; a plurality of capacitor structures are connected to the other ends of the plurality of first semiconductor patterns in the first horizontal direction; and a capacitor trench filling insulating layer surrounds the plurality of capacitor structures, wherein, in the first horizontal direction, the ends of the plurality of second semiconductor patterns are in contact with the line trench filling insulating layer, and the other ends of the plurality of second semiconductor patterns are in contact with the interlayer insulating layer.

[0007] According to an aspect of the disclosed concept, a method for manufacturing a semiconductor memory device is provided, the method comprising: forming a stacked structure by alternately forming a plurality of semiconductor layers and a plurality of sacrificial layers in a vertical direction; forming a plurality of first semiconductor layers and a plurality of second semiconductor layers by separating the plurality of semiconductor layers, each of the plurality of first semiconductor layers extending in a first horizontal direction and spaced apart from each other in each of a second horizontal direction and a vertical direction, the second horizontal direction being substantially orthogonal to the first horizontal direction, and each of the plurality of second semiconductor layers extending in the first horizontal direction, each second semiconductor layer having a horizontal width in the second horizontal direction smaller than the horizontal width of each of the plurality of first semiconductor patterns, being spaced apart from each other in each of the second horizontal direction and the vertical direction, and being alternately arranged spaced apart from the plurality of first semiconductor patterns in the second horizontal direction; removing a plurality of A sacrificial layer; forming a plurality of first semiconductor patterns and a plurality of second semiconductor patterns by removing a portion of each of a plurality of first semiconductor layers and a plurality of second semiconductor layers; forming a plurality of gate structures surrounding the plurality of first semiconductor patterns and the plurality of second semiconductor patterns, each gate structure extending in a second horizontal direction and spaced apart from each other in a vertical direction; forming a plurality of bit lines connected to the ends of the first semiconductor patterns arranged in the vertical direction at intervals in the first horizontal direction, spaced apart from the plurality of second semiconductor patterns, each of the plurality of second semiconductor patterns extending in the vertical direction and spaced apart from each other in the second horizontal direction; and forming a plurality of capacitor structures connected to the other ends of the plurality of first semiconductor patterns in the first horizontal direction and spaced apart from the plurality of second semiconductor patterns.

[0008] In one embodiment, forming a plurality of first semiconductor layers and a plurality of second semiconductor layers by separating a plurality of semiconductor layers may include: forming a plurality of trimming spaces, each trimming space penetrating the stacked structure and arranged spaced apart from each other in a second horizontal direction; and forming wire trenches and capacitor trenches, each wire trench and capacitor trench extending along one side and the other side of the plurality of trimming spaces in the first horizontal direction in the second horizontal direction, and each wire trench and capacitor trench penetrating the stacked structure, the second horizontal direction being substantially orthogonal to the first horizontal direction.

[0009] In an implementation, in a plan view, each of the plurality of trimming spaces may have a U-shape, including a pair of separate trimming spaces and a short-axis trimming space, the pair of separate trimming spaces extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, and the short-axis trimming space connecting the ends of the pair of separate trimming spaces to each other in the second horizontal direction.

[0010] In one embodiment, forming wire grooves and capacitor grooves may include forming capacitor grooves on one side of a short-axis trimming space in a first horizontal direction, the short-axis trimming space connecting the ends of a pair of individual trimming spaces of each of the plurality of trimming spaces to each other, and forming wire grooves on one side of the other end of a pair of individual trimming spaces of each of the plurality of trimming spaces in the first horizontal direction.

[0011] In an embodiment, the method may further include: forming a first insulating layer that fills a plurality of trimmed spaces; forming a second insulating layer that fills a plurality of first removed spaces where line trenches, capacitor trenches, and a plurality of sacrificial layers have been removed; removing a portion of the second insulating layer, which fills the line trenches, before forming a plurality of first semiconductor patterns and a plurality of second semiconductor patterns; forming a plurality of gate recesses by removing portions of the plurality of gate structures after forming the plurality of gate structures; and forming a third insulating layer that fills the line trenches and the plurality of gate recesses before forming a plurality of bit lines.

[0012] In one embodiment, in the first horizontal direction, the ends of the plurality of second semiconductor patterns may contact the third insulating layer, and the other ends of the plurality of second semiconductor patterns may contact the first insulating layer.

[0013] In an embodiment, each of the plurality of first semiconductor patterns may include a first portion, a second portion, and a third portion. The first portion is surrounded by one of the gate structures of the plurality of gate structures. The second portion is surrounded by a third insulating layer and connected to one of the bit lines of the plurality of bit lines. The third portion is surrounded by a first insulating layer and a second insulating layer and connected to one of the capacitor structures of the plurality of capacitor structures. Each of the plurality of second semiconductor patterns may include a first dummy portion and a second dummy portion. The first dummy portion is surrounded by one of the gate structures of the plurality of gate structures, and the second dummy portion is surrounded by a third insulating layer. In a first horizontal direction, the length of the first dummy portion of each of the plurality of second semiconductor patterns may be less than the length of the first portion of each of the plurality of first semiconductor patterns, and in the first horizontal direction, the length of the second dummy portion of each of the plurality of second semiconductor patterns may be equal to the length of the second portion of each of the plurality of first semiconductor patterns.

[0014] In one embodiment, in the second horizontal direction, the horizontal width of the third portion of each of the plurality of first semiconductor patterns can be greater than the horizontal width of the first portion and the horizontal width of the second portion, and in the vertical direction, the thickness of the third portion of each of the plurality of first semiconductor patterns can be greater than the thickness of the first portion and the thickness of the second portion.

[0015] In an implementation, a plurality of first semiconductor patterns and a plurality of second semiconductor patterns may be formed such that, in a first horizontal direction, the ends of the plurality of first semiconductor patterns may be aligned with the ends of the plurality of second semiconductor patterns in a second horizontal direction, and in the first horizontal direction, the length of each of the plurality of first semiconductor patterns may be greater than the length of each of the plurality of second semiconductor patterns.

[0016] In one implementation, a plurality of first semiconductor layers and a plurality of second semiconductor layers may be formed by separating a plurality of semiconductor layers, such that in a first horizontal direction, the length of each of the plurality of first semiconductor patterns may be greater than the length of each of the plurality of second semiconductor patterns. Attached Figure Description

[0017] The embodiments will become clearer through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 This is an equivalent circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment;

[0019] Figure 2 This is a block diagram illustrating a semiconductor memory device according to an embodiment;

[0020] Figure 3A , Figure 3B , Figure 3C and Figure 3D This is a diagram illustrating a semiconductor memory device according to an embodiment;

[0021] Figures 4A to 4C , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9C , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figures 13A to 13C , Figures 14A to 14C , Figures 15A to 15C as well as Figures 16A to 16C This is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment;

[0022] Figure 17 This is an equivalent circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment; and

[0023] Figure 18A , Figure 18B and Figure 18C This is a diagram illustrating a semiconductor memory device according to an embodiment. Detailed Implementation

[0024] A three-dimensional semiconductor memory device has been proposed in which memory capacity is increased by stacking multiple memory cells in a vertical direction on a substrate.

[0025] Figure 1 This is an equivalent circuit diagram showing the memory cell array of the semiconductor memory device 1 according to an embodiment.

[0026] refer to Figure 1 According to an embodiment, the memory cell array CAR of the semiconductor memory device 1 may include multiple sub-cell arrays SCA. The sub-cell array SCA may include multiple bit lines BL, multiple word lines WL, and multiple memory cells MC. Each of the multiple memory cells MC may include a cell transistor CT and an information storage element SP. A cell transistor CT may be arranged between a word line WL and a bit line BL. The information storage element SP may be a memory element capable of storing data.

[0027] Word lines (WL) can be conductive patterns (e.g., metal lines) disposed above and spaced from the substrate. Each of multiple word lines (WL) can extend in a first horizontal direction (X direction). Word lines (WL) within a subcell array (SCA) can be spaced apart from each other in a vertical direction (Z direction). Each bit line (BL) can extend from the substrate in a vertical direction (Z direction). Bit lines (BL) within a subcell array (SCA) can be spaced apart from each other in a first horizontal direction (X direction).

[0028] In the memory cell array CAR of the semiconductor memory device 1, multiple word lines WL can extend in a first horizontal direction (X direction) and can be spaced apart from each other in each of a second horizontal direction (Y direction) and a vertical direction (Z direction). In the memory cell array CAR of the semiconductor memory device 1, multiple bit lines BL can extend in the vertical direction (Z direction) and can be spaced apart from each other in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0029] In some embodiments, the information storage element SP can be a memory element using a capacitor, a memory element using a magnetic tunnel junction pattern, or a memory element using a variable resistor including a phase change material. For example, the memory cell MC can be a dynamic random access memory (DRAM) cell, and the information storage element SP can be a capacitor. In another embodiment, the information storage element SP can be a transistor capable of storing data together with the cell transistor CT.

[0030] The gate of a cell transistor CT can be connected to the word line WL, and the source region of the cell transistor CT can be connected to the bit line BL. An information storage element SP can be connected to the drain region of the cell transistor CT. In some embodiments, the information storage element SP can be a capacitor including a first electrode, a second electrode, and a capacitor dielectric layer provided between the first and second electrodes, wherein the first electrode of the capacitor can be connected to the drain region of the cell transistor CT, and the second electrode of the capacitor can be connected to the ground wiring PP. In some embodiments, the second electrode of the capacitor can be part of the ground wiring PP.

[0031] The memory cell array (CAR) of the semiconductor memory device 1 may include multiple sub-cell arrays (SCAs), each sub-cell array (SCA) including: multiple memory cells (MCs) arranged spaced apart from each other in rows and columns in a first horizontal direction (X direction) and a vertical direction (Z direction); multiple bit lines (BLs) connected to cell transistors (CTs) of the memory cells (MCs), extending in the vertical direction (Z direction) and arranged spaced apart from each other in the first horizontal direction (X direction), the memory cells (MCs) being arranged in the vertical direction (Z direction); and multiple word lines (WLs) extending in the first horizontal direction (X direction) and arranged spaced apart from each other in the vertical direction (Z direction), wherein the multiple sub-cell arrays (SCAs) may be arranged in a second horizontal direction (Y direction). The semiconductor memory device 1 may include multiple memory cell arrays (CARs).

[0032] The first horizontal direction (X direction), the second horizontal direction (Y direction), and the vertical direction (Z direction) can be referred to as the first direction, the second direction, and the third direction, respectively. Alternatively, the first horizontal direction (X direction), the vertical direction (Z direction), and the second horizontal direction (Y direction) can be referred to as the first direction, the second direction, and the third direction, respectively. The first direction, the second direction, and the third direction can be substantially orthogonal to each other.

[0033] Two adjacent sub-cell arrays (SCAs) in the second horizontal direction (Y direction) can share a bit line BL. The source regions of the cell transistors CT included in the two sub-cell arrays (SCAs) can be connected to the bit line BL shared by the two adjacent sub-cell arrays (SCAs) in the second horizontal direction (Y direction). From each bit line BL shared by the two sub-cell arrays (SCAs), the source and drain regions of the individual cell transistors CT and the individual information storage elements SP of the two sub-cell arrays (SCAs) can be arranged in opposite directions. For example, the cell transistors CT of one sub-cell array (SCA) and the cell transistors CT of the other sub-cell array (SCA) can be connected to a bit line BL shared by the two sub-cell arrays (SCAs). The source region, drain region, and information storage element SP of the cell transistor CT of one sub-cell array (SCA) can be arranged sequentially in the second horizontal direction (Y direction). The source region, drain region, and information storage element SP of the cell transistor CT of the other sub-cell array (SCA) can be arranged sequentially in the opposite direction to the second horizontal direction (Y direction). For example, between a pair of bit lines BL arranged sequentially adjacent to each other in the second horizontal direction (Y direction) among multiple bit lines BL, two memory cells MC can be arranged at the same vertical level in the second horizontal direction (Y direction).

[0034] Figure 2 This is a block diagram illustrating a semiconductor memory device 1000 according to an embodiment.

[0035] refer to Figure 2 The semiconductor memory device 1000 may include a memory cell array 1010 containing DRAM cells and various circuit blocks for driving the DRAM cells, where the DRAM cells are memory units. For example, when a chip select signal is received... Timer register 1020 can be activated when it changes from an invalid level (e.g., logic high) to an valid level (e.g., logic low). Timer register 1020 can receive command signals from external sources, such as the clock signal CLK, the clock enable signal CKE, and the chip select signal. Row address strobe signal Column address strobe signal Write enable signal It can also process received command signals to generate various internal command signals for controlling circuit blocks, such as LCKE, LRAS, LCBR, LWE, LCAS, LWCBR, and LDQM.

[0036] Some internal command signals generated by the timer register 1020 can be stored in the programming register 1040. For example, delay information or burst length information associated with data output can be stored in the programming register 1040. The internal command signals stored in the programming register 1040 can be provided to the delay / burst length controller 1060, and the delay / burst length controller 1060 can provide control signals for controlling the delay or burst length of data output through the column address buffer 1080 to the column decoder 1100 or the output buffer 1120.

[0037] Address register 1200 can receive clock signal CLK and address signal ADD from an external source. The row address signal can be provided to row decoder 1240 via row address buffer 1220. Furthermore, column address signals can be provided to column decoder 1100 via column address buffer 1080. Row address buffer 1220 can also receive refresh address signals generated by the refresh counter in response to refresh commands LRAS and LCBR, and can provide one of the row address signal and refresh address signal to row decoder 1240. Additionally, address register 1200 can provide bank signals for selecting a bank to bank selector 1260.

[0038] The row decoder 1240 can decode the row address signal or refresh address signal input from the row address buffer 1220. The row decoder 1240 may include a plurality of sub-word line drivers (SWDs) 1250. The sub-word line drivers 1250 can activate word lines WL of the memory cell array 1010. The sub-word line drivers 1250 can be arranged in blocks at intervals within the row decoder 1240 so as to be adjacent to the memory cell array 1010. For example, the sub-word line drivers 1250 can be arranged adjacent to the ends of the memory cell array 1010 so as to be perpendicular to the sense amplifier 1300.

[0039] The column decoder 1100 can decode the column address signal and perform a selection operation on the bit lines BL of the memory cell array 1010. For example, the column select lines can be applied to the semiconductor memory device 1000, and a selection operation can be performed through the column select lines.

[0040] The sense amplifier 1300 amplifies data from memory cells selected by the row decoder 1240 and column decoder 1100, and provides the amplified data to the output buffer 1120. The output buffer 1120 outputs output data DQi. The output data DQi to be written to data cells can be provided to the memory cell array 1010 through the data input register 1320, and the input / output controller 1340 can control the data transfer operation through the data input register 1320.

[0041] Figure 3A , Figure 3B , Figure 3C and Figure 3D This is a diagram illustrating a semiconductor memory device 1 according to an embodiment. In detail, Figure 3A This is a plan view showing the main components of semiconductor memory device 1. Figure 3B It is along Figure 3A A cross-sectional view of semiconductor memory device 1 taken by line B-B'. Figure 3C It is along Figure 3A A cross-sectional view of semiconductor memory device 1 taken by line C-C'. Figure 3D It is along Figure 3A A cross-sectional view of semiconductor memory device 1 taken by line D-D'.

[0042] refer to Figure 3A , Figure 3B , Figure 3C and Figure 3D The semiconductor memory device 1 may include a plurality of first semiconductor patterns 212R, a plurality of second semiconductor patterns 214D, a plurality of gate dielectric layers 252 surrounding at least a portion of the plurality of first semiconductor patterns 212R and the plurality of second semiconductor patterns 214D, a plurality of gate electrodes 254 surrounding at least a portion of the plurality of first semiconductor patterns 212R and the plurality of second semiconductor patterns 214D and located therebetween the plurality of gate dielectric layers 252, a plurality of bit lines 270 connected to one end of the plurality of first semiconductor patterns 212R, and a plurality of capacitor structures 280 connected to the other end of the plurality of first semiconductor patterns 212R.

[0043] Each of the plurality of first semiconductor patterns 212R and the plurality of second semiconductor patterns 214D may extend in a first horizontal direction (X direction). Each of the plurality of gate electrodes 254 may extend in a second horizontal direction (Y direction). The second horizontal direction (Y direction) may be substantially orthogonal to the first horizontal direction (X direction). The plurality of first semiconductor patterns 212R may be referred to as unit semiconductor patterns, and the plurality of second semiconductor patterns 214D may be referred to as dummy semiconductor patterns. A plurality of bit lines 270 may be connected to one end of the plurality of first semiconductor patterns 212R in the first horizontal direction (X direction), and a plurality of capacitor structures 280 may be connected to the other end of the plurality of first semiconductor patterns 212R in the first horizontal direction (X direction). The gate electrodes 254 may be Figure 1 The word line WL is shown. Bit line 270 can be... Figure 1 The bit line BL is shown. Capacitor structure 280 can be... Figure 1 The information storage element SP shown in the diagram. A first semiconductor pattern 212R, a gate dielectric layer 252, a gate electrode 254, and a bit line 270 can be formed. Figure 1 The unit transistor CT shown is shown.

[0044] Multiple first semiconductor patterns 212R can be arranged spaced apart from each other in each of the first horizontal direction (X direction), the second horizontal direction (Y direction), and the vertical direction (Z direction). The multiple first semiconductor patterns 212R can have a matrix arrangement in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction) in a planar view, and can be arranged to be aligned in the vertical direction (Z direction). Multiple second semiconductor patterns 214D can be arranged spaced apart from each other in each of the first horizontal direction (X direction), the second horizontal direction (Y direction), and the vertical direction (Z direction). The multiple second semiconductor patterns 214D can have a matrix arrangement in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction) in a planar view, and can be arranged to be aligned in the vertical direction (Z direction). Second semiconductor patterns 214D can be arranged between a pair of first semiconductor patterns 212R that are adjacent to each other in the second horizontal direction (Y direction). For example, the first semiconductor patterns 212R and the second semiconductor patterns 214D can be arranged alternately, spaced apart from each other, in the second horizontal direction (Y direction).

[0045] Each of the first semiconductor pattern 212R and the second semiconductor pattern 214D may include a semiconductor material. In some embodiments, each of the first semiconductor pattern 212R and the second semiconductor pattern 214D may include silicon (Si). In some embodiments, each of the first semiconductor pattern 212R and the second semiconductor pattern 214D may include a single-crystal semiconductor material. For example, each of the first semiconductor pattern 212R and the second semiconductor pattern 214D may include single-crystal Si. In some other embodiments, each of the first semiconductor pattern 212R and the second semiconductor pattern 214D may include a 2D semiconductor material or an oxide semiconductor material. For example, a 2D semiconductor material may include MoS2, WSe2, graphene, carbon nanotubes, or combinations thereof. For example, an oxide semiconductor material may include In. x Ga y Zn z O, In doped with tin (Sn) x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, InO and InZn doped with tungsten (W) x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Yttrium (Y)-doped ZnO, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga yO or combinations thereof. In some embodiments, each of the first semiconductor pattern 212R and the second semiconductor pattern 214D may have the same impurity concentration overall, or may be an intrinsic semiconductor without implanted impurities overall. For example, each of the first semiconductor pattern 212R and the second semiconductor pattern 214D may have a junctionless structure. The first semiconductor pattern 212R and the second semiconductor pattern 214D may comprise the same material.

[0046] The first semiconductor pattern 212R may include a first portion 212C, a second portion 212S, and a third portion 212D. The second portion 212S and the third portion 212D may be located on opposite sides of the first portion 212C in a first horizontal direction (X direction). The second portion 212S, the first portion 212C, and the third portion 212D may be arranged sequentially from the bit line 270 to the capacitor structure 280 in the first horizontal direction (X direction). The first portion 212C of the first semiconductor pattern 212R may be surrounded by a gate structure 250, the second portion 212S of the first semiconductor pattern 212R may be surrounded by a third insulating layer 260 and connected to the bit line 270, and the third portion 212D of the first semiconductor pattern 212R may be surrounded by a first insulating layer 230 and a second insulating layer 240 and connected to the first electrode 282 of the capacitor structure 280. The second portion 212S of the first semiconductor pattern 212R may be surrounded by an insulating spacer 260SP, which is part of the third insulating layer 260.

[0047] For example, the two side surfaces of the third portion 212D of the first semiconductor pattern 212R in the second horizontal direction (Y direction) can be covered by the first insulating layer 230, and the upper and lower surfaces of the third portion 212D of the first semiconductor pattern 212R can be covered by the second insulating layer 240. The second portion 212S, the first portion 212C, and the third portion 212D of the first semiconductor pattern 212R can be referred to as the source region, the channel region, and the drain region, respectively. In the first horizontal direction (X direction), the first semiconductor pattern 212R can have a cell length LC. In the first horizontal direction (X direction), the first portion 212C of the first semiconductor pattern 212R can have a first length L1, the second portion 212S of the first semiconductor pattern 212R can have a second length L2, and the third portion 212D of the first semiconductor pattern 212R can have a third length L3. The cell length LC can be the sum of the first length L1, the second length L2, and the third length L3. The first length L1 can be greater than the second length L2 and the third length L3. In some embodiments, the third length L3 may be greater than the second length L2, but the embodiments are not limited thereto. The first portion 212C and the second portion 212S of the first semiconductor pattern 212R may have a first horizontal width W1 in the second horizontal direction (Y direction). The third portion 212D of the first semiconductor pattern 212R may have a horizontal width greater than the first horizontal width W1 in the second horizontal direction (Y direction). In the vertical direction (Z direction), the third portion 212D of the first semiconductor pattern 212R may have a greater thickness than each of the first portion 212C and the second portion 212S of the first semiconductor pattern 212R. That is, compared to each of the first portion 212C and the second portion 212S of the first semiconductor pattern 212R, the third portion 212D of the first semiconductor pattern 212R may have a greater thickness in the vertical direction (Z direction) and a greater horizontal width in the second horizontal direction (Y direction). In some embodiments, each of the first portion 212C and the second portion 212S of the first semiconductor pattern 212R may have substantially the same horizontal width in the second horizontal direction (Y direction). In some embodiments, each of the first portion 212C and the second portion 212S of the first semiconductor pattern 212R may have substantially the same thickness in the vertical direction (Z direction).

[0048] In the first horizontal direction (X direction), the second semiconductor pattern 214D may have a dummy length LD. The dummy length LD may be less than the cell length LC. A portion of the second semiconductor pattern 214D may be surrounded by a gate structure 250, and another portion of the second semiconductor pattern 214D may be surrounded by insulating spacers 260SP. In the first horizontal direction (X direction), the portion of the second semiconductor pattern 214D surrounded by the gate structure 250 may have a fourth length L4, and the portion of the second semiconductor pattern 214D surrounded by the insulating spacers 260SP may have a fifth length L5. The fourth length L4 may be less than the first length L1. The fifth length L5 may be substantially equal to the second length L2. The portion of the second semiconductor pattern 214D surrounded by the gate structure 250 and having a fourth length L4 in the first horizontal direction (X direction) can be referred to as the first dummy portion. The portion of the second semiconductor pattern 214D surrounded by the insulating spacer 260SP and having a fifth length L5 in the first horizontal direction (X direction) can be referred to as the second dummy portion. The second semiconductor pattern 214D may have a second horizontal width W2 in the second horizontal direction (Y direction). In some embodiments, the second semiconductor pattern 214D may extend from one end to the other in the first horizontal direction (X direction) and may have substantially the same horizontal width in the second horizontal direction (Y direction) and substantially the same thickness in the vertical direction (Z direction). For example, in the vertical direction (Z direction), the thickness of the second semiconductor pattern 214D may be substantially the same as the thickness of each of the first portion 212C and the second portion 212S of the first semiconductor pattern 212R. The second horizontal width W2 may be smaller than the first horizontal width W1. For example, the first horizontal width W1 may have a value that is at least twice the second horizontal width W2. The first semiconductor pattern 212R and the second semiconductor pattern 214D, which are adjacent to each other in the second horizontal direction (Y direction), can be spaced apart by a pattern spacing ITY. The pattern spacing ITY can be less than the first horizontal width W1 and greater than the second horizontal width W2.

[0049] In the first horizontal direction (X direction), one end of the first semiconductor pattern 212R can contact the bit line 270, and one end of the second semiconductor pattern 214D can contact the third insulating layer 260. The second semiconductor pattern 214D is electrically insulated from the bit line 270 by being spaced apart from it by the third insulating layer 260. In the first horizontal direction (X direction), another end of the first semiconductor pattern 212R can contact the first electrode 282 of the capacitor structure 280, and another end of the second semiconductor pattern 214D can contact the first insulating layer 230. The second semiconductor pattern 214D is electrically insulated from the capacitor structure 280 by being spaced apart from it by the first insulating layer 230. In the first horizontal direction (X direction), the ends of the first semiconductor pattern 212R and the ends of the second semiconductor pattern 214D can be aligned in the second horizontal direction (Y direction). In the first horizontal direction (X direction), the other end of the first semiconductor pattern 212R may not be aligned with the other end of the second semiconductor pattern 214D in the second horizontal direction (Y direction).

[0050] The first insulating layer 230 may fill the space between adjacent third portions 212D of the first semiconductor pattern 212R in the second horizontal direction (Y direction), and may cover the end of the second semiconductor pattern 214D facing the capacitor trench CTR in the first horizontal direction (X direction). In some embodiments, the first insulating layer 230 may further cover the two side surfaces of the portion of the second semiconductor pattern 214D facing the capacitor trench CTR in the second horizontal direction (Y direction). The first insulating layer 230 may cover the aligned ends of the second semiconductor pattern 214D in the vertical direction (Z direction) and may extend in the vertical direction (Z direction) to form a monomer. The second insulating layer 240 may fill the space between adjacent first semiconductor patterns 212R in the vertical direction (Z direction) and the space between adjacent second semiconductor patterns 214D in the vertical direction (Z direction). The first insulating layer 230 and the second insulating layer 240 may be collectively referred to as interlayer insulating layers. The interlayer insulating layer may surround a plurality of first semiconductor patterns 212R, a plurality of second semiconductor patterns 214D, and a plurality of gate structures 250.

[0051] The gate structure 250 may include a gate dielectric layer 252 and a gate electrode 254. The gate dielectric layer 252 may conformally cover the surfaces of each of the first insulating layer 230, the second insulating layer 240, the first semiconductor pattern 212R, and the second semiconductor pattern 214D located in the space outside the gate recess 250RS within the second removal space 210RS. The gate electrode 254 may surround the first semiconductor pattern 212R and the second semiconductor pattern 214D, with the gate dielectric layer 252 located therebetween. The gate electrode 254 may extend in a second horizontal direction (Y direction) and may cover the upper and lower surfaces of each of the first semiconductor pattern 212R and the second semiconductor pattern 214D, as well as two side surfaces in the second horizontal direction (Y direction). For example, the gate electrode 254 may have a gate all-around (GAA) structure that completely surrounds the first semiconductor pattern 212R in a vertical cross-section (YZ vertical cross-section) formed by the second horizontal direction (Y direction) and the vertical direction (Z direction). The gate electrode 254 may be spaced apart from the bit line 270 and therebetween a third insulating layer 260 including insulating spacers 260SP.

[0052] The third insulating layer 260 may surround multiple bit lines 270 and may fill the line trench LTR. The multiple bit lines 270 may fill multiple bit line vias 270H penetrating the third insulating layer 260. The multiple bit lines 270 may be connected to the ends of multiple first semiconductor patterns 212R in a first horizontal direction (X direction). The third insulating layer 260 may further fill multiple gate recesses 250RS, which are portions of multiple second removal spaces 210RS. Each of the multiple insulating spacers 260SP (which are portions of the third insulating layer 260 filling the multiple gate recesses 250RS) may surround a second portion 212S of the first semiconductor pattern 212R or a portion of the second semiconductor pattern 214D adjacent to the line trench LTR.

[0053] Multiple capacitor structures 280 may include multiple first electrodes 282, a capacitor dielectric layer 284, and a second electrode 286. The multiple capacitor structures 280 may be connected to the other end of multiple first semiconductor patterns 212R in a first horizontal direction (X direction). Multiple first electrodes 282 may be formed on the other end of the multiple first semiconductor patterns 212R in the first horizontal direction (X direction), the capacitor dielectric layer 284 may cover the multiple first electrodes 282, and the second electrode 286 may cover the multiple first electrodes 282 with the capacitor dielectric layer 284 located therebetween. The capacitor dielectric layer 284 may be formed to conformally cover the multiple first electrodes 282. In some embodiments, the capacitor dielectric layer 284 may be formed as a single unit within a capacitor trench CTR to conformally cover the multiple first electrodes 282, the multiple first insulating layers 230, and the second insulating layer 240. In some embodiments, the second electrode 286 may be formed as a single unit within the capacitor trench CTR to conformally cover a plurality of first electrodes 282, a plurality of first insulating layers 230 and a second insulating layer 240, with a capacitor dielectric layer 284 located therebetween. The second electrode 286 may be coupled with… Figure 1 The grounding wiring PP connection shown may be a part of the grounding wiring PP. The fourth insulating layer 290 may cover multiple capacitor structures 280 and may fill the capacitor trench CTR.

[0054] The third insulating layer 260 may be referred to as a wire trench filling insulating layer or a first filling insulating layer, and the fourth insulating layer 290 may be referred to as a capacitor trench filling insulating layer or a second filling insulating layer.

[0055] In the semiconductor memory device 1 according to the present invention, since the second semiconductor pattern 214D is arranged between first semiconductor patterns 212R that are adjacent to each other in the second horizontal direction (Y direction), gaps can be prevented from appearing in the gate 254 included in the gate structure 250. Therefore, the gate electrode 254 can be prevented from thinning or breaking due to gaps, thereby improving the operational reliability of the semiconductor memory device 1.

[0056] In some implementations... Figures 3A to 3D The semiconductor memory device 1 shown can be stacked with peripheral circuit structures to form a semiconductor device. For example, the semiconductor device may have a peripheral cell-on-a-Pack (CoP) structure or a cell-on-periphery (PoC) structure, wherein the peripheral circuit structure is formed on... Figures 3A to 3D The semiconductor memory device 1 shown is located below or above, or is attached to, the semiconductor memory device 1. The peripheral circuit structure may include a peripheral circuit board and a plurality of peripheral circuit transistors. The plurality of peripheral circuit transistors may be configured to transmit signals and / or power to, included in, the semiconductor memory device 1. Figures 3A to 3DThe semiconductor memory device 1 shown contains multiple memory cells. For example, the multiple peripheral circuit transistors can form various circuits, such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, and data input / output circuits. Each of the multiple peripheral circuit transistors can be a planar transistor, a FinFET, and / or a vertical gate transistor.

[0057] In some implementations... Figures 3A to 3D The peripheral circuit structure and semiconductor memory device 1 shown can be bonded to each other using a hybrid bonding method. For example, the peripheral circuit structure may include peripheral circuit bonding pads and a peripheral circuit bonding insulating layer surrounding the peripheral circuit bonding pads. Figures 3A to 3D The semiconductor memory device 1 shown may include cell bonding pads and a cell bonding insulating layer surrounding the cell bonding pads. The cell bonding insulating layer and the peripheral circuit bonding insulating layer may be covalently bonded to each other, the cell bonding pads and the peripheral circuit bonding pads may face each other and expand due to heat to contact each other, and the cell bonding pads and the peripheral circuit bonding pads may be diffusion bonded to form monomers through the diffusion of metal atoms included therein. The cell bonding pads and the peripheral circuit bonding pads may include a material containing copper (Cu). The cell bonding insulating layer and the peripheral circuit bonding insulating layer may include silicon oxide or silicon carbon nitride (SiCN).

[0058] In some implementations... Figures 3A to 3D The peripheral circuit structure and semiconductor memory device 1 shown can be bonded to each other using a direct bonding method. For example, the peripheral circuit structure may include a peripheral circuit bonding insulating layer. Figures 3A to 3D The semiconductor memory device 1 shown may include a cell bonding insulating layer. The cell bonding insulating layer and the peripheral circuit bonding insulating layer can be covalently bonded together, and Figures 3A to 3D The peripheral circuit structure and semiconductor memory device 1 shown can be electrically connected to each other through multiple through-holes in the penetrating cell bonding insulating layer and the peripheral circuit bonding insulating layer.

[0059] In some embodiments, a plurality of first semiconductor patterns 212R, a plurality of second semiconductor patterns 214D, a plurality of gate dielectric layers 252, a plurality of gate electrodes 254, a plurality of bit lines 270, and a plurality of capacitor structures 280, including those in the semiconductor memory device 1, may be disposed on a substrate. The substrate may include, for example, silicon (Si), such as crystalline Si, polycrystalline Si, or amorphous Si. Alternatively, the substrate may include a semiconductor element such as germanium (Ge) or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, the substrate may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. For example, the substrate may include a buried oxide (BOX) layer. The substrate may include conductive regions, such as impurity-doped wells or impurity-doped structures. A plurality of peripheral circuit transistors may be disposed on the substrate.

[0060] Figures 4A to 4C , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9C , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figures 13A to 13C , Figures 14A to 14C , Figures 15A to 15C as well as Figures 16A to 16C This is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment. In detail, Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A This is a plan view illustrating a method for manufacturing a semiconductor memory device. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B It is along Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A A cross-sectional view taken from line B-B'. Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C and Figure 16C It is along Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A The cross-sectional view taken from line C-C'.

[0061] refer to Figures 4A to 4C Multiple semiconductor layers 210 and multiple sacrificial layers 220 are alternately formed in the vertical direction (Z direction) to form a stacked structure. Each of the multiple semiconductor layers 210 and multiple sacrificial layers 220 may include a semiconductor material. The sacrificial layer 220 may include a semiconductor material that has etch selectivity relative to the semiconductor layer 210. For example, the semiconductor layer 210 may include Si, and the sacrificial layer 220 may include SiGe or SiGeC. In some embodiments, the semiconductor layer 210 may include a 2D semiconductor material or an oxide semiconductor material.

[0062] In some embodiments, a plurality of semiconductor layers 210 and a plurality of sacrificial layers 220 may be formed on a support substrate. The support substrate may be a semiconductor substrate, a ceramic substrate, or a glass substrate.

[0063] refer to Figures 5A to 5CMultiple trim spaces (TRS) are formed to penetrate multiple semiconductor layers 210 and multiple sacrificial layers 220 and are spaced apart from each other in a planar view. The multiple trim spaces (TRS) can be arranged spaced apart from each other in each of a first horizontal direction (X direction) and a second horizontal direction (Y direction). Trim spaces (TRS) arranged in the second horizontal direction (Y direction) can have the same planar shape. A pair of trim spaces (TRS) adjacent to each other in the first horizontal direction (X direction) can have a planar shape that is mirror-symmetrical to each other.

[0064] For example, the trimming space TRS can have a U-shape in a plan view. The trimming space TRS may include a pair of separate trimming spaces DTRS extending in a first horizontal direction (X direction) and spaced apart from each other in a second horizontal direction (Y direction), and a short-axis trimming space STRS connecting the ends of the pair of separate trimming spaces DTRS to each other in the second horizontal direction (Y direction).

[0065] The horizontal width of the portion of semiconductor layer 210 located between a pair of individual trimming spaces DTRS in a trimming space TRS in the second horizontal direction (Y direction) may be smaller than the horizontal width of the portion of semiconductor layer 210 located between a pair of adjacent trimming spaces TRS in the second horizontal direction (Y direction) in the second horizontal direction (Y direction). For example, among the individual trimming spaces DTRS arranged in the second horizontal direction (Y direction), the gap between a pair of individual trimming spaces DTRS that are adjacent to each other in the second horizontal direction (Y direction) and connected to each other by a short axis trimming space SRS may be smaller than the gap between a pair of individual trimming spaces DTRS that are adjacent to each other in the second horizontal direction (Y direction) and not connected to each other by a short axis trimming space SRS. The horizontal width of the portion of semiconductor layer 210 located between a pair of individual trimming spaces DTRS in a trimming space TRS in the first horizontal direction (X direction) may be smaller than the horizontal width of the portion of semiconductor layer 210 located between a pair of adjacent trimming spaces TRS in the second horizontal direction (Y direction) in the first horizontal direction (X direction). For example, the horizontal width of the portion of semiconductor layer 210 located between a pair of separate trim spaces DTRS in a trim space TRS in the first horizontal direction may be smaller than the horizontal width of the portion of semiconductor layer 210 located between a pair of adjacent trim spaces TRS in the second horizontal direction (Y direction) in the first horizontal direction (X direction) in the first horizontal direction (X direction) in the first horizontal direction (X direction) in the first horizontal direction (X direction) in the first horizontal direction (X direction) in the second horizontal direction (Y direction) in the first horizontal direction (Y direction) in the first horizontal direction (X direction) in the first horizontal direction (X direction) in the first horizontal direction (X direction) in the first horizontal direction (X direction) in the first horizontal direction (X direction) in the first horizontal direction (X direction) in the second horizontal direction (Y ...

[0066] refer to Figures 6A to 6CMultiple first insulating layers 230 are formed to fill multiple trimming spaces TRS. The first insulating layers 230 may include oxides, nitrides, oxynitrides, carbonitrides, or combinations thereof. Corresponding to the trimming spaces TRS, the first insulating layers 230 may have a U-shape in a plan view.

[0067] refer to Figures 6A to 6C and Figures 7A to 7C The line trench LTR and capacitor trench CTR are formed such that trimmed spaces TRS adjacent to each other in a first horizontal direction (X direction) extend in a second horizontal direction (Y direction) and penetrate multiple semiconductor layers 210 and multiple sacrificial layers 220. The line trench LTR and capacitor trench CTR may be formed alternately in the first horizontal direction (X direction). A first insulating layer 230 filling the trimmed spaces TRS may be exposed on the inner surface of each of the line trench LTR and capacitor trench CTR. The capacitor trench CTR may be formed in the first horizontal direction (X direction) on one side of a short-axis trimmed space SRS that connects the ends of a pair of individual trimmed spaces DTRS of each of the multiple trimmed spaces TRS to each other, and the line trench LTR may be formed in the first horizontal direction (X direction) on one side of the other end of a pair of individual trimmed spaces DTRS of each of the multiple trimmed spaces TRS. For example, portions of the first insulating layer 230 that fill the individual trimming spaces DTRS may be exposed on the inner surface of the line trench LTR, and portions of the first insulating layer 230 that fill the short axis trimming spaces STRS may be exposed on the inner surface of the capacitor trench CTR.

[0068] The multiple semiconductor layers 210 can be separated into multiple first semiconductor layers 210C and multiple second semiconductor layers 210D through line trenches (LTR) and capacitor trenches (CTR). For example, the first semiconductor layers 210C can be arranged between a pair of trimming spaces (TRS) adjacent to each other in the second horizontal direction (Y direction), and the second semiconductor layers 210D can be arranged between a pair of separate trimming spaces (DTRS) and short-axis trimming spaces (STRS) included in a trimming space (TRS).

[0069] A portion of the first insulating layer 230 may be provided between the first semiconductor layers 210C and 210D that are adjacent to each other in the second horizontal direction (Y direction). The plurality of first insulating layers 230 may cover two sidewalls of the plurality of first semiconductor layers 210C in the second horizontal direction (Y direction). The plurality of first insulating layers 230 may cover two sidewalls of the plurality of second semiconductor layers 210D in the second horizontal direction (Y direction) and the sidewalls of the plurality of second semiconductor layers 210D facing the capacitor trench CTR in the first horizontal direction (X direction). The sidewalls of the plurality of first semiconductor layers 210C in the first horizontal direction (X direction) may be exposed in the capacitor trench CTR, and the other sidewall of the plurality of first semiconductor layers 210C in the first horizontal direction (X direction) may be exposed in the line trench LTR. The sidewalls of the plurality of second semiconductor layers 210D facing the capacitor trench CTR in the first horizontal direction (X direction) may be covered by a portion of the first insulating layer 230, and the other sidewall of the plurality of second semiconductor layers 210D in the first horizontal direction (X direction) may be exposed in the line trench LTR.

[0070] refer to Figures 7A to 7C as well as Figures 8A to 8C Multiple sacrificial layers 220 are removed to form multiple first removal spaces 220RS. The multiple first removal spaces 220RS can be connected to each of the line trench LTR and the capacitor trench CTR. The multiple first removal spaces 220RS can be formed between first semiconductor layers 210C that are adjacent to each other in the vertical direction (Z direction) and between second semiconductor layers 210D that are adjacent to each other in the vertical direction (Z direction).

[0071] refer to Figures 9A to 9C A second insulating layer 240 is formed to fill the line trench LTR, capacitor trench CTR, and a plurality of first removal spaces 220RS. The second insulating layer 240 may include oxides, nitrides, oxynitrides, carbonitrides, or combinations thereof. In some embodiments, the second insulating layer 240 may include the same material as the first insulating layer 230, but embodiments are not limited thereto. For example, the second insulating layer 240 may include an insulating material that has etch selectivity relative to the first insulating layer 230.

[0072] refer to Figures 10A to 10C The portion of the second insulating layer 240 filling the line trench LTR is removed to expose a plurality of first semiconductor layers 210C, a plurality of second semiconductor layers 210D and a plurality of first insulating layers 230 on the inner sidewall of the line trench LTR.

[0073] refer to Figures 10A to 10C as well as Figures 11A to 11CA portion of each of a plurality of first semiconductor layers 210C and a plurality of second semiconductor layers 210D is removed by a line trench LTR to form a plurality of first semiconductor patterns 212R and a plurality of second semiconductor patterns 214D.

[0074] In some embodiments, portions of the plurality of first semiconductor layers 210C and the plurality of second semiconductor layers 210D may also be removed during the process of removing a portion of each of the plurality of first semiconductor layers 210C and the plurality of second semiconductor layers 210D. For example, during the process of removing a portion of each of the plurality of first semiconductor layers 210C and the plurality of second semiconductor layers 210D, portions of the first insulating layer 230 disposed between the first semiconductor layers 210C and the second semiconductor layers 210D in the second horizontal direction (Y direction) may also be removed.

[0075] In some embodiments, a portion of the second insulating layer 240 may also be removed during the process of removing a portion of each of the plurality of first semiconductor layers 210C and the plurality of second semiconductor layers 210D. For example, during the process of removing a portion of each of the plurality of first semiconductor layers 210C and the plurality of second semiconductor layers 210D, a portion of the second insulating layer 240 that is adjacent to the plurality of first semiconductor layers 210C and the plurality of second semiconductor layers 210D in the vertical direction (Z direction) may also be removed.

[0076] Multiple second removal spaces 210RS can be defined within the space where portions of multiple first semiconductor layers 210C and multiple second semiconductor layers 210D have been removed. In some embodiments, the multiple second removal spaces 210RS may further include spaces where portions of multiple first insulating layers 230 and / or second insulating layers 240 have been removed. In some embodiments, the horizontal width of the second removal spaces 210RS in the first horizontal direction (X direction) may be smaller than the horizontal width of the first semiconductor pattern 212R in the first horizontal direction (X direction) and larger than the horizontal width of the second semiconductor pattern 214D in the first horizontal direction (X direction).

[0077] Compared to the corresponding second semiconductor layer 210D, the second semiconductor pattern 214D can be formed with a reduced horizontal width in the second horizontal direction (Y direction) and a reduced thickness in the vertical direction (Z direction). In the first horizontal direction (X direction), the second semiconductor pattern 214D can have substantially the same horizontal width in the second horizontal direction (Y direction) and thickness in the vertical direction (Z direction). Compared to at least a corresponding portion of the first semiconductor layer 210C, at least a portion of the first semiconductor pattern 212R can be formed with a reduced horizontal width in the second horizontal direction (Y direction) and a reduced thickness in the vertical direction (Z direction). In some embodiments, the horizontal width in the second horizontal direction (Y direction) and the thickness in the vertical direction (Z direction) of a portion of the first semiconductor pattern 212R can be substantially the same as the horizontal width and thickness of the corresponding portion of the first semiconductor layer 210C. For example, compared to the portion of the first semiconductor pattern 212R adjacent to the line trench LTR, the portion of the first semiconductor pattern 212R adjacent to the capacitor trench CTR in the first horizontal direction (X direction) can have a larger horizontal width in the second horizontal direction (Y direction) and a larger thickness in the vertical direction (Z direction).

[0078] refer to Figures 12A to 12C A preliminary dielectric layer 252P is formed to conformally cover the surfaces exposed within the plurality of second removal spaces 210RS and the wire trench LTR. Then, a preliminary electrode layer 254P is formed to cover the preliminary dielectric layer 252P and fill the plurality of second removal spaces 210RS and at least a portion of the wire trench LTR. (Reference) Figures 12A to 12C as well as Figures 13A to 13C A portion of the initial dielectric layer 252P and a portion of the initial electrode layer 254P are removed from the fill line trench LTR and a portion of the multiple second removal spaces 210RS to form a plurality of gate structures 250 and a plurality of gate recesses 250RS that fill the remaining portions of the multiple second removal spaces 210RS.

[0079] The multiple gate structures 250 may include multiple gate dielectric layers 252 and multiple gate electrodes 254 covering the multiple gate dielectric layers 252.

[0080] Multiple gate dielectric layers 252 may be formed conformally covering the surfaces of multiple first semiconductor patterns 212R, multiple second semiconductor patterns 214D, multiple first insulating layers 230, and the second insulating layer 240, these surfaces being exposed within the remaining portions of multiple second removal spaces 210RS. Multiple gate electrodes 254 may be formed covering the multiple gate dielectric layers 252 and filling the remaining portions of the multiple second removal spaces 210RS. Gate dielectric layers 252 may be formed surrounding at least a portion of the first semiconductor patterns 212R. For example, gate dielectric layers 252 may be formed covering the upper and lower surfaces of at least a portion of the first semiconductor patterns 212R, as well as two side surfaces in the second horizontal direction (Y direction). Gate dielectric layers 252 may be formed surrounding the second semiconductor patterns 214D. For example, gate dielectric layers 252 may be formed covering the upper and lower surfaces of the second semiconductor patterns 214D, as well as two side surfaces in the second horizontal direction (Y direction).

[0081] The gate structure 250 can be formed to surround the first semiconductor pattern 212R and the second semiconductor pattern 214D and extend in the second horizontal direction (Y direction). When the second semiconductor pattern 214D is absent, the gap between adjacent first semiconductor patterns 212R in the second horizontal direction (Y direction) may be relatively large when forming the gate electrode 254, thus, gaps may appear in the gate electrode 254 where the gate electrode 254 is not completely filled. However, when the second semiconductor pattern 214D is arranged between adjacent first semiconductor patterns 212R in the second horizontal direction (Y direction), the gap between adjacent first semiconductor patterns 212R and the second semiconductor pattern 214D in the second horizontal direction (Y direction) can be relatively small, thus preventing gaps from appearing in the gate electrode 254.

[0082] The gate dielectric layer 252 may include at least one selected from silicon oxide, a high-k dielectric material having a higher dielectric constant than silicon oxide, and a ferroelectric material. For example, the high-k dielectric material and the ferroelectric material may include at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the gate dielectric layer 252 may include a metal oxide.

[0083] The gate electrode 254 may include a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the gate electrode 254 may include a conductive barrier layer and a conductive filling layer covering the conductive barrier layer. The conductive barrier layer may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. For example, the conductive barrier layer may include TiN. The conductive filling layer may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SrRuO (SRO), (Ba,Sr)RuO (BSRO), CaRuO (CRO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof. In some embodiments, the conductive filling layer may include W.

[0084] Multiple gate recesses 250RS can be connected to the line trench LTR. The multiple gate recesses 250RS can correspond to portions of multiple second removal spaces 210RS adjacent to the line trench LTR. For example, the multiple gate recesses 250RS can be formed by removing a portion of the initial dielectric layer 252P and a portion of the initial electrode layer 254P, which fill the portions of the multiple second removal spaces 210RS adjacent to the line trench LTR.

[0085] In some implementations, a portion of the initial dielectric layer 252P and a portion of the initial electrode layer 254P of the filling line trench LTR, as well as a portion of the initial dielectric layer 252P and a portion of the initial electrode layer 254P of the filling portion of the plurality of second removal spaces 210RS, can be sequentially removed in a single process to form a plurality of gate structures 250 and a plurality of gate recesses 250RS.

[0086] refer to Figures 14A to 14C A third insulating layer 260 is formed to fill the line trench LTR and the plurality of gate recesses 250RS. The portion of the third insulating layer 260 filling the plurality of gate recesses 250RS may be referred to as a plurality of insulating spacers 260SP. The third insulating layer 260 may include oxides, nitrides, oxynitrides, carbonitrides, or combinations thereof. In some embodiments, the third insulating layer 260 may include an insulating material having etch selectivity relative to the second insulating layer 240.

[0087] refer to Figures 15A to 15C A plurality of bit line holes 270H are formed penetrating the third insulating layer 260, and a plurality of bit lines 270 fill the plurality of bit line holes 270H. The plurality of bit line holes 270H and the plurality of bit lines 270 extend in the vertical direction (Z direction) within the line trench LTR and may be arranged spaced apart from each other in the second horizontal direction (Y direction). The ends of a plurality of first semiconductor patterns 212R may be exposed on the inner surfaces of the plurality of bit line holes 270H. For example, the ends of the first semiconductor patterns 212R arranged spaced apart from each other in the vertical direction (Z direction) may be exposed on the two inner surfaces of each of the plurality of bit line holes 270H in the first horizontal direction (X direction). The plurality of bit line holes 270H may be formed such that a plurality of second semiconductor patterns 214D are not exposed within the plurality of bit line holes 270H. Each of the plurality of bit lines 270 may be connected to the ends of the first semiconductor patterns 212R arranged spaced apart from each other in the vertical direction (Z direction). Multiple bit lines 270 can be electrically insulated from multiple second semiconductor patterns 214D by being spaced apart by a third insulating layer 260 therebetween. Bit lines 270 can correspond to... Figure 1 The bit line BL is shown in the diagram.

[0088] Bit line 270 may include a conductive barrier layer covering the inner surface of bit line via 270H and contacting the end of the first semiconductor pattern 212R, and a conductive filling layer covering the conductive barrier layer. The conductive barrier layer may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. For example, the conductive barrier layer may include TiN. The conductive filling layer may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SrRuO (SRO), (Ba,Sr)RuO (BSRO), CaRuO (CRO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof. In some embodiments, the conductive filling layer may include W.

[0089] refer to Figures 16A to 16C The portion of the second insulating layer 240 filling the capacitor trench CTR is removed. The opposite ends of the plurality of first semiconductor patterns 212R, opposite to the plurality of bit lines 270, may be exposed on the inner surface of the capacitor trench CTR. The plurality of second semiconductor patterns 214D may not be exposed within the capacitor trench CTR. A plurality of first insulating layers 230 may be provided between the capacitor trench CTR and the plurality of second semiconductor patterns 214D. For example, within the capacitor trench CTR, the plurality of first semiconductor patterns 212R, the plurality of first insulating layers 230, and the second insulating layer 240 may be exposed, but the plurality of second semiconductor patterns 214D may not be exposed.

[0090] Subsequently, refer to Figures 3A to 3D Multiple capacitor structures 280, including multiple first electrodes 282, a capacitor dielectric layer 284 covering the multiple first electrodes 282, and a second electrode 286 covering the capacitor dielectric layer 284, are formed on the other end of multiple first semiconductor patterns 212R. The multiple first electrodes 282 may be formed to contact the corresponding other end of the multiple first semiconductor patterns 212R. The capacitor dielectric layer 284 may be formed to conformally cover the multiple first electrodes 282. The multiple first electrodes 282 may be electrically insulated from the multiple second semiconductor patterns 214D by being spaced apart from them by multiple first insulating layers 230 therebetween. Figure 3A and Figure 3BThe illustration shows capacitor dielectric layers 284, each covering a plurality of first electrodes 282, formed separately from each other; however, this is merely an example, and implementations are not limited thereto. For instance, the capacitor dielectric layer 284 may be formed as a single unit within a capacitor trench CTR to conformally cover a plurality of first electrodes 282, a plurality of first insulating layers 230, and a second insulating layer 240. A second electrode 286 may be formed to cover at least some of the plurality of first electrodes 282, with the capacitor dielectric layer 284 located therebetween. In some embodiments, the second electrode 286 may be formed as a single unit within a capacitor trench CTR to conformally cover a plurality of first electrodes 282, a plurality of first insulating layers 230, and a second insulating layer 240, with the capacitor dielectric layer 284 located therebetween.

[0091] The first electrode 282 may include a metal or a conductive metal nitride. For example, the first electrode 282 may include high-melting-point metals such as cobalt, titanium, nickel, tungsten, and molybdenum and / or conductive metal nitrides such as titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, and tungsten nitride. The capacitor dielectric layer 284 may include at least one selected from high-k dielectric materials and ferroelectric materials having a higher dielectric constant than silicon oxide. For example, the capacitor dielectric layer 284 may include at least one selected from metal oxides and dielectric materials having a perovskite structure. In some embodiments, the capacitor dielectric layer 284 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium nitride (HfON), hafnium silicon nitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium nitride (ZrON), zirconium silicon nitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the second electrode 286 may include doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SrRuO (SRO), (Ba,Sr)RuO (BSRO), CaRuO (CRO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or combinations thereof. In some embodiments, the second electrode 286 may include W.

[0092] Subsequently, a fourth insulating layer 290 can be formed covering multiple capacitor structures 280 and filling the capacitor trenches CTR, thereby forming a semiconductor memory device 1. The fourth insulating layer 290 may include oxides, nitrides, oxynitrides, carbonitrides, or combinations thereof.

[0093] In the method of manufacturing the semiconductor memory device 1 according to the present invention, since the gate structure 250 is formed after the second semiconductor pattern 214D is formed between the first semiconductor patterns 212R that are adjacent to each other in the second horizontal direction (Y direction), voids can be prevented from appearing in the gate electrode 254 included in the gate structure 250 during the formation process. Therefore, it is possible to prevent the gate electrode 254 from becoming thinner or breaking due to voids.

[0094] Figure 17 This is an equivalent circuit diagram showing the memory cell array of the semiconductor memory device 1a according to an embodiment.

[0095] refer to Figure 17 According to an embodiment, the memory cell array CAR of the semiconductor memory device 1a may include a plurality of sub-cell arrays SCA. The sub-cell array SCA may include a plurality of bit lines BLa, a plurality of word lines WL, and a plurality of memory cells MC. Each of the plurality of memory cells MC may include a cell transistor CT and an information storage element SP. A cell transistor CT may be arranged between a word line WL and a bit line BLa. The plurality of sub-cell arrays SCA may be arranged in a second horizontal direction (Y direction).

[0096] Multiple word lines (WL) can extend in the first horizontal direction (X direction). Word lines (WL) within a subcell array (SCA) can be spaced apart in the vertical direction (Z direction). Bit lines (BLa) can extend in the vertical direction (Z direction). Bit lines (BLa) within a subcell array (SCA) can be spaced apart in the first horizontal direction (X direction). Two adjacent subcell arrays (SCAs) in the second horizontal direction (Y direction) may not share bit lines (BLa).

[0097] The gate of the unit transistor CT can be connected to the word line WL, and the source region of the unit transistor CT can be connected to the bit line BLa. The information storage element SP can be connected to the drain region of the unit transistor CT.

[0098] In some embodiments, the source and drain regions of the unit transistor CT and the information storage element SP can be arranged in a second horizontal direction (Y direction) or in a direction opposite to the second horizontal direction (Y direction), connected from the bit line BLa to the source region of the unit transistor CT. The source and drain regions of the unit transistor CT connected to one of two adjacent bit lines BLa in the second horizontal direction (Y direction), and the information storage element SP connected to the unit transistor CT, can be arranged sequentially in a direction opposite to the direction in which the source and drain regions of the unit transistor CT connected to the other bit line BLa, and the information storage element SP connected to the unit transistor CT, are arranged sequentially. For example, the source and drain regions of the unit transistor CT connected to one of two adjacent bit lines BLa in the second horizontal direction (Y direction), and the information storage element SP connected to the unit transistor CT, can be arranged sequentially in the second horizontal direction (Y direction), and the source and drain regions of the unit transistor CT connected to the other bit line BLa, and the information storage element SP connected to the unit transistor CT, can be arranged sequentially in a direction opposite to the second horizontal direction (Y direction). For example, multiple bit lines BLa may include a first bit line, a second bit line, a third bit line, and a fourth bit line arranged sequentially adjacent to each other in the second horizontal direction (Y direction). Memory cells MC may not be arranged between the first bit line and the second bit line. Two memory cells MC may be arranged in the same vertical horizontal direction (Y direction) between the second bit line and the third bit line. Furthermore, memory cells MC may not be arranged between the third bit line and the fourth bit line.

[0099] Figure 18A , Figure 18B and Figure 18C This is a diagram illustrating a semiconductor memory device 1a according to an embodiment. In detail, Figure 18A This is a plan view showing the main components of the semiconductor memory device 1a. Figure 18B It is along the semiconductor memory device 1a Figure 18A A cross-sectional view taken from line B-B'. Figure 18C It is along the semiconductor memory device 1a Figure 18A A cross-sectional view taken along line C-C'. Figure 3A The position corresponding to line D-D' is intercepted. Figures 18A to 18C The cross-sectional view of the semiconductor memory device 1a shown is... Figure 3D They are basically the same, therefore, the following text can also be referenced. Figure 3D .

[0100] refer to Figure 18A , Figure 18B , Figure 18C and Figure 3DThe semiconductor memory device 1a may include a plurality of first semiconductor patterns 212R, a plurality of second semiconductor patterns 214D, a plurality of gate dielectric layers 252 surrounding at least a portion of the plurality of first semiconductor patterns 212R and the plurality of second semiconductor patterns 214D, a plurality of gate electrodes 254 surrounding at least a portion of the plurality of first semiconductor patterns 212R and the plurality of second semiconductor patterns 214D and located therebetween the plurality of gate dielectric layers 252, a plurality of bit lines 270a connected to one end of the plurality of first semiconductor patterns 212R, and a plurality of capacitor structures 280 connected to the other end of the plurality of first semiconductor patterns 212R.

[0101] Each of the plurality of first semiconductor patterns 212R and the plurality of second semiconductor patterns 214D can extend in a first horizontal direction (X direction). The plurality of first semiconductor patterns 212R can be arranged spaced apart from each other in each of the first horizontal direction (X direction), the second horizontal direction (Y direction), and the vertical direction (Z direction). The plurality of first semiconductor patterns 212R can have a matrix form in a planar view, arranged in rows in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction), and can be arranged to be aligned in the vertical direction (Z direction). The plurality of second semiconductor patterns 214D can be arranged spaced apart from each other in each of the first horizontal direction (X direction), the second horizontal direction (Y direction), and the vertical direction (Z direction). The second semiconductor patterns 214D can be arranged between a pair of first semiconductor patterns 212R that are adjacent to each other in the second horizontal direction (Y direction). For example, the first semiconductor patterns 212R and the second semiconductor patterns 214D can be arranged alternately, spaced apart from each other in the second horizontal direction (Y direction).

[0102] The first semiconductor pattern 212R may include a first portion 212C, a second portion 212S, and a third portion 212D. The second portion 212S and the third portion 212D may be located on opposite sides of the first portion 212C in a first horizontal direction (X direction). The second portion 212S, the first portion 212C, and the third portion 212D may be arranged sequentially from the bit line 270a to the capacitor structure 280 in the first horizontal direction (X direction). The first portion 212C of the first semiconductor pattern 212R may be surrounded by the gate structure 250, the second portion 212S of the first semiconductor pattern 212R may be surrounded by an insulating spacer 260SP and connected to the bit line 270a, and the third portion 212D of the first semiconductor pattern 212R may be surrounded by a first insulating layer 230 and a second insulating layer 240 (i.e., the interlayer insulating layer described above) and connected to the first electrode 282 of the capacitor structure 280.

[0103] In the first horizontal direction (X direction), one end of the first semiconductor pattern 212R can contact the bit line 270a, and one end of the second semiconductor pattern 214D can contact the third insulating layer 260. In the first horizontal direction (X direction), the other end of the first semiconductor pattern 212R can contact the first electrode 282 of the capacitor structure 280, and the other end of the second semiconductor pattern 214D can contact the first insulating layer 230.

[0104] Each of the plurality of gate electrodes 254 may extend in a second horizontal direction (Y direction). A plurality of bit lines 270a may be connected to one end of the plurality of first semiconductor patterns 212R in the first horizontal direction (X direction), and a plurality of capacitor structures 280 may be connected to the other end of the plurality of first semiconductor patterns 212R in the first horizontal direction (X direction). The gate electrodes 254 may be... Figure 17 The word line WL shown is shown. Bit line 270a can be... Figure 17 The bit line BLa is shown. Capacitor structure 280 can be... Figure 17 The information storage element SP shown in the diagram. A first semiconductor pattern 212R, a gate dielectric layer 252, a gate electrode 254, and a bit line 270a can be formed. Figure 17 The unit transistor CT shown has a gate electrode 254 that may be spaced apart from the bit line 270a and a third insulating layer 260 therebetween, including insulating spacers 260SP.

[0105] The second portion 212S, the first portion 212C, and the third portion 212D of the first semiconductor pattern 212R can be arranged sequentially from the bit line 270a in the second horizontal direction (Y direction) or in the direction opposite to the second horizontal direction (Y direction).

[0106] The third insulating layer 260 may surround multiple bit lines 270a and may fill the line trench LTR. The multiple bit lines 270a may fill multiple bit line vias 270Ha penetrating the third insulating layer 260. The multiple bit lines 270a may be connected to the ends of multiple first semiconductor patterns 212R in the first horizontal direction (X direction). The multiple bit line vias 270Ha and the multiple bit lines 270a may extend in the vertical direction (Z direction) within the line trench LTR. Within the line trench LTR, a pair of bit line vias 270Ha spaced apart from each other in the first horizontal direction (X direction) and a pair of bit lines 270a filling the pair of bit line vias 270Ha may be arranged in a row spaced apart from each other in the second horizontal direction (Y direction).

[0107] The plurality of capacitor structures 280 may include a plurality of first electrodes 282, a capacitor dielectric layer 284, and a second electrode 286. The plurality of capacitor structures 280 may be connected to the other end of a plurality of first semiconductor patterns 212R in a first horizontal direction (X direction). A fourth insulating layer 290 may cover the plurality of capacitor structures 280 and may fill the capacitor trench CTR.

[0108] While the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0109] This application claims priority and benefit to Korean Patent Application No. 10-2025-0023161, filed on February 21, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: The first semiconductor pattern extends in a first horizontal direction; The second semiconductor pattern has a horizontal width in the second horizontal direction that is smaller than the horizontal width of the first semiconductor pattern, is spaced apart from the first semiconductor pattern in the second horizontal direction, and extends in the first horizontal direction, wherein the second horizontal direction is substantially orthogonal to the first horizontal direction; A gate structure, surrounding the first semiconductor pattern and the second semiconductor pattern and extending in the second horizontal direction; Bit lines are connected to the end of the first semiconductor pattern in the first horizontal direction and extend in the vertical direction; as well as A capacitor structure is connected to the other end of the first semiconductor pattern in the first horizontal direction. The second semiconductor pattern is spaced apart from each of the bit lines and the capacitor structure.

2. The semiconductor memory device according to claim 1, wherein, In the first horizontal direction, the length of the first semiconductor pattern is greater than the length of the second semiconductor pattern.

3. The semiconductor memory device according to claim 2, wherein, In the first horizontal direction, the end of the first semiconductor pattern is aligned with the end of the second semiconductor pattern in the second horizontal direction.

4. The semiconductor memory device according to claim 1, wherein, In the second horizontal direction, the first semiconductor pattern and the second semiconductor pattern are spaced apart from each other by a pattern spacing that is smaller than the horizontal width of the first semiconductor pattern and larger than the horizontal width of the second semiconductor pattern.

5. The semiconductor memory device of claim 1, further comprising a wire trench-filled insulating layer surrounding the bit line. The second semiconductor pattern is in contact with the trench-filling insulating layer at its end in the first horizontal direction and is electrically insulated from the bit line.

6. The semiconductor memory device of claim 5, further comprising an interlayer insulating layer surrounding the first semiconductor pattern, the second semiconductor pattern, and the gate structure. The first semiconductor pattern includes a first portion, a second portion, and a third portion. The first portion is surrounded by the gate structure, the second portion is surrounded by the trench-filled insulating layer and connected to the bit line, and the third portion is surrounded by the interlayer insulating layer and connected to the capacitor structure. The second portion, the first portion, and the third portion of the first semiconductor pattern are arranged sequentially from the bit line to the capacitor structure in the first horizontal direction.

7. The semiconductor memory device according to claim 6, wherein, In the first horizontal direction, the length of the first part is greater than the length of the second part and the length of the third part.

8. The semiconductor memory device according to claim 6, wherein, In the second horizontal direction, the horizontal width of the third part is greater than each of the horizontal widths of the first part and the second part.

9. The semiconductor memory device according to claim 6, wherein, In the vertical direction, the thickness of the third portion is greater than the thickness of each of the first portion and the second portion.

10. The semiconductor memory device according to claim 9, wherein, In the vertical direction, the thickness of the second semiconductor pattern is equal to each of the thickness of the first portion and the thickness of the second portion.

11. A semiconductor memory device, comprising: Multiple first semiconductor patterns, each extending in a first horizontal direction and spaced apart from each other in each of a second horizontal and vertical direction, wherein the second horizontal direction is substantially orthogonal to the first horizontal direction; A plurality of second semiconductor patterns extend in the first horizontal direction, each second semiconductor pattern having a horizontal width in the second horizontal direction that is smaller than the horizontal width of each of the plurality of first semiconductor patterns, and are arranged spaced apart from each other in each of the second horizontal direction and the vertical direction, and are arranged alternately with the plurality of first semiconductor patterns in the second horizontal direction. A plurality of gate structures are arranged around the plurality of first semiconductor patterns and the plurality of second semiconductor patterns, each gate structure extending in the second horizontal direction and spaced apart from each other in the vertical direction; An interlayer insulating layer surrounds the plurality of first semiconductor patterns, the plurality of second semiconductor patterns, and the plurality of gate structures; Multiple bit lines are connected to the ends of the first semiconductor patterns arranged at intervals in the vertical direction among the plurality of first semiconductor patterns, each bit line extending in the vertical direction and arranged at intervals in the second horizontal direction. The wire trench is filled with an insulating layer surrounding the plurality of bit lines; Multiple capacitor structures are connected to the other end of the multiple first semiconductor patterns in the first horizontal direction; as well as The capacitor trenches are filled with an insulating layer surrounding the plurality of capacitor structures. The plurality of second semiconductor patterns are spaced apart from the plurality of bit lines and the plurality of capacitor structures.

12. The semiconductor memory device according to claim 11, wherein, In the first horizontal direction, the ends of the plurality of first semiconductor patterns are aligned with the ends of the plurality of second semiconductor patterns in the second horizontal direction, and In the first horizontal direction, the length of each of the plurality of first semiconductor patterns is greater than the length of each of the plurality of second semiconductor patterns.

13. The semiconductor memory device according to claim 11, wherein, In the first horizontal direction, the ends of the plurality of second semiconductor patterns are in contact with the trench-filling insulating layer and electrically insulated from the plurality of bit lines, and the other ends of the plurality of second semiconductor patterns are in contact with the interlayer insulating layer and electrically insulated from the plurality of capacitor structures.

14. The semiconductor memory device of claim 11, wherein each of the plurality of first semiconductor patterns includes a first portion, a second portion, and a third portion, the first portion being surrounded by a gate structure of the plurality of gate structures, the second portion being surrounded by the trench-filled insulating layer and connected to a bit line of the plurality of bit lines, and the third portion being surrounded by the interlayer insulating layer and connected to a capacitor structure of the plurality of capacitor structures. The second portion, the first portion, and the third portion of each of the plurality of first semiconductor patterns are arranged sequentially in the first horizontal direction from one of the plurality of bit lines to one of the plurality of capacitor structures, and In the first horizontal direction, the length of the first part is greater than the length of the second part and the length of the third part.

15. The semiconductor memory device of claim 14, wherein each of the plurality of second semiconductor patterns includes a first dummy portion and a second dummy portion, the first dummy portion being surrounded by one of the plurality of gate structures, and the second dummy portion being surrounded by the trench-filled insulating layer. In the first horizontal direction, the length of the first dummy portion of each of the plurality of second semiconductor patterns is greater than the length of the second dummy portion and less than the length of the first portion of each of the plurality of first semiconductor patterns.

16. The semiconductor memory device according to claim 15, wherein, In the first horizontal direction, the length of the second dummy portion of each of the plurality of second semiconductor patterns is equal to the length of the second portion of each of the plurality of first semiconductor patterns.

17. The semiconductor memory device of claim 14, wherein, The thickness of the third part and its horizontal width in the second horizontal direction are respectively greater than the thickness of the first part and its horizontal width in the second horizontal direction, as well as the thickness of the second part and its horizontal width in the second horizontal direction.

18. A semiconductor memory device, comprising: Multiple first semiconductor patterns, each extending in a first horizontal direction and spaced apart from each other in each of a second horizontal and vertical direction, wherein the second horizontal direction is substantially orthogonal to the first horizontal direction; A plurality of second semiconductor patterns extend in the first horizontal direction, each second semiconductor pattern having a horizontal width in the second horizontal direction that is smaller than the horizontal width of each of the plurality of first semiconductor patterns, and are arranged spaced apart from each other in each of the second horizontal direction and the vertical direction, and are arranged alternately with the plurality of first semiconductor patterns in the second horizontal direction. A plurality of gate structures are arranged around the plurality of first semiconductor patterns and the plurality of second semiconductor patterns, each gate structure extending in the second horizontal direction and spaced apart from each other in the vertical direction; An interlayer insulating layer surrounds the plurality of first semiconductor patterns, the plurality of second semiconductor patterns, and the plurality of gate structures; Multiple bit lines are connected to the ends of the first semiconductor patterns arranged at intervals in the vertical direction among the plurality of first semiconductor patterns, each bit line extending in the vertical direction and arranged at intervals in the second horizontal direction. The wire trench is filled with an insulating layer surrounding the plurality of bit lines; Multiple capacitor structures are connected to the other end of the multiple first semiconductor patterns in the first horizontal direction; as well as The capacitor trenches are filled with an insulating layer surrounding the plurality of capacitor structures. In the first horizontal direction, one end of the plurality of second semiconductor patterns contacts the trench-filling insulating layer, and the other end of the plurality of second semiconductor patterns contacts the interlayer insulating layer.

19. The semiconductor memory device of claim 18, wherein, Each of the plurality of first semiconductor patterns includes a first portion, a second portion, and a third portion, the first portion being surrounded by one of the plurality of gate structures, the second portion being surrounded by the line trench-filled insulating layer and connected to one of the plurality of bit lines, and the third portion being surrounded by the interlayer insulating layer and connected to one of the plurality of capacitor structures. Each of the plurality of second semiconductor patterns includes a first dummy portion and a second dummy portion, the first dummy portion being surrounded by one of the plurality of gate structures, and the second dummy portion being surrounded by the trench-filled insulating layer. In the first horizontal direction, the length of the first dummy portion of each of the plurality of second semiconductor patterns is greater than the length of the second dummy portion and less than the length of the first portion of each of the plurality of first semiconductor patterns. In the first horizontal direction, the length of the second dummy portion of each of the plurality of second semiconductor patterns is equal to the length of the second portion of each of the plurality of first semiconductor patterns.

20. The semiconductor memory device of claim 19, wherein, In the second horizontal direction, the horizontal width of the third portion of each of the plurality of first semiconductor patterns is greater than the horizontal width of each of the first portion and the horizontal width of the second portion, and In the vertical direction, the thickness of the third portion of each of the plurality of first semiconductor patterns is greater than the thickness of each of the first portion and the thickness of the second portion.

Images