Semiconductor memory device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor storage device capable of improving characteristics of a semiconductor layer and a manufacturing method thereof. The semiconductor storage device of the present embodiment includes a laminate and a columnar portion. The laminate is obtained by laminating a plurality of first conductive layers in a first direction with insulating layers interposed therebetween. The columnar portion penetrates the laminate and extends in the first direction. The columnar portion has a semiconductor layer and a storage film. The semiconductor layer penetrates the laminate and extends in the first direction. The storage film includes a first insulating film provided between the laminate and the semiconductor layer, a charge accumulation layer, and a second insulating film. The semiconductor storage device further includes a second conductive layer electrically connected to the semiconductor layer at an end portion of the columnar portion. At least one crystal grain within the semiconductor layer has a shape in contact with the storage film. The semiconductor layer at the end portion of the columnar portion has a first opening portion, or a grain boundary exists in the semiconductor layer at the end portion of the columnar portion.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor memory devices and methods for manufacturing the same. Background Technology

[0002] The characteristics of the channel semiconductor layer in a semiconductor memory have a significant impact on the performance of the memory cell. For example, when the mobility of the channel semiconductor layer is low, the threshold voltage of the memory cell will increase, and the operating voltage of the memory cell will also increase. Summary of the Invention

[0003] A semiconductor memory device and its manufacturing method are provided, which can improve the properties of the semiconductor layer.

[0004] The semiconductor memory device according to this embodiment includes a laminate and a columnar portion. The laminate is a laminate obtained by stacking multiple first conductive layers in a first direction with an insulating layer between them. The columnar portion extends through the laminate and in the first direction. The columnar portion has a semiconductor layer and a memory film. The semiconductor layer extends through the laminate and in the first direction. The memory film includes a first insulating film, a charge storage layer, and a second insulating film disposed between the laminate and the semiconductor layer. The semiconductor memory device also includes a second conductive layer electrically connected to the semiconductor layer at the end of the columnar portion. At least one grain in the semiconductor layer has a shape that is in contact with the memory film. The semiconductor layer at the end of the columnar portion has a first opening, or a grain boundary exists in the semiconductor layer at the end of the columnar portion. Attached Figure Description

[0005] Figure 1 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device according to the first embodiment.

[0006] Figure 2A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment.

[0007] Figure 2B Is following Figure 2A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0008] Figure 2C Is following Figure 2B The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0009] Figure 3A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment.

[0010] Figure 3B Is following Figure 3A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0011] Figure 3C Is following Figure 3B The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0012] Figure 3D Is following Figure 3C The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0013] Figure 3E Is following Figure 3D The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0014] Figure 3F Is following Figure 3E The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0015] Figure 3G Is following Figure 3F The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0016] Figure 4A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device, a variation of the first embodiment.

[0017] Figure 4B Is following Figure 4A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0018] Figure 5A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the second embodiment.

[0019] Figure 5B Is following Figure 5A The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0020] Figure 5C Is following Figure 5B The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0021] Figure 5D Is following Figure 5C The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0022] Figure 5E Is following Figure 5D The following is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device.

[0023] Label Explanation

[0024] 1. Substrate; 3. Source-side conductive layer; 5. Electrode layer; 6. Insulating layer; 12. Block insulating film; 13. Charge storage layer; 14. Tunnel insulating film; 15. Channel semiconductor layer; 16. Core insulating film; 21. Semiconductor layer; 22. Metal atom; 41. Film; 56. Protective film; CL. Columnar portion; M. Storage hole Detailed Implementation

[0025] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts may not be the same as in reality. In the specification and drawings, the same reference numerals are used for elements that are described with reference to the accompanying drawings, and detailed descriptions are omitted where appropriate.

[0026] (First Embodiment)

[0027] Figure 1 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device according to the first embodiment. Figure 1 The semiconductor memory device has a three-dimensional semiconductor memory.

[0028] Figure 1 The semiconductor memory device includes a substrate 1, a lower insulating film 2, a source-side conductive layer 3, an upper insulating film 4, multiple electrode layers 5, multiple insulating layers 6, a cover insulating film 7, a drain-side conductive layer 8, a first interlayer insulating film 9, a second interlayer insulating film 10, multiple contact plugs 11, a barrier insulating film 12 (an example of the second insulating film), a charge storage layer 13, a tunnel insulating film 14 (an example of the first insulating film), a channel semiconductor layer 15, and a core insulating film 16 (an example of the third insulating film).

[0029] Substrate 1 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Figure 1 The X and Y directions, which are parallel to and perpendicular to the surface of substrate 1, and the Z direction, which is perpendicular to the surface of substrate 1, are shown. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not be aligned with the direction of gravity. The Z direction is an example of the first direction.

[0030] The lower insulating film 2 is formed on the diffusion layer L formed in the substrate 1. The source-side conductive layer 3 is formed on the lower insulating film 2. The upper insulating film 4 is formed on the source-side conductive layer 3.

[0031] Multiple electrode layers 5 and multiple insulating layers 6 are alternately stacked on the upper insulating film 4, and are stacked in the Z direction. The electrode layers 5 are conductive layers such as metal layers, and function as word lines or select lines. The number of electrode layers 5 is, for example, 64 or more. The insulating layers 6 are, for example, SiO2 films (silicon oxide films). The number of insulating layers 6 is, for example, 64 or more. Figure 1 The storage hole M penetrating the electrode layer 5 and the insulating layer 6 is shown, as well as the contact hole H formed on the stepped region of the electrode layer 5 and the insulating layer 6.

[0032] A cover insulating film 7 is formed on the laminate including the electrode layers 5 and the insulating layer 6. A drain-side conductive layer 8 is formed on the cover insulating film 7 adjacent to the stepped region. A first interlayer insulating film 9 is formed on the cover insulating film 7 to fill the space in the stepped region. A second interlayer insulating film 10 is formed on the drain-side conductive layer 8 and the first interlayer insulating film 9.

[0033] Multiple contact plugs 11 are formed within contact holes H that penetrate the insulating film 7, the first interlayer insulating film 9, and the second interlayer insulating film 10. These contact plugs 11 are electrically connected to different electrode layers 5. Each contact plug 11 is formed, for example, from a plug material layer such as a Ti (titanium) layer containing a barrier metal layer and a W (tungsten) layer.

[0034] A barrier insulating film 12, a charge storage layer 13, a tunnel insulating film 14, a channel semiconductor layer 15, and a core insulating film 16 are sequentially formed on the side of a storage hole M that penetrates the lower insulating film 2, the source-side conductive layer 3, the upper insulating film 4, the electrode layer 5, the insulating layer 6, the cover insulating film 7, the drain-side conductive layer 8, and the second interlayer insulating film 10. The barrier insulating film 12 is, for example, a SiO2 film. The charge storage layer 13 is, for example, a SiN film (silicon nitride film), but can also be a polycrystalline silicon layer, a polycrystalline silicon germanium layer, or other semiconductor layer. The tunnel insulating film 14 is, for example, a SiO2 film. The channel semiconductor layer 15 is, for example, a polycrystalline silicon layer or a polycrystalline silicon germanium layer, and is electrically connected to the substrate 1. The core insulating film 16 is, for example, a SiO2 film. Reference numeral 17 indicates a storage film including the barrier insulating film 12, the charge storage layer 13, and the tunnel insulating film 14. The core insulating film 16 has a generally cylindrical shape extending in the Z direction. The channel semiconductor layer 15, the tunnel insulating film 14, the charge storage layer 13, and the barrier insulating film 12 have a generally cylindrical shape extending in the Z direction and sequentially surround the core insulating film 16 in an annular shape.

[0035] The barrier insulating film 12, charge storage layer 13, tunnel insulating film 14, channel semiconductor layer 15, and core insulating film 16 are formed, for example, by the following steps: First, the barrier insulating film 12, charge storage layer 13, and tunnel insulating film 14 are sequentially formed on the side and bottom surfaces of the storage hole M. Next, the tunnel insulating film 14, charge storage layer 13, and barrier insulating film 12 are removed from the bottom surface of the storage hole M. Then, the channel semiconductor layer 15 and core insulating film 16 are sequentially filled into the storage hole M.

[0036] Next, the details of the channel semiconductor layer 15 and the tunnel insulating film 14 in this embodiment will be described.

[0037] The channel semiconductor layer 15 in this embodiment contains trace amounts of metal atoms. The concentration of metal atoms within the channel semiconductor layer 15 is, for example, 4.0 × 10⁻⁶. 17 [pieces / cm] 3 In this embodiment, these metal atoms are distributed substantially uniformly within the channel semiconductor layer 15. These metal atoms are, for example, Ni (nickel) atoms. In this embodiment, the thickness of the tunnel insulating film 14 is, for example, 5 nm or more and 10 nm or less, and the thickness of the channel semiconductor layer 15 is, for example, 15 nm or less (preferably 10 nm or less).

[0038] In this embodiment, after a film containing metal atoms is formed on the surface of the channel semiconductor layer 15 (semiconductor layer 21 described later) before crystallization, the channel semiconductor layer 15 is crystallized. This allows the channel semiconductor layer 15 to be crystallized at low temperatures, increasing the grain size within the channel semiconductor layer 15. As a result, the mobility of the channel semiconductor layer 15 can be increased, and the threshold voltage of the memory cells in the three-dimensional semiconductor memory can be reduced. During the crystallization of the channel semiconductor layer 15, these metal atoms enter the channel semiconductor layer 15.

[0039] According to this embodiment, by forming a film containing metal atoms on the surface of the channel semiconductor layer 15 before crystallization and then crystallizing the channel semiconductor layer 15, the grain size within the channel semiconductor layer 15 can be set to, for example, 80 nm or more and 1600 nm or less. Such a grain size can be achieved, for example, by forming a concentration of metal atoms within the channel semiconductor layer 15 of 5.0 × 10⁻⁶ on the surface of the channel semiconductor layer 15. 17 [pieces / cm] 3 This is achieved using a film containing the amount of metal atoms mentioned above.

[0040] In this embodiment, after crystallizing the channel semiconductor layer 15, a portion of the metal atoms within the channel semiconductor layer 15 are removed. As described above, this reduces the concentration of metal atoms within the channel semiconductor layer 15 to 4.0 × 10⁻⁶. 17 [pieces / cm]3 ]the following.

[0041] Based on 5.0 × 10⁻⁶ before removing metal atoms 17 [pieces / cm] 3 At this concentration, particle sizes of, for example, 80 nm or larger and 1600 nm or smaller can be achieved. On the other hand, based on a particle size of 4.0 × 10⁻⁶ after removing metal atoms... 17 [pieces / cm] 3 The following concentration, for example, can reduce the leakage current in the tunnel insulating film 14 compared to the case where metal atoms are not removed.

[0042] The metal atom in this embodiment is, for example, a Ni atom, but it can also be other metal atoms. Preferably, the metal atom in this embodiment includes at least one atom selected from, for example, Au (gold), Al (aluminum), Cu (copper), Ag (silver), Pd (palladium), Ni (nickel), and Pt (platinum) (Example 1). Alternatively, the metal atom in this embodiment may also include, for example, at least one atom selected from, Mn (manganese), Rh (rhodium), Co (cobalt), Fe (iron), Cr (chromium), Ti (titanium), Nb (niobium), Ir (iridium), Ta (tantalum), Re (rhenium), Mo (molybdenum), V (vanadium), Hf (hafnium), Ru (ruthenium), Zr (zirconium), and W (tungsten) (Example 2). Both the metal atoms in Example 1 and Example 2 have the effect of lowering the crystallization temperature of the channel semiconductor layer 15, but generally, the effect is greater in Example 1 than in Example 2.

[0043] Using materials such as Al and Ti has the following advantages: by performing oxidation or nitriding treatments after crystallization of the channel semiconductor layer 15, an insulating film can be formed on the surface of the channel semiconductor layer 15. When Al or Ti is present in the channel semiconductor layer 15, the short-channel characteristics of the tunnel insulating film 14 and the channel semiconductor layer 15 may deteriorate. However, if the channel semiconductor layer 15 containing Al is oxidized or nitrided, AlO is formed on the surface of the channel semiconductor layer 15. X The film, specifically the AlN film, serves as an insulating film and can suppress the degradation of short-channel characteristics. Similarly, if the Ti-containing channel semiconductor layer 15 is oxidized, TiO2 is formed on the surface of the channel semiconductor layer 15. X As an insulating membrane, the membrane can suppress the degradation of short-channel characteristics.

[0044] The channel semiconductor layer 15 may also contain boron (B), phosphorus (P), or arsenic (As) atoms in addition to metal atoms. In this embodiment, the channel semiconductor layer 15 contains, for example, 1.0 × 10⁻⁶ atoms. 16 [pieces / cm] 3 Above and 1.0 × 10 19 [pieces / cm] 3The concentrations of B, P, or As atoms below a certain level are used. This allows the threshold voltage of the storage cells in a three-dimensional semiconductor memory to be adjusted to an appropriate value.

[0045] Figures 2A to 2C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment.

[0046] First, such as Figure 2A As shown, a laminate is formed above the substrate 1 by alternately stacking multiple electrode layers 5 and multiple insulating layers 6 in the Z direction. Then, a laminate penetrating the first region in the Z-axis direction and reaching the storage via M of the substrate 1 is formed. Next, a storage film 17 (a barrier insulating film 12, a charge storage layer 13, and a tunnel insulating film 14) and a semiconductor layer 21 are sequentially formed on the sides of the electrode layers 5 and insulating layers 6 within the storage via M. The storage film 17 and the semiconductor layer 21 are also formed on the upper surface of the laminate structure of the electrode layers 5 and insulating layers 6.

[0047] Semiconductor layer 21 is used to form Figure 1 The channel semiconductor layer 15 is an amorphous semiconductor layer, such as an amorphous silicon layer. The semiconductor layer 21 is formed, for example, by LPCVD (Low Pressure Chemical Vapor Deposition) at a temperature of 400°C to 600°C and a pressure of 1 Pa to 500 Pa. Examples of source gases for the semiconductor layer 21 are SiH4 gas, Si2H6 gas, SiH2Cl2 gas, Si2Cl6 gas, and organic gases containing Si (H represents hydrogen, Cl represents chlorine). In addition, the thickness of the tunnel insulating film 14 is set to be, for example, 5 nm or more and 10 nm or less, and the thickness of the semiconductor layer 21 is set to be, for example, 15 nm or less (preferably 10 nm or less).

[0048] In addition, Figure 2A In the process, instead of alternately stacking multiple electrode layers 5 and multiple insulating layers 6, multiple sacrificial layers and multiple insulating layers 6 can also be alternately stacked. The sacrificial layer is, for example, a SiN film. In this case, the sacrificial layer is replaced by the electrode layer 5 in a later process. Specifically, the sacrificial layer between the insulating layers 6 is removed, multiple cavities are formed between the insulating layers 6, and the electrode layer 5 is filled into these cavities.

[0049] Next, as Figure 2B As shown, a film 41 containing metal atoms is formed on the upper surface of the stacked structure of electrode layer 5 and insulating layer 6, that is, in the second region of the stack without storage holes M. The film 41 is formed, for example, by PVD (Physical Vapor Deposition) such as sputtering. The metal atoms are, for example, Ni atoms.

[0050] Next, as Figure 2C As shown, the semiconductor layer 21 is annealed. Annealing is performed, for example, at a temperature of 500°C to 1000°C and a pressure of 100 Pa to atmospheric pressure. As a result, metal atoms enter the semiconductor layer 21, and the semiconductor layer 21 is crystallized. Figure 2C A channel semiconductor layer 15, obtained by modifying semiconductor layer 21, is shown. The channel semiconductor layer 15 is, for example, a polycrystalline silicon layer. Annealing can be performed in an atmosphere containing at least one of H2 gas, D2 (deuterium) gas, N2 gas, and rare gases.

[0051] At least one grain within the channel semiconductor layer 15 has a shape that is in contact with the storage film 17. The grain within the channel semiconductor layer 15 can be 65 nm or larger, and the channel semiconductor layer 15 can also be a single crystal.

[0052] In this embodiment, it is also possible to... Figure 2C After annealing in the process, in comparison Figure 2C The channel semiconductor layer 15 is further annealed at a high temperature. This improves the crystallinity of the channel semiconductor layer 15. The annealing can also be performed in an atmosphere containing at least one of H2 gas, D2 gas, N2 gas, and rare gases.

[0053] Next, the process after the crystallization of the channel semiconductor layer 15 will be described.

[0054] Figures 3A to 3G This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment.

[0055] exist Figures 3A to 3G In the example shown, a semiconductor layer 51, an intermediate film 52, a sacrificial film 53, an intermediate film 54, and a semiconductor layer 55 are disposed on a substrate 1. Semiconductor layers 51 and 55 may comprise, for example, polycrystalline silicon. Intermediate films 52 and 54 may comprise, for example, silicon oxide films. Sacrificial film 53 may comprise, for example, a silicon nitride film.

[0056] First, with Figure 2C Similarly, as Figure 3A As shown, the semiconductor layer 21 is annealed to crystallize it. After forming the crystallized channel semiconductor layer 15, metal atoms 22 and a silicon compound 61 are deposited (condensed) in the channel semiconductor layer 15 at the bottom of the memory hole M. The compound 61 is, for example, NiSi2. In addition, elemental metal atoms 22 are also present in the channel semiconductor layer 15.

[0057] Next, as Figure 3BAs shown, a protective film 56 is formed on the channel semiconductor layer 15. The protective film 56 is, for example, a silicon oxide film. The protective film 56 protects the sidewalls of the channel semiconductor layer 15 in subsequent processes.

[0058] Next, as Figure 3C As shown, an opening 56a is formed in the protective film 56 at the bottom of the storage hole M. The opening 56a is formed, for example, by RIE (Reactive Ion Etching).

[0059] Next, as Figure 3D As shown, a portion of the channel semiconductor layer 15 at the bottom of the memory hole M is removed. More specifically, a portion of the channel semiconductor layer 15 is removed via the opening 56a. Thus, the channel semiconductor layer 15 at the bottom of the memory hole M is truncated, forming an opening 15a in the channel semiconductor layer 15. The portion of the channel semiconductor layer 15 is removed, for example, by wet etching. Compound 61 is removed along with the portion of the channel semiconductor layer 15.

[0060] Next, as Figure 3E As shown, after removing the protective film 56, a core insulating film 16 is formed to fill the storage via M, and gettering of the metal atoms 22 within the channel semiconductor layer 15 is performed. Gettering is performed, for example, by forming a getter layer (not shown) on the laminate and annealing the getter layer. As a result, some of the metal atoms 22 within the channel semiconductor layer 15 move toward the getter layer, and the concentration (and / or total amount) of the metal atoms 22 within the channel semiconductor layer 15 decreases. The getter layer is, for example, an amorphous semiconductor layer, specifically an amorphous silicon layer.

[0061] Next, as Figure 3F As shown, the intermediate film 52, sacrificial film 53, and intermediate film 54 are removed, and the exposed storage film 17 is also removed. As a result, the channel semiconductor layer 15 is exposed.

[0062] Next, as Figure 3G As shown, a source-side conductive layer 3 is formed that is electrically connected to the channel semiconductor layer 15. The channel semiconductor layer 15 is connected to the source-side conductive layer 3 on the side of the memory hole M. The source-side conductive layer 3 contains, for example, silicon. Furthermore, the opening 15a of the channel semiconductor layer 15 does not affect the connection with the source-side conductive layer 3.

[0063] like Figure 3GAs shown, the semiconductor memory device includes a columnar portion CL. The columnar portion CL extends in the Z direction, penetrating the stack of electrode layer 5 and insulating layer 6. The columnar portion CL includes a memory film 17 embedded in a memory hole M, a channel semiconductor layer 15, and a core insulating film 16. The channel semiconductor layer 15 extends in the Z direction, penetrating the stack of electrode layer 5 and insulating layer 6. The memory film 17 is disposed between the stack of electrode layer 5 and insulating layer 6 and the channel semiconductor layer 15. The memory film 17 is disposed along the bottom surface of the memory hole M.

[0064] The channel semiconductor layer 15 at the end of the columnar portion CL has an opening 15a. The core insulating film 16 is provided in such a way that it penetrates the opening 15a of the channel semiconductor layer 15.

[0065] The source-side conductive layer 3 is electrically connected to the channel semiconductor layer 15 at the end of the pillar CL. More specifically, the channel semiconductor layer 15 is connected to the source-side conductive layer 3 on the side surface of the end of the pillar CL.

[0066] As described above, according to the first embodiment, a channel semiconductor layer 15 with a relatively large grain size is formed by crystallizing a film 41 containing metal atoms. Furthermore, the concentration of metal atoms 22 within the channel semiconductor layer 15 is reduced through the removal of the etch-based compound 61 and the gettering of the metal atoms 22. Therefore, the characteristics of the channel semiconductor layer 15 are improved, such as increasing the mobility of the channel semiconductor layer 15, while suppressing leakage current in the tunnel insulating film 14.

[0067] Furthermore, in the first embodiment, compound 61 can be removed by directly etching the channel semiconductor layer 15 containing compound 61. This increases the gettering efficiency of the metal atoms 22 and compound 61.

[0068] As another example of removing compound 61, sometimes annealing is used to thermally decompose compound 61 into metal atoms 22, which then segregate to the getter layer, and the getter layer is peeled off. However, the higher the stack of electrode layer 5 and insulating layer 6 is, the longer the distance to the getter layer becomes. In addition, the more tapered the bottom of the storage hole M becomes, the higher the density of compound 61 will be. Therefore, thermal decomposition of compound 61 accumulated at the bottom of the storage hole M becomes difficult, and the getter efficiency may deteriorate. Increasing the required high temperature, long duration, or multiple cycles of gettering may lead to a high concentration of residual metal atoms 22 due to diffusion of metal atoms 22, and a deterioration of unit cell characteristics.

[0069] In contrast, in the first embodiment, compound 61 can be removed by directly etching the channel semiconductor layer 15 containing compound 61. This improves the getter efficiency of the metal atoms 22. Furthermore, gettering based on the body film of the channel semiconductor layer 15 is possible. Additionally, costs can be reduced by decreasing the number of processing steps.

[0070] (A variation of the first embodiment)

[0071] Figure 4A and Figure 4B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to a variation of the first embodiment. The variation of the first embodiment differs from the first embodiment in that the memory hole M is a pointed shape.

[0072] Figure 4A The process shown is in relation to Figures 2A to 2C , Figure 3A as well as Figure 3B The same process is then performed. Figure 4A The process shown is the same as that of the first embodiment for forming the opening 56a. Figure 3C The process shown corresponds to the steps.

[0073] like Figure 4A As shown, when the storage hole M is a pointed shape, compound 61 tends to condense (at a relatively high density) in a relatively narrow area at the front end of the storage hole M.

[0074] Next, as Figure 4B As shown, a portion of the channel semiconductor layer 15 at the bottom of the storage hole M is removed. This forms an opening 15a in the channel semiconductor layer 15. The portion of the channel semiconductor layer 15 is removed, for example, by dry etching. Compound 61 is removed along with the portion of the channel semiconductor layer 15.

[0075] Dry etching removes the narrow channel semiconductor layer 15 condensed by compound 61.

[0076] Then, proceed with the method described in the first embodiment. Figure 3E The same process will be repeated thereafter.

[0077] As in the variation of the first embodiment, the storage hole M can also be a pointed shape. The semiconductor storage device of the variation of the first embodiment can achieve the same effect as the first embodiment.

[0078] (Second Implementation)

[0079] Figures 5A-5EThis is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. The second embodiment differs from the first embodiment in that the channel semiconductor layer 15 is connected to the source-side conductive layer 3 at the end face of the columnar portion CL.

[0080] Figure 5A The process shown is in relation to Figures 2A to 2C and Figures 3A-3C The same process is then performed. Figure 5A The process shown is the removal of a portion of the channel semiconductor layer 15 at the bottom of the storage hole M, in the first embodiment. Figure 3D The process shown corresponds to this. In addition, an intermediate membrane 57 is provided instead of intermediate membrane 52, sacrificial membrane 53, and intermediate membrane 54.

[0081] Next, as Figure 5B As shown, silicon epitaxial growth is performed on the channel semiconductor layer 15. Single crystals of the channel semiconductor layer 15 grow along the memory film 17 from various directions along the edge of the opening 15a. That is, single crystals of the channel semiconductor layer 15 grow along the side and bottom surfaces of the memory hole M. As a result, the channel semiconductor layer 15 is reconnected at the bottom of the memory hole M, so that the opening 15a is closed. The grain boundary B of the channel semiconductor layer 15 is the reconnected portion. The channel semiconductor layer 15 near the grain boundary B can include relatively large-diameter grains or single crystals.

[0082] Furthermore, in the reconnection portion of the channel semiconductor layer 15 forming the grain boundary B, the channel semiconductor layer 15 may not be neatly connected, but may have a bulging shape. That is, the channel semiconductor layer 15 where the grain boundary B exists (the channel semiconductor layer 15 near the grain boundary B) may be thicker than other portions of the channel semiconductor layer 15.

[0083] Next, as Figure 5C As shown, the protective film 56 is removed to form a core insulating film 16 that fills the storage hole M, and metal atoms 22 in the channel semiconductor layer 15 are getted. Figure 5C The process shown is the same as Figure 3E The procedures shown are the same.

[0084] Next, as Figure 5D As shown, the substrate 1 is peeled off, and a portion of the storage film 17, the semiconductor layer 51, and a portion of the intermediate film 57 are removed from the bottom side of the storage hole M. Furthermore, the semiconductor layer 51 is completely removed. The core insulating film 16 is not removed because it is covered by the channel semiconductor layer 15, which serves as a protective layer.

[0085] Next, as Figure 5EAs shown, a semiconductor layer 58 is formed on the storage film 17 and the intermediate film 57, and a conductive layer 59 is formed on the channel semiconductor layer 15 and the semiconductor layer 58. The conductive layer 59 functions as the source-side conductive layer 3. The semiconductor layer 58 contains, for example, amorphous silicon. The conductive layer 59 contains, for example, W (tungsten).

[0086] like Figure 5E As shown, the channel semiconductor layer 15 is connected to the source-side conductive layer 3 at the bottom of the storage hole M (the end face of the columnar portion CL).

[0087] A grain boundary B exists in the channel semiconductor layer 15 at the end of the columnar portion CL.

[0088] As in the second embodiment, the channel semiconductor layer 15 can also be connected to the source-side conductive layer 3 at the end face of the pillar portion CL. The semiconductor memory device of the second embodiment can achieve the same effect as the first embodiment. In addition, the semiconductor memory device of the second embodiment can also incorporate variations of the first embodiment.

[0089] Furthermore, in the first embodiment, the grain boundary B may be formed instead of the opening 15a.

[0090] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included in the scope and / or spirit of the invention, as well as in the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: A laminate formed by stacking multiple first conductive layers in a first direction, separated by insulating layers; and A columnar portion that penetrates the laminate and extends in the first direction. The columnar portion has: A semiconductor layer, which penetrates the stack and extends in the first direction; and The storage film includes a first insulating film, a charge storage layer, and a second insulating film disposed between the laminate and the semiconductor layer. The semiconductor memory device further includes a second conductive layer electrically connected to the semiconductor layer at the end of the columnar portion. At least one grain within the semiconductor layer has a shape that is in contact with the storage film. The semiconductor layer at the end of the columnar portion has a first opening, or the semiconductor layer at the end of the columnar portion has a grain boundary.

2. The semiconductor memory device according to claim 1, The semiconductor layer in which the grain boundary is located is thicker than the other portions of the semiconductor layer.

3. The semiconductor memory device according to claim 1, The grain size of the crystals in the semiconductor layer is 65 nm or larger, or the semiconductor layer is a single crystal.

4. The semiconductor memory device according to claim 1, The columnar portion also has a third insulating film that penetrates the laminate and extends in the first direction. The semiconductor layer is disposed in a manner that surrounds the third insulating film. The third insulating film is provided in such a manner that it penetrates the first opening of the semiconductor layer.

5. The semiconductor memory device according to claim 1, The semiconductor layer is in contact with the second conductive layer on the side of the end of the columnar portion.

6. The semiconductor memory device according to claim 1, The semiconductor layer is in contact with the second conductive layer at the end face of the columnar portion.

7. A method for manufacturing a semiconductor memory device, comprising: A laminate is formed by stacking multiple first conductive layers in the first direction with an insulating layer between them; A hole is formed that penetrates the first region and extends in the first direction; A storage film comprising a first insulating film, a charge storage layer, and a second insulating film is formed within the hole. A semiconductor layer is formed on the storage film; A first film containing metal atoms is formed on the laminate in the second region; The semiconductor layer is annealed to crystallize it. as well as Remove a portion of the semiconductor layer at the bottom of the hole.

8. The method for manufacturing a semiconductor memory device according to claim 7, Removing a portion of the semiconductor layer at the bottom of the hole includes: A second film is formed on the semiconductor layer; The second membrane at the bottom of the hole forms a second opening; as well as A portion of the semiconductor layer is removed through the second opening.

Images