memory elements
Patent Information
- Application Number
- CN202510275400.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-02-20
- Filing Date
- 2025-03-10
- Publication Date
- 2026-08-21
Smart Images
Figure CN122622249A_ABST
Abstract
Description
Technical Field
[0001] This invention and some embodiments relate to a memory element. Background Technology
[0002] Non-volatile memory (NDRAM) has the advantage of preserving stored data even after power loss, making it widely used in personal computers and other electronic devices. Currently, the most commonly used 3D memory types include NOR (Neuron OR) and NAND (Non-AND) memory. Another type of 3D memory is AND (AND) memory, which can be used in multi-dimensional memory arrays, offering high integration, high area utilization, and fast operation speeds. Therefore, the development of 3D memory devices has gradually become a current trend. Summary of the Invention
[0003] A memory element according to an embodiment of the present invention includes a substrate, a stacked structure, a plurality of first partition structures, and a plurality of second partition structures. The substrate has a memory array region and a stepped region. The stacked structure has a first gate stacked structure and a plurality of second gate stacked structures, the first gate stacked structure being located in the memory array region, and the plurality of second gate stacked structures being located in the stepped region, wherein the first gate stacked structure and the second gate stacked structure include a plurality of gate layers and a plurality of first insulating layers alternately stacked on top of each other. The first partition structures and the second partition structures are staggered along a first direction and extend in a second direction. The first partition structure includes a first sub-partition structure and a second sub-partition structure, the first sub-partition structure extending on the stepped region, the second sub-partition structure extending on the memory array region, and a spacer between the first sub-partition structure and the second sub-partition structure, and the plurality of second partition structures extending from the memory array region to the stepped region. Attached Figure Description
[0004] Figure 1A A circuit diagram of a 3D AND flash memory array according to some embodiments is shown.
[0005] Figure 1B Show Figure 1A A partial 3D view of the storage array in the middle section.
[0006] Figure 1C and Figure 1D Show Figure 1B A cross-sectional view of the tangent line I-I'.
[0007] Figure 1E Show Figure 1B , Figure 1C and Figure 1D Top view of the tangent line II-II'.
[0008] Figure 2A top view of a memory element according to an embodiment of the present invention is shown.
[0009] Figure 3A Illustrations of some embodiments Figure 2 A top view of the block.
[0010] Figure 3B yes Figure 3A A 3D view of a local area.
[0011] Figure 3C These are some embodiments Figure 3A A cross-sectional view of the tangent A-A'.
[0012] Figure 3D In other embodiments Figure 3A A cross-sectional view of the tangent A-A'.
[0013] Figure 3E yes Figure 3A A 3D view of a local area.
[0014] Figure 4A Other embodiments are illustrated. Figure 2 A top view of the block.
[0015] Figure 4B yes Figure 4A A 3D view of a local area.
[0016] Figure 4C These are some embodiments Figure 4A A cross-sectional view of the tangent line B-B'.
[0017] Figure 4D yes Figure 4A A 3D view of a local area.
[0018] Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A A top view illustrating a method for manufacturing a memory element according to some embodiments of the present invention.
[0019] Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B for Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11AA three-dimensional schematic diagram of a local area.
[0020] Figures 12A to 12B A cross-sectional schematic diagram illustrating the interface between the insulating layer, the conductor layer, and the intermediate layer during the manufacture of a memory element according to some embodiments of the present invention.
[0021] Figures 13A to 13C Cross-sectional schematic diagrams illustrating various perforations in some embodiments of the present invention are shown.
[0022] Figures 14A to 14C Cross-sectional schematic diagrams illustrating various partition structures of some embodiments of the present invention are shown.
[0023] Explanation of reference numerals in the attached figures:
[0024] 10. A (i) A (i+1) Storage array
[0025] 12: Charge storage layer
[0026] 14: Tunneling Layer
[0027] 16: Channel Column
[0028] 20: Storage unit
[0029] 24: Insulating filler layer
[0030] 28: Insulating Post
[0031] 32a: Source post / Conductor post
[0032] 32b: Drain post / Conductor post
[0033] 36: Barrier layer
[0034] 38: Gate layer / word line
[0035] 40: Charge storage structure
[0036] 48: Substrate
[0037] 49: Internal Wiring Structure
[0038] 50: Dielectric substrate
[0039] 52: Intermediate layer
[0040] 53, 64, TM: Conductor layer
[0041] 54, 58, 59: Insulation layer
[0042] 55, 66: Dielectric layer
[0043] 56: Insulating post
[0044] 57: Conductor dielectric window
[0045] 60: Arrow
[0046] 61: Spacer
[0047] 62: Lining
[0048] 62': Insulating material
[0049] 133, 134, 135, 136: Dividing channels
[0050] AG: Air gap
[0051] AR: Memory Array Area
[0052] A-A', B-B', I-I', II-II': tangent
[0053] BLOCK, BLOCK (i) BLOCK (i+1) Block
[0054] BLn, BLn+1: Bit lines
[0055] C1, C2: District
[0056] COA: Contact Window
[0057] ER: Edge region
[0058] GSK, GSK1, GSK2: Gate stacking structure
[0059] DP (i) n DP (i) n+1 DP (i+1) n DP (i+1) n+1 Drain post
[0060] ISK1, ISK2: Insulating stacked structure
[0061] M1, M2, N1, N2: Local regions
[0062] MC-1: Memory chip
[0063] OP1, OP2: Openings
[0064] SC: Stepped structure
[0065] SK: Stacked structure
[0066] SLT1, SLT2, SLT3: Separated Structures
[0067] SSLT1, SSLT2: Sub-delimiter structure
[0068] SP1, SP2: Spacing section
[0069] SP (i) n SP (i) n+1 SP (i+1) n SP (i+1) n+1 Source pole
[0070] SR: Staircase Area
[0071] T: Block
[0072] TV1, TV2, TV3: Piercing
[0073] WL (i) m WL (i) m+1 WL (i+1) m WL (i+1) m+1 : Word line
[0074] VC: Opening
[0075] X, Y, Z: Direction Detailed Implementation
[0076] Figure 1A A circuit diagram of a 3D AND flash memory array according to some embodiments is shown. Figure 1B Show Figure 1A A partial 3D view of the storage array in the middle section. Figure 1C and Figure 1D Show Figure 1B A cross-sectional view of the tangent line I-I'. Figure 1E Show Figure 1B , Figure 1C and Figure 1D Top view of the tangent line II-II'.
[0077] Figure 1A For two blocks of a vertical AND storage array 10 configured in columns and rows. (i) With BLOCK (i+1) A schematic diagram. Block (i) Includes storage array A (i) Storage array A (i) A column (e.g., column m+1) has a common word line (e.g., WL). (i) m+1 A set of 20 AND storage cells. Storage array A (i)Each column (e.g., the (m+1)th column) of the AND storage cell 20 corresponds to a common word line (e.g., WL). (i) m+1 ), and coupled to different source posts (e.g., SP). (i) n With SP (i) n+1 ) and drain post (e.g., DP) (i) n With DP (i) n+1 This causes the AND memory cell 20 to move along a common word line (e.g., WL). (i) m+1 Logically configured into a column.
[0078] Storage Array A (i) A row (e.g., the nth row) has a common source pole (e.g., SP). (i) n ) and common drain post (e.g., DP) (i) n A set of 20 AND storage cells. Storage array A (i) Each row (e.g., the nth row) of AND storage cells 20 corresponds to a different word line (e.g., WL). (i) m+1 With WL (i) m ), and coupled to a common source post (e.g., SP). (i) n ) and a common drain post (e.g., DP) (i) n Therefore, storage array A (i) AND memory cell 20 along a common source post (e.g., SP) (i) n ) and common drain post (e.g., DP) (i) n They are logically arranged in a row. In a solid layout, rows or columns may be twisted, configured in a honeycomb pattern or other ways, depending on the manufacturing method applied, for high density or other reasons.
[0079] exist Figure 1A In the block (i) In the middle, storage array A (i) The AND memory cells 20 in the nth row share a common source pillar (e.g., SP). (i) n ) and a common drain post (e.g., DP) (i) n The AND storage cells 20 in row n+1 share a common source pillar (e.g., SP). (i) n+1) and a common drain post (e.g., DP) (i) n+1 ).
[0080] Common source pole (e.g., SP) (i) n Coupled to a common source line (e.g., SL) n ); common drain post (e.g., DP) (i) n Coupled to a common bit line (e.g., BL) n Common source pole (e.g., SP) (i) n+1 Coupled to a common source line (e.g., SL) n+1 ); common drain post (e.g., DP) (i) n+1 Coupled to a common bit line (e.g., BL) n+1 ).
[0081] Similarly, block (i+1) Including storage array A (i+1) It is related to the block BLOCK (i) Storage array A in (i) Similar. Storage array A (i+1) A column (e.g., column m+1) has a common word line (e.g., WL). (i+1) m+1 A set of 20 AND storage cells. Storage array A (i+1) Each column (e.g., the (m+1)th column) of the AND storage cell 20 corresponds to a common word line (e.g., WL). (i+1) m+1 ), and coupled to different source posts (e.g., SP). (i+1) n With SP (i+1) n+1 ) and drain post (e.g., DP) (i+1) n With DP (i +1) n+1 ). Storage array A (i+1) A row (e.g., the nth row) has a common source pole (e.g., SP). (i+1) n ) and common drain post (e.g., DP) (i+1) n A set of 20 AND storage cells. Storage array A (i+1) Each row (e.g., the nth row) of AND storage cells 20 corresponds to a different word line (e.g., WL). (i+1) m+1 With WL (i+1) m), and coupled to a common source post (e.g., SP). (i+1) n ) and a common drain post (e.g., DP) (i+1) n Therefore, storage array A (i+1) AND memory cell 20 along a common source post (e.g., SP) (i +1) n ) and common drain post (e.g., DP) (i+1) n Logically configured in one row.
[0082] Block (i+1) With Block (i) Shared source line (e.g., SL) n With SL n+1 ) and bit lines (e.g., BL) n BL n+1 Therefore, the source line SL n With bit line BL n Coupled to block BLOCK (i) AND storage array A (i) The nth row AND storage unit 20 in the block is coupled to the block BLOCK. (i+1) AND storage array A in (i+1) The nth row of the AND memory cell is 20. Similarly, the source line SL... n+1 With bit line BL n+1 Coupled to block BLOCK (i) AND storage array A (i) The (n+1)th row of the AND storage unit 20, coupled to the block BLOCK. (i+1) AND storage array A in (i+1) The (n+1)th row of the AND storage unit is 20.
[0083] Please refer to Figures 1B to 1D The memory array 10 may be disposed on the interconnect structure of a semiconductor die, such as above one or more active elements (e.g., transistors) formed on a semiconductor substrate. Therefore, the dielectric substrate 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed above the metal interconnect structure on a silicon substrate. The memory array 10 may include a gate stack structure GSK, a plurality of channel pillars 16, a plurality of first conductor pillars (also referred to as source pillars) 32a and a plurality of second conductor pillars (also referred to as drain pillars) 32b, and a plurality of charge storage structures 40.
[0084] Please refer to Figure 1BA gate stack structure (GSK) is formed on a dielectric substrate 50 with an array region (not shown) and a stepped region (not shown). The GSK includes multiple gate layers (also called word lines) 38 vertically stacked on the surface 50s of the dielectric substrate 50, and multiple insulating layers 54. In the Z direction, these gate layers 38 are electrically isolated from each other by insulating layers 54 disposed between them. The gate layers 38 extend in a direction parallel to the surface of the dielectric substrate 50. The gate layers 38 in the stepped region may have a stepped structure (not shown). Therefore, the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. Contact windows (not shown) for connecting the gate layers 38 may land at the ends of the gate layers 38 to connect each gate layer 38 to a respective wire.
[0085] Please refer to Figures 1B to 1D The memory array 10 also includes a plurality of channel pillars 16. The channel pillars 16 extend continuously through the gate stack structure GSK. In some embodiments, the channel pillars 16 may have a ring-shaped profile when viewed from a top angle. The material of the channel pillars 16 may be a semiconductor, such as undoped polysilicon.
[0086] Please refer to Figures 1B to 1D The memory array 10 also includes insulating pillars 28, a plurality of first conductor pillars 32a, and a plurality of second conductor pillars 32b. In this example, the first conductor pillars 32a serve as source pillars; the second conductor pillars 32b serve as drain pillars. The first conductor pillars 32a and 32b, as well as the insulating pillars 28, each extend in a direction perpendicular to the surface of the gate layer 38 (i.e., the XY plane) (i.e., the Z direction). The first conductor pillars 32a and 32b are separated by the insulating pillars 28. The first conductor pillars 32a and 32b are electrically connected to the channel pillars 16. The first conductor pillars 32a and 32b comprise doped polysilicon or metallic materials. The insulating pillars 28 are, for example, silicon nitride or silicon oxide.
[0087] Please refer to Figure 1C and Figure 1D A charge storage structure 40 is disposed between the channel pillar 16 and the multilayer gate layer 38. The charge storage structure 40 may include a tunneling layer (or bandgap engineered tunneling oxide layer) 14, a charge storage layer 12, and a barrier layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the barrier layer 36. In some embodiments, the tunneling layer 14 and the barrier layer 36 comprise silicon oxide. The charge storage layer 12 comprises silicon nitride, or other materials capable of capturing charges. In some embodiments, such as... Figure 1CAs shown, a portion of the charge storage structure 40 (tunneling layer 14 and charge storage layer 12) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the Z direction), while another portion of the charge storage structure 40 (barrier layer 36) surrounds the gate layer 38. In other embodiments, such as Figure 1D As shown, the charge storage structure 40 (tunneling layer 14, charge storage layer 12 and barrier layer 36) surrounds the gate layer 38.
[0088] Please refer to Figure 1E The charge storage structure 40, channel post 16, and source post 32a and drain post 32b are surrounded by gate layer 38, defining the storage cell 20. The storage cell 20 can be operated in 1-bit or 2-bit modes using different methods. For example, when a voltage is applied to the source post 32a and drain post 32b, electrons can be transported along the channel post 16 and stored throughout the charge storage structure 40 because the source post 32a and drain post 32b are connected to the channel post 16, thus enabling 1-bit operation of the storage cell 20. Furthermore, for operations utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source post 32a and drain post 32b. For source-side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection operations, electrons or holes can be locally trapped in a charge storage structure 40 of one of the two adjacent source posts 32a and drain posts 32b, thus enabling single-cell (SLC, 1-bit) or multi-cell (MLC, greater than or equal to 2 bits) operations on the storage cell 20.
[0089] During operation, a voltage is applied to the selected word line (gate layer) 38, for example, applying a voltage higher than the corresponding start voltage (V) of the corresponding memory cell 20. th When the selected word line 38 is selected, the channel region of the channel post 16 intersecting the selected word line 38 is turned on, allowing current to flow from the bit line BL. n Or BL n+1 (shown in) Figure 1B It enters the drain terminal 32b and flows through the conductive channel region to the source terminal 32a (e.g., in the direction indicated by arrow 60), and finally flows to the source line SL. n or SL n+1 (shown in) Figure 1B ).
[0090] Figure 2A top view of a memory element according to an embodiment of the present invention is shown. Figure 3A Illustrations of some embodiments Figure 2 A top view of block T. Figure 3B yes Figure 3A A 3D view of a local area M1. Figure 3C These are some embodiments Figure 3A A cross-sectional view of the tangent line A-A'. Figure 3D In other embodiments Figure 3A A cross-sectional view of the tangent A-A'. Figure 3E yes Figure 3A A 3D view of the local region N1.
[0091] Please refer to Figure 2 and Figure 3A The memory chip MC-1 is, for example, an AND memory element. The memory chip MC-1 may include regions C1 and C2. Region C1 may include multiple blocks T that are separate from each other. The blocks T may be arranged in an array with multiple rows and columns. Figure 2 It is a block array formed by 7 rows and 8 columns; however, the embodiments of the present invention are not limited thereto. Each block T in region C1 has multiple memory arrays. Region C2 includes peripheral circuitry, such as complementary metal-oxide-semiconductor (CMOS) devices disposed around the block array.
[0092] Please refer to Figure 3A and Figure 3B The memory chip MC-1 also includes a substrate 48, an interconnect structure 49, a dielectric substrate 50, a conductor layer 53, a stacked structure SK, multiple first separation structures SLT1, multiple second separation structures SLT2, and a separation structure SLT3. The substrate 48 may include a memory array region AR, a stepped region SR, and an edge region ER. The memory array region AR is surrounded by the stepped region SR, and the stepped region SR is surrounded by the edge region ER. The interconnect structure 49, the dielectric substrate 50, the conductor layer 53, and the stacked structure SK are on the substrate 48. The stacked structure SK has a gate stacked structure GSK1, a gate stacked structure GSK2, and an insulating stacked structure ISK1. The gate stacked structure GSK1 is located in the memory array region AR, and the gate stacked structures GSK2 and ISK1 are alternately arranged along the Y direction in the stepped region SR. The gate stacked structures GSK1 and GSK2 include multiple gate layers 38 and multiple insulating layers 54 stacked alternately. The insulating stacked structure ISK1 includes multiple insulating layers 58 and multiple insulating layers 54 stacked alternately. Insulating layer 58 is adjacent to gate layer 38, and insulating layer 54 extends from gate stack structure GSK2 to insulating stack structure ISK1. In the stepped region SR, gate stack structure GSK2 and insulating stack structure ISK1 have a stepped structure.
[0093] In this invention, the multiple gate layers 38 of the gate stack structures GSK1 and GSK2 are replaced by multiple intermediate layers 52. However, a portion of the intermediate layers 52 in this invention will not be replaced by the multiple gate layers 38, but will remain in the memory element and form an insulating stack structure ISK2. The insulating stack structure ISK2 includes multiple intermediate layers 52 and multiple insulating layers 54 stacked alternately. The insulating stack structure ISK2 may be located between the insulating stack structure ISK1 and the gate stack structure GSK2. Furthermore, a portion of the intermediate layers 52 in this invention will not be replaced by the multiple gate layers 38, but will be replaced by insulating layers 58 adjacent to the gate layers 38. In addition, a portion of the conductor layers 53 in this invention will be replaced by insulating layers 59. In this way, the conductor layers 53 remain below the gate stack structure GSK1 and between the gate stack structure GSK1 and the substrate 48, and between the gate stack structure GSK2 and the substrate 48. The insulating layer 59 is below the insulating stack structure ISK1 and between the insulating stack structure ISK1 and the substrate 48.
[0094] A third partition structure SLT3 surrounds the periphery of multiple first partition structures SLT1 and multiple second partition structures SLT2, with the multiple first partition structures SLT1 and multiple second partition structures SLT2 formed within the third partition structure SLT3. The top view of the third partition structure SLT3 can be annular. The first partition structures SLT1 and second partition structures SLT2 are elongated strips, and are staggered along the Y direction and extend in the X direction. In some embodiments, the Y direction is also referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction. The first partition structure SLT1 includes a first sub-partition structure SSLT1 and a second sub-partition structure SSLT2. The first sub-partition structure SSLT1 extends on the stepped region SR, and the second sub-partition structure SSLT2 extends on the memory array region AR. A gap (e.g., between the first sub-partition structures SSLT1 and the second sub-partition structure SSLT2) is present between them. Figure 3E The second partition structure SLT2 extends from the memory array region AR to the step region SR.
[0095] Reference Figure 3A , Figure 3B and Figure 3C The memory element includes multiple contact windows (COAs), multiple through-holes (TV1), multiple through-holes (TV2), and multiple through-holes (TV3). The multiple contact windows (COAs) are located in the stepped region SR, passing through the dielectric layer 55 and the gate stack structure GSK2, and are electrically connected to the gate layer 38 or barrier layer (not shown) of each step of the stepped region SR. The contact windows (COAs) include a conductive material.
[0096] Reference Figure 3A , Figure 3B and Figure 3C Multiple vias TV1 are located in the stepped region SR, passing through the dielectric layer 55 and the gate stack structure GSK2 and extending to the conductor layer 53. Each via TV1 includes an insulating pillar, electrically insulated from the gate layer 38 of the gate stack structure GSK2 and from the interconnect structure 49. Therefore, the via TV1 is also called an insulating via TV1.
[0097] Reference Figure 3A , Figure 3B and Figure 3C Multiple vias TV2 are located in the stepped region SR and the edge region ER, passing through the dielectric layer 55, the insulating stack structure ISK1, and the insulating layer 59, extending to the conductor layer 53 and the interconnect structure 49, landing on and electrically connecting to the top conductor layer TM of the interconnect structure 49. Therefore, the via TV2 is also called a conductor via TV2. The via TV2 includes an insulating pillar 56 and a conductor dielectric window 57. The insulating pillar 56 passes through the dielectric layer 55 and extends through the conductor layer 53. The conductor dielectric window 57 is located in the insulating pillar 56 and passes through the insulating pillar 56 and the dielectric substrate 50, landing on and electrically connecting to the top conductor layer TM of the interconnect structure 49. Figure 3A , Figure 3B and Figure 3C In the embodiment, all the through-hole TV2 are surrounded by the insulating stack structure ISK1 and the insulating layer 59, and the gate layer 38 of the gate stack structure GSK2 does not overlap with the through-hole TV2 in the top view.
[0098] Reference Figure 3A , Figure 3B and Figure 3C Multiple vias (TV3) are located in the memory array region AR, the stepped region SR, and the edge region ER. These vias (TV3) pass through the dielectric layer 55, the gate stack structure GSK2 (or the insulating stack structure ISK1), and extend to the conductor layer 53. Each via (TV3) includes insulating pillars and is electrically insulated from the gate layer 38 of the gate stack structure GSK2 and from the interconnect structure 49. Therefore, the vias (TV3) are also called insulating vias (TV3).
[0099] In some embodiments, the diameter of the perforated TV2 is larger than the diameter of the perforated TV1 and / or larger than the diameter of the contact window COA. The diameter of the perforated TV2 is substantially equal to the diameter of the perforated TV3.
[0100] Reference Figure 3CThe insulating pillar 56 and conductive dielectric window 57 of the through-hole TV2 have a structure that is wider at the top and narrower at the bottom. Generally, in the lower part of the through-hole TV2, especially when it is surrounded by the conductive layer 53 and the lower gate layer 38, the insulating pillar 56 of the through-hole TV2 may be too narrow, causing the conductive dielectric window 57 to not be completely covered by the insulating pillar 56 and to contact the conductive layer 53 and the gate layer 38. This may lead to leakage current between the through-hole TV2 and the conductive layer 53 and the gate layer 38. In this invention, to avoid the above situation, the gate layer 38 is replaced with an insulating layer 58, and the conductive layer 53 is replaced with an insulating layer 59, so that the through-hole TV2 is separated from the gate layer 38 of the stepped structure SC by the insulating layer 58, and the through-hole TV2 is separated from the conductive layer 53 by the insulating layer 59. This reduces the probability of leakage current between the through-hole TV2 and the conductive layer 53 and the gate layer 38.
[0101] Reference Figure 3D The conductor window 57 of the through-hole TV2 may not be completely covered by the insulating pillar 56, allowing the conductor window 57 of the through-hole TV2 to directly contact the insulating stack structure ISK1, the dielectric layer 55, and the insulating layer 59. In this case, the gate layer 38 is replaced by the insulating layer 58, and the conductor layer 53 is replaced by the insulating layer 59. Therefore, even if the conductor window 57 is not completely covered by the insulating pillar 56, the conductor window 57 will not contact the conductor layer 53 and the gate layer 38, thus preventing current leakage between the through-hole TV2 and the conductor layer 53 and the gate layer 38.
[0102] Reference Figure 3E The first sub-separation structure SSLT1 of the first separation structure SLT1 and the second sub-separation structure SSLT2 are not in direct contact, and the first sub-separation structure SSLT1 and the second sub-separation structure SSLT2 are separated by a spacer SP1. Figure 3A In some embodiments, the first sub-separation structure SSLT1 is surrounded by an insulating stack structure ISK1 and an insulating layer 59, and the second sub-separation structure SSLT2 is surrounded by a gate stack structure GSK1 and a conductor layer 53. Therefore, the spacer SP1 may include a portion of the gate stack structure GSK1, a portion of the conductor layer 53, a portion of the insulating stack structure ISK1, and a portion of the insulating layer 59, with the first sub-separation structure SSLT1 and the conductor layer 53 separated by the insulating layer 59. In some embodiments, the spacer SP1 has a contact surface between the gate stack structure GSK1 and the insulating stack structure ISK1, and a contact surface between the conductor layer 53 and the insulating layer 59. In some embodiments, the first sub-separation structure SSLT1 and the second sub-separation structure SSLT2 may be selected from a material selected from the group consisting of silicon oxide, polycrystalline silicon encapsulated in silicon oxide, and silicon oxide with air gaps, and the materials of the first sub-separation structure SSLT1 and the second sub-separation structure SSLT2 may be the same or different.
[0103] Figure 4A Other embodiments are illustrated. Figure 2 A top view of block T. Figure 4B yes Figure 4A A 3D view of the local area M2. Figure 4C These are some embodiments Figure 4A A cross-sectional view of the tangent line B-B'. Figure 4D yes Figure 4A A 3D view of the local region N2.
[0104] Figure 4A and Figure 4B The illustrated block T and Figure 3A The illustrated block T is similar. The difference is that... Figure 4A and Figure 4B In this invention, the intermediate layer 52 will not be replaced by multiple gate layers 38 in the end, but will remain in the memory element. The remaining portions of the intermediate layer 52 will all be replaced by multiple gate layers 38 in the end. That is, the gate layers 38 will not be replaced by the insulating layer 58. In this way, the conductor layer 53 remains below the gate stack structure GSK1 and a portion of the gate stack structure GSK2, and between the gate stack structure GSK1 and the substrate 48, and between a portion of the gate stack structure GSK2 and the substrate 48. The insulating layer 59 is located between another portion of the gate stack structure GSK2 and the substrate 48.
[0105] Reference Figure 4A , Figure 4B and Figure 4C The insulating pillar 56 and conductor window 57 of the perforated TV2 have a structure that is wider at the top and narrower at the bottom. Generally, in the lower part of the perforated TV2, especially when surrounded by the conductor layer 53, the conductor window 57 may not be completely covered by the insulating pillar 56 and may contact the conductor layer 53. This may lead to leakage current between the perforated TV2 and the conductor layer 53. In this invention, to avoid the above situation, the conductor layer 53 is replaced by an insulating layer 59, so that the perforated TV2 and the conductor layer 53 are separated by the insulating layer 59. This reduces the probability of leakage current between the perforated TV2 and the conductor layer 53.
[0106] Reference Figure 4D The first sub-separation structure SSLT1 of the first separation structure SLT1 and the second sub-separation structure SSLT2 are not in direct contact, and the first sub-separation structure SSLT1 and the second sub-separation structure SSLT2 are separated by a spacer SP2. Figure 4AIn some embodiments, the first sub-separator structure SSLT1 is surrounded by the gate stack structure GSK2 and the insulating layer 59, and the second sub-separator structure SSLT2 is surrounded by the gate stack structure GSK1 and the conductor layer 53. Therefore, the spacer SP2 may include a portion of the gate stack structure GSK1, a portion of the gate stack structure GSK2, a portion of the conductor layer 53, and a portion of the insulating layer 59, with the first sub-separator structure SSLT1 and the conductor layer 53 separated by the insulating layer 59. In some embodiments, the spacer SP2 has a contact surface between the conductor layer 53 and the insulating layer 59.
[0107] Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A A top view illustrating a method for manufacturing a memory element according to some embodiments of the present invention. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B With 11B Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A A three-dimensional schematic diagram of a local region M1 of the 11A.
[0108] Please refer to Figure 5A and Figure 5B A substrate 48 is provided. The substrate 48 includes a memory array region AR, a stepped region SR, and an edge region ER. The substrate 48 may include a semiconductor substrate, such as a silicon substrate. Active components (e.g., PMOS, NMOS, CMOS, JFET, BJT, or diode devices) or passive components may be included on the substrate 48. An interconnect structure 49 is formed on the memory array region AR and the stepped region SR of the substrate 48. The interconnect structure 49 may include inner dielectric layers, contact windows, wires, interlayer dielectric layers, and interlayer windows. The material of the inner dielectric layers and the interlayer dielectric layers is, for example, silicon oxide. Next, a dielectric substrate 50 is formed on the interconnect structure 49. The material of the dielectric substrate 50 is, for example, silicon oxide.
[0109] Next, please continue to refer to Figure 5A and Figure 5B A blanket-like conductor layer 53 is formed on the dielectric substrate 50 of the memory array region AR and the step region SR. The conductor layer 53 also extends to the edge region ER. The conductor layer 53 is, for example, a grounded P-type doped polysilicon layer. The conductor layer 53 can also be called a dummy gate, which can be used to shut off leakage paths.
[0110] Please continue to refer to Figure 5A and Figure 5B A stacked structure SK is formed on the conductor layer 53, and the stacked structure SK is patterned to form a stepped structure SC of the stacked structure SK in the stepped region SR. In this embodiment, the stacked structure SK is composed of an insulating layer 54 and an intermediate layer 52 sequentially and alternately stacked on the conductor layer 53. Furthermore, in this embodiment, the topmost layer of the stacked structure SK is the insulating layer 54. The material of the insulating layer 54 is, for example, silicon oxide. The material of the intermediate layer 52 is, for example, silicon nitride. The intermediate layer 52 can be partially removed in subsequent processes. In this embodiment, the number of insulating layers 54 and intermediate layers 52 can be formed according to actual needs.
[0111] A dielectric layer 55 is formed above the substrate 48 (e.g., Figure 3C As shown), a dielectric layer 55 is formed to cover the stacked structure SK. The material of the dielectric layer 55 is, for example, silicon oxide. The method for forming the dielectric layer 55 is, for example, forming a dielectric material to fill and cover the stacked structure SK. A planarization process is then performed, for example, by chemical mechanical polishing. For clarity, the dielectric layer 55 is not shown. Figure 5A and Figure 5B middle.
[0112] Reference Figure 6A and Figure 6B Subsequently, multiple vias VC are formed in the stacked structure SK. The vias VC expose the conductor layer 53. The etching process can be a dry etching process, a wet etching process, or a combination thereof. A dry etching process is, for example, a plasma etching process. In this embodiment, the vias VC have a circular outline when viewed from above, but the invention is not limited thereto. In other embodiments, the vias VC may have other shapes, such as polygons (not shown). Next, in some embodiments, a tunneling layer 14 and channel pillars 16 are formed in the vias VC, such as... Figure 1D as well as Figure 1E As shown. The tunneling layer 14 can also be formed subsequently. For simplicity, Figure 6A The passage pillar 16 and the tunnel layer 14 are not shown in the diagram.
[0113] Reference Figure 1D as well as Figure 1EThe tunneling layer 14 and the channel pillar 16 may extend through the stacked structure SK but not through the conductor layer 53, but are not limited thereto. The top view of the channel pillar 16 is, for example, annular, and may be continuous in its extension direction (e.g., in the direction perpendicular to the surface of the substrate 48). That is, the channel pillar 16 is integral in its extension direction and is not divided into multiple unconnected portions. In some embodiments, the channel pillar 16 may have a circular outline when viewed from a top angle, but the invention is not limited thereto. In other embodiments, the channel pillar 16 may also have other shapes (e.g., polygonal) when viewed from a top angle.
[0114] Reference Figure 1D as well as Figure 1E An insulating filler material is filled into the stacked structure SK and the opening VC. The insulating filler material is, for example, low-temperature silicon oxide. The insulating filler material filled into the opening VC forms an insulating filler layer 24, leaving a circular aperture in the center of the insulating filler layer 24. Then, an anisotropic etching process is performed to enlarge the circular aperture to form a hole. An insulating material is formed on the insulating filler layer 24 and in the hole. Then, an anisotropic etching process is performed to remove part of the insulating material to form an insulating pillar 28 in the hole. The material of the insulating pillar 28 is different from the material of the insulating filler layer 24. The material of the insulating pillar 28 is, for example, silicon nitride.
[0115] Reference Figure 1D as well as Figure 1E A patterning process, such as photolithography and etching, is performed to form holes (not shown) in the insulating fill layer 24. During etching, the conductor layer 53 can be used as an etch stop layer. Therefore, the formed holes extend from the stacked structure SK to expose the conductor layer 53. The outline of the hole pattern defined by the patterning process can be tangent to the outline of the insulating pillar 28. The outline of the hole pattern defined by the patterning process can also extend beyond the outline of the insulating pillar 28 (not shown).
[0116] Reference Figure 1D as well as Figure 1E Then, conductor pillars 32a and 32b are formed in the holes. Conductor pillars 32a and 32b can serve as source pillars and drain pillars, respectively, and are electrically connected to channel pillar 16. Conductor pillars 32a and 32b can be formed by forming conductor layers on the insulating filling layer 24 and in the holes, and then by etching back. Conductor pillars 32a and 32b are, for example, doped polysilicon.
[0117] Next, continue to refer to Figure 6A and Figure 6B Photolithography and etching processes are performed to form the first opening OP1. And refer to... Figure 7A and Figure 7BPhotolithography and etching processes are performed to form the second opening OP2. The size of the second opening OP2 can be larger than the size of the first opening OP1. Then, insulating material is filled into the first opening OP1 and the second opening OP2 to form insulating pillars 56 for the through holes TV1, TV2, and TV3, as shown below. Figure 13B As shown. It should be noted that at this stage, perforated TV1 is formed in the first opening OP1. Perforated TV2 and perforated TV3 are both formed in the second opening OP2, therefore perforated TV2 and perforated TV3 have substantially the same dimensions.
[0118] In some embodiments, the perforated TV1, TV2, and TV3 may also be insulating pillars 56, and the insulating pillars 56 are covered by spacers 61, such as polysilicon or silicon nitride. Figure 13A As shown. In some other embodiments, the perforated TV1, TV2, and TV3 can also be insulating posts 56, and the insulating posts 56 cover the air gap AG without any conductive material, such as... Figure 13C As shown.
[0119] Reference Figure 8A and Figure 8B Next, the stacked structure SK and the conductor layer 53 are patterned to form a first separation channel 133 in the stepped region SR. During the etching process, either the dielectric substrate 50 or the conductor layer 53 can be used as an etching stop layer, exposing the conductor layer 53 with the first separation channel 133. In some embodiments, the first separation channel 133 may further expose the dielectric substrate 50. The etching process can be a dry etching process, such as a plasma etching process. The first separation channel 133 can be formed between two adjacent rows of vias TV2.
[0120] Reference Figure 9A and Figure 9BThrough the first separating trench 133, a portion of the conductor layer 53 is replaced with the insulating layer 59, and a portion of the intermediate layer 52 is replaced with the insulating layer 58. In this way, insulating layers 58 and 54 are alternately stacked to form an insulating stack structure ISK1, with insulating layer 59 below the insulating stack structure ISK1. The insulating stack structure ISK1 and insulating layer 59 are formed in the stepped region SR. First, an etching process, such as a wet etching process, is performed to remove portions of the conductor layer 53 and the intermediate layer 52 to form multiple horizontal openings (not shown). When the conductor layer 53 and the intermediate layer 52 are removed from the separating trench 133 using a wet etching process, its etching characteristics result in the removed conductor layer 53 and the intermediate layer 52 having inwardly recessed sidewalls. Next, insulating layers 58 and 59 are deposited in the horizontal openings. Insulating layer 58 is, for example, silicon oxide. Insulating layer 59 is, for example, silicon oxide. In this way, insulating layers 58 and 54 are stacked alternately to form an insulating stack structure ISK1. After insulating layers 58 and 59 are filled, the interfaces between the intermediate layer 52, conductor layer 53, insulating layers 58, 59, and 54 can be as follows: Figure 12A As shown. When insulating layers 58 and 59 are formed in a horizontal opening, discontinuous pores may naturally form between insulating layers 58, 59, and 54. These pores may be formed because the filling material cannot completely adhere to the existing material, and the pores between insulating layers 58 and 54, and between insulating layers 59 and 54, may be arranged along the X direction. Furthermore, since the etched conductor layer 53 and intermediate layer 52 have inwardly recessed sidewalls, the filled insulating layer 59 has a sidewall recessed towards the conductor layer 53, and the filled insulating layer 58 has a sidewall recessed towards the intermediate layer 52. This embodiment corresponds to... Figures 3A to 3E Examples of implementations.
[0121] In some embodiments, the conductor layer 53 may be replaced with the insulating layer 59 simply by separating the channel 133, while the intermediate layer 52 is not replaced in this step. After the insulating layer 59 is filled, the interface between the conductor layer 53, the insulating layer 59, and the insulating layer 54 can be as follows: Figure 12B As shown. A discontinuous gap may naturally form between insulating layer 59 and insulating layer 54. Furthermore, the filled insulating layer 59 has sidewalls recessed towards the conductor layer 53 between it and the conductor layer 53. This embodiment corresponds to... Figures 4A to 4D Examples of implementations.
[0122] Subsequently, a first sub-separation structure SSLT1 of the first separation structure SLT1 is formed in the separation channel 133. The method for forming the first sub-separation structure SSLT1 of the first separation structure SLT1 is as follows. An insulating liner and a conductor material are filled on the stacked structure SK and in the separation channel 133. The insulating liner is, for example, silicon oxide. The conductor material is, for example, polysilicon. Then, excess insulating liner material and conductor material on the stacked structure SK and the edge region ER are removed by an etch-back process or a planarization process to form a liner 62 and a conductor layer 64. Then, a dielectric material is formed on the substrate 48. After that, an etch-back process or a planarization process can be performed to planarize the dielectric material to form a dielectric layer 66. The liner 62, the conductor layer 64, and part of the dielectric layer 66 form the first separation structure SLT1, as follows. Figure 14A As shown.
[0123] In some embodiments, the first sub-segment SSLT1 of the first partition structure SLT1 may also be entirely filled with insulating material 62', without any conductive material, such as... Figure 14B As shown. In some other embodiments, the first sub-segment structure SSLT1 of the first separation structure SLT1 can also be a liner 62, and the liner 62 covers the air gap AG without any conductive material, such as... Figure 14C As shown.
[0124] Please refer to Figure 10A and Figure 10B The stacked structure SK and conductor layer 53 are patterned to form the second partition channel 134, partition channel 135, and partition channel 136. The formation of partition channels 134, 135, and 136 is similar to that of partition channel 133. The difference is that partition channel 134 is formed in the memory array region AR and extends in the X direction to the step region SR and the edge region ER. Furthermore, partition channel 134 is aligned along the Y direction with the first sub-partition structure SSLT1 of the first partition structure SLT1. Partition channel 135 is located between partition channel 134 and the first sub-partition structure SSLT1 of the first partition structure SLT1. Partition channel 136 is formed around partition channels 134 and 135 and the first sub-partition structure SSLT1 of the first partition structure SLT1. The sidewalls of partition channels 134, 135 and 136 expose multiple layers of intermediate layer 52 and multiple layers of insulating layer 54, but the sidewalls of partition channels 134, 135 and 136 do not expose the first sub-partition structure SSLT1 of the first partition structure SLT1.
[0125] Next, a replacement process is performed on the multilayer intermediate layer 52. First, an etching process, such as a wet etching process, is performed to remove portions of the multilayer intermediate layer 52 from the partition channels 134, 135, and 136 to form multiple horizontal openings (not shown). A multilayer charge storage layer 12, a multilayer barrier layer 36, and a multilayer gate layer 38 are formed within these horizontal openings. For clarity, the multilayer charge storage layer 12, the multilayer barrier layer 36, and the multilayer gate layer 38 are not shown. Figure 10A and Figure 10B The structure of the multilayer charge storage layer 12, the multilayer barrier layer 36, and the multilayer gate layer 38 is as follows: Figure 1C and Figure 1D As shown. The charge storage layer 12 is, for example, silicon nitride. The barrier layer 36 is, for example, a material with a high dielectric constant greater than or equal to 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or combinations thereof. The gate layer 38 is, for example, tungsten. In some embodiments, a barrier layer (not shown) is also formed before forming the multilayer gate layer 38. The barrier layer is, for example, made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.
[0126] The charge storage layer 12, barrier layer 36, barrier layer, and gate layer 38 are formed, for example, by sequentially forming a storage material, a barrier material, a potential barrier material, and a conductor material in the partition channels 134, 135, and 136 and the horizontal opening, and then performing an etch-back process to remove the storage material, barrier material, potential barrier material, and conductor material from the partition channels 134, 135, and 136. The tunneling layer 14, charge storage layer 12, and barrier layer 36 are collectively referred to as the charge storage structure 40 (e.g., Figure 1C (As shown). Thus, gate stack structures GSK1 and GSK2 are formed. Gate stack structure GSK1 is disposed on the memory array region AR of substrate 48, and gate stack structure GSK2 is disposed on the stepped region SR of substrate 48. Gate stack structures GSK1 and GSK2 include multiple gate layers 38 and multiple insulating layers 54 that are stacked on top of each other.
[0127] Subsequently, a second sub-segment structure SLT2 of the first separation structure SLT1 is formed in the separation channel 134, the second separation structure SLT2 is formed in the separation channel 135, and the third separation structure SLT3 is formed in the separation channel 136, as follows. Figures 10A to 10BAs shown. The formation methods of the second sub-separation structure SSLT2, the second sub-separation structure SLT2, and the third sub-separation structure SLT3 of the first separation structure SLT1 are similar to those of the first separation structure SLT1. The resulting first separation structure SLT1 has a gap between its first sub-separation structure SSLT1 and its second sub-separation structure SSLT2 (e.g., ...). Figure 3E or Figure 4D (As shown).
[0128] Reference Figure 11A and Figure 11B Conductor dielectric windows 57 are formed in the insulating pillars 56 of some perforated TV2, and contact windows COA are formed. For example... Figure 3C or Figure 4C As shown, the conductor window 57 is located in the insulating pillar 56 of the through-hole TV2 and extends through the insulating pillar 56 and the dielectric substrate 50, landing on and electrically connected to the top conductor layer TM of the interconnect structure 49. The contact window COA lands on the gate layer 38. The conductor window 57 is formed, for example, by photolithography and etching processes to form a third opening (not shown) in the insulating pillar 56. The third opening extends through the insulating pillar 56 of the through-hole TV2 and the dielectric substrate 50, exposing the top conductor layer TM of the interconnect structure 49. Next, a conductor material is formed on the substrate 48 and filled into the third opening. The conductor material is, for example, tungsten or polysilicon. Afterward, a planarization process, such as chemical mechanical polishing, is performed to remove the conductor material outside the via. The contact window COA can be formed using a similar method to the conductor window 57 or any known method. It should be noted that the conductor dielectric window 57 will only be formed in the insulating post 56 of the perforated TV2, and not in the insulating post 56 of the perforated TV3. Therefore, the perforated TV3 remains an insulating perforation.
[0129] This invention can be used not only in 3D AND flash memory, but also in 3D NOR flash memory and 3D NAND flash memory.
[0130] In summary, in some embodiments of the present invention, to avoid leakage current between the conductive via, the conductor layer, and the gate layer, a first separation structure can be formed for replacing the gate layer and the conductor layer with an insulating layer. The via and the stepped gate layer and conductor layer are separated by insulating layers. This reduces the probability of leakage current between the via and the conductor layer and gate layer.
Claims
1. A memory element comprising: The substrate includes a memory array region and a stepped region; A stacked structure having a first gate stacked structure and a plurality of second gate stacked structures, wherein the first gate stacked structure is located in the memory array region, and the plurality of second gate stacked structures are located in the stepped region, wherein the first gate stacked structure and the plurality of second gate stacked structures include a plurality of gate layers and a plurality of first insulating layers that are stacked alternately on each other; The first and second partition structures are arranged alternately along the first direction and extend in the second direction; wherein The plurality of first partition structures include a first sub-partition structure and a second sub-partition structure. The first sub-partition structure extends on the stepped region, and the second sub-partition structure extends on the memory array region. A spacer is provided between the first sub-partition structure and the second sub-partition structure. The plurality of second partition structures extend from the memory array region to the stepped region.
2. The memory element of claim 1, wherein the stacked structure further comprises a plurality of insulating stacked structures, the plurality of second gate stacked structures and the plurality of insulating stacked structures being arranged alternately along the first direction in the stepped region, and the spacer having a contact surface between the first gate stacked structure and one of the plurality of insulating stacked structures.
3. The memory element of claim 2, wherein the plurality of insulating stack structures comprise a plurality of second insulating layers and a plurality of first insulating layers stacked alternately on each other, the plurality of second insulating layers being adjacent to the plurality of gate layers, the plurality of first insulating layers extending from the plurality of second gate stack structures to the plurality of insulating stacks, and having a plurality of apertures between the plurality of second insulating layers and the plurality of first insulating layers, the plurality of apertures being arranged along the second direction.
4. The memory element according to claim 2, further comprising: A conductor layer is located between the first gate stack structure and the substrate; and A third insulating layer is provided between the insulating stack structure and the substrate, wherein the spacer portion further has a contact surface between the conductor layer and the third insulating layer.
5. The memory element according to claim 2, further comprising: The interconnect structure is located on the stepped area; and Multiple perforations are arranged on the stepped area and electrically connected to the interconnect structure, and the multiple perforations are surrounded by one of the multiple insulating stack structures.
6. The memory element of claim 5, wherein any one of the plurality of through-holes comprises an insulating post and a conductive dielectric window, and the conductive dielectric window extends through the insulating post.
7. The memory element of claim 5, wherein any one of the plurality of vias comprises an insulating pillar and a conductive dielectric window, and the conductive dielectric window contacts one of the plurality of insulating stack structures.
8. The memory element according to claim 5, further comprising: Multiple contact windows are arranged on the stepped area and surrounded by one of the multiple second gate stack structures.
9. The memory element according to claim 1, further comprising: A conductor layer is located between the first gate stack structure and the substrate; and A third insulating layer is provided between the second gate stack structure and the substrate, wherein the spacer portion further has a contact surface between the conductor layer and the third insulating layer.
10. The memory element of claim 9, further comprising: The interconnect structure is located on the stepped area; and Multiple perforations are arranged on the stepped area and electrically connected to the internal interconnect structure, and the multiple perforations are surrounded by the third insulating layer.