Memory device

Abstract

A memory device that increases the withstand voltage of a transistor. A memory device of one embodiment includes a first region, a third region, and a second region that are arranged in this order apart from each other in a first direction in a substrate and each include impurities of a first conductivity type; a fourth region that is provided in the third region and includes impurities of a second conductivity type different from the first conductivity type; a first conductor layer that is provided over the first region and has a first opening portion; a second conductor layer that is provided over the second region and has a second opening portion; a first contact connected to the first region through the first opening portion; a second contact connected to the second region through the second opening portion; a first memory cell connected to the first contact; and a second memory cell connected to the second contact.

Description

Technical Field

[0001] The implementation involves storage devices. Background Technology

[0002] NAND flash memory is a known type of memory that can store data in a non-volatile manner. NAND flash memory employs a three-dimensional memory structure for high integration and large capacity. Summary of the Invention

[0003] This increases the voltage withstand capability of the transistor.

[0004] The storage device according to the embodiment includes: a first region, a third region, and a second region disposed within a substrate and arranged separately from each other in a first direction, each containing impurities of a first conductivity type; a fourth region disposed within the third region and containing impurities of a second conductivity type different from the first conductivity type; a first conductor layer disposed above the first region and having a first opening; a second conductor layer disposed above the second region and having a second opening; a first contact member connected to the first region and passing through the first opening; a second contact member connected to the second region and passing through the second opening; a first storage cell connected to the first contact member; and a second storage cell connected to the second contact member. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the configuration of a storage system containing storage devices according to an embodiment.

[0006] Figure 2 This is a circuit diagram illustrating an example of the circuit structure of a memory cell array provided in a memory device according to an embodiment.

[0007] Figure 3 This is a top view showing an example of the planar layout of the memory cell array provided in the memory device of the embodiment.

[0008] Figure 4 This refers to the planar layout of the memory cell array provided by the memory device in the embodiment. Figure 3 A top view of an example of region IV.

[0009] Figure 5 This is an example of a cross-sectional structure along which the memory cell array of the memory device described in the embodiment is shown. Figure 4 A cross-sectional view of the VV line.

[0010] Figure 6 This is an example of the cross-sectional structure of the memory pillars provided by the memory cell array in the embodiment. Figure 5A sectional view along line VI-VI.

[0011] Figure 7 This is a circuit diagram illustrating an example of the circuit structure of a line decoder module included in a storage device according to an embodiment.

[0012] Figure 8 This is a top view showing an example of the planar layout of the line decoder module included in the storage device of the embodiment.

[0013] Figure 9 This represents the planar layout of the line decoder module included in the storage device of the embodiment. Figure 8 A top view of an example of region IX.

[0014] Figure 10 This is an example of the cross-sectional structure of a line decoder module included in a storage device according to an embodiment. Figure 9 A cross-sectional view along the XX line.

[0015] Figure 11 This is a perspective view showing the outline of the bonding structure of the storage device according to the embodiment.

[0016] Figure 12 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the embodiment.

[0017] Figure 13 This is a diagram illustrating an example of the potential distribution generated by the transistors in the comparative example's memory device.

[0018] Figure 14 This is a diagram illustrating an example of the potential distribution generated by a transistor in a storage device included in an embodiment.

[0019] Figure 15 This diagram illustrates an example of the characteristics of a transistor included in a storage device according to an embodiment.

[0020] Figure 16 This is a top view showing an example of the planar layout of the line decoder module provided by the storage device in the first modified example.

[0021] Figure 17 This is a top view showing an example of the planar layout of the line decoder module provided by the storage device in the second variation.

[0022] Explanation of reference numerals in the attached figures

[0023] 1…Storage system; 2…Storage controller; 3…Storage device; 10…Storage cell array; 11…Command register; 12…Address register; 13…Sequencer; 14…Driver module; 15…Line decoder module; 16…Sense amplifier module; 21…Semiconductor layer; 22, 23, 24…Wiring layers; 25, 26, 27, 51, 53, 54, 55, 56, 57, 58…Conductor layers; 30…Protective layer; 31, 32, 33, 34, 35, 52, 59…Insulator layer; 41…Core film; 42…Semiconductor film; 43…Layered film; 44…Channel insulating film; 45…Charge storage film; 46…Block insulating film; 50…Substrate; 100…Storage chip; 200…Circuit chip. Detailed Implementation

[0024] The embodiments will now be described with reference to the accompanying drawings. The dimensions and scale of the drawings may not be the same as those in reality.

[0025] Furthermore, in the following description, constituent elements with substantially the same function and structure are marked with the same symbol. When elements with the same structure are specifically distinguished from each other, sometimes different words or numbers are appended to the end of the same symbol.

[0026] 1. Composition

[0027] 1.1 Storage System

[0028] Figure 1 This is a block diagram illustrating an example of the configuration of a storage system including the storage device described in the embodiment. Storage system 1 is a storage device configured to connect to an external host (not shown). Storage system 1 is, for example, an SD card. TM Storage systems include memory cards such as memory cards, UFS (universal flash storage), and SSDs (solid state drives). Storage system 1 includes a storage controller 2 and storage devices 3.

[0029] The storage controller 2 is, for example, an integrated circuit such as a system-on-a-chip (SoC). The storage controller 2 controls the storage device 3 based on requests from the host. Specifically, for example, the storage controller 2 writes data requested to be written from the host to the storage device 3. Additionally, the storage controller 2 reads data requested to be read from the host from the storage device 3 and sends it to the host.

[0030] Storage device 3 is non-volatile memory. Storage device 3 is, for example, NAND flash memory. Storage device 3 stores data in a non-volatile manner.

[0031] The communication between the storage controller 2 and the storage device 3 follows, for example, an SDR (single data rate) interface, a ToggleDDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0032] 1.2 Storage devices

[0033] Next, refer to Figure 1 The block diagram shown illustrates the internal structure of the storage device in the embodiment. The storage device 3 includes, for example, a storage cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0034] The storage cell array 10 contains multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). The storage cell array 10 may also contain only one block BLK. A block BLK is a collection of multiple storage cells. A block BLK is used, for example, as a unit for data erasure. Furthermore, the storage cell array 10 is provided with multiple bit lines and multiple word lines. Each storage cell is associated with, for example, one bit line and one word line. The detailed configuration of the storage cell array 10 will be described later.

[0035] Command register 11 stores commands CMD received by storage device 3 from storage controller 2. Commands CMD include, for example, commands that cause sequencer 13 to perform read, write, erase, etc.

[0036] Address register 12 stores the address information ADD received by storage device 3 from storage controller 2. The address information ADD includes, for example, block address BAd, page address PAd, and column address CAd. For example, block address BAd, page address PAd, and column address CAd are used for the selection of block BL, word line, and bit line, respectively.

[0037] The sequencer 13 controls the overall operation of the storage device 3. For example, the sequencer 13 controls the driver module 14, the line decoder module 15, and the sense amplifier module 16 based on the command CMD stored in the command register 11, and performs read, write, and erase operations.

[0038] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Furthermore, the driver module 14 applies the generated voltages to the signal lines corresponding to the selected word lines, for example, based on the page address PAd stored in the address register 12.

[0039] The row decoder module 15 selects a block BLK within the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Furthermore, the row decoder module 15, for example, transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK.

[0040] During the write operation, the sense amplifier module 16 applies the desired voltage to each bit line based on the write data DAT received from the memory controller 2. Furthermore, during the read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit lines, reads the determination result, and transmits it as data DAT to the memory controller 2.

[0041] 1.3 Storage Cell Array

[0042] Next, the configuration of the memory cell array included in the memory device of the embodiment will be described.

[0043] 1.3.1 Circuit Structure

[0044] Figure 2 This is a circuit diagram illustrating an example of the circuit structure of a memory cell array included in a memory device according to an embodiment. Figure 2 The image shows one of the multiple block BLKs contained in the storage cell array 10. For example... Figure 2 As shown, block BLK contains, for example, four string groups SU0 to SU3.

[0045] Each string group SU contains multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). The number of bit lines BL can also be one. Each NAND string NS, for example, contains memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT contains a control gate and a charge storage film to store data in a non-volatile manner. Select transistors ST1 and ST2 are used to select the string group SU for various operations.

[0046] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of select transistor ST1 is connected to the associated bit line BL. The source of select transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of select transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of select transistor ST2 is connected to the source line SL.

[0047] Within the same BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistors ST1 within the serial groups SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. The gates of multiple select transistors ST2 are connected to select gate line SGS.

[0048] Bit lines BL0 to BLm are each assigned a different column address. Each bit line BL is shared among multiple BLK blocks by the NAND string NS, which is assigned the same column address. Word lines WL0 to WL7 are each set for each BLK block. Source lines SL are shared among multiple BLK blocks, for example.

[0049] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string group SU is called a cell group CU. For example, the storage capacity of a cell group CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". Depending on the number of bits of data stored by the memory cell transistors MT, a cell group CU can have a storage capacity of 2 pages or more.

[0050] Furthermore, the circuit structure of the memory cell array 10 provided in the memory device 3 is not limited to the configuration described above. For example, the number of string groups SU contained in each BLK can be designed to be arbitrary. The number of memory cell transistors MT and selection transistors ST1 and ST2 contained in each NAND string NS can also be designed to be arbitrary.

[0051] 1.3.2 Floor Plan

[0052] Figure 3 This is a top view illustrating an example of the planar layout of a memory cell array included in a memory device according to an embodiment. Figure 3 The example shown is four blocks BLK0 to BLK3 of the multiple blocks BLK in the storage cell array 10.

[0053] The memory cell array 10 includes a stacked wiring structure. The stacked wiring structure is a structure formed by stacking wiring layers (word lines WL0 to WL7 and select gate lines SGD and SGS).

[0054] Hereinafter, the plane that is approximately parallel to the stack-up plane of the wiring layer is defined as the XY plane. Directions orthogonal to each other on the XY plane are defined as the X direction and the Y direction. Furthermore, the direction approximately perpendicular to the XY plane and extending from the select gate line SGS towards the select gate line SGD is defined as the Z1 direction. The direction approximately perpendicular to the XY plane and extending from the select gate line SGD towards the select gate line SGS is defined as the Z2 direction. If neither the Z1 nor Z2 direction is specified, it will be referred to as the Z direction.

[0055] like Figure 3 As shown, the stacked wiring structure has memory regions MRa and MRb arranged in the X direction, and a lead-out region HR. Memory regions MRa and MRb are areas where memory cell transistors MT are disposed. The lead-out region HR is an area where contacts are disposed to electrically connect each wiring layer to the row decoder module 15. The lead-out region HR is, for example, located between memory regions MRa and MRb.

[0056] Each block of the multiple block BLKs includes a portion of the stacked wiring configuration that extends along the X direction by transecting the memory region MRa, the lead-out region HR, and the memory region MRb. The multiple block BLKs are arranged in the Y direction. The memory cell array 10 includes, for example, multiple components SLT and multiple components SHE.

[0057] Each component SLT extends along the X direction by transecting the memory region MRa, the lead-out region HR, and the memory region MRb. Multiple component SLTs are arranged in the Y direction. Each component SLT has, for example, a structure with embedded insulators. Each component SLT separates the wiring layers adjacent to it. In the memory cell array 10, each region separated by the component SLTs corresponds to one block BLK.

[0058] The multiple component SHEs include multiple component SHEs arranged in the Y direction in storage region MRa and multiple component SHEs arranged in the Y direction in storage region MRb. Each component SHE located in storage region MRa extends in the X direction, traversing storage region MRa. Each component SHE located in storage region MRb extends in the X direction, traversing storage region MRb. Figure 3 In the example, in each region of memory regions MRa and MRb, three components SHE are arranged between two adjacent components SLT in the Y direction. Each component SHE has, for example, a structure with embedded insulator. Each component SHE isolates the select gate line SGD in the wiring layer adjacent to that component SHE. In the memory cell array 10, the regions separated by groups of adjacent components SLT and SHE, or groups of two adjacent components SHE, correspond to one string group SU.

[0059] Furthermore, the planar layout of the storage cell array 10 can also be other layouts. For example, the number of components SHEs configured between two adjacent components SLTs can be designed to be any number. The number of serial groups SUs in each BLK can be changed based on the number of components SHEs configured between two adjacent components SLTs.

[0060] Figure 4 This refers to the planar layout of the memory cell array provided by the memory device in the embodiment. Figure 3 A top view of an example of region IV. Figure 4 The diagram shows the lead-out region HR in block BLK0, and the boundary between the lead-out region HR and the storage regions MRa and MRb.

[0061] First, the planar layout of the memory cell array 10 in memory regions MRa and MRb will be described.

[0062] like Figure 4 As shown, the memory cell array 10 includes multiple memory pillars MP, multiple contacts CV, and multiple bit lines BL in each region of memory regions MRa and MRb.

[0063] Each memory column (MP) functions as a NAND string (NS). Multiple memory columns (MPs) are arranged in a zigzag pattern, for example, in 19 columns, in the area between two adjacent components (SLTs). For example, counting from the top of the paper, the memory columns (MPs) in the 5th, 10th, and 15th columns are each arranged as one component (SHE).

[0064] Multiple bit lines (BLs) are arranged in the X direction. Each bit line (BL) is configured to overlap with at least one memory column (MP) per string group (SU). Figure 4 In the example, two bit lines BL are arranged overlappingly in one memory column MP. The memory column MP is electrically connected to one of the multiple bit lines BL arranged overlappingly via a contact CV. On the other hand, the contact CV between the memory column MP and the bit line BL that are connected to two different select gate lines SGD (i.e., arranged overlappingly with the component SHE) can be omitted.

[0065] Furthermore, the planar layout within the memory region (MR) can also be other layouts. For example, the number and arrangement of memory cylinders (MPs) and components (SHEs) configured between two adjacent component SLTs can be appropriately changed. The number of bit lines (BLs) overlapping each memory cylinder (MP) can be designed to be arbitrary.

[0066] Next, the planar layout of the storage cell array 10 in the outgoing area HR will be described.

[0067] The memory cell array 10 includes multiple contacts CC in the lead-out area HR. Additionally, the stacked wiring configuration has a platform portion and a trunk portion HW in the lead-out area HR. The platform portion is the part of the wiring layer constituting the stacked wiring configuration that does not overlap with the upper wiring layer in the Z1 direction. The trunk portion HW is the portion arranged in the Y direction with the platform portion.

[0068] The layered wiring configuration forms a stepped structure on the platform section. Figure 4In the example, steps are formed between the select gate line SGS and the word line WL0, between word line WL0 and word line WL1, ..., between word line WL6 and word line WL7, and between word line WL7 and the select gate line SGD. Furthermore, all steps do not necessarily have to be arranged in a single direction. For example, it could be that the select gate line SGS and a portion of the word lines WL0 to WL7 (in...) Figure 4 In the example, the select gate line SGS and word lines WL0~WL2) are formed in descending order in the X direction as a ladder, and the remaining parts (in Figure 4 In the example, word lines WL3 to WL7 are formed in ascending order in the X direction as steps. Alternatively, for example, select gate line SGS and a portion of word lines WL0 to WL7 can also be formed in the Y direction as steps.

[0069] Except for the select gate line SGD, the wiring layers of memory region MRa and memory region MRb are continuously arranged across a trunk section HW. That is, the trunk section HW is the portion that electrically connects the wiring layers, excluding the select gate line SGD, between memory region MRa and memory region MRb. The select gate line SGD is separated into portions of memory region MRa and memory region MRb by the lead-out region HR.

[0070] Contacts CC are conductors used for connections between the row decoder module 15 and each wiring layer. Multiple contacts CC corresponding to block BLK are respectively connected to the select gate lines SGS and SGD located in the lead-out region HR, and to the platform portions of word lines WL0 to WL7. Furthermore, different contacts CC are provided for the select gate line SGD on the memory region MRa side and the select gate line SGD on the memory region MRb side. The select gate lines SGD on the memory region MRa side and the select gate line SGD on the memory region MRb side, corresponding to the same string group SU, are electrically connected, for example, via their respective contacts CC and an upper wiring layer (not shown).

[0071] 1.3.3 Cross-sectional structure

[0072] Figure 5 This is an example of a cross-sectional structure along which the memory cell array of the memory device described in the embodiment is shown. Figure 4 A cross-sectional view of the VV line. In Figure 5 The image shows a cross-sectional view of the storage region MRb and a portion of the lead-out region HR.

[0073] like Figure 5 As shown, the memory cell array 10 includes, for example, a semiconductor layer 21, wiring layers 22, 23, and 24, conductive layers 25 (25a and 25b), and insulating layers 31, 32, 33, 34, and 35. Insulating layers 31 to 35, for example, comprise silicon oxide. Figure 5 In the diagram, the Z1 direction corresponds to the top of the paper.

[0074] A semiconductor layer 21 is disposed on the insulating layer 31. The semiconductor layer 21 is formed, for example, as a plate extending along the XY plane. The semiconductor layer 21 contains, for example, silicon and is used as a source line SL.

[0075] An insulating layer 32 is disposed on the semiconductor layer 21. A wiring layer 22 is disposed on the insulating layer 32. The wiring layer 22 is formed, for example, as a plate extending along the XY plane. The wiring layer 22 contains, for example, tungsten and is used as a select gate line (SGS).

[0076] On the wiring layer 22, a plurality of insulating layers 33 and wiring layers 23 are alternately disposed. The plurality of wiring layers 23 are formed, for example, in a plate shape extending along the XY plane. The plurality of wiring layers 23 contain, for example, tungsten and are used as word lines WL0 to WL7 sequentially from the semiconductor layer 21 side.

[0077] An insulating layer 34 is disposed on the uppermost wiring layer 23. A wiring layer 24 is disposed on the insulating layer 34. The wiring layer 24 is formed, for example, as a plate extending along the XY plane. The wiring layer 24 contains, for example, tungsten for use as a select gate line (SGD).

[0078] In the storage region MRb, multiple storage pillars MP each extend along the Z-direction, penetrating wiring layers 22-24 and insulating layers 32-34. Each of the multiple storage pillars MP has, for example, a shape whose diameter gradually decreases (taperes) along the Z2 direction. Furthermore, although in Figure 5 The illustration is omitted, but multiple storage columns MP are also set up in the storage area MRa.

[0079] Each of the multiple memory pillars (MP) includes, for example, a core film 41, a semiconductor film 42, and a laminated film 43. The core film 41 is an insulator extending along the Z-direction. The semiconductor film 42 covers the core film 41. The lower part of the semiconductor film 42 is in contact with the semiconductor layer 21. The laminated film 43 covers the sides of the semiconductor film 42.

[0080] Figure 6 This is an example of the cross-sectional structure of the memory pillars provided by the storage device in the embodiment. Figure 5 A sectional view along line VI-VI. Figure 6 The image shows a cross-section containing the storage column MP and wiring layer 23, parallel to the XY plane. (See image for details.) Figure 6 As shown, the laminated film 43 includes, for example, a channel insulating film 44, a charge storage film 45, and a block insulating film 46.

[0081] The core film 41 is disposed, for example, in the central portion of the memory pillar MP. A semiconductor film 42 surrounds the sides of the core film 41. A channel insulating film 44 surrounds the sides of the semiconductor film 42. A charge storage film 45 surrounds the sides of the channel insulating film 44. A bulk insulating film 46 surrounds the sides of the charge storage film 45. A wiring layer 23 surrounds the sides of the bulk insulating film 46. The semiconductor film 42 serves as a channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The channel insulating film 44 and the bulk insulating film 46 each contain, for example, silicon oxide. The charge storage film 45 contains, for example, silicon nitride.

[0082] With the above configuration, each memory pillar MP functions as a NAND string NS. Specifically, the portion where memory pillar MP intersects with wiring layer 22 functions as selection transistor ST2. The portion where memory pillar MP intersects with wiring layer 23 functions as memory cell transistor MT. The portion where memory pillar MP intersects with wiring layer 24 functions as selection transistor ST1.

[0083] A contact CV is provided on the upper surface of the semiconductor film 42 in the Z1 direction within the storage column MP. The contact CV has, for example, a shape in which the diameter gradually tapers towards the Z2 direction. A conductive layer 25a is provided on the upper surface of the contact CV in the Z1 direction. The conductive layer 25a is, for example, formed as a line extending along the Y direction. The conductive layer 25a contains, for example, copper and is used as a bit line BL.

[0084] In the lead-out area HR, multiple contacts CC each extend along the Z direction. Each of the multiple contacts CC has, for example, a shape in which the diameter gradually tapers towards the Z2 direction. Each of the multiple contacts CC is connected to the platform portion of the corresponding wiring layer 22-24, and is separately disposed from non-corresponding wiring layers 22-24.

[0085] A conductive layer 25b is provided on the upper surface of the contact CC in the Z1 direction. The conductive layer 25b contains, for example, copper and is provided in the same layer as the conductive layer 25a. Hereinafter, the layer in which the conductive layers 25a and 25b are provided will be referred to as layer M0.

[0086] The above-described stacked wiring structure includes an insulating layer 35 that covers the contacts CC and CV and the conductive layers 25a and 25b.

[0087] 1.4 Line Decoder Module

[0088] Next, the configuration of the row decoder module in the implementation method will be described.

[0089] 1.4.1 Circuit Structure

[0090] Figure 7This is a circuit diagram illustrating an example of the circuit structure of a line decoder module included in a storage device according to an embodiment. For example... Figure 7 As shown, the line decoder module 15 includes multiple line decoders RD (RD0, RD1, ...). The number of line decoders RD corresponds to the number of blocks BLK. Each of the multiple line decoders RD has an identical structure. Figure 7 In the example, the configuration of the row decoder RD0 corresponding to block BLK0 is shown. The row decoder RD0 includes the block decoder BD and the switch group WLSW. The switch group WLSW contains multiple transistors TR (TR0 to TR17).

[0091] Transistors TR0 through TR12 are, for example, N-type transistors. The first terminal of each of transistors TR0 through TR7 is connected to block BLK0 via word lines WL0 through WL7. The second terminal of each of transistors TR0 through TR7 is connected to driver module 14 via wirings CG0 through CG7. The gate of each of transistors TR0 through TR7 is connected to block decoder BD via wiring BLKSEL.

[0092] For example, during a write operation, transistors TR0 to TR7 can respectively deliver write voltages to word lines WL0 to WL7. The write voltage is a high voltage capable of raising the threshold voltage of the memory cell transistor MT. Therefore, transistors TR0 to TR7 have a high withstand voltage sufficient to deliver the write voltage. Hereinafter, transistors with a high withstand voltage sufficient to deliver the write voltage are also called "high-voltage transistors" or "HV transistors." The gate oxide film thickness of an HV transistor is at least 10 nm or more; if the transistor can operate up to 30V, the film thickness is designed to be, for example, around 40 nm. Furthermore, transistors with a lower withstand voltage than HV transistors are also called "low-voltage transistors" or "LV transistors." The gate oxide film thickness of an LV transistor is designed to be, for example, 5 nm or more and 7 nm or less. Furthermore, transistors with an even lower withstand voltage than LV transistors are also called "ultra-low-voltage transistors" or "VLV transistors." The gate oxide film thickness of a VLV transistor is designed to be, for example, 2.5 nm or more and 3.5 nm or less.

[0093] Transistor TR8 is, for example, an N-type HV transistor. Terminal 1 of transistor TR8 is connected to block BLK0 via the select gate line SGS. Terminal 2 of transistor TR8 is connected to driver module 14 via the wiring SGSD. The gate of transistor TR8 is connected to block decoder BD via the wiring BLKSEL.

[0094] Transistors TR9 through TR12 are, for example, N-type HV transistors. The first terminal of each transistor TR9 through TR12 is connected to block BLK0 via select gate lines SGD0 through SGD3. The second terminal of each transistor TR9 through TR12 is connected to driver module 14 via wiring SGDD0 through SGDD3. The gate of each transistor TR9 through TR12 is connected to block decoder BD via wiring BLKSEL.

[0095] Transistor TR13 is, for example, an N-type HV transistor. Terminal 1 of transistor TR13 is connected to block BLK0 via the select gate line SGS. Terminal 2 of transistor TR13 is connected to driver module 14 via wiring USGS. The gate of transistor TR13 is connected to block decoder BD via wiring BLKSELn.

[0096] Transistors TR14 to TR17 are, for example, N-type HV transistors. The first terminal of each of transistors TR14 to TR17 is connected to block BLK0 via select gate lines SGD0 to SGD3. The second terminal of each of transistors TR14 to TR17 is connected to driver module 14 via wiring USGD. The gate of each of transistors TR14 to TR17 is connected to block decoder BD via wiring BLKSELn.

[0097] The block decoder BD supplies different logic levels to the wiring BLKSEL and BLKSELn. When block BLK0 is selected, the block decoder BD supplies an "H" level voltage to wiring BLKSEL and an "L" level voltage to wiring BLKSELn. When block BLK0 is not selected, the block decoder BD supplies an "L" level voltage to wiring BLKSEL and an "H" level voltage to wiring BLKSELn.

[0098] 1.4.2 Floor Plan

[0099] Figure 8 This is a top view showing an example of the planar layout of a line decoder module included in a storage device according to an embodiment. Figure 8 The diagram shows a planar layout of multiple transistors TR in region XR of the line decoder module 15, which constitute four switch groups WLSW corresponding to four blocks BLK0 to BLK3.

[0100] like Figure 8 As shown, in region XR, multiple transistors TR of each switch group constituting multiple switch groups WLSW are arranged in the X direction. Furthermore, the multiple switch groups WLSW are arranged in the Y direction. Figure 8In the example, the switch group WLSW corresponding to block BLK3, the switch group WLSW corresponding to block BLK2, the switch group WLSW corresponding to block BLK1, and the switch group WLSW corresponding to block BLK0 are arranged in this order in the Y direction.

[0101] Each transistor TR includes a sludge diffusion region NR that functions as the source, a sludge diffusion region NR that functions as the drain, and an electrode GE that functions as the gate. One of the two sludge diffusion regions NR constituting a transistor TR, the electrode GE, and the other of the two sludge diffusion regions NR are arranged in this order in the Y direction.

[0102] As described above, the multiple transistors TR arranged in the X direction correspond to the same BLK. Therefore, the multiple electrodes GE arranged in the X direction are electrically connected. Figure 8 The example shows a configuration where multiple electrodes GE arranged in the X direction are separated from each other, but this is not the only possibility. Multiple electrodes GE arranged in the X direction can also be configured as a single conductor extending along the X direction.

[0103] Two transistors (TR) arranged in the Y direction share a single impurity diffusion region (NR). Figure 8 In the example, one transistor TR in the transistor TR corresponding to block BLK0 and one transistor TR in the transistor TR corresponding to block BLK1 share one impurity diffusion region NR. One transistor TR in the transistor TR corresponding to block BLK2 and one transistor TR in the transistor TR corresponding to block BLK3 share one impurity diffusion region NR.

[0104] Two transistors TR sharing a single impurity diffusion region NR contain three impurity diffusion regions NR and two electrodes GE. The three impurity diffusion regions NR and the two electrodes GE are arranged in the Y direction in the following order: impurity diffusion region NRc, electrode GEb, shared impurity diffusion region NRb, electrode GEa, and impurity diffusion region NRa.

[0105] Figure 9 This represents the planar layout of the line decoder module included in the storage device of the embodiment. Figure 8 A top view of an example of region IX. Figure 9 The diagram shows two transistors TR sharing a common impurity diffusion region NRb. One of these transistors TR corresponds to block BLK0, and the other corresponds to block BLK1.

[0106] like Figure 9As shown, the two transistors TR include: impurity diffusion regions NRa, NRb, NRc and PR, electrodes GEa, GEb, REa, REb, REc, REd, REe, REf and OE, contacts C0a, C0b, CSa, CSb, CSc, CSd, CSe and CSf, and component separation region STI.

[0107] Impurity diffusion regions NRa, NRb, and NRc are arranged separately from each other in the Y direction. Each of the impurity diffusion regions NRa, NRb, and NRc has, for example, a rectangular shape. Impurity diffusion region PR is disposed within impurity diffusion region NRb. Impurity diffusion region PR has, for example, a four-cornered annular shape. Impurity diffusion region NRb is located inside the annulus of impurity diffusion region PR.

[0108] Viewed in the Z direction, electrodes REa, REb, and REc are positioned at locations overlapping with the impurity diffusion regions NRa, NRb, and NRc, respectively. That is, electrodes REa, REb, and REc are arranged separately from each other in the Y direction. Each electrode REa, REb, and REc has a four-cornered annular shape. In other words, each electrode REa, REb, and REc has an opening.

[0109] A contact CSa extending along the Z2 direction is provided on the impurity diffusion region NRa. The contact CSa passes through the opening of the electrode REa without contacting the electrode REa. A contact CSd extending along the Z2 direction is provided on the electrode REa. Furthermore, an electrode REd extending along the Y direction is provided such that the upper surfaces of the contact CSa and CSd in the Z2 direction are connected to each other. Thus, the electrode REa and the impurity diffusion region NRa are electrically connected and have approximately the same potential.

[0110] A contact CSb extending in the Z2 direction is provided on the portion of the impurity diffusion region NRb surrounded by the impurity diffusion region PR. The contact CSb passes through the opening of the electrode REb without contacting the electrode REb. A contact CSe extending in the Z2 direction is provided on the electrode REb. Furthermore, an electrode REe extending in the Y direction is provided such that the upper surfaces of the contact CSb and CSe in the Z2 direction are connected to each other. Thus, the electrode REe is electrically connected to the impurity diffusion region NRb and is at approximately the same potential.

[0111] A contact CSc extending along the Z2 direction is provided on the impurity diffusion region NRc. The contact CSc passes through the opening of the electrode REc without contacting the electrode REc. A contact CSf extending along the Z2 direction is provided on the electrode REc. Furthermore, an electrode REf extending along the Y direction is provided such that the upper surfaces of the contact CSc and CSf in the Z2 direction are connected to each other. Thus, the electrode REc and the impurity diffusion region NRc are electrically connected and have approximately the same potential.

[0112] Electrode GEa is disposed between electrodes REa and REb. Viewed in the Z direction, electrode GEa has a portion overlapping with the impurity diffusion region NRa and a portion overlapping with the impurity diffusion region NRb. A contact C0a extending along the Z2 direction is disposed on electrode GEa.

[0113] Electrode GEb is disposed between electrode REb and electrode REc. Viewed in the Z direction, electrode GEb has a portion overlapping with the impurity diffusion region NRc and a portion overlapping with the impurity diffusion region NRb. A contact C0b extending along the Z2 direction is disposed on electrode GEb.

[0114] For example, when viewed in the Z direction, the boundary between the impurity diffusion region PR and the impurity diffusion region NRb is located in the region between the electrodes GEa and REb. Similarly, when viewed in the Z direction, the boundary between the impurity diffusion region PR and the impurity diffusion region NRc is located in the region between the electrodes GEc and REb. From the viewpoint of improving the withstand voltage of the transistor TR, it is preferable to have a longer length d in the Y direction for the portion of the impurity diffusion region PR between the contact CSb and the contact C0a. Likewise, from the viewpoint of improving the withstand voltage of the transistor TR, it is preferable to have a longer length d in the Y direction for the portion of the impurity diffusion region PR between the contact CSb and the contact C0b.

[0115] The component separation region STI is configured to surround the impurity diffusion regions NRa, NRb, and NRc, as well as the electrodes REa, REb, REc, GEa, and GEb. Thus, the two transistors TR are electrically isolated from the other transistors TR.

[0116] Electrode OE is configured to surround the impurity diffusion regions NRa, NRb, and NRc, as well as electrodes REa, REb, REc, GEa, and GEb. Viewed in the Z-direction, electrode OE is positioned to overlap with the component separation region STI. Electrode OE is electrically insulated from other electrodes and the impurity diffusion regions. Electrode OE is in a floating state, for example, during write and read operations.

[0117] 1.4.3 Cross-sectional structure

[0118] Figure 10This is an example of the cross-sectional structure of a line decoder module included in a storage device according to an embodiment. Figure 9 A cross-sectional view along the XX line. In Figure 10 The image shows a cross-sectional structure of two transistors TR that share the impurity diffusion region NRb in region XR. Figure 10 In the diagram, the Z2 direction corresponds to the top of the paper.

[0119] like Figure 10 As shown, transistor TR is disposed on substrate 50. Substrate 50 is, for example, a silicon substrate.

[0120] A well region NW is formed on the upper part of the substrate 50. The well region NW is a region containing N-type impurities such as phosphorus (P) or arsenic (As). The upper surface of the well region NW in the Z2 direction is aligned with the upper surface of the substrate 50 in the Z2 direction.

[0121] A well region PW is formed on top of the well region NW. The well region PW is a region containing P-type impurities, such as boron (B) or indium (In), which have a different conductivity type than N-type impurities. Viewed in the Z direction, the well region PW is contained within the well region NW. The upper surface of the well region PW in the Z2 direction is aligned with the upper surface of the substrate 50 in the Z2 direction.

[0122] Above the well region NW, a component separation region STI is further formed in a manner that surrounds the well region PW. The depth of the component separation region STI is deeper than that of the well region PW but shallower than that of the well region NW. The upper surface of the component separation region STI in the Z2 direction is located on the Z2-direction side of the upper surface of the substrate 50.

[0123] Above the well region PW, impurity diffusion regions NRa, NRb, and NRc are formed separately from each other in the Y direction. Each of the impurity diffusion regions NRa, NRb, and NRc is a region containing N-type impurities. Viewed in the Z direction, the impurity diffusion regions NRa, NRb, and NRc are contained within the well region PW. The upper surfaces of each of the impurity diffusion regions NRa, NRb, and NRc in the Z2 direction are aligned with the upper surface of the substrate 50 in the Z2 direction.

[0124] Impurity diffusion regions NRa, NRb, and NRc each contain region N - and region N + Region N - This is a region with a relatively low concentration of N-type impurities. Region N + This is a region with a relatively high concentration of N-type impurities. Region N + Located at the center of each of the impurity diffusion regions NRa, NRb, and NRc. Viewed along the Z direction, region N... - Enclosed region N + .

[0125] In the impurity diffusion region NRb, region N - The upper part forms an impurity diffusion region PR. The impurity diffusion region PR is a region containing P-type impurities. The impurity concentration in the impurity diffusion region PR is, for example, that in region N. - The impurity concentration in region N is above a certain level. The upper surface of the impurity diffusion region PR in the Z2 direction is aligned with the upper surface of the substrate 50 in the Z2 direction. Viewed in the Z direction, the impurity diffusion region PR is contained within region N. - Therefore, the impurity diffusion region PR is discontinuous with the trap region PW.

[0126] In the region N of the impurity diffusion region NRa + A conductive layer 51a is disposed on the upper surface in the Z2 direction. In the region N of the impurity diffusion region NRb... + A conductive layer 51b is disposed on the upper surface in the Z2 direction. In the region N of the impurity diffusion region NRc... + A conductive layer 51c is disposed on the upper surface in the Z2 direction. Each of the conductive layers 51a, 51b and 51c contains, for example, at least one compound selected from nickel silicide (NiSi), nickel platinum silicide (NiPtSi) and cobalt silicide (CoSi).

[0127] The portion of the upper surface of the substrate 50 in the Z2 direction, excluding the conductive layers 51a, 51b, and 51c (i.e., the well regions NW and PW and region N) - An insulating layer 52 is disposed on the upper surface in the Z2 direction. The insulating layer 52 functions as the gate insulating film of the transistor TR.

[0128] Conductor layers 53 and 54 are stacked in this order on the upper surface of the insulating layer 52 and the component separation region STI in the Z2 direction. Conductor layer 53 comprises, for example, polycrystalline silicon. Conductor layer 54 comprises, for example, at least one compound selected from nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi).

[0129] Conductor layer 53 includes portions 53ga, 53gb, 53ra, 53rb, 53rc, and 53o that are disposed separately from each other. Conductor layer 54 includes portions 54ga, 54gb, 54ra, 54rb, 54rc, and 54o that are respectively stacked with portions 53ga, 53gb, 53ra, 53rb, 53rc, and 53o of conductor layer 53. Portions 53ga and 54ga function as electrodes GEa. Portions 53gb and 54gb function as electrodes GEb. Portions 53ra and 54ra function as electrodes REa. Portions 53rb and 54rb function as electrodes REb. Portions 53rc and 54rc function as electrodes REc. Portions 53o and 54o function as electrodes OE.

[0130] An insulating film SW is provided on the side of each part in the conductive layers 53 and 54 where each electrode GEa, GEb, REa, REb, REc and OE functions.

[0131] A contact CSa is provided on the upper surface of the conductive layer 51a in the Z2 direction. A contact CSb is provided on the upper surface of the conductive layer 51b in the Z2 direction. A contact CSc is provided on the upper surface of the conductive layer 51c in the Z2 direction.

[0132] A contact C0a is provided on the upper surface of portion 54ga of conductor layer 54 in the Z2 direction. A contact C0b is provided on the upper surface of portion 54gb of conductor layer 54 in the Z2 direction.

[0133] A conductive layer 55 is provided on the upper surface of each of the contacts C0a, C0b, CSa, CSb, and CSc in the Z2 direction. The layer on which the conductive layer 55 is provided is called layer D0. In addition to the conductive layer 55 described above, multiple conductive layers 55 may be provided in layer D0.

[0134] The transistor TR, constructed as described above, is covered by an insulating layer 59.

[0135] As described above, the impurity diffusion region PR has a length d in the Y direction, for example. For example, when viewed in the Z direction, the region N of the impurity diffusion region NRb within the impurity diffusion region PR... + The portion between the impurity diffusion region NRa and the impurity diffusion region NRa, located at the end of the impurity diffusion region NRa, between electrodes GEa and REb, is where the insulating film SW is disposed. For example, viewed in the Z direction, the region N of the impurity diffusion region PR and the impurity diffusion region NRb. +The portion between the impurity diffusion region NRc and the impurity diffusion region NRc, specifically the end of the impurity diffusion region NRc, is the region where an insulating film SW is disposed between electrodes GEb and REb. From the viewpoint of improving the withstand voltage of the transistor TR, it is preferable that the width d is not adjacent to region N. + and the region N adjacent to the conductor layer 51b + It extends relatively far to the side.

[0136] 1.5 Overall Structure

[0137] Next, the overall structure of the storage device according to the embodiment will be described.

[0138] 1.5.1 Fitting Structure

[0139] Figure 11 This is a perspective view showing the outline of the bonding structure of the storage device according to the embodiment. (e.g.) Figure 11 As shown, the storage device 3 includes a storage chip 100 and a circuit chip 200.

[0140] The memory chip 100 and the circuit chip 200 each include multiple bonding pads BP. The memory device 3 is formed by bonding the memory chip 100 and the circuit chip 200 together via the multiple bonding pads BP.

[0141] The memory chip 100 includes a configuration corresponding to the memory cell array 10. The circuit chip 200 includes, for example, a configuration corresponding to the command register 11, the address register 12, the sequencer 13, the driver module 14, the row decoder module 15, and the sense amplifier module 16.

[0142] As described above, the memory chip 100 has memory regions MRa and MRb and a lead-out region HR. The circuit chip 200, in addition to region XR, also has regions SRa and SRb. Region XR is where the row decoder module 15 is located. Regions SRa and SRb are where the command register 11, address register 12, sequencer 13, driver module 14, and sense amplifier module 16 are located. The memory regions MRa, HR, and MRb in the memory chip 100 are respectively attached in a manner opposite to the regions SRa, XR, and SRb in the circuit chip 200.

[0143] 1.5.2 Cross-sectional structure

[0144] Figure 12 This is a cross-sectional view illustrating an example of the cross-sectional structure of a storage device according to an embodiment. Figure 12 In the diagram, the Z2 direction corresponds to the top of the paper.

[0145] like Figure 12As shown, the memory device 3 in the memory chip 100 further includes conductive layers 26 and 27, a protective layer 30, and contacts V0 and V1. The memory device 3 in the circuit chip 200 further includes conductive layers 56, 57 and 58, contacts C1, C2 and C3, and a transistor T.

[0146] First, let's explain the memory chip 100.

[0147] A protective layer 30 is disposed on the upper surface of the insulating layer 31 in the Z2 direction. The protective layer 30 is a layer corresponding to the surface of the storage device 3, and may contain, for example, a resin material such as polyimide. In an area not shown, a portion of the protective layer 30 is removed. Furthermore, in the portion where the protective layer 30 has been removed, a power pad responsible for electrical connection to the outside is provided.

[0148] A contact V0 is provided on the upper surface of each of the conductive layers 25a and 25b in the Z1 direction. The contact V0 has, for example, a shape in which the diameter gradually tapers in the Z2 direction. A conductive layer 26 is provided on the upper surface of the contact V0 in the Z1 direction.

[0149] A contact V1 is provided on the upper surface of the conductive layer 26 in the Z1 direction. The contact V1 has, for example, a shape whose diameter gradually tapers towards the Z2 direction. A conductive layer 27 is provided on the upper surface of the contact V1 in the Z1 direction. The conductive layer 27 functions as a bonding pad BP on the bonding surface of the memory chip 100 and the circuit chip 200. Conductive layers 26 and 27, and contacts V0 and V1, are covered by an insulating layer 35. The layers on which conductive layers 26 and 27 are provided are referred to as layer M1 and bonding layer B1, respectively.

[0150] Next, the circuit chip 200 will be described.

[0151] Transistors TR and T are disposed in regions XR and SR on substrate 50, respectively. Transistor T is, for example, a transistor constituting sense amplifier module 16. Transistor T may have the same configuration as transistor TR. In transistor TR, the drain, gate, and source are arranged in the Y direction, while in contrast, the drain, gate, and source of transistor T are arranged in the X direction.

[0152] A contact C0 is provided on the upper surface of the gate insulating film of transistors TR and T in the Z2 direction. A contact CS is provided on the upper surface of the source or drain of transistors TR and T in the Z2 direction. A conductive layer 55 is provided on the upper surface of the contacts CS and C0 in the Z2 direction.

[0153] A contact C1 is provided on the upper surface of the conductive layer 55 in the Z2 direction. A conductive layer 56 is provided on the upper surface of the contact C1 in the Z2 direction. A contact C2 is provided on the upper surface of the conductive layer 56 in the Z2 direction. A conductive layer 57 is provided on the upper surface of the contact C2 in the Z2 direction. A contact C3 is provided on the upper surface of the conductive layer 57 in the Z2 direction. A conductive layer 58 is provided on the upper surface of the contact C3 in the Z2 direction. The conductive layer 58 is in contact with the corresponding conductive layer 27 and functions as a bonding pad BP at the bonding surface with the memory chip 100. The conductive layers 55, 56, 57, and 58 and the contacts CS, C0, C1, C2, and C3 are covered by an insulating layer 59. The layers on which the conductive layers 56, 57, and 58 are provided are referred to as layers D1, D2, and bonding layer B2, respectively.

[0154] As described above, transistor TR is electrically connected to the gate of memory cell transistor MT via word line WL. Transistor T is electrically connected to one end of the select transistor ST1 in the NAND string NS via bit line BL.

[0155] 2. Effects

[0156] Transistors (TRs) require high voltage withstand capability because high voltages are applied during write and read operations. According to the embodiments, the voltage withstand capability of transistor TRs can be improved. This effect will be explained below.

[0157] Figure 13 This is a diagram illustrating an example of the potential distribution generated by the transistors in the comparative example's memory device. Figure 14 This is a diagram illustrating an example of the potential distribution generated by the transistors in the memory device of the embodiment. The comparative example corresponds to the case where no impurity diffusion region PR is formed within the impurity diffusion region NRb. Figure 13 as well as Figure 14 The potential distributions E1 and E2 generated in the impurity diffusion region NRb when a high voltage is applied are shown by dashed lines.

[0158] like Figure 13 As shown in region A1, without the formation of the impurity diffusion region PR, the potential distribution E1 in region N... - At the boundary with insulating layer 52, the electrode REb side has a low density and is biased towards the electrode GEa side. Therefore, an electric field concentration occurs in region N. - The GEa side of the electrode is prone to failure.

[0159] In contrast, such as Figure 14 As shown in region A2, when the impurity diffusion region PR is formed, the potential distribution E2 in region N... -The electric field at the boundary with insulating layer 52 is dispersed not only on the electrode GEa side but also on the electrode REb side. Therefore, the electric field concentration on the electrode GEa side can be mitigated, and the generation of faults can be suppressed.

[0160] Figure 15 This diagram illustrates an example of the characteristics of a transistor included in a storage device according to an embodiment. Figure 15 In the diagram, the vertical axis corresponds to the current Id flowing to the drain of transistor TR, and the horizontal axis corresponds to the voltage Vd applied to the drain of transistor TR. Furthermore, the current-voltage characteristic of transistor TR in the comparative example is represented by a dashed line L1. In contrast, the current-voltage characteristic of transistor TR in the embodiment is represented by solid lines L2 and L3. The difference between solid lines L2 and L3 lies in the length of the width d. That is, the width d corresponding to solid line L3 is longer than the width d corresponding to solid line L2.

[0161] like Figure 15 As shown, without the formation of the impurity diffusion region PR, a fault occurs at voltage Vd1. Conversely, with the formation of the impurity diffusion region PR, the fault can be suppressed up to a voltage Vd2, which is higher than voltage Vd1. Furthermore, if the width d of the impurity diffusion region PR is increased, the fault can be further suppressed up to a voltage Vd3, which is higher than voltage Vd2.

[0162] Thus, according to the implementation method, through region N - The formation of an impurity diffusion region PR within the transistor can improve the voltage withstand capability of the transistor TR.

[0163] 3. Variations, etc.

[0164] Various modifications can be applied to the above-described implementation methods.

[0165] 3.1 First Variation

[0166] In the above embodiments, the case where the contact CSa passes through the opening of the electrode REa and the contact CSc passes through the opening of the electrode REc has been described, but it is not limited to this. For example, it may also be configured such that the contact CSa passes through the opening of the electrode GEa and the contact CSc passes through the opening of the electrode GEb.

[0167] Figure 16 This is a top view showing an example of the planar layout of the line decoder module provided by the storage device in the first modified example. Figure 16 Corresponding to the implementation method Figure 9 .

[0168] like Figure 16As shown, electrodes CSa and CSc may also be omitted. In this case, electrode GEa is configured to cover the impurity diffusion region NRa when viewed in the Z direction and has an opening. Contact CSa extends in the Z direction through the opening of electrode GEa. Electrode GEb is configured to cover the impurity diffusion region NRc when viewed in the Z direction and has an opening. Contact CSc extends in the Z direction through the opening of electrode GEb.

[0169] In the above configuration, by setting an impurity diffusion region PR within the impurity diffusion region NRb, the impurity diffusion region N can be mitigated. - The electric field is concentrated in the transistor. Therefore, the voltage withstand capability of the transistor TR can be improved.

[0170] 3.2 Second Variation

[0171] In the above-described embodiments and the first modification, the case where the contact CSb passes through the opening of the electrode REb has been described, but it is not limited to this. For example, the electrode REb may not be provided, and the contact CSb may be configured to pass between the electrodes GEa and GEb.

[0172] Figure 17 This is a top view showing an example of the planar layout of the line decoder module provided by the storage device in the second variation. Figure 17 Corresponding to the first variation Figure 16 .

[0173] like Figure 17 As shown, electrode CSb may also be omitted. In this case, electrode GEa is positioned to cover the impurity diffusion region NRb relative to contact CSb on the contact CSa side when viewed in the Z direction. Electrode GEb is positioned to cover the impurity diffusion region NRb relative to contact CSb on the contact CSc side when viewed in the Z direction. Contact CSb extends along the Z direction through the space between electrodes GEa and GEb.

[0174] In the above configuration, by setting an impurity diffusion region PR within the impurity diffusion region NRb, the impurity diffusion region N can be mitigated. - The electric field is concentrated in the transistor. Therefore, the voltage withstand capability of the transistor TR can be improved.

[0175] 3.3 Other

[0176] In the above-described embodiments, the first modification, and the second modification, the impurity diffusion region PR is surrounded by a region N that encloses the impurity diffusion region NRb. + The method in region N -The case where the inner part is set in a ring shape has been described, but it is not limited to this. For example, the impurity diffusion region PR can be set in region N of the impurity diffusion region NRb. + Region N with impurity diffusion region NRa + The portion extending along the X direction between and the region N in the impurity diffusion region NRb + Region N with impurity diffusion region NRc + The portion extending along the X direction is sufficient; alternatively, the portion extending along the Y direction can be omitted. This configuration also improves the voltage withstand capability of the transistor TR.

[0177] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, with various omissions, substitutions, and modifications possible without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage device comprising: Region 1, Region 3 and Region 2 are disposed in the substrate and arranged separately from each other in the first direction, and each contains impurities of the first conductivity type. The fourth region, located within the third region, contains impurities of a second conductivity type that are different from the first conductivity type; A first conductive layer is disposed above the first region and has a first opening; A second conductive layer is disposed above the second region and has a second opening; The first contact element is connected to the first region and passes through the first opening; The second contact element is connected to the second region and passes through the second opening; The first storage unit is connected to the first contact; and The second storage unit is connected to the second contact.

2. The storage device according to claim 1, The impurity concentration of the second conductivity type contained in the fourth region is greater than or equal to the impurity concentration of the first conductivity type contained in the third region.

3. The storage device according to claim 1, further comprising: A first well region, disposed within the substrate, contains impurities of the first conductivity type; and The second well region, located within the first well region, contains impurities of the second conductivity type. The first region, the second region, and the third region are located within the second trap region.

4. The storage device according to claim 3, The third region includes the portion between the fourth region and the second well region.

5. The storage device according to claim 3, It also includes an insulating film disposed within the first well region. The insulating film surrounds the second well region.

6. The storage device according to claim 1, It also includes a third contact member connected to the third region, through the first conductive layer and the second conductive layer.

7. The storage device according to claim 6, When viewed from above, the fourth region includes a portion extending along the first direction between the first conductive layer and the third contact, and a portion extending along the first direction between the second conductive layer and the third contact.

8. The storage device according to claim 6, When viewed from above, the fourth region surrounds the third contact.

9. The storage device according to claim 6, It also includes a third conductive layer, which is disposed above the third region and has a third opening through which the third contact passes.

10. The storage device according to claim 9, The third conductive layer is electrically connected to the third region.

11. The storage device according to claim 9, When viewed from above, the boundary between the third region and the fourth region is located between the third conductor layer and the first conductor layer, and between the third conductor layer and the second conductor layer.

12. The storage device according to claim 9, further comprising: A fourth conductor layer is disposed between the first conductor layer and the third conductor layer in the first direction; and The fifth conductor layer is disposed between the second conductor layer and the third conductor layer in the first direction.

13. The storage device according to claim 12, The fourth conductive layer is electrically connected to the first region. The fifth conductive layer is electrically connected to the second region.

14. The storage device according to claim 12, When viewed from above, the boundary between the third region and the fourth region is located between the third conductor layer and the fourth conductor layer, and between the third conductor layer and the fifth conductor layer.

15. The storage device according to claim 1, further comprising: A first transistor has a first terminal electrically connected to the first region and a second terminal electrically connected to the third region; and The second transistor has a first terminal electrically connected to the second region and a second terminal electrically connected to the third region.

16. The storage device according to claim 1, further comprising: A first block comprising multiple storage units, wherein the multiple storage units include the first storage unit; and A second block comprising multiple storage units, wherein the multiple storage units include the second storage unit. The first block and the second block are the data erasure units.

17. The storage device according to claim 16, It also includes multiple transistors that are respectively connected to multiple memory cells within the first block. The plurality of transistors are arranged in a second direction that intersects the first direction.

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