Semiconductor device and method of manufacturing the same, storage system

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, and a storage system, and relates to the technical field of semiconductor chips. The semiconductor device comprises at least two semiconductor structures arranged in a stack, and a bonding part arranged between adjacent two semiconductor structures. The semiconductor structure comprises at least two semiconductor units arranged in a stack, and bonding contacts arranged on both sides of the semiconductor units in the stacking direction, wherein the bonding contacts between adjacent two semiconductor units in the same semiconductor structure are connected in contact. In the adjacent two semiconductor structures, the bonding contact in the semiconductor unit close to the second semiconductor structure in the first semiconductor structure is connected with the bonding contact in the semiconductor unit close to the first semiconductor structure in the second semiconductor structure through the bonding part. The semiconductor device is applied in a dynamic random access memory to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method and storage system. Background Technology

[0002] With improvements in process technology, circuit design, and manufacturing processes, dynamic random access memory (DRAM) has been scaled to smaller sizes. However, as the feature size of the semiconductor structure within DRAM approaches its lower limit, planar processes and manufacturing technologies become challenging and costly, causing the density of semiconductor structures to approach its upper limit. Consequently, it becomes difficult to further miniaturize the semiconductor stack structure obtained by stacking multiple semiconductor structures.

[0003] Therefore, how to miniaturize semiconductor stacked structures has become a technical problem that urgently needs to be solved by engineers. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor device, a method for fabricating the same, and a storage system.

[0005] The embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a semiconductor device is provided. The semiconductor device includes at least two stacked semiconductor structures and a bonding portion disposed between two adjacent semiconductor structures. Each semiconductor structure includes at least two stacked semiconductor units, and each semiconductor unit has bonding contacts on both sides in the stacking direction. The bonding contacts between two adjacent semiconductor units located within the same semiconductor structure are in contact with each other. In the two adjacent semiconductor structures, the bonding contacts in the semiconductor unit of the first semiconductor structure closest to the second semiconductor structure are connected to the bonding contacts in the semiconductor unit of the second semiconductor structure closest to the first semiconductor structure via the bonding portion.

[0007] In some embodiments, the dimension of the bonding contact in the stacking direction is smaller than the dimension of the bonding portion in the stacking direction.

[0008] In some embodiments, the semiconductor device further includes an insulating fill layer. The insulating fill layer is disposed between two adjacent semiconductor structures, and the bonding portion is disposed within the insulating fill layer.

[0009] In some embodiments, the semiconductor device further includes an insulating wall. The insulating wall is disposed around at least two stacked semiconductor structures.

[0010] In some embodiments, the semiconductor cell includes a memory layer and a support layer stacked together. The support layer includes a connection portion that extends through the support layer along the stacking direction, with one end of the connection portion connected to the memory layer in the stacking direction and the other end of the connection portion connected to a bonding contact.

[0011] In some embodiments, the memory layer includes a transistor structure layer and a capacitor cell layer. The transistor structure layer is disposed on one side of the support layer along the stacking direction, and the transistor structure layer includes multiple transistor structures. The capacitor cell layer is disposed on one side of the transistor structure layer along the stacking direction, and the capacitor cell layer includes multiple capacitor cells, with each capacitor cell connected to one end of a transistor structure.

[0012] In some embodiments, the memory layer further includes a peripheral device layer. The peripheral device layer is disposed on one side of the memory array layer, which includes the transistor structure layer and the capacitor cell layer, along the stacking direction, and is coupled to the memory array layer.

[0013] In some embodiments, the semiconductor device further includes a logic chip. The logic chip is stacked on one side of at least two stacked semiconductor structures and is bonded to bonding contacts of adjacent semiconductor structures.

[0014] In another aspect, a method for fabricating a semiconductor device is provided. This method includes: forming at least two semiconductor structures, each semiconductor structure comprising at least two stacked semiconductor units, with bonding contacts provided on both sides of each semiconductor unit along the stacking direction. The bonding contacts between adjacent semiconductor units within the same semiconductor structure are connected in contact. A bonding portion is formed on one surface of the semiconductor structure along the stacking direction. The at least two semiconductor structures are stacked, wherein the bonding portion is located between adjacent semiconductor structures, and in the two adjacent semiconductor structures, a bonding contact in a semiconductor unit of the first semiconductor structure near the second semiconductor structure is connected to a bonding contact in a semiconductor unit of the second semiconductor structure near the first semiconductor structure via the bonding portion.

[0015] In some embodiments, forming at least two semiconductor structures includes: forming a stacked structure comprising at least two stacked wafers, each wafer comprising at least two semiconductor units; and dividing the stacked structure to form at least two semiconductor structures.

[0016] In some embodiments, forming a stacked structure includes: forming two wafers. The two wafers are stacked such that the bonding contacts of semiconductor cells on one wafer are in contact with the bonding contacts of semiconductor cells on the other wafer to form the stacked structure.

[0017] In some embodiments, forming a stacked structure includes: forming two wafers, the wafers including a first wafer and a second wafer; dividing the second wafer to obtain at least two semiconductor cells; and stacking the at least two semiconductor cells on one side of the first wafer, such that the bonding contacts of the at least two semiconductor cells are in contact with the bonding contacts of the semiconductor cells of the first wafer to form a stacked structure.

[0018] In some embodiments, the method for fabricating a semiconductor device further includes: forming a first insulating film between two adjacent semiconductor structures, wherein a bonding portion is disposed within the first insulating film; and curing the first insulating film to form an insulating filling layer.

[0019] In some embodiments, the method for fabricating a semiconductor device further includes: forming a second insulating film, the second insulating film surrounding at least two stacked semiconductor structures; and curing the second insulating film to form an insulating wall.

[0020] In another aspect, a storage system is provided, comprising the semiconductor device and controller as described above. The controller is coupled to the semiconductor device to control the semiconductor device to store data. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0022] Figure 1 This is a structural block diagram of an electronic device provided in some embodiments of the present disclosure;

[0023] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this disclosure;

[0024] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in some embodiments of this disclosure;

[0025] Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in some embodiments of the present disclosure;

[0026] Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in some embodiments of the present disclosure;

[0027] Figure 6A structural block diagram of a semiconductor cell provided in some embodiments of this disclosure;

[0028] Figure 7 This is a schematic diagram of the structure of a storage array layer provided in some embodiments of this disclosure;

[0029] Figure 8 This is a structural block diagram of another semiconductor cell provided in some embodiments of the present disclosure;

[0030] Figure 9 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure;

[0031] Figure 10 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure;

[0032] Figure 11 A flowchart illustrating a method for fabricating a stacked structure according to some embodiments of this disclosure;

[0033] Figure 12 To and Figure 11 A schematic diagram of the structure of a wafer corresponding to the preparation method described in the figure;

[0034] Figure 13 To and Figure 11 A schematic diagram of a stacked structure corresponding to the preparation method described in the text;

[0035] Figure 14 A flowchart illustrating a method for preparing another stacked structure according to some embodiments of this disclosure;

[0036] Figure 15 To and Figure 14 A schematic diagram of a stacked structure corresponding to the preparation method described in the text;

[0037] Figure 16 To and Figure 10 A schematic diagram of a stacked structure corresponding to the preparation method described in the text;

[0038] Figure 17 To and Figure 9 A schematic diagram of a semiconductor structure corresponding to the preparation method described in the figure;

[0039] Figure 18 A flowchart illustrating another method for fabricating a semiconductor device according to some embodiments of this disclosure;

[0040] Figure 19 To and Figure 18 A schematic diagram of the structure of a semiconductor device corresponding to the fabrication method described in the figure;

[0041] Figure 20A flowchart illustrating another method for fabricating a semiconductor device according to some embodiments of this disclosure;

[0042] Figure 21 To and Figure 20 The diagram shows the structure of a semiconductor device corresponding to the fabrication method described in the text. Detailed Implementation

[0043] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0046] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0047] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0048] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0049] Figure 1 This is a structural block diagram of an electronic device 9000 provided for some embodiments of this disclosure. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0050] like Figure 1 As shown, the electronic device 9000 may include a storage system 910 and a host 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0051] The host 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SOC), such as an application processor (AP). The host 920 may be configured to send data to or receive data from memory.

[0052] In some embodiments, the storage system 910 may have one or more semiconductor devices 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the semiconductor device 911 and the host 920 and is configured to control data in the semiconductor device 911 while also being able to communicate with external devices (e.g., the host).

[0053] The number of semiconductor devices 911 in the storage system 910 can be one or more. Figure 1The diagram illustrates three semiconductor devices 911 as an example. Controller 912 manages the data stored in each semiconductor device 911 and communicates with host 920. Controller 912 can be configured to control the operation of each semiconductor device 911, such as read, write, and refresh operations. Controller 912 can also be configured to manage various functions related to data stored or to be stored in each semiconductor device 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, controller 912 is also configured to determine the maximum memory capacity usable by the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 912 can also perform any other suitable functions. Controller 912 can communicate with external devices (e.g., host 920) according to specific communication protocols. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0054] As the demand for storage performance in semiconductor devices, such as end products, increases, the integration level of packaged semiconductor devices faces increasingly severe challenges. However, for three-dimensional semiconductor devices, issues such as manufacturing productivity, product yield, product performance, and internal space utilization after packaging all limit the development of high integration, making it difficult to further improve the integration level. Based on this, this disclosure provides a semiconductor device.

[0055] Figure 2 This is a schematic diagram of the structure of a semiconductor device 911 provided in some embodiments of this disclosure.

[0056] in, Figure 2 For illustrative purposes only, and may not actually reflect the actual device structure (e.g., interconnects).

[0057] like Figure 2 As shown, in some embodiments, the semiconductor device 911 includes at least two stacked semiconductor structures 110 and a bonding portion 120 disposed between two adjacent semiconductor structures 110. Each semiconductor structure 110 includes at least two stacked semiconductor units 130, and each semiconductor unit 130 has a bonding contact 131 on both sides in the stacking direction Z.

[0058] For example, the bonding contact 131 may include, for example, a metal contact or a metal pad; the bonding portion 120 may include, for example, a solder ball or a connecting portion that can achieve bonding, and the embodiments disclosed herein do not limit this.

[0059] As a feasible implementation, the following embodiments use the example of bonding contact 131 including pads and bonding portion 120 including solder balls to describe the structure of semiconductor device 911.

[0060] The bonding contact 131 may have a dimension H1 in the stacking direction Z that is smaller than the bonding portion 120 in the stacking direction Z that is smaller than the dimension H2 in the stacking direction Z. Furthermore, the bonding contacts 131 between two adjacent semiconductor units 130 located within the same semiconductor structure 110 may be in contact and connected.

[0061] With this configuration, the bonding contacts 131 that connect two adjacent semiconductor units 130 within the same semiconductor structure 110 can achieve hybrid bonding between the two adjacent semiconductor units 130. Thus, while using the bonding contacts 131 to achieve bonding connection, signal transmission between the two adjacent semiconductor units 130 can also be achieved.

[0062] Hybrid bonding is a direct bonding technique, which means that a bond is formed between two adjacent surfaces without the use of an intermediate layer (such as solder or adhesive), and metal-to-metal bonding and dielectric-to-dielectric bonding can be obtained simultaneously.

[0063] In this embodiment, by using bonding contacts 131 to co-bond two adjacent semiconductor units 130, the size of the stacked semiconductor structure 110 in the Z-direction can be reduced, thereby enabling miniaturization of the semiconductor structure 110. Furthermore, while maintaining the same size of the semiconductor structure 110 in the Z-direction, this arrangement also increases the space for stacking and bonding multiple semiconductor units 130 within the semiconductor structure 110, thereby reducing the operational difficulty of stacking and bonding multiple semiconductor units 130 and improving the heat dissipation capacity of the semiconductor structure 110.

[0064] Furthermore, since the dimension H1 of the bonding contact 131 in the stacking direction Z can be smaller than the dimension H2 of the bonding portion 120 in the stacking direction Z, the hybrid bonding between two adjacent semiconductor units 130 can shorten the data transmission path within the semiconductor structure 110, thereby reducing the power loss of data transmission and improving the storage performance of the semiconductor structure 110 and even the semiconductor device 911.

[0065] In other examples, the dimension of the bonding contact 131 in the direction perpendicular to the stacking direction Z may be smaller than the dimension of the bonding portion 120 in the direction perpendicular to the stacking direction Z. In this case, by using the bonding contact 131 to achieve hybrid bonding between two adjacent semiconductor units 130, the device density (e.g., I / O density) of the bonding contact 131 can be increased, thereby increasing the bandwidth of data transmission, improving the data transmission rate, and reducing the latency of data transmission.

[0066] Furthermore, the hybrid bonding between two adjacent semiconductor units 130 allows for the independent fabrication of multiple semiconductor units 130, meaning that two adjacent semiconductor units 130 can be fabricated independently on different production lines. By fabricating multiple semiconductor units 130 simultaneously, the fabrication efficiency of the semiconductor units 130 can be improved, thereby increasing the fabrication efficiency of the semiconductor device 911.

[0067] Please continue reading. Figure 2 In some implementations, in two adjacent semiconductor structures 110, the bonding contact 131 in the semiconductor unit 130 of the first semiconductor structure 110 that is close to the second semiconductor structure 110 is connected to the bonding contact 131 in the semiconductor unit 130 of the second semiconductor structure 110 that is close to the first semiconductor structure 110 through the bonding portion 120.

[0068] With this configuration, the bonding section 120 can be used to achieve thermal compression bonding (TCB) between two adjacent semiconductor structures 110. In this way, while keeping the size of the semiconductor device 911 in the stacking direction Z unchanged, the number of semiconductor units 130 stacked in each semiconductor structure 110 can be reduced. This avoids the warping of multilayer semiconductor units 130 caused by low single-wafer yield in hybrid bonding, as well as the contamination of impurities (such as dust, small particles, etc.) caused by wafer dicing in hybrid bonding processes, thereby improving the product yield of semiconductor structure 110 and even semiconductor device 911.

[0069] Furthermore, since hybrid bonding is used between multiple semiconductor units 130 within each semiconductor structure 110, the hybrid bonding process can be used to optimize the space of the semiconductor structure 110 in the stacking direction Z while keeping the number of semiconductor structures 110 in the semiconductor device 911 constant. This increases the operating window for thermo-press bonding between two adjacent semiconductor structures 110, thereby reducing the process difficulty of thermo-press bonding and increasing the production rate of the semiconductor device 911.

[0070] Figure 3 This is a schematic diagram of the structure of another semiconductor device 911 provided in some embodiments of the present disclosure. Figure 4 This is a schematic diagram of the structure of another semiconductor device 911 provided in some embodiments of this disclosure.

[0071] In some implementations, when the semiconductor devices 911 have the same height in the stacking direction Z, such as Figure 3 and Figure 4 In the case where the semiconductor device 911 shown includes 12 layers of semiconductor units 130, the number of semiconductor units 130 in the semiconductor structure 110 of different semiconductor devices 911 may be the same or different, and this disclosure does not limit this.

[0072] Figure 5 This is a schematic diagram of the structure of another semiconductor device 911 provided in some embodiments of this disclosure.

[0073] In other implementations, where the height of the semiconductor device 911 differs along the stacking direction Z, for example, as Figure 4 The semiconductor device 911 shown includes 12 layers of semiconductor units 130 and, as shown in the figure, Figure 5 In the case where the semiconductor device 911 shown includes 16 layers of semiconductor units 130, the number of semiconductor units 130 in the semiconductor structure 110 of different semiconductor devices 911 may be the same or different, and this disclosure does not limit this.

[0074] Please continue reading. Figure 2 In some embodiments, the semiconductor device 911 further includes an insulating fill layer 140 and an insulating wall 150. The insulating fill layer 140 is disposed between two adjacent semiconductor structures 110, and the bonding portion 120 is disposed within the insulating fill layer 140. The insulating wall 150 is disposed around at least two stacked semiconductor structures 110.

[0075] In this embodiment, by providing an insulating filling layer 140, the gap between two adjacent semiconductor structures 110 can be filled, thereby providing support for the two adjacent semiconductor structures 110. Furthermore, the insulating filling layer 140 can surround the bonding portion 120, thereby protecting and isolating the bonding portion 120, thereby improving the stability and reliability of the semiconductor structure 110 and the semiconductor device 911 formed by stacking multiple semiconductor structures 110.

[0076] Furthermore, by providing insulating walls 150 around the multiple stacked semiconductor structures 110, protection can be achieved for the semiconductor structures 110 and the multiple semiconductor units 130 within the semiconductor structures 110, thereby improving the stability and reliability of the semiconductor units 130.

[0077] For example, the insulating filler layer 140 and the insulating wall 150 may comprise organic materials such as resin, or any other suitable material, which is not limited in this embodiment. The materials of the insulating filler layer 140 and the insulating wall 150 may be the same or different. When the materials of the insulating filler layer 140 and the insulating wall 150 are the same, the insulating filler layer 140 and the insulating wall 150 may be an integral structure, that is, there is no clear structural boundary between them.

[0078] Please continue reading. Figure 5 In some embodiments, the semiconductor device 911 further includes a logic chip 160. The logic chip 160 is stacked on one side of at least two stacked semiconductor structures 110 and is bonded to the bonding contacts 131 of the adjacent semiconductor structures 110.

[0079] In this embodiment, the logic chip 160 stacked on one side of at least two stacked semiconductor structures 110 can control one or more semiconductor structures 110 within the semiconductor device 911, thereby enabling the semiconductor device 911 to perform data writing, reading, or clearing operations.

[0080] Furthermore, the logic chip 160 can be integrated with the controller 912 via a silicon chip with interconnect capabilities (see [link]). Figure 1 The connection is made so that the controller 912 controls the logic chip 160, thereby controlling one or more semiconductor structures 110 within the semiconductor device 911.

[0081] In some examples, controller 912 (see [link]) Figure 1 This can include CPU, graphics processing unit (GPU), or SoC, etc.

[0082] Figure 6This is a structural block diagram of a semiconductor unit 130 provided for some embodiments of the present disclosure.

[0083] like Figure 6 As shown, semiconductor cell 130 includes a memory array layer 913 and a peripheral device layer 914 for controlling the memory array layer 913. The peripheral device layer 914 may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory array layer 913. For example, the peripheral device layer 914 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0084] For example, the peripheral device layer 914 can use complementary metal-oxide-semiconductor (CMOS) technology, for example, it can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0085] The memory array layer 913 and the peripheral device layer 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory array layer 913 and the peripheral device layer 914 can be located in the same semiconductor structure. Alternatively, the memory array layer 913 and the peripheral device layer 914 can be formed on different wafers and bonded together face-to-face. Figure 6 As shown, when the memory array layer 913 and the peripheral device layer 914 are formed on different wafers and bonded together face-to-face, the semiconductor device 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 may include the memory array layer 913, and the second semiconductor structure 902 may include the peripheral device layer 914.

[0086] The memory array layer 913 may be an array of memory cells using vertical transistors as switches and selection devices. In some embodiments, the memory array layer 913 may be a dynamic random access memory cell array. For ease of description, a DRAM cell array may be used to describe an example of the memory array layer 913 in this disclosure. However, it should be understood that the memory array layer 913 is not limited to a DRAM cell array, and may include any other suitable type of memory array layer 913 that can use vertical transistors as switches and selection devices, such as a PCM cell array, a static random-access memory (SRAM) cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, etc.

[0087] Figure 7 This is a schematic diagram of the structure of a storage array layer 913 provided in some embodiments of this disclosure.

[0088] like Figure 7 As shown, when the storage array layer 913 is a DRAM cell array, the storage array layer 913 may include a transistor structure layer 132 and a capacitor cell layer 133 stacked along the stacking direction Z. The capacitor cell layer 133 is disposed on one side of the transistor structure layer 132 along the stacking direction Z, and the capacitor cell layer 133 may include a plurality of capacitor cells 141.

[0089] In some implementations, a capacitor cell 141 is connected to one end of a transistor structure 142 to form a DRAM cell, wherein the connection may include a direct connection or an indirect connection.

[0090] For example, capacitor cells 141 in a DRAM cell can be used to store data bits as positive or negative charges, and transistor structures 142 can control (e.g., switch and select) access to the DRAM cell. Furthermore, according to some embodiments, the DRAM cell can be refreshed via peripheral device layer 914 to retain data.

[0091] Figure 8 This is a structural block diagram of another semiconductor unit 130 provided in some embodiments of the present disclosure.

[0092] like Figure 8 As shown, in some embodiments, the semiconductor cell 130 may further include a support layer 134, which is disposed along the stacking direction on one side of the memory layer 135, which includes the memory array layer 913 and the peripheral device layer 914.

[0093] In this embodiment, by providing a support layer 134 on one side of the storage layer 135, a semiconductor structure 110 consisting of a single semiconductor unit 130 or multiple semiconductor units 130 stacked together can be constructed (see [link to documentation]). Figure 2 It provides support, thereby ensuring that the semiconductor structure 110 has sufficient strength during preparation, testing and transportation, thereby improving the stability and reliability of the semiconductor structure 110 and even the semiconductor device.

[0094] Please continue reading for more details. Figure 2 The support layer 134 includes a connecting portion 136, which extends through the support layer 134 along the stacking direction Z. One end of the connecting portion 136 in the stacking direction Z is connected to the storage layer 135, and the other end of the connecting portion 136 in the stacking direction Z is connected to the bonding contact 131.

[0095] In this embodiment, by providing a connecting portion 136 extending along the stacking direction Z in the support layer 134, signal transmission within a single semiconductor unit 130 can be achieved while ensuring good stability and reliability of the semiconductor unit 130. Furthermore, by utilizing the connection between the connecting portion 136 and the storage layer 135 and the bonding contact 131, signal transmission between two adjacent semiconductor units 130 can be achieved.

[0096] Based on this, this embodiment can also realize signal transmission between multiple semiconductor structures 110 stacked sequentially in the Z-direction, and between the stacked multiple semiconductor structures 110 and the logic chip 160 (see [link]). Figure 5 The electrical connection between the semiconductor structures 110 and the logic chip 160 is used to control one or more semiconductor structures 110, thereby controlling the semiconductor structures 110 to perform data writing, reading or clearing operations.

[0097] For example, the connection portion 136 may include metal wiring or any other conductive line or conductive contact that can achieve electrical connection. For example, the conductive material of the connection portion 136 may be one or more combinations of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials, which are not limited in this embodiment.

[0098] In practical applications, during the bonding process of two adjacent semiconductor units 130 within the semiconductor structure 110, the orientation of the support layer 134 of the semiconductor unit 130 in the stacking direction is not restricted. That is, after bonding, the support layers 134 of two adjacent semiconductor units 130 may or may not be in contact, and this disclosure embodiment does not impose any restrictions on this.

[0099] Based on the semiconductor device 911 provided in the above embodiments, this disclosure also provides a method for preparing the semiconductor device 911, and the semiconductor device 911 can be prepared by the method for preparing the semiconductor device 911.

[0100] Figure 9 This is a flowchart illustrating a method for fabricating a semiconductor device 911, provided for some embodiments of this disclosure.

[0101] like Figure 9 As shown, in some embodiments, the method for fabricating the semiconductor device 911 includes the following steps S1 to S3.

[0102] S1. Form at least two semiconductor structures, each semiconductor structure comprising at least two stacked semiconductor units, with bonding contacts on both sides of each semiconductor unit in the stacking direction. The bonding contacts between adjacent semiconductor units within the same semiconductor structure are connected.

[0103] Figure 10 A flowchart illustrating a method for fabricating a semiconductor structure 110 according to some embodiments of this disclosure.

[0104] like Figure 10 As shown, in some embodiments, step S1 may further include steps S11 to S12.

[0105] S11. Form a stacked structure, the stacked structure including at least two stacked wafers, each wafer including at least two semiconductor units.

[0106] Figure 11 This is a flowchart illustrating a method for fabricating a stacked structure 300 according to some embodiments of the present disclosure. Figure 12 To and Figure 11 A schematic diagram of the structure of a wafer 200 corresponding to the preparation method described in the figure. Figure 13 To and Figure 11 The preparation method in the diagram corresponds to a stacked structure 300.

[0107] like Figure 11 As shown, in some embodiments, step S11 may include the following steps S111 to S112.

[0108] S111, forming two wafers.

[0109] In some examples, wafer 200 may include a plurality of semiconductor cells 130 arranged in an array, and in this scenario, semiconductor cells 130 may be a single die formed on wafer 200.

[0110] S112. Two wafers are stacked together, and the bonding contacts of the semiconductor units of one wafer are connected to the bonding contacts of the semiconductor units of the other wafer to form a stacked structure.

[0111] like Figure 13 As shown, in step S112, two wafers 200 are stacked, and a hybrid bonding process can be used to achieve bonding connections between two adjacent wafers 200 in the stacking direction Z. Since the semiconductor unit 130 has bonding contacts 131 on both sides of the stacking direction, the hybrid bonding process can achieve contact connections between the bonding contacts 131 of the semiconductor units 130 on the two bonded wafers 200.

[0112] With this configuration, the bonding contacts 131 can be used to bond two adjacent wafers 200 together, while also enabling signal transmission between semiconductor units 130 within the two adjacent wafers 200.

[0113] Furthermore, by using a hybrid bonding process to bond two adjacent wafers 200 together, the height of the stacked structure 300 formed by stack bonding in the stacking direction Z can be reduced. This allows for an increase in the bonding space of multiple wafers 200 within the stacked structure 300 while keeping the height in the stacking direction Z constant. It also reduces the operational difficulty of stacking and bonding multiple wafers 200, thereby increasing the stacking density of the stacked structure 300.

[0114] Furthermore, using a hybrid bonding process to bond two adjacent wafers 200 can shorten the data transmission path between the semiconductor cells 130 within the two wafers 200, thereby increasing transmission bandwidth, improving data transmission rate, reducing data transmission latency, and reducing power loss during data transmission. Moreover, performing bonding at the wafer level reduces the operational difficulty of hybrid bonding, thus avoiding contamination issues (such as dust, small particles, etc.) caused by wafer dicing during die-level bonding.

[0115] Furthermore, the hybrid bonding between two adjacent wafers 200 allows for the independent fabrication of multiple wafers 200, meaning that two adjacent wafers 200 can be fabricated independently on different production lines. By fabricating multiple wafers 200 simultaneously, the fabrication efficiency of the stacked structure 300 can be improved, thereby increasing the fabrication efficiency of the semiconductor device 911.

[0116] In other examples, when there are multiple wafers 200, the fabrication process of multiple wafers 200 can be interspersed with the stacking and bonding process. That is, after stacking any two wafers 200, the fabrication of the next wafer 200 is carried out, and then the next wafer 200 is stacked with the aforementioned two wafers 200, and so on in a cyclical manner.

[0117] In other examples, the preparation steps may be carried out in other reasonable preparation sequences, which are not limited in this disclosure.

[0118] Figure 14 This is a flowchart illustrating a method for fabricating another stacked structure 300 provided in some embodiments of this disclosure. Figure 15 To and Figure 14 The preparation method in the diagram corresponds to a stacked structure 300.

[0119] like Figure 14 As shown, in some other embodiments, step S11 may also include steps S101 to S102.

[0120] S101. Form two wafers, including a first wafer and a second wafer.

[0121] In this step S101, the first wafer 201 (see [link]) Figure 15 ) and second wafer 202 (see Figure 15 Each of these may include multiple semiconductor units 130 arranged in an array (see [link]). Figure 12 Furthermore, in this scenario, the semiconductor unit 130 can also be a single die formed on the first wafer 201 or the second wafer 202.

[0122] S102, Divide the second wafer to obtain at least two semiconductor units.

[0123] like Figure 15 As shown, in this step S102, any of the cutting methods such as laser cutting, tool cutting or etching cutting can be used to cut the second wafer 202 into multiple semiconductor units 130. The second wafer 202 is divided along the cutting path on the second wafer 202 to form at least two semiconductor units 130.

[0124] S103. At least two semiconductor units are stacked on one side of the first wafer, and the bonding contacts of the at least two semiconductor units are made to contact and connect with the bonding contacts of the semiconductor units of the first wafer to form a stacked structure.

[0125] Please continue reading. Figure 15 In this step S103, at least two semiconductor units 130 are stacked on the semiconductor units 130 of the first wafer 201, and a hybrid bonding process is used to achieve bonding connection between two adjacent semiconductor units 130 in the stacking direction Z.

[0126] Since the semiconductor unit 130 has bonding contacts 131 on both sides in the stacking direction, the bonding contacts 131 between the two semiconductor units 130 after bonding can be connected by a hybrid bonding process.

[0127] With this configuration, the semiconductor unit 130 of the first wafer 201 and the semiconductor unit 130 of the second wafer 202 can be bonded together using the bonding contact 131, while signal transmission between two adjacent semiconductor units 130 can also be achieved.

[0128] Furthermore, in this embodiment, the second wafer 202 can be pre-divided to achieve bonding between the bare-die level semiconductor unit 130 and the first wafer 201. This fabrication method avoids the low yield of multilayer stacked structures and wafer warpage issues caused by single-wafer yield problems in scenarios where the first wafer 201 is directly bonded to the second wafer 202, thereby improving the product yield of the stacked structure 300.

[0129] Figure 16 To and Figure 10 The preparation method in the diagram corresponds to a stacked structure 300.

[0130] S12. Divide the stacked structure to form at least two semiconductor structures.

[0131] like Figure 16 As shown, for example, any cutting method such as laser cutting, tool cutting, or etching can be used to cut the stacked structure 300 into multiple semiconductor structures 110 along the first wafer 201 (see [reference]). Figure 15 The dicing channel on the stacked structure 300 is used to divide the stacked structure 300, thereby forming at least two semiconductor structures 110.

[0132] This configuration allows for the fabrication of multiple semiconductor structures 110 in the same fabrication process, thereby reducing the number of dicing operations in the fabrication process, improving the fabrication efficiency of the semiconductor structures 110, and reducing the fabrication cost of the semiconductor structures 110.

[0133] In practical applications, the semiconductor structures 110 prepared by the above two stacked structures 300 methods may have different morphologies. For example, by comparing the flatness of the sidewalls of the prepared semiconductor structures 110, the methods of preparing the above two stacked structures 300 can be distinguished. This disclosure does not limit this aspect.

[0134] Figure 17 To and Figure 9 The preparation method in the diagram shows a schematic diagram of a semiconductor structure 110.

[0135] S2. A bonding portion is formed on one side surface of the semiconductor structure along the stacking direction.

[0136] like Figure 17 As shown, in this step S2, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to deposit conductive material on one side of the semiconductor structure 110 to form the bonding portion 120.

[0137] In one feasible implementation, the bonding portion 120 may exist in the form of solder balls; or, in other implementations, the bonding portion 120 may also exist in other feasible forms, which are not limited in the embodiments disclosed herein.

[0138] For example, the conductive material of the bonding portion 120 may include, but is not limited to, one or more combinations of germanium-tin, nickel, tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials may be used.

[0139] For example, in step S2, the material of the bonding portion 120 may include tin, or a nickel-tin metal compound, or a copper-nickel-tin metal compound, etc. This disclosure does not limit the specific materials used in this embodiment.

[0140] In cases where the conductive material of the bonding portion 120 is a non-metallic material, for example, the material of the bonding portion 120 may include a copper-nickel-tin metal compound, the bonding portion 120 may be prepared in at least one process.

[0141] S3. A configuration of at least two semiconductor structures stacked together, wherein a bonding portion is located between two adjacent semiconductor structures, and in the two adjacent semiconductor structures, a bonding contact in a semiconductor unit of the first semiconductor structure near the second semiconductor structure is connected to a bonding contact in a semiconductor unit of the second semiconductor structure near the first semiconductor structure via the bonding portion.

[0142] In step S3, two semiconductor structures 110 are stacked, and a thermo-press bonding process can be used to achieve bonding connections between two adjacent semiconductor structures 110 in the Z-direction of the stack, to obtain the desired result. Figure 2 The semiconductor device 911 shown is shown.

[0143] For example, thermocompression bonding can be implemented using any suitable process such as non-conductive adhesive film or mass reflow soldering (MR-MUF), and this disclosure does not limit the implementation of such processes.

[0144] Since the semiconductor unit 130 has bonding contacts 131 on both sides in the stacking direction, the bonding contacts 131 between the semiconductor units 130 in the two semiconductor structures 110 after bonding can be connected to the bonding part 120 by using the hot-press bonding process.

[0145] With this configuration, the bonding section 120 can be used to achieve thermo-press bonding of two adjacent semiconductor structures 110, thereby reducing the number of semiconductor units 130 stacked in each semiconductor structure 110. This avoids the warping of multilayer semiconductor units 130 caused by low single-wafer yield when using hybrid bonding, as well as the contamination of impurities (such as dust, small particles, etc.) caused by wafer dicing in the hybrid bonding process, thereby improving the product yield of semiconductor structure 110 and even semiconductor device 911.

[0146] Furthermore, since hybrid bonding is used between multiple semiconductor units 130 within each semiconductor structure 110, the hybrid bonding process can be used to optimize the space of the semiconductor structure 110 in the stacking direction Z while keeping the number of semiconductor structures 110 in the semiconductor device 911 constant. This increases the operation window for thermo-press bonding between two adjacent semiconductor structures 110, thereby reducing the process difficulty of thermo-press bonding and increasing the production rate of the semiconductor device 911.

[0147] Figure 18 This is a flowchart illustrating a method for fabricating another semiconductor device 911 provided in some embodiments of this disclosure. Figure 19 To and Figure 18 The diagram shows the structure of a semiconductor device 911 corresponding to the fabrication method described in the figure.

[0148] like Figure 18 As shown, in some embodiments, the method for fabricating the semiconductor device 911 may further include the following steps S4 to S5.

[0149] S4. A first insulating film is formed between two adjacent semiconductor structures, and the bonding portion is disposed within the first insulating film.

[0150] like Figure 19 As shown, in some examples, in step S4, an insulating solvent can be filled between two adjacent semiconductor structures to form a first insulating film 310. Exemplarily, the insulating solvent can be any suitable solvent, such as an organic material like a resin or a polymer, and this disclosure does not limit the specific application of the embodiments.

[0151] S5. Cure the first insulating film to form an insulating filler layer.

[0152] In step S5, a photocuring process can be used to cure the first insulating film 310. For example, an ultraviolet projector can be used as a light source to irradiate the first insulating film 310, thereby curing it and forming a structure as shown. Figure 2 The insulating filler layer 140 shown is shown.

[0153] In this embodiment, by preparing an insulating filling layer 140, the gap between two adjacent semiconductor structures 110 can be filled, thereby providing support for the two adjacent semiconductor structures 110. Furthermore, the insulating filling layer 140 can surround the bonding portion 120, thereby protecting and isolating the bonding portion 120, thereby improving the stability and reliability of the semiconductor structure 110 and the semiconductor device 911 formed by stacking multiple semiconductor structures 110.

[0154] Figure 20 This is a flowchart illustrating a method for fabricating another semiconductor device 911 provided in some embodiments of this disclosure. Figure 21 To and Figure 20 The diagram shows the structure of a semiconductor device 911 corresponding to the fabrication method described in the figure.

[0155] like Figure 20 As shown, in some embodiments, the method for fabricating the semiconductor device 911 may further include the following steps S6 to S7.

[0156] S6. Form a second insulating film, the second insulating film surrounding at least two stacked semiconductor structures.

[0157] like Figure 21 As shown, in some examples, in step S6, the second insulating film 320 can be formed on the outer surface of the stacked semiconductor structures 110 by any suitable coating method such as direct spraying or scraping, thereby achieving the coverage of the sidewalls of the stacked semiconductor structures 110 by the second insulating film 320. In step S6, the sidewalls can refer to the surfaces of the semiconductor structures 110 other than the surfaces in the stacking direction.

[0158] For example, the insulating solvent may include any suitable solvent such as an organic material like a resin or a polymer material, and this disclosure does not limit the embodiments thereof.

[0159] S7. Cure the second insulating film to form an insulating wall.

[0160] In step S7, a photocuring process can be used to cure the second insulating film 320. For example, an ultraviolet projector can be used as a light source to irradiate the second insulating film 320, thereby curing the second insulating film 320 and forming a film as shown in the image. Figure 2 The insulating wall shown is 150.

[0161] In this embodiment, by preparing an insulating wall 150 around the stacked semiconductor structures 110, the semiconductor structures 110 and the multiple semiconductor units 130 within the semiconductor structures 110 can be protected, thereby improving the stability and reliability of the semiconductor units 130.

[0162] In other embodiments, the insulating filler layer 140 and the insulating wall 150 described above can be prepared in the same preparation process. For example, multiple stacked semiconductor structures 110 are immersed in an organic solvent, so that the organic solvent can cover the sidewalls of the multiple stacked semiconductor structures 110 and fill the gaps between two adjacent semiconductor structures 110.

[0163] A photopolymerization process can be used to cure organic solvents, thereby forming a product such as... Figure 2 The insulating filler layer 140 and the insulating wall 150 are shown. In the case where the insulating filler layer 140 and the insulating wall 150 are made of the same material, the resulting insulating filler layer 140 and insulating wall 150 can be an integral structure.

[0164] Furthermore, the above preparation process is described and analyzed with the example that the semiconductor unit 130 is a bare die on a wafer. In other examples, when the semiconductor unit 130 is another device with storage function, the preparation process of the semiconductor device 911 may be different from the preparation process in the above steps. This disclosure does not limit this process.

[0165] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: At least two stacked semiconductor structures, each semiconductor structure comprising at least two stacked semiconductor units, wherein each semiconductor unit has bonding contacts on both sides in the stacking direction; wherein the bonding contacts between two adjacent semiconductor units located within the same semiconductor structure are in contact connection. A bonding portion is disposed between two adjacent semiconductor structures. In the two adjacent semiconductor structures, the bonding contact in the semiconductor unit of the first semiconductor structure near the second semiconductor structure is connected to the bonding contact in the semiconductor unit of the second semiconductor structure near the first semiconductor structure through the bonding portion.

2. The semiconductor device according to claim 1, characterized in that, The dimension of the bonding contact in the stacking direction is smaller than the dimension of the bonding portion in the stacking direction.

3. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: An insulating filler layer is disposed between two adjacent semiconductor structures, and the bonding portion is disposed within the insulating filler layer.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes: An insulating wall is provided around the at least two stacked semiconductor structures.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor unit includes a memory layer and a support layer stacked together. The support layer includes a connection portion that extends through the support layer along the stacking direction. One end of the connection portion in the stacking direction is connected to the memory layer, and the other end of the connection portion in the stacking direction is connected to the bonding contact.

6. The semiconductor device according to claim 5, characterized in that, The storage layer includes: A transistor structure layer is disposed on one side of the support layer along the stacking direction, and the transistor structure layer includes a plurality of transistor structures; A capacitor cell layer is disposed on one side of the transistor structure layer along the stacking direction. The capacitor cell layer includes a plurality of capacitor cells, and one capacitor cell is connected to one end of the transistor structure.

7. The semiconductor device according to claim 6, characterized in that, The storage layer also includes: A peripheral device layer is disposed on one side of the memory array layer, which includes the transistor structure layer and the capacitor cell layer, along the stacking direction, and the peripheral device layer is coupled to the memory array layer.

8. The semiconductor device according to any one of claims 1-7, characterized in that, The semiconductor device further includes: A logic chip, wherein the logic chip is stacked on one side of the at least two stacked semiconductor structures and is bonded to the bonding contacts of the adjacent semiconductor structures.

9. A method for fabricating a semiconductor device, characterized in that, include: At least two semiconductor structures are formed, each semiconductor structure comprising at least two stacked semiconductor units, each semiconductor unit having bonding contacts on both sides in the stacking direction; wherein the bonding contacts between two adjacent semiconductor units located within the same semiconductor structure are in contact connection. A bonding portion is formed on one side surface of the semiconductor structure along the stacking direction; The semiconductor structures are stacked in a manner in which the bonding portion is located between two adjacent semiconductor structures, and in the two adjacent semiconductor structures, the bonding contact in the semiconductor unit of the first semiconductor structure near the second semiconductor structure is connected to the bonding contact in the semiconductor unit of the second semiconductor structure near the first semiconductor structure through the bonding portion.

10. The preparation method according to claim 9, characterized in that, The formation of at least two semiconductor structures includes: A stacked structure is formed, the stacked structure comprising at least two stacked wafers, each wafer comprising at least two semiconductor units; The stacked structure is divided to form at least two of the semiconductor structures.

11. The preparation method according to claim 10, characterized in that, The formation of the stacked structure includes: Two wafers are formed; The two wafers are stacked such that the bonding contacts of the semiconductor cells of one wafer are in contact with the bonding contacts of the semiconductor cells of the other wafer to form the stacked structure.

12. The preparation method according to claim 10, characterized in that, The formation of the stacked structure includes: Two wafers are formed, the wafers comprising a first wafer and a second wafer; The second wafer is diced to obtain at least two of the semiconductor cells; The at least two semiconductor units are stacked on one side of the first wafer, and the bonding contacts of the at least two semiconductor units are made to contact and connect with the bonding contacts of the semiconductor units of the first wafer to form the stacked structure.

13. The preparation method according to any one of claims 9-12, characterized in that, The preparation method further includes: A first insulating film is formed between two adjacent semiconductor structures, and the bonding portion is disposed within the first insulating film; The first insulating film is cured to form an insulating filler layer.

14. The preparation method according to claim 13, characterized in that, The preparation method further includes: A second insulating film is formed, the second insulating film surrounding at least two of the semiconductor structures stacked together; The second insulating film is cured to form an insulating wall.

15. A storage system, characterized in that, include: A semiconductor device, wherein the semiconductor device is the semiconductor device as described in any one of claims 1-8; A controller coupled to the semiconductor device to control the semiconductor device to store data.

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