Semiconductor structure and method of manufacturing the same, storage system

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof and a storage system, and relates to the technical field of semiconductor chips, aiming to improve the problem that the first conductive structure expands due to heat and diffuses into the isolation layer. The semiconductor structure comprises a substrate, a dielectric layer, a first conductive structure, an isolation layer and a first barrier layer. The dielectric layer is located on one side of the substrate along a first direction. The first conductive structure penetrates at least part of the substrate and part of the dielectric layer, and the first conductive structure has a first surface and a second surface arranged along the first direction, and a first side surface connecting the first surface and the second surface; at least part of the isolation layer is located between the first side surface and the substrate; part of the first barrier layer is located between the first side surface and the isolation layer, and in the direction of the substrate pointing to the dielectric layer, part of the first barrier layer protrudes from the first surface and the isolation layer. In this way, the expanded first conductive structure is also blocked by the protruding part of the first barrier layer, which is conducive to blocking the diffusion of the first conductive structure into the isolation layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] Through-Silicon Vias (TSVs) are a three-dimensional integrated circuit (3D IC) interconnect technology. Structurally, they are characterized by vertically penetrating different layers of the same chip or different chips that make up a stack. These channels are called "through" silicon channels because they effectively penetrate from one layer to another. Compared to traditional two-dimensional layouts, TSVs can significantly shorten signal transmission path lengths, reduce latency, and improve overall system integration and signal transmission efficiency. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0004] The embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor structure is provided, comprising: a substrate, a dielectric layer, a first conductive structure, an isolation layer, and a first barrier layer. The dielectric layer is located on one side of the substrate along a first direction, the first direction being the thickness direction of the substrate. The first conductive structure penetrates at least a portion of the substrate and a portion of the dielectric layer, the first conductive structure having a first surface and a second surface arranged along the first direction, and a first side surface connecting the first surface and the second surface, the first surface being farther away from the substrate than the second surface; at least a portion of the isolation layer is located between the first side surface and the substrate, and the isolation layer is disposed around the first side surface; a portion of the first barrier layer is located between the first side surface and the isolation layer, and in the direction from the substrate to the dielectric layer, the portion of the first barrier layer protrudes beyond the first surface and the isolation layer.

[0006] In some embodiments, in the second direction, a portion of the isolation layer is located between the substrate and the first barrier layer, and a portion of the isolation layer is located between the dielectric layer and the first barrier layer; the second direction intersects the first direction.

[0007] In some embodiments, in the second direction, the isolation layer is located between the substrate and the first barrier layer, and the isolation layer is located on one side of the dielectric layer along the first direction; the second direction intersects the first direction.

[0008] In some embodiments, in the second direction, the isolation layer is located between the substrate and the first barrier layer, and a portion of the dielectric layer is located between the substrate and the barrier layer; the second direction intersects the first direction.

[0009] In some embodiments, the area of ​​the second surface is larger than the area of ​​the first surface.

[0010] In some embodiments, the semiconductor structure further includes: a second conductive structure, a second barrier layer, and a third barrier layer, wherein the second conductive structure and the first conductive structure are stacked together along the first direction; the second barrier layer is disposed around the second conductive structure and connected to the first barrier layer; the third barrier layer is located between the second conductive structure and the first surface and is connected to the first barrier layer, and a portion of the first barrier layer protrudes from the third barrier layer in the direction from the substrate to the dielectric layer.

[0011] In some embodiments, the second barrier layer includes a first sublayer and a second sublayer connected to each other, the second sublayer being disposed around the second conductive structure, the first sublayer being located on one side of the second conductive structure along the first direction, and the first sublayer connecting the first barrier layer and the second sublayer; in the direction from the substrate to the dielectric layer, a portion of the first barrier layer protrudes beyond the first sublayer.

[0012] In some embodiments, a portion of the first barrier layer is located inside the second conductive structure.

[0013] In some embodiments, the material of the first conductive structure and the material of the second conductive structure are the same.

[0014] In some embodiments, the semiconductor structure further includes a fourth barrier layer located on the side of the dielectric layer away from the substrate, and the second barrier layer penetrates the fourth barrier layer.

[0015] In some embodiments, the material of the second barrier layer is different from the material of the fourth barrier layer.

[0016] In some embodiments, the materials of the first barrier layer, the second barrier layer, and the third barrier layer are the same.

[0017] In some embodiments, the second conductive structure has a third surface and a fourth surface arranged along the first direction, the third surface being closer to the first surface than the fourth surface, and the area of ​​the third surface being larger than the area of ​​the first surface.

[0018] In some embodiments, the area of ​​the fourth surface is greater than the area of ​​the third surface.

[0019] On the other hand, a method for fabricating a semiconductor structure is also provided, comprising: providing a substrate; forming a first barrier layer, a first conductive structure, a dielectric layer, and an isolation layer, wherein the dielectric layer is located on one side of the substrate along a first direction, the first direction being the thickness direction of the substrate; the first conductive structure penetrates at least a portion of the substrate and a portion of the dielectric layer; the first conductive structure has a first surface and a second surface arranged along the first direction, and a first side surface connecting the first surface and the second surface; the first surface is farther from the substrate than the second surface; at least a portion of the isolation layer is located between the first side surface and the substrate, and the isolation layer is disposed around the first side surface; a portion of the first barrier layer is located between the first side surface and the isolation layer; and in a direction away from the substrate along the first direction, a portion of the first barrier layer protrudes from the first surface and the isolation layer.

[0020] In some embodiments, forming the first barrier layer, the main body, the dielectric layer, and the isolation layer includes: sequentially forming an isolation material layer, a first barrier material layer, and a conductive pillar penetrating a portion of the substrate on a first side of the substrate along the first direction, wherein the isolation material layer surrounds the first barrier material layer and the first barrier material layer surrounds the conductive pillar; removing a portion of the substrate on a second side of the substrate along the first direction to expose a portion of the isolation material layer; forming a first dielectric layer on the second side; and removing a portion of the first dielectric layer and a portion of the first barrier material layer to form the first barrier layer.

[0021] In some embodiments, forming the first barrier layer further includes removing a portion of the insulating material layer to make the insulating material layer flush with the first barrier layer.

[0022] In some embodiments, forming the first barrier layer further includes: removing a portion of the insulating material layer to form an insulating layer, wherein the first dielectric layer and the first barrier layer have a first gap.

[0023] In some embodiments, removing a portion of the substrate on a second side along the first direction further includes: removing a portion of the isolation material layer to form the isolation layer, wherein a second gap exists between the substrate and the first barrier material layer; forming a first dielectric layer on the second side further includes: forming a portion of the first dielectric layer within the second gap.

[0024] In some embodiments, forming the first barrier layer, the main body, and the dielectric layer further includes removing a portion of the conductive pillars to form the first conductive structure.

[0025] In some embodiments, forming the first barrier layer, the main body, the dielectric layer, and the isolation layer further includes: depositing a dielectric material on the second side; removing a portion of the dielectric material and a portion of the first dielectric layer to form a groove, the groove exposing the first surface, and a portion of the first barrier layer protruding from the bottom of the groove.

[0026] In some embodiments, removing a portion of the first dielectric layer and a portion of the first barrier material layer further includes: removing a portion of the isolation material layer so that the isolation material layer is flush with the first barrier layer; removing a portion of the dielectric material and a portion of the first dielectric layer further includes: removing a portion of the isolation material layer to form the isolation layer.

[0027] In some embodiments, the method further includes: depositing a barrier material within the groove to form a second barrier layer and a third barrier layer, the second barrier layer covering the sidewalls and part of the bottom of the groove, and the third barrier layer covering the first surface; and depositing a conductive material within the groove to form a second conductive structure.

[0028] In another aspect, a storage system is provided, comprising: a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor device to control the semiconductor device to store data. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0030] Figure 1 A block diagram of an electronic device according to some embodiments;

[0031] Figure 2 A block diagram of a memory according to some embodiments;

[0032] Figure 3 This is a schematic diagram of a semiconductor structure according to some embodiments;

[0033] Figure 4 For partial magnification of a semiconductor structure according to some embodiments Figure 1 ;

[0034] Figure 5 For partial magnification of a semiconductor structure according to some embodiments Figure 2 ;

[0035] Figure 6 For partial magnification of a semiconductor structure according to some embodiments Figure 3 ;

[0036] Figure 7 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. Figure 1 ;

[0037] Figure 8 This is a schematic diagram of the structure after the substrate is formed, according to some embodiments;

[0038] Figure 9 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. Figure 2 ;

[0039] Figure 10 This is a schematic diagram of the structure after the conductive pillars are formed, according to some embodiments;

[0040] Figures 11-19 This is a magnified view of a portion of the semiconductor structure during fabrication according to some embodiments;

[0041] Figure 20 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. Figure 3 ;

[0042] Figures 21-26 This is a partial magnified view of the semiconductor structure during fabrication according to some other embodiments;

[0043] Figure 27 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. Figure 4 ;

[0044] Figures 28-34 This is a partial magnified view of the semiconductor structure during fabrication according to some of the embodiments.

[0045] Reference numerals: 9000, Electronic device; 910, Storage system; 911, Memory; 912, Controller; 920, Motherboard; X, First direction; Y, Second direction; 1000, Semiconductor structure; 10, Substrate; 20, Dielectric layer; 30, First conductive structure; 301, First surface; 302, Second surface; 303, First side surface; 40, Isolation layer; 50, First barrier layer; 60, Second conductive structure; 601, Third surface; 602, Second... Four surfaces; 603, second side surface; 70, second barrier layer; 701, first sub-layer; 702, second sub-layer; 80, third barrier layer; 90, fourth barrier layer; 100, isolation material layer; 110, first barrier material layer; 120, conductive pillar; 130, first dielectric layer; 140, groove; 141, sidewall; 142, groove bottom; 150, first gap; 160, second gap; 170, dielectric material; 101, first side; 102, second side. Detailed Implementation

[0046] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0047] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0048] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0049] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0050] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0051] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0052] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0053] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0054] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0055] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0056] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, the difference between the two equalities being less than or equal to 5% of either one.

[0057] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0058] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0059] Figure 1 This is a block diagram of an electronic device according to some embodiments. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, server, in-vehicle equipment, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0060] like Figure 1As shown, the electronic device 9000 may include a storage system 910 and a motherboard 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0061] The motherboard 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The motherboard 920 may be configured to send data to or receive data from memory.

[0062] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the motherboard 920 and is configured to control the memory 911 to store data while also communicating with external devices (e.g., a host computer).

[0063] The number of memories 911 in the storage system 910 can be one or more. Figure 1The diagram uses three memories 911 as an example. The controller 912 manages the data stored in each memory 911 and communicates with the motherboard 920. The controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0064] In some implementations, controller 912 is also configured to determine the maximum memory capacity available to the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 912 may also perform any other suitable functions. Controller 912 can communicate with external devices (e.g., motherboard 920) according to a specific communication protocol. For example, controller 912 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0065] The controller 912 mentioned above may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0066] In this embodiment, the storage system 910 can be integrated into various types of storage devices, and is not limited to the electronic device 9000 in the above embodiment.

[0067] Figure 2 This is a block diagram of a memory according to some embodiments. For example... Figure 2 As shown, memory 911 includes a memory cell array 913 and peripheral circuitry 914 for controlling the memory cell array 913. Peripheral circuitry 914 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 913. For example, peripheral circuitry 914 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0068] For example, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0069] The memory cell array 913 and the peripheral circuitry 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory cell array 913 and the peripheral circuitry 914 can be located in the same semiconductor device. Alternatively, the memory cell array 913 and the peripheral circuitry 914 can be formed on different wafers and bonded together face-to-face. Figure 2 As shown, when the memory cell array 913 and the peripheral circuitry 914 are formed on different wafers and bonded together face-to-face, the memory 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 may include the memory cell array 913, and the second semiconductor structure 902 may include the peripheral circuitry 914.

[0070] This disclosure also provides a semiconductor structure in some embodiments, which in some embodiments can serve as the memory 911 in the above embodiments. In other embodiments, the semiconductor device can be the first semiconductor structure 901 in the above embodiments.

[0071] Figure 3This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 4 For partial magnification of a semiconductor structure according to some embodiments Figure 1 . Figure 5 For partial magnification of a semiconductor structure according to some embodiments Figure 2 . Figure 6 For partial magnification of a semiconductor structure according to some embodiments Figure 3 Please refer to this. Figure 3 , Figure 4 , Figure 5 and Figure 6 The semiconductor structure 1000 includes: a substrate 10, a dielectric layer 20, an isolation layer 40, and a first barrier layer 50.

[0072] Exemplarily, the constituent materials of substrate 10 may include, for example, monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. In some examples, a die may be formed from substrate 10 through a series of semiconductor manufacturing processes to create extremely small circuit structures, followed by dicing. Substrate 10 may be, for example, a wafer. After packaging and testing, the die can be formed into a chip. A chip may include multiple dies. In this embodiment of the disclosure, a die refers to a bare die to be packaged. In this embodiment, semiconductor structure 1000 may be a die or a chip.

[0073] The dielectric layer 20 is located on one side of the substrate 10 along a first direction X, where the first direction X is the thickness direction of the substrate 10. Exemplarily, if there is a circuit structure on the front side of the substrate 10 along the first direction X, the dielectric layer 20 is located on the back side of the substrate 10. The material of the dielectric layer 20 includes an insulating material, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials. The dielectric layer 20 may be a single-layer dielectric layer 20, or it may include multiple dielectric layers 20. For example, in this embodiment, the dielectric layer 20 includes a double-layer dielectric layer 20, where one dielectric layer 20 may be made of silicon nitride and the other dielectric layer 20 may be made of silicon oxide.

[0074] The first conductive structure 30 penetrates at least a portion of the substrate 10 and a portion of the dielectric layer 20. This can be understood as the first conductive structure 30 penetrating a portion of the substrate 10, or the first conductive structure 30 penetrating the entire substrate 10. The first conductive structure 30 penetrates a portion of the dielectric layer 20, and a portion of the first conductive structure 30 is located within the dielectric layer 20.

[0075] The first conductive structure 30 has a first surface 301 and a second surface 302 arranged along a first direction X, and a first side surface 303 connecting the first surface 301 and the second surface 302, wherein the first surface 301 is farther from the substrate 10 than the second surface 302. Figure 3 In this structure, the first surface 301 is the upper surface of the first conductive structure 30, and the second surface 302 is the lower surface of the first conductive structure 30. Exemplarily, the first surface 301 and the second surface 302 can be planar, and the first side surface 303 can be planar or curved. For example, when the first conductive structure 30 is a cylindrical or frustum-shaped structure, the first side surface 303 is curved; when the first conductive structure 30 is a cubic structure, the first side surface 303 consists of multiple connected planar surfaces. Since the first conductive structure 30 penetrates at least a portion of the substrate 10 and a portion of the dielectric layer 20, the first surface 301 is located inside the dielectric layer 20, and the second surface 302 can be located inside the substrate 10, or the second surface 302 can be flush with the lower surface of the substrate 10 (the second surface 302 can be located in the same plane as the lower surface of the substrate 10). Taking the semiconductor structure 1000 as a chip as an example, the first conductive structure 30 can form a through-silicon via (TSV), thereby enabling connection between different layers of the same chip or different chips. For example, when the first conductive structure 30 penetrates a portion of the substrate 10, the first conductive structure 30 can connect different layers of the semiconductor structure 1000; when the first conductive structure 30 penetrates the entire substrate 10, the first conductive structure 30 can be used to connect the semiconductor structure 1000 to other chips. Through the above configuration, vertical interconnection between chips can be achieved, thereby reducing the interconnection length between chips, reducing signal delay, and enabling multiple chips to be stacked together at a higher density, which is beneficial for miniaturizing device integration.

[0076] For example, the constituent materials of the first conductive structure 30 may include conductive materials, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials.

[0077] At least a portion of the insulating layer 40 is located between the first side 303 and the substrate 10. In some examples, a portion of the insulating layer 40 is located between the first side 303 and the substrate 10, and a portion of the insulating layer 40 is located between the first side 303 and the dielectric layer 20. In other examples, all of the insulating layer 40 is located between the first side 303 and the substrate 10. Furthermore, the insulating layer 40 is also disposed around the first side 303, thereby serving to isolate the first conductive structure 30 from the substrate 10.

[0078] For example, the constituent material of the insulating layer 40 may include an insulating material. The insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or may be other suitable insulating materials.

[0079] The first barrier layer 50 is disposed around the first conductive structure 30, and a portion of the first barrier layer 50 is located between the first side surface 303 and the insulating layer 40, in the direction from the substrate 10 to the dielectric layer 20. Figure 3 In the first direction (X) pointing upwards, a portion of the first barrier layer 50 protrudes from the first surface 301 and the isolation layer 40. For example, in Figure 3 In the middle, taking the plane where the second surface 302 is located as the lowest plane, the first barrier layer 50 is higher than the isolation layer 40 and the first conductive structure 30 by a certain amount.

[0080] Taking copper as an example, the first conductive structure 30 is composed of copper. Copper diffuses rapidly in silicon and its oxides, as well as in most of the dielectric layer 20. Furthermore, once copper enters the substrate 10, it exerts a strong trapping effect on the charge carriers in the substrate 10, causing the semiconductor structure 1000 to degrade or even fail. An effective way to prevent copper diffusion is to add a barrier layer between the copper and the dielectric. In this embodiment, this is the first barrier layer 50 located between the first conductive structure 30 and the isolation layer 40. The first barrier layer 50 can prevent copper diffusion at a certain high temperature, and it has good bonding with both the copper and the dielectric, as well as low contact resistance.

[0081] For example, the material of the first barrier layer 50 may include a refractory metal and its nitride, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN).

[0082] With the above configuration, even if the first conductive structure 30 expands due to heat, since part of the first barrier layer 50 protrudes from the first surface 301 and the isolation layer 40 in the direction from the substrate 10 to the dielectric layer 20, and the first barrier layer 50 has a height difference from the first surface 301, and the first barrier layer 50 also has a height difference from the isolation layer 40, the expanded first conductive structure 30 will be blocked by the protruding part of the first barrier layer 50. This is beneficial for the first barrier layer 50 to better prevent the material of the first conductive structure 30 from diffusing into the isolation layer 40, thereby improving the reliability of the semiconductor structure 1000.

[0083] In some embodiments described below, a second direction Y is introduced, which intersects the first direction X. For ease of explanation, in some embodiments of this disclosure, the second direction Y is set to be perpendicular to the first direction X.

[0084] As can be seen from the preceding embodiments, the first barrier layer 50 is composed of a refractory metal, thus the first barrier layer 50 also has conductive properties. In the second direction Y, the first barrier layer 50 is located between the insulating layer 40 and the first conductive structure 30, and the insulating layer 40 is located between the first conductive structure 30 and the substrate 10. Therefore, the insulating layer 40 is located between the first barrier layer 50 and the substrate 10, thereby isolating the first barrier layer 50 from the substrate 10. The following description, in conjunction with... Figure 4 , Figure 5 and Figure 6 The location of the isolation layer 40 will be explained.

[0085] In some embodiments, reference Figure 4 In the second direction Y, part of the isolation layer 40 is located between the substrate 10 and the first barrier layer 50, and part of the isolation layer 40 is located between the dielectric layer 20 and the first barrier layer 50.

[0086] In this embodiment, the isolation layer 40 not only penetrates a portion of the substrate 10, but also a portion of the dielectric layer 20, so that the portion of the isolation layer 40 is located between the dielectric layer 20 and the first barrier layer 50 in the second direction Y, and also between the substrate 10 and the first barrier layer 50. This arrangement helps to mitigate the leakage problem at the edge of the isolation layer 40 caused by process errors between the first barrier layer 50 and the substrate 10, thereby improving the isolation layer 40's ability to isolate the substrate 10 and the first barrier layer 50, and ultimately enhancing the reliability of the semiconductor structure 1000.

[0087] It should be noted that even in the second direction Y, where a portion of the isolation layer 40 is located between the dielectric layer 20 and the first barrier layer 50, the first barrier layer 50 still protrudes from the isolation layer 40 in the direction from the substrate 10 to the dielectric layer 20, and there is still a height difference between the first barrier layer 50 and the isolation layer 40. Therefore, even if the first conductive structure 30 expands due to heat, it will be blocked by the first barrier layer 50, and the material of the first conductive structure 30 cannot diffuse into the isolation layer 40, which is beneficial to improving the stability of the semiconductor structure 1000.

[0088] In other embodiments, reference is made to Figure 5 In the second direction Y, the isolation layer 40 is located between the substrate 10 and the first barrier layer 50, and the isolation layer 40 is located on one side of the dielectric layer 20 along the first direction X.

[0089] In this embodiment, all the isolation layers 40 are located between the substrate 10 and the first barrier layer 50, serving to isolate the first barrier layer 50 from the substrate 10. Furthermore, a dielectric layer 20 is also provided on one side of the isolation layer 40 along the first direction X. The dielectric layer 20 does not extend between the substrate 10 and the first barrier layer 50. Figure 5In the indicated position, the dielectric layer 20 also covers the top of the isolation layer 40. This arrangement helps to improve the leakage problem between the first barrier layer 50 and the substrate 10 at the edge of the isolation layer 40 caused by process errors. The isolation layer 40 isolates the substrate 10 from the first barrier layer 50, and the dielectric layer 20 further isolates the substrate 10 from the first barrier layer 50. The dielectric layer 20 can prevent leakage between the first barrier layer 50 and the substrate 10 at the edge of the isolation layer 40, thereby improving the reliability of the semiconductor structure 1000.

[0090] Furthermore, since the isolation layer 40 is located only between the substrate 10 and the first barrier layer 50, there is a height difference between the first conductive structure 30 and the first barrier layer 50, and the isolation layer 40 also has a height difference with the first barrier layer 50. Moreover, compared to some of the previous embodiments, in this embodiment, the height difference between the isolation layer 40 and the first barrier layer 50 is further increased, which is beneficial for the first barrier layer 50 to prevent the material in the first conductive structure 30 from diffusing into the isolation layer 40, thereby further improving the stability and reliability of the semiconductor structure 1000.

[0091] In other embodiments, such as Figure 6 As shown, in the second direction Y, the isolation layer 40 is located between the substrate 10 and the first barrier layer 50, the isolation layer 40 is located on one side of the dielectric layer 20 along the first direction X, and a portion of the dielectric layer 20 is located between the substrate 10 and the barrier layer.

[0092] In this embodiment, a portion of the dielectric layer 20 extends between the substrate 10 and the first barrier layer 50, and the dielectric layer 20 can contact the isolation layer 40. The dielectric layer 20 and the isolation layer 40 can jointly isolate the first barrier layer 50 from the substrate 10. This arrangement helps to improve the leakage problem at the edge of the isolation layer 40 caused by process errors between the first barrier layer 50 and the substrate 10. The isolation layer 40 and the dielectric layer 20 jointly isolate the substrate 10 from the first barrier layer 50, which improves the isolation effect and thus enhances the reliability of the semiconductor structure 1000.

[0093] Furthermore, since the isolation layer 40 is located only between the substrate 10 and the first barrier layer 50, and part of the first conductive structure 30 is located within the dielectric layer 20, there is a height difference between the first conductive structure 30 and the isolation layer 40. Compared with the previous embodiment where the dielectric layer 20 does not extend to the space between the substrate 10 and the first barrier layer 50, this embodiment further expands the height difference between the first barrier layer 50 and the isolation layer 40. This is beneficial for the first barrier layer 50 to prevent the material in the first conductive structure 30 from diffusing into the isolation layer 40, and further improves the stability and reliability of the semiconductor structure 1000.

[0094] It should be noted that when some embodiments of this disclosure involve height or height difference, the second surface 302 is used as the lowest plane of the semiconductor structure 1000 for description and comparison.

[0095] In some embodiments, reference Figure 3 The area of ​​the second surface 302 is greater than the area of ​​the first surface 301. In this embodiment, when the shape of the first surface 301 and the shape of the second surface 302 are both circular, the radial length of the second surface 302 is greater than the radial length of the first surface 301, so that the area of ​​the second surface 302 is greater than the area of ​​the first surface 301.

[0096] The second surface 302 has a larger area, making it easier to connect with other conductive structures, such as TSVs of other chips. This configuration also helps to improve the process window for connecting the semiconductor structure 1000 with other conductive structures.

[0097] In other embodiments, reference is made to Figure 3 The area of ​​the first surface 301 is greater than the area of ​​the second surface 302. When the shapes of the first surface 301 and the second surface 302 are both circular, the radial length of the first surface 301 is greater than the radial length of the second surface 302, so that the area of ​​the first surface 301 is greater than the area of ​​the second surface 302.

[0098] The larger area of ​​the first surface 301 facilitates connection with other conductive structures, such as TSVs of other chips. This configuration also improves the process window for connecting the semiconductor structure 1000 to other conductive structures.

[0099] In some embodiments, reference Figure 4 , Figure 5 and Figure 6 The semiconductor structure 1000 further includes a second conductive structure 60, a second barrier layer 70, and a third barrier layer 80. The second conductive structure 60 is stacked with the first conductive structure 30 along a first direction X. The second conductive structure 60 may include a third surface 601 and a fourth surface 602 arranged along the first direction X, and a second side surface 603 connecting the third surface 601 and the fourth surface 602. In the first direction X, the third surface 601 is located between the fourth surface 602 and the first surface 301. The second conductive structure 60 penetrates a portion of the dielectric layer 20, thereby being stacked with the first conductive structure 30 along the first direction X. The third surface 601 and a portion of the second side surface 603 of the second conductive structure 60 are located within the dielectric layer 20.

[0100] For example, the material of the second conductive structure 60 may include a conductive material, which may be as described in the above embodiments and will not be repeated here.

[0101] The second barrier layer 70 is disposed around the second conductive structure 60 and connected to the first barrier layer 50. Exemplarily, a portion of the second barrier layer 70 may be disposed around the second side surface 603, and a portion of the second barrier layer 70 may be located on one side of the third surface 601 along the first direction X. The second barrier layer 70 located on the side of the third surface 601 along the first direction X may be connected to the first barrier layer 50.

[0102] The third barrier layer 80 is located between the second conductive structure 60 and the first surface 301, that is, the third barrier layer 80 is located between the third surface 601 and the first surface 301. Furthermore, the third barrier layer 80 is connected to the first barrier layer 50. The second barrier layer 70 and the third barrier layer 80 together prevent the material of the second conductive structure 60 from diffusing into the dielectric layer 20.

[0103] Since the function of the second barrier layer 70 and the third barrier layer 80 is to prevent the material in the second conductive structure 60 from diffusing into the dielectric layer 20, the materials of the second barrier layer 70 and the third barrier layer 80 can also be refractory metals, such as tantalum or tantalum nitride. In some examples, the materials of the first barrier layer 50, the second barrier layer 70, and the third barrier layer 80 are the same. This arrangement is more conducive to the connection between the second barrier layer 70 and the first barrier layer 50, and the connection between the third barrier layer 80 and the first barrier layer 50.

[0104] In this embodiment, in the direction from the substrate 10 to the dielectric layer 20, a portion of the first barrier layer 50 protrudes beyond the third barrier layer 80. The top of the first barrier layer 50 is higher than the third barrier layer 80, and the first barrier layer 50 can be disposed around the third barrier layer 80. With this arrangement, even if the first conductive structure 30 expands due to heat, because a portion of the first barrier layer 50 protrudes beyond the third barrier layer 80 in the direction from the substrate 10 to the dielectric layer 20, and the third barrier layer 80 covers the first surface 301, the expanded first conductive structure 30 is difficult to squeeze out from the connection between the first barrier layer 50 and the third barrier layer 80, and even more difficult to contact the connection between the first barrier layer 50 and the second barrier layer 70. This helps the first barrier layer 50 better prevent the first conductive structure 30 from diffusing into the isolation layer 40, thereby improving the reliability of the semiconductor structure 1000.

[0105] In some embodiments, reference Figure 4 , Figure 5 and Figure 6 The second barrier layer 70 includes a first sub-layer 701 and a second sub-layer 702 connected to each other. The second sub-layer 702 is disposed around the second conductive structure 60. The first sub-layer 701 is located on one side of the second conductive structure 60 along the first direction X, and the first sub-layer 701 is connected to the first barrier layer 50 and the second sub-layer 702.

[0106] For example, the first sublayer 701 may be located between the second side 603 and the dielectric layer 20, and the first sublayer 701 may surround the second side 603. The first sublayer 701 may be located on one side of the third surface 601 along the first direction X. The first sublayer 701 is in contact with the first barrier layer 50.

[0107] In this embodiment, the material of the first sub-layer 701 can be the same as the material of the second sub-layer 702. The first sub-layer 701 and the second sub-layer 702 can be integrally molded, which means forming a complete structure in one process.

[0108] With the above configuration, the second barrier layer 70 can cover all surfaces of the second conductive layer located within the dielectric layer 20, thereby preventing the material of the second conductive layer from diffusing into the dielectric layer 20, thus improving the reliability of the semiconductor structure 1000.

[0109] In this embodiment, in the direction from the substrate 10 to the dielectric layer 20, a portion of the first barrier layer 50 protrudes beyond the first sub-layer 701. That is, in the first direction X, the first barrier layer 50 is higher than the first sub-layer 701. The first sub-layer 701 is in contact with the sidewall of the first barrier layer 50, but not with the top of the first barrier layer 50, and there is a height difference between the first sub-layer 701 and the top of the first barrier layer 50. With the above arrangement, even if the first conductive structure 30 expands due to heat, it cannot contact the connection between the first barrier layer 50 and the first sub-layer 701, nor will it be squeezed out at the connection between the first barrier layer 50 and the first sub-layer 701. This helps to better prevent the first conductive structure 30 from diffusing into the isolation layer 40, thereby improving the reliability of the semiconductor structure 1000.

[0110] In some embodiments, reference Figure 4 , Figure 5 and Figure 6 A portion of the first barrier layer 50 is located inside the second conductive structure 60. This can be understood as the first barrier layer 50 penetrating a portion of the second conductive structure 60, thus allowing the portion of the first barrier layer 50 to be located inside the second conductive structure 60.

[0111] The first conductive structure 30 and the second conductive structure 60 are electrically connected through the first barrier layer 50 and the third barrier layer 80. Since part of the first barrier layer 50 is located inside the second conductive structure 60, it is beneficial to improve the stability of the electrical connection between the first conductive structure 30 and the second conductive structure 60, and also beneficial to improve the structural stability of the first conductive structure 30 and the second conductive structure 60.

[0112] In some embodiments, reference Figure 4 , Figure 5 and Figure 6The materials of the first conductive structure 30 and the second conductive structure 60 are the same. Since the first conductive structure 30 and the second conductive structure 60 are made of the same material, such as copper, and the functions of the first barrier layer 50, the second barrier layer 70, and the third barrier layer 80 are all to prevent the same material from diffusing into the dielectric material, the first barrier layer 50, the second barrier layer 70, and the third barrier layer 80 can also be made of the same material. The same material can be formed using the same process, thus allowing fabrication using existing processes without the need for additional processes, which simplifies the fabrication of the semiconductor structure 1000.

[0113] The above settings help simplify the fabrication process and material preparation of the semiconductor structure 1000, as well as control costs and improve the fabrication efficiency of the semiconductor structure 1000.

[0114] In some embodiments, reference Figure 4 , Figure 5 and Figure 6 The semiconductor structure 1000 further includes a fourth barrier layer 90. The fourth barrier layer 90 is located on the side of the dielectric layer 20 away from the substrate 10, i.e., the dielectric layer 20 is located between the fourth barrier layer 90 and the substrate 10. The fourth barrier layer 90 covers the surface of the dielectric layer 20, and the second barrier layer 70 penetrates the fourth barrier layer 90. With this configuration, even if the second conductive structure 60 is extruded upwards, it will be blocked by the fourth barrier layer 90, preventing the material of the second conductive structure 60 from diffusing into the dielectric layer 20, thereby improving the reliability of the semiconductor structure 1000.

[0115] In some embodiments, reference Figure 4 , Figure 5 and Figure 6 The material of the second barrier layer 70 is different from the material of the fourth barrier layer 90. For example, the material of the second barrier layer 70 may include tantalum or tantalum nitride, and the material of the fourth barrier layer 90 may include silicon carbide. Silicon carbide is easy to fabricate into thin films, and it is a semiconductor material that does not conduct electricity under normal conditions.

[0116] The fourth barrier layer 90 is used to prevent the material of the second conductive structure 60 from diffusing into the dielectric layer 20, and does not need to have a conductive function. The second barrier layer 70 can be in contact with the second conductive structure 60 and is connected to the first barrier layer 50. The second barrier layer 70 can have a conductive function, thereby improving the stability of the electrical connection between the first conductive structure 30 and the second conductive structure 60. Therefore, the material of the fourth barrier layer 90 can be different from the material of the second barrier layer 70. This reduces the use of metal materials and helps control the fabrication cost of the semiconductor structure 1000.

[0117] In some embodiments, reference Figure 4 , Figure 5 and Figure 6 The materials of the first barrier layer 50, the second barrier layer 70, and the third barrier layer 80 are the same. For example, the materials of the first barrier layer 50, the second barrier layer 70, and the third barrier layer 80 all include conductive materials, as described in the above embodiments, and will not be repeated here.

[0118] Since the second barrier layer 70, the first barrier layer 50, and the third barrier layer 80 are used to connect the first conductive structure 30 and the second conductive structure 60, and need to have conductive properties, they can be made of the same material. The same material can be formed using the same process.

[0119] The above settings help simplify the fabrication process and material preparation of the semiconductor structure 1000, as well as control costs and improve the fabrication efficiency of the semiconductor structure 1000.

[0120] Furthermore, the first barrier layer 50, the second barrier layer 70, and the third barrier layer 80 can be made of the same material, while the fourth barrier layer 90 can be made of a different material than the first barrier layer 50, the second barrier layer 70, and the third barrier layer 80. This reduces the amount of metal material used and helps control the fabrication cost of the semiconductor structure 1000.

[0121] In some embodiments, reference Figure 4 , Figure 5 and Figure 6 The area of ​​the third surface 601 is greater than the area of ​​the first surface 301. When the shape of the third surface 601 is circular and the shape of the first surface 301 is also circular, the radial length of the third surface 601 is greater than the radial length of the first surface 301.

[0122] The above arrangement facilitates the extension of a portion of the first barrier layer 50 into the interior of the second conductive structure 60, which helps to prevent the first conductive structure 30 from diffusing into the isolation layer 40. Furthermore, the area of ​​the third surface 601 is larger than the area of ​​the first surface 301, which increases the contact area between the third surface 601 and the first barrier layer 50, as well as the contact area between the third surface 601 and the third barrier layer 80, thereby improving the stability of the electrical connection between the second conductive structure 60 and the first conductive structure 30.

[0123] In some embodiments, the area of ​​the fourth surface 602 is greater than the area of ​​the third surface 601. In this embodiment, when both the shape of the third surface 601 and the shape of the fourth surface 602 are circular, the radial length of the fourth surface 602 is greater than the radial length of the third surface 601.

[0124] In this embodiment, the area of ​​the third surface 601 is larger than the area of ​​the first surface 301, and the area of ​​the fourth surface 602 is larger than the area of ​​the third surface 601, which facilitates the connection of the semiconductor structure 1000 with other conductive structures, such as the TSVs of other chips. This arrangement also helps to further improve the process window for connecting the semiconductor structure 1000 with other conductive structures.

[0125] This disclosure also provides a method for fabricating a semiconductor structure 1000, which is described below in conjunction with some embodiments. Figures 7 to 34 The fabrication method of semiconductor structure 1000 is explained.

[0126] Figure 7 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. Figure 1 .like Figure 7 As shown, the method for fabricating the semiconductor structure 1000 includes: S1 to S2.

[0127] S1, Provide the base.

[0128] In this step, refer to Figure 8 The substrate 10 may be composed of materials such as monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. In some examples, the substrate 10 may be formed into extremely small circuit structures along one side of the first direction X through a series of semiconductor manufacturing processes.

[0129] S2. A first barrier layer, a first conductive structure, a dielectric layer, and an isolation layer are formed. The dielectric layer is located on one side of the substrate along a first direction, which is the thickness direction of the substrate. The first conductive structure penetrates at least a portion of the substrate and a portion of the dielectric layer. The first conductive structure has a first surface and a second surface arranged along the first direction, and a first side surface connecting the first surface and the second surface. The first surface is farther from the substrate than the second surface. At least a portion of the isolation layer is located between the first side surface and the substrate, and the isolation layer is disposed around the first side surface. A portion of the first barrier layer is located between the first side surface and the isolation layer. In the direction away from the substrate along the first direction, a portion of the first barrier layer protrudes from the first surface and the isolation layer.

[0130] Some embodiments of this disclosure are combined with Figures 9 to 34 Three feasible implementations are provided for step S2.

[0131] Figure 9 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. Figure 2 In some embodiments, reference is made to Figure 9 The preparation method in this step includes: S201~S209.

[0132] S201. On a first side of the substrate along a first direction, an isolation material layer, a first barrier material layer, and a conductive pillar are sequentially formed, penetrating a portion of the substrate. The isolation material layer surrounds the first barrier material layer, and the first barrier material layer surrounds the conductive pillar.

[0133] In this step, refer to Figure 10 On the first side 101 of the substrate 10 along the first direction X, an etching process can be used to remove a portion of the substrate 10, thereby forming a structural hole. The etching process includes wet etching or dry etching. After forming the structural hole, a thin film deposition process can be used to sequentially deposit an insulating material, a refractory metal material, and a conductive material within the structural hole, thereby sequentially forming an insulating material layer 100, a first barrier material layer 110, and a conductive pillar 120 penetrating a portion of the substrate 10. The thin film deposition process includes any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).

[0134] For example, the insulating material may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials. Refractory metal materials may include tantalum and its nitrides. Conductive materials may include, but are not limited to, one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or other suitable conductive materials.

[0135] S202. On the second side of the substrate along the first direction, a portion of the substrate is removed to expose a portion of the insulating material layer.

[0136] In this step, refer to Figure 11 and Figure 12 A wet etching process or a dry etching process can be used to remove a portion of the substrate 10 on the second side 102 along the first direction X, thereby exposing a portion of the isolation material layer 100 on the second side 102. It should be noted that the first side 101 and the second side 102 are respectively two sides of the substrate 10 disposed opposite to each other along the first direction X.

[0137] S203, A first dielectric layer is formed on the second side.

[0138] In this step, refer to Figure 12 and Figure 13 A first dielectric layer 130 can be formed by depositing a dielectric material on the second side 102 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD.

[0139] For example, the dielectric material may include silicon oxide or silicon nitride. Since some portions of the isolation material layer 100 need to be selectively removed in subsequent steps, the etching rates of the materials of the isolation material layer 100 and the first dielectric layer 130 are different. Therefore, different materials can be used to prepare the isolation material layer 100 and the first dielectric layer 130 respectively. For example, silicon oxide can be chosen as the material for preparing the isolation material layer 100, and silicon nitride can be chosen as the material for preparing the first dielectric layer 130 in this step.

[0140] S204. Remove a portion of the first dielectric layer, a portion of the first barrier material layer, and a portion of the isolation material layer to form a first barrier layer, and make the isolation material layer flush with the first barrier layer.

[0141] In this step, refer to Figure 13 and Figure 14 On the second side 102, a portion of the first dielectric layer 130, a portion of the first barrier material layer 110, and a portion of the insulating material layer 100 can be removed by chemical mechanical polishing (CMP) to planarize the surface of the second side 102. For example, the upper surfaces of the first dielectric layer 130, the first barrier material layer 110, the insulating material layer 100, and the conductive pillar 120 can be flush, thereby exposing the conductive pillar 120 on the second side 102. In this step, the first barrier material layer 110 that is not removed constitutes the first barrier layer 50.

[0142] S205. Remove part of the conductive pillars to form the first conductive structure.

[0143] In this step, continue to refer to Figure 13 and Figure 14 A portion of the conductive pillars 120 can be removed using either wet or dry etching processes to form the first conductive structure 30. (Reference) Figure 13 , Figure 14 and combined Figure 3 The first conductive structure 30 has a first surface 301 and a second surface 302 arranged along a first direction X, and a first side surface 303 connecting the first surface 301 and the second surface 302. The first surface 301 is farther away from the substrate 10 than the second surface 302. In the first direction X, the first conductive structure 30 is recessed within the first barrier layer 50. That is, in the direction from the substrate 10 to the first dielectric layer 130, a portion of the first barrier layer 50 protrudes from the first surface 301 of the first conductive structure 30.

[0144] S206, deposited medium material on the second side.

[0145] In this step, refer to Figure 14 , Figure 15 , Figure 16 and Figure 17 The dielectric material 170 can be deposited once or multiple times on the second side 102 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. In this embodiment, a two-stage deposition of the dielectric material 170 is taken as an example. (Refer to...) Figure 14 and Figure 15 When depositing the medium material 170 for the first time, the constituent material can be the same as that of the first medium layer 130, such as silicon nitride. When depositing the medium material 170 for the second time, a constituent material different from that of the first medium layer 130 can be selected, such as silicon oxide.

[0146] In some other embodiments, more depositions may be performed, or only one deposition may be performed; this disclosure does not limit the number of depositions of the dielectric material 170. In some other embodiments, the dielectric material 170 used in each deposition may be the same or different.

[0147] In this step, after the deposition process, the upper surface of the media material 170 can also be polished using CMP process to make the upper surface flat, which makes it easier to continue deposition to form other thin film structures.

[0148] In this step, a dielectric material 170 of a certain thickness is formed on the second side 102 by a deposition process, which facilitates the formation of the second conductive structure 60 on the first conductive structure 30.

[0149] In other embodiments, reference is made to Figure 17 and Figure 18 After depositing the dielectric material 170 on the second side 102, silicon carbide material can be deposited on the dielectric material 170 to form a fourth barrier layer 90.

[0150] S207. Remove part of the dielectric material, part of the first dielectric layer and part of the isolation material layer to form a groove and an isolation layer, the groove exposing the first surface and part of the first barrier layer protruding from the bottom of the groove.

[0151] In this step, refer to Figure 17 , Figure 18 and Figure 19 The groove 140 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed over the dielectric material 170 (or the fourth barrier layer 90). The patterned photoresist layer can expose the portion of the dielectric material 170 used to form the groove 140. A suitable etching process can be performed to remove portions of the dielectric material 170, portions of the first dielectric layer 130, and portions of the isolation material layer 100 used to form the groove 140. For example, the etching process can include a dry etching process.

[0152] After the groove 140 is formed, the groove 140 can expose the first surface 301 of the first conductive structure 30. It can also be understood that the first surface 301 of the first conductive structure 30 constitutes part of the bottom 142 of the groove 140. In the direction from the substrate 10 to the first dielectric layer 130, part of the first barrier layer 50 protrudes from the bottom 142 of the groove 140, that is, part of the first barrier layer 50 protrudes from the first surface 301.

[0153] S208. Deposit barrier material in the groove to form a second barrier layer and a third barrier layer, wherein the second barrier layer covers the sidewalls and part of the bottom of the groove, and the third barrier layer covers the first surface.

[0154] In this step, refer to Figure 19 and Figure 4 After the groove 140 is formed, a barrier material, such as tantalum and its nitride, can be deposited in the groove 140 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a second barrier layer 70 and a third barrier layer 80. The second barrier layer 70 covers the sidewall 141 and part of the bottom 142 of the groove 140, and the third barrier layer 80 covers the first surface 301.

[0155] In this step, the materials used to prepare the second barrier layer 70 and the third barrier layer 80 can be the same, so that the steps of preparing the second barrier layer 70 and the third barrier layer 80 can be combined. The second barrier layer 70 and the third barrier layer 80 can be formed in a single thin film deposition process, which helps to reduce process steps, control costs, and improve the fabrication efficiency of the semiconductor structure 1000.

[0156] S209. Deposit conductive material in the groove to form a second conductive structure.

[0157] In this step, refer to Figure 19 and Figure 4 After the second barrier layer 70 and the third barrier layer 80 are formed, conductive material, such as copper, can be deposited in the groove 140 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a second conductive structure 60. The second conductive structure 60 is electrically connected to the first conductive structure 30 through the first barrier layer 50, the second barrier layer 70, and the third barrier layer 80. The first dielectric layer 130 and the deposited dielectric material 170 together constitute the dielectric layer 20.

[0158] Even if the first conductive structure 30 of the semiconductor structure 1000 prepared by the above preparation method expands due to heat, the first barrier layer 50 protrudes from the first surface 301 and the isolation layer 40 in the direction from the substrate 10 to the dielectric layer 20. Therefore, the expanded first conductive structure 30 will be blocked by the protruding part of the first barrier layer 50, which helps to better prevent the first conductive structure 30 from diffusing into the isolation layer 40, thereby improving the reliability of the semiconductor structure 1000.

[0159] Figure 20 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments. Figure 3 In other embodiments, reference is made to... Figure 20 The preparation method in this step includes: S210~S218.

[0160] S210. On a first side of the substrate along a first direction, an isolation material layer, a first barrier material layer, and a conductive pillar are sequentially formed, penetrating a portion of the substrate. The isolation material layer surrounds the first barrier material layer, and the first barrier material layer surrounds the conductive pillar.

[0161] In this step, refer to Figure 10 On the first side 101 of the substrate 10 along the first direction X, an etching process can be used to remove a portion of the substrate 10, thereby forming a structural hole. The etching process includes wet etching or dry etching. After forming the structural hole, an insulating material, a refractory metal material, and a conductive material can be sequentially deposited in the structural hole using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, thereby sequentially forming an insulating material layer 100, a first barrier material layer 110, and a conductive pillar 120 penetrating a portion of the substrate 10.

[0162] The insulating materials, refractory metal materials, and conductive materials are as described in the above embodiments and will not be repeated here.

[0163] S211. On the second side of the substrate along the first direction, a portion of the substrate is removed to expose a portion of the insulating material layer.

[0164] In this step, refer to Figure 11 and Figure 12 A wet etching process or a dry etching process can be used to remove part of the substrate 10 on the second side 102 along the first direction X, thereby exposing part of the isolation material layer 100 on the second side 102.

[0165] S212, A first dielectric layer is formed on the second side.

[0166] In this step, refer to Figure 12 and Figure 13A first dielectric layer 130 can be formed by depositing a dielectric material on the second side 102 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD.

[0167] S213. Remove a portion of the first dielectric layer, a portion of the first barrier material layer, and a portion of the isolation material layer to form a first barrier layer and an isolation layer, wherein a first gap exists between the first dielectric layer and the first barrier layer.

[0168] In this step, refer to Figure 13 and Figure 14 On the second side 102, part of the first dielectric layer 130, part of the first barrier material layer 110 and part of the isolation material layer 100 can be removed by chemical mechanical polishing to flatten the surface of the second side 102, for example, to make the upper surfaces of the first dielectric layer 130, the first barrier material layer 110, the isolation material layer 100 and the conductive post 120 flush, thereby exposing the conductive post 120 on the second side 102.

[0169] In this step, the first barrier material layer 110 that has not been removed constitutes the first barrier layer 50.

[0170] Continue to refer to Figure 13 and combined Figure 21 Further wet or dry etching processes can be used to remove a portion of the isolation material layer 100 located between the first dielectric layer 130 and the first barrier layer 50 to form the isolation layer 40. A first gap 150 is then created between the first dielectric layer 130 and the first barrier layer 50. Thus, in the first direction X, the isolation layer 40 is recessed within the first barrier layer 50. That is, in the direction from the substrate 10 to the first dielectric layer 130, the first barrier layer 50 protrudes from the isolation layer 40.

[0171] S214. Remove part of the conductive pillars to form a first conductive structure.

[0172] In this step, continue to refer to Figure 13 and combined Figure 21 A portion of the conductive pillars 120 can be removed using either wet or dry etching processes to form the first conductive structure 30. (Reference) Figure 13 , Figure 21 and combined Figure 4The first conductive structure 30 has a first surface 301 and a second surface 302 arranged along a first direction X, and a first side surface 303 connecting the first surface 301 and the second surface 302. The first surface 301 is farther away from the substrate 10 than the second surface 302. In the first direction X, both the first conductive structure 30 and the insulating layer 40 are recessed within the first barrier layer 50. That is, in the direction from the substrate 10 to the first dielectric layer 130, a portion of the first barrier layer 50 protrudes from the first surface 301 of the first conductive structure 30, and a portion of the first barrier layer 50 protrudes from the insulating layer 40.

[0173] S215, deposited medium material on the second side.

[0174] In this step, refer to Figure 21 , Figure 22 , Figure 23 and Figure 24 The dielectric material 170 can be deposited once or multiple times on the second side 102 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. Furthermore, the dielectric material 170 also fills the first gap 150.

[0175] In this embodiment, taking the double-deposited medium material 170 as an example, refer to... Figure 22 and Figure 23 When depositing the medium material 170 for the first time, the constituent material can be the same as that of the first medium layer 130, such as silicon nitride. When depositing the medium material 170 for the second time, a constituent material different from that of the first medium layer 130 can be selected, such as silicon oxide.

[0176] In this step, after the deposition process, the upper surface of the dielectric material 170 can be polished using CMP process to make the upper surface flat, which makes it easier to continue deposition to form other thin film structures, such as continuing to deposit to form the fourth barrier layer 90.

[0177] In this step, a dielectric material 170 of a certain thickness is formed on the second side 102 by a deposition process, which facilitates the formation of the second conductive structure 60 on the first conductive structure 30.

[0178] S216. Remove part of the dielectric material and part of the first dielectric layer to form a groove, the groove exposing the first surface, and part of the first barrier layer protruding from the bottom of the groove.

[0179] In this step, refer to Figure 25 and Figure 26The groove 140 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed over the dielectric material 170 (or the fourth barrier layer 90). The patterned photoresist layer can expose the portion of the dielectric material 170 used to form the groove 140. A suitable etching process can be performed to remove portions of the dielectric material 170, portions of the first dielectric layer 130, and portions of the isolation material layer 100 used to form the groove 140. For example, the etching process can include a dry etching process.

[0180] After the groove 140 is formed, the groove 140 can expose the first surface 301 of the first conductive structure 30. It can also be understood that the first surface 301 of the first conductive structure 30 constitutes part of the bottom 142 of the groove 140. In the direction from the substrate 10 to the first dielectric layer 130, part of the first barrier layer 50 protrudes from the bottom 142 of the groove 140, that is, part of the first barrier layer 50 protrudes from the first surface 301.

[0181] S217. Deposit barrier material in the groove to form a second barrier layer and a third barrier layer, wherein the second barrier layer covers the sidewall and part of the bottom of the groove, and the third barrier layer covers the first surface.

[0182] In this step, refer to Figure 26 and Figure 5 After the groove 140 is formed, a barrier material, such as tantalum and its nitride, can be deposited in the groove 140 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a second barrier layer 70 and a third barrier layer 80. The second barrier layer 70 covers the sidewall 141 and part of the bottom 142 of the groove 140, and the third barrier layer 80 covers the first surface 301.

[0183] In this step, the materials used to prepare the second barrier layer 70 and the third barrier layer 80 can be the same, so that the steps of preparing the second barrier layer 70 and the third barrier layer 80 can be combined. The second barrier layer 70 and the third barrier layer 80 can be formed in a single thin film deposition process, which helps to reduce process steps, control costs, and improve the fabrication efficiency of the semiconductor structure 1000.

[0184] S218. Deposit conductive material in the groove to form a second conductive structure.

[0185] In this step, refer to Figure 26 and Figure 5After the second barrier layer 70 and the third barrier layer 80 are formed, conductive material, such as copper, can be deposited in the groove 140 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a second conductive structure 60. The second conductive structure 60 is electrically connected to the first conductive structure 30 through the first barrier layer 50, the second barrier layer 70, and the third barrier layer 80. The first dielectric layer 130 and the deposited dielectric material 170 together constitute the dielectric layer 20.

[0186] In the semiconductor structure 1000 prepared in this embodiment, a first barrier layer 50 protrudes from the first conductive structure 30 in the direction from the substrate 10 to the dielectric layer 20, with a height difference between the first barrier layer 50 and the first conductive structure 30. A second barrier layer 70 protrudes from the isolation layer 40, also with a height difference between the second barrier layer 70 and the isolation layer 40. Even if the first conductive structure 30 expands due to heat, the first barrier layer 50 can prevent the material in the first conductive structure 30 from diffusing into the isolation layer 40, further improving the stability and reliability of the semiconductor structure 1000.

[0187] Figure 27 This is a flowchart of a method for fabricating a semiconductor structure 1000 according to some embodiments. Figure 4 In other embodiments, reference is made to... Figure 27 The preparation method in this step includes: S220~S229.

[0188] S220. On a first side of the substrate along a first direction, an isolation material layer, a first barrier material layer, and a conductive pillar are sequentially formed, penetrating a portion of the substrate. The isolation material layer surrounds the first barrier material layer, and the first barrier material layer surrounds the conductive pillar.

[0189] In this step, refer to Figure 10 On the first side 101 of the substrate 10 along the first direction X, an etching process can be used to remove a portion of the substrate 10, thereby forming a structural hole. The etching process includes wet etching or dry etching. After forming the structural hole, an insulating material, a refractory metal material, and a conductive material can be sequentially deposited in the structural hole using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, thereby sequentially forming an insulating material layer 100, a first barrier material layer 110, and a conductive pillar 120 penetrating a portion of the substrate 10.

[0190] The insulating materials, refractory metal materials, and conductive materials are as described in the above embodiments and will not be repeated here.

[0191] S221. On the second side of the substrate along the first direction, a portion of the substrate is removed to expose a portion of the insulating material layer.

[0192] In this step, refer to Figure 11and Figure 12 A wet etching process or a dry etching process can be used to remove part of the substrate 10 on the second side 102 along the first direction X, thereby exposing part of the isolation material layer 100 on the second side 102.

[0193] S222, Remove part of the isolation material layer to form an isolation layer, with a second gap between the substrate and the first barrier material layer.

[0194] In this step, refer to Figure 12 and Figure 28 A wet etching process or a dry etching process is used to remove part of the isolation material layer 100 to form an isolation layer 40. Furthermore, a second gap 160 is created between the substrate 10 and the first barrier material layer 110.

[0195] S223. A first dielectric layer is formed on the second side, and a portion of the first dielectric layer is formed within the second gap.

[0196] In this step, refer to Figure 12 and Figure 29 A first dielectric layer 130 can be formed by depositing a dielectric material on the second side 102 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The first dielectric layer 130 also fills the second gap 160. The first dielectric layer 130 can contact the isolation layer 40, and the first dielectric layer 130 and the isolation layer 40 together can isolate the first barrier layer 50 from the substrate 10, preventing leakage between the first barrier layer 50 and the substrate 10.

[0197] S224. Remove a portion of the first dielectric layer and a portion of the first barrier material layer to form a first barrier layer.

[0198] In this step, refer to Figure 29 and Figure 30 On the second side 102, part of the first dielectric layer 130, part of the first barrier material layer 110 and part of the isolation material layer 100 can be removed by chemical mechanical polishing to flatten the surface of the second side 102, for example, to make the upper surfaces of the first dielectric layer 130, the first barrier material layer 110, the isolation material layer 100 and the conductive post 120 flush, thereby exposing the conductive post 120 on the second side 102.

[0199] In this step, the first barrier material layer 110 that has not been removed constitutes the first barrier layer 50.

[0200] S225. Remove part of the conductive pillars to form a first conductive structure.

[0201] In this step, continue to refer to Figure 29 and Figure 30A portion of the conductive pillars 120 can be removed using either wet or dry etching processes to form the first conductive structure 30. (Reference) Figure 29 , Figure 30 and combined Figure 6 The first conductive structure 30 has a first surface 301 and a second surface 302 arranged along a first direction X, and a first side surface 303 connecting the first surface 301 and the second surface 302. The first surface 301 is farther away from the substrate 10 than the second surface 302. In the first direction X, both the first conductive structure 30 and the insulating layer 40 are recessed within the first barrier layer 50. That is, in the direction from the substrate 10 to the first dielectric layer 130, a portion of the first barrier layer 50 protrudes from the first surface 301 of the first conductive structure 30, and a portion of the first barrier layer 50 protrudes from the insulating layer 40.

[0202] S226, deposited medium material on the second side.

[0203] In this step, refer to Figure 30 , Figure 31 , Figure 32 and Figure 33 One or more dielectric materials 170 can be deposited on the second side 102 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD.

[0204] In this embodiment, taking the double-deposited medium material 170 as an example, refer to... Figure 31 When depositing the medium material 170 for the first time, the constituent material can be the same as that of the first medium layer 130, such as silicon nitride. When depositing the medium material 170 for the second time, a constituent material different from that of the first medium layer 130 can be selected, such as silicon oxide.

[0205] In this step, after the deposition process, the upper surface of the dielectric material 170 can be polished using CMP process to make the upper surface flat, which makes it easier to continue deposition to form other thin film structures, such as continuing to deposit to form the fourth barrier layer 90.

[0206] S227. Remove part of the dielectric material and part of the first dielectric layer to form a groove, the groove exposing the first surface, and part of the first barrier layer protruding from the bottom of the groove.

[0207] In this step, refer to Figure 33 and Figure 34The groove 140 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed over the dielectric material 170 (or the fourth barrier layer 90). The patterned photoresist layer can expose the portion of the dielectric material 170 used to form the groove 140. A suitable etching process can be performed to remove portions of the dielectric material 170, portions of the first dielectric layer 130, and portions of the isolation material layer 100 used to form the groove 140. For example, the etching process can include a dry etching process.

[0208] After the groove 140 is formed, the groove 140 can expose the first surface 301 of the first conductive structure 30. It can also be understood that the first surface 301 of the first conductive structure 30 constitutes part of the bottom 142 of the groove 140. In the direction from the substrate 10 to the first dielectric layer 130, part of the first barrier layer 50 protrudes from the bottom 142 of the groove 140, that is, part of the first barrier layer 50 protrudes from the first surface 301.

[0209] S228. Deposit barrier material in the groove to form a second barrier layer and a third barrier layer, the second barrier layer covering the sidewall and part of the bottom of the groove, and the third barrier layer covering the first surface.

[0210] In this step, refer to Figure 34 and Figure 6 After the groove 140 is formed, a barrier material, such as tantalum and its nitride, can be deposited in the groove 140 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a second barrier layer 70 and a third barrier layer 80. The second barrier layer 70 covers the sidewall 141 and part of the bottom 142 of the groove 140, and the third barrier layer 80 covers the first surface 301.

[0211] In this step, the materials used to prepare the second barrier layer 70 and the third barrier layer 80 can be the same, so that the steps of preparing the second barrier layer 70 and the third barrier layer 80 can be combined. The second barrier layer 70 and the third barrier layer 80 can be formed in a single thin film deposition process, which helps to reduce process steps, control costs, and improve the fabrication efficiency of the semiconductor structure 1000.

[0212] S229. Deposit conductive material in the groove to form a second conductive structure.

[0213] In this step, refer to Figure 34 and Figure 6After the second barrier layer 70 and the third barrier layer 80 are formed, conductive material, such as copper, can be deposited in the groove 140 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a second conductive structure 60. The second conductive structure 60 is electrically connected to the first conductive structure 30 through the first barrier layer 50, the second barrier layer 70, and the third barrier layer 80. The first dielectric layer 130 and the deposited dielectric material 170 together constitute the dielectric layer 20.

[0214] In the semiconductor structure 1000 prepared in this embodiment, a first barrier layer 50 protrudes from the first conductive structure 30 in the direction from the substrate 10 to the dielectric layer 20, with a height difference between the first barrier layer 50 and the first conductive structure 30. A second barrier layer 70 protrudes from the isolation layer 40, also with a height difference between the second barrier layer 70 and the isolation layer 40. Furthermore, the preparation process in this embodiment increases the height difference between the second barrier layer 70 and the isolation layer 40. Even if the first conductive structure 30 expands due to heat, the first barrier layer 50 can prevent the material in the first conductive structure 30 from diffusing into the isolation layer 40, further improving the stability and reliability of the semiconductor structure 1000.

[0215] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A dielectric layer is located on one side of the substrate along a first direction, where the first direction is the thickness direction of the substrate; A first conductive structure extends through at least a portion of the substrate and a portion of the dielectric layer. The first conductive structure has a first surface and a second surface arranged along the first direction, and a first side surface connecting the first surface and the second surface. The first surface is farther from the substrate than the second surface. An isolation layer, at least a portion of which is located between the first side and the substrate, and which is disposed around the first side; A first barrier layer, a portion of which is located between the first side surface and the isolation layer, protrudes from the first surface and the isolation layer in the direction from the substrate to the dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, In the second direction, a portion of the isolation layer is located between the substrate and the first barrier layer, and a portion of the isolation layer is located between the dielectric layer and the first barrier layer; the second direction intersects the first direction.

3. The semiconductor structure according to claim 1, characterized in that, In the second direction, the isolation layer is located between the substrate and the first barrier layer, and the isolation layer is located on one side of the dielectric layer along the first direction; the second direction intersects the first direction.

4. The semiconductor structure according to claim 1, characterized in that, In the second direction, the isolation layer is located between the substrate and the first barrier layer, and a portion of the dielectric layer is located between the substrate and the barrier layer; the second direction intersects the first direction.

5. The semiconductor structure according to claim 1, characterized in that, The area of ​​the second surface is greater than the area of ​​the first surface.

6. The semiconductor structure according to claim 1, characterized in that, Also includes: The second conductive structure is stacked with the first conductive structure along the first direction; A second barrier layer is disposed around the second conductive structure and is connected to the first barrier layer; A third barrier layer is located between the second conductive structure and the first surface, and is connected to the first barrier layer. In the direction from the substrate to the dielectric layer, a portion of the first barrier layer protrudes from the third barrier layer.

7. The semiconductor structure according to claim 6, characterized in that, The second barrier layer includes a first sub-layer and a second sub-layer connected to each other. The second sub-layer is disposed around the second conductive structure. The first sub-layer is located on one side of the second conductive structure along the first direction, and the first sub-layer connects the first barrier layer and the second sub-layer. In the direction from the substrate to the dielectric layer, a portion of the first barrier layer protrudes beyond the first sublayer.

8. The semiconductor structure according to claim 6, characterized in that, A portion of the first barrier layer is located inside the second conductive structure.

9. The semiconductor structure according to claim 6, characterized in that, The material of the first conductive structure is the same as the material of the second conductive structure.

10. The semiconductor structure according to claim 6, characterized in that, Also includes: A fourth barrier layer is located on the side of the dielectric layer away from the substrate, and the second barrier layer penetrates the fourth barrier layer.

11. The semiconductor structure according to claim 10, characterized in that, The material of the second barrier layer is different from that of the fourth barrier layer.

12. The semiconductor structure according to any one of claims 6-11, characterized in that, The materials of the first barrier layer, the second barrier layer, and the third barrier layer are the same.

13. The semiconductor structure according to claim 6, characterized in that, The second conductive structure has a third surface and a fourth surface arranged along the first direction, the third surface being closer to the first surface than the fourth surface, and the area of ​​the third surface being larger than the area of ​​the first surface.

14. The semiconductor structure according to claim 13, characterized in that, The area of ​​the fourth surface is greater than the area of ​​the third surface.

15. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A first barrier layer, a first conductive structure, a dielectric layer, and an isolation layer are formed. The dielectric layer is located on one side of the substrate along a first direction, where the first direction is the thickness direction of the substrate. The first conductive structure penetrates at least a portion of the substrate and a portion of the dielectric layer. The first conductive structure has a first surface and a second surface arranged along the first direction, and a first side surface connecting the first surface and the second surface. The first surface is farther from the substrate than the second surface. At least a portion of the isolation layer is located between the first side surface and the substrate, and the isolation layer is disposed around the first side surface. A portion of the first barrier layer is located between the first side surface and the isolation layer. In a direction away from the substrate along the first direction, a portion of the first barrier layer protrudes from the first surface and the isolation layer.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The formation of the first barrier layer, the main body, the dielectric layer, and the isolation layer includes: On a first side of the substrate along the first direction, an insulating material layer, a first barrier material layer, and a conductive pillar are sequentially formed, penetrating a portion of the substrate. The insulating material layer surrounds the first barrier material layer, and the first barrier material layer surrounds the conductive pillar. On a second side of the substrate along the first direction, a portion of the substrate is removed to expose a portion of the insulating material layer; A first dielectric layer is formed on the second side; A portion of the first dielectric layer and a portion of the first barrier material layer are removed to form the first barrier layer.

17. The method for preparing a semiconductor structure according to claim 16, characterized in that, The formation of the first barrier layer further includes: Remove a portion of the insulating material layer so that the insulating material layer is flush with the first barrier layer.

18. The method for preparing a semiconductor structure according to claim 16, characterized in that, The formation of the first barrier layer further includes: A portion of the insulating material layer is removed to form an insulating layer, wherein a first gap exists between the first dielectric layer and the first barrier layer.

19. The method for preparing a semiconductor structure according to claim 16, characterized in that, The step of removing a portion of the substrate on the second side of the substrate along the first direction further includes: A portion of the insulating material layer is removed to form the insulating layer, and a second gap is formed between the substrate and the first barrier material layer; The method of forming a first dielectric layer on the second side further includes: forming a portion of the first dielectric layer within the second gap.

20. The method for preparing a semiconductor structure according to any one of claims 16-19, characterized in that, The formation of the first barrier layer, the main body, and the dielectric layer further includes: A portion of the conductive pillars is removed to form the first conductive structure.

21. The method for preparing a semiconductor structure according to claim 20, characterized in that, The formation of the first barrier layer, the main body, the dielectric layer, and the isolation layer further includes: Deposited medium material on the second side; A portion of the dielectric material and a portion of the first dielectric layer are removed to form a groove that exposes the first surface, and a portion of the first barrier layer protrudes from the bottom of the groove.

22. The method for preparing a semiconductor structure according to claim 21, characterized in that, The removal of a portion of the first dielectric layer and a portion of the first barrier material layer also includes: Remove part of the insulating material layer so that the insulating material layer is flush with the first barrier layer; The removal of a portion of the dielectric material and a portion of the first dielectric layer further includes: Remove a portion of the insulating material layer to form the insulating layer.

23. The method for preparing a semiconductor structure according to claim 21 or 22, characterized in that, Also includes: A barrier material is deposited within the groove to form a second barrier layer and a third barrier layer. The second barrier layer covers the sidewalls and part of the bottom of the groove, and the third barrier layer covers the first surface. Conductive material is deposited within the groove to form a second conductive structure.

24. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-14; A controller, the control being coupled to the semiconductor structure, to control the semiconductor structure to store data.

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