Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof. The semiconductor structure comprises: a first conductive plug in an input region and electrically connected with a second electrode layer, a third conductive plug in an output region and electrically connected with the second electrode layer, and a second conductive plug at a position of a first opening of a grounding region; in this embodiment, since the first conductive plug of the input region and the third conductive plug of the output region are both electrically connected with the second electrode layer, the second conductive plug is used as a grounding terminal, when a current signal is applied to the first conductive plug of the input region, the current can be transmitted to the third conductive plug of the output region through the first conductive plug of the input region, that is, the current flows into and out of the second electrode layer, avoiding the current passing through unnecessary paths, therefore, the equivalent inductance of the second electrode layer can be ignored, thereby reducing the equivalent inductance of the whole capacitor, and further improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in materials and design have led to generation after generation of integrated circuits. Each generation features smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of fabricating and manufacturing integrated circuits, requiring similar developments in IC fabrication and manufacturing to achieve these advancements. Throughout the development of integrated circuits, functional density (the number of interconnect devices per chip area) has gradually increased, while geometric dimensions (the smallest components that can be manufactured using specific processes) have gradually decreased.

[0003] One type of capacitor is the metal-insulator-metal (MIM) capacitor, which is typically used in mixed-signal devices and logic devices such as embedded memory and radio frequency devices to store charge.

[0004] However, the performance of MIM capacitors still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which reduces the equivalent inductance of the entire capacitor.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including an input region, an output region, and a junction region located between the input region and the output region; a first electrode layer located on the substrate in the junction region, the first electrode layer having a third opening located in both the input region and the output region and penetrating the first electrode layer; a first dielectric layer located on the first electrode layer; a second electrode layer located on the first dielectric layer and also on the substrate of the input region and the output region, the second electrode layer having a first opening located in the junction region and penetrating the second electrode layer; a second dielectric layer located on the second electrode layer; a third electrode layer located on the second dielectric layer in the junction region and also on the first electrode layer at the location of the first opening; a first conductive plug located in the input region and electrically connected to the second electrode layer; a second conductive plug located at the location of the first opening in the junction region and electrically connected to both the first electrode layer and the third electrode layer; and a third conductive plug located in the output region and electrically connected to the second electrode layer.

[0007] This invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including an input region, an output region, and a junction region located between the input region and the output region; forming a first electrode layer on the substrate of the junction region, the first electrode layer having a third opening located in the input region and the output region respectively and penetrating the first electrode layer; forming a first dielectric layer covering the first electrode layer; forming a second electrode layer on the first dielectric layer, the second electrode layer also being formed on the substrate of the input region and the output region, the second electrode layer having a first opening located in the junction region and penetrating the second electrode layer; forming a second dielectric layer covering the second electrode layer; forming a third electrode layer on the second dielectric layer of the junction region, the third electrode layer also being located on the first electrode layer at the location of the first opening; forming a first conductive plug in the input region, the first conductive plug being electrically connected to the second electrode layer; forming a second conductive plug at the location of the first opening in the junction region, the second conductive plug being electrically connected to the first electrode layer and the third electrode layer; forming a third conductive plug in the output region, the third conductive plug being electrically connected to the second electrode layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a semiconductor structure comprising: a substrate including an input region, an output region, and a junction region between the input and output regions; a first electrode layer located on the substrate in the junction region, the first electrode layer having a third opening located in both the input and output regions and penetrating the first electrode layer; a first dielectric layer located on the first electrode layer; a second electrode layer located on the first dielectric layer and also on the substrate of the input and output regions, the second electrode layer having a first opening located in the junction region and penetrating the second electrode layer; a second dielectric layer located on the second electrode layer; a third electrode layer located on the second dielectric layer in the junction region and also on the first electrode layer at the location of the first opening; a first conductive plug located in the input region and electrically connected to the second electrode layer; a second conductive plug located at the location of the first opening in the junction region and electrically connected to both the first and third electrode layers; and a third conductive plug located in the output region and electrically connected to the second electrode layer. In this embodiment, since the first conductive plug in the input region and the third conductive plug in the output region are only electrically connected to the second electrode layer, and the second conductive plug is used as a ground terminal, when a current signal is applied to the first conductive plug in the input region, the current can be transmitted to the third conductive plug in the output region through the first conductive plug in the input region. That is, the current flows in and out from the second electrode layer, avoiding the current from passing through unnecessary paths. Therefore, the equivalent inductance of the second electrode layer can be ignored, thereby reducing the equivalent inductance of the entire capacitor and thus improving the performance of the semiconductor structure.

[0010] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate including an input region, an output region, and a junction region between the input and output regions; forming a first electrode layer on the substrate in the junction region, the first electrode layer having a third opening located in both the input and output regions and penetrating the first electrode layer; forming a first dielectric layer covering the first electrode layer; forming a second electrode layer on the first dielectric layer, the second electrode layer also being formed on the substrate of the input and output regions, the second electrode layer having a first opening located in the junction region and penetrating the second electrode layer; forming a second dielectric layer covering the second electrode layer; forming a third electrode layer on the second dielectric layer in the junction region, the third electrode layer also being located on the first electrode layer at the location of the first opening; forming a first conductive plug in the input region, the first conductive plug being electrically connected to the second electrode layer; forming a second conductive plug at the location of the first opening in the junction region, the second conductive plug being electrically connected to both the first and third electrode layers; and forming a third conductive plug in the output region, the third conductive plug being electrically connected to the second electrode layer. In this embodiment, since the first conductive plug in the input region and the third conductive plug in the output region are only electrically connected to the second electrode layer, and the second conductive plug is used as a ground terminal, when a current signal is applied to the first conductive plug in the input region, the current can be transmitted to the third conductive plug in the output region through the first conductive plug in the input region. That is, the current flows in and out from the second electrode layer, avoiding the current from passing through unnecessary paths. Therefore, the equivalent inductance of the second electrode layer can be ignored, thereby reducing the equivalent inductance of the entire capacitor and thus improving the performance of the semiconductor structure. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a semiconductor structure.

[0012] Figure 2 yes Figure 1 A sectional view along the AA1 direction;

[0013] Figure 3 yes Figure 1 A cross-sectional view along the BB1 ​​direction;

[0014] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0015] Figure 5 yes Figure 4 A sectional view along direction AA2;

[0016] Figures 6 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0017] Currently, the equivalent inductance of capacitors still needs to be reduced. This paper analyzes the reasons why the equivalent inductance of capacitors needs to be reduced, using a schematic diagram of a semiconductor structure as an example.

[0018] Figure 1 This is a schematic diagram of a semiconductor structure. Figure 2 yes Figure 1 A cross-sectional view along the AA1 direction. Figure 3 yes Figure 1 A cross-sectional view along the BB1 ​​direction.

[0019] refer to Figures 1 to 3 The semiconductor structure includes: a substrate 10, the substrate 10 including an input region i (e.g., Figure 3 (as shown) and the output area ii adjacent to input area i (as shown) Figure 2 (As shown); a first electrode layer 11 is located on the substrate 10 of the input region i and the output region ii, and the first electrode layer 11 has a first opening 12 located in the output region ii and penetrating the first electrode layer 11 (as shown). Figure 2 (as shown); a first dielectric layer 13, located on the first electrode layer 11; a second electrode layer 14, located on the first dielectric layer 13, and also located on the substrate 10 of the output region ii, the second electrode layer 14 having a second opening 15 located in the input region i and penetrating the second electrode layer 14 ... Figure 3 (as shown); a second dielectric layer 16, located on the second electrode layer 14; a third electrode layer 17, located on the second dielectric layer 16 of the output region ii, and also on the first electrode layer 11 at the location of the second opening 15, the third electrode layer 17 having a third opening 18 located in the output region ii and penetrating the third electrode layer 17 (as shown); a second dielectric layer 16, located on the second electrode layer ii and penetrating the third electrode layer 14; a third electrode layer 17, located on the second dielectric layer ii and penetrating the third electrode layer 14 (as shown); a second dielectric layer 16, located on the second electrode layer ii, and a third electrode layer 17 having a third opening 18 located in the output region ii and penetrating the third electrode layer 17 (as shown); a second dielectric layer 16, located on the second electrode layer 14; a third electrode layer 17, located on the second dielectric layer 16 of the output region ii, and also on the first electrode layer 11 at the location of the second opening 15, the ... Figure 2 As shown), and the positions of the first openings 12 correspond one-to-one; the first conductive plugs 19 (as shown) Figure 2 As shown), it is located at the position of the third opening 18 in the output area ii, and is electrically connected to the second electrode layer 14; the second conductive plug 20 (as shown) Figure 3 As shown in the figure, it is located at the position of the second opening 15 of the input area i, and is electrically connected to the first electrode layer 11 and the third electrode layer 17.

[0020] Research has revealed that the first conductive plug 19 is electrically connected to the second electrode layer 14, and the second conductive plug 20 is electrically connected to the first electrode layer 11 and the third electrode layer 17. Therefore, when a voltage is applied to the second conductive plug 20 of the input region i, a potential is generated between the first electrode layer 11 of the input region i and the second electrode layer 14 of the output region ii, and between the third electrode layer 17 of the input region i and the second electrode layer 14 of the output region ii. This results in the first electrode layer 11 of the input region i and the second electrode layer 14 of the output region ii forming a capacitor, and the third electrode layer 17 of the input region i and the second electrode layer 14 of the output region ii forming a capacitor. This means that the first electrode layer 11, the second electrode layer 14, and the third electrode layer 17 all generate an equivalent inductance, resulting in a high equivalent inductance of the entire capacitor, which in turn affects the performance of the semiconductor structure.

[0021] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including an input region, an output region, and a junction region located between the input region and the output region; a first electrode layer located on the substrate in the junction region, the first electrode layer having a third opening located in both the input region and the output region and penetrating the first electrode layer; a first dielectric layer located on the first electrode layer; a second electrode layer located on the first dielectric layer and also on the substrate of the input region and the output region, the second electrode layer having a first opening located in the junction region and penetrating the second electrode layer; a second dielectric layer located on the second electrode layer; a third electrode layer located on the second dielectric layer in the junction region and also on the first electrode layer at the location of the first opening; a first conductive plug located in the input region and electrically connected to the second electrode layer; a second conductive plug located at the location of the first opening in the junction region and electrically connected to both the first electrode layer and the third electrode layer; and a third conductive plug located in the output region and electrically connected to the second electrode layer.

[0022] In the scheme disclosed in the embodiments of the present invention, since the first conductive plug in the input region and the third conductive plug in the output region are only electrically connected to the second electrode layer, and the second conductive plug is used as a ground terminal, when a current signal is applied to the first conductive plug in the input region, the current can be transmitted to the third conductive plug in the output region through the first conductive plug in the input region, that is, the current flows in and out from the second electrode layer, avoiding the current from passing through unnecessary paths. Therefore, the equivalent inductance of the second electrode layer can be ignored, thereby reducing the equivalent inductance of the entire capacitor and thus improving the performance of the semiconductor structure.

[0023] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 5 yes Figure 4 A sectional view along AA2.

[0025] refer to Figures 4 to 5 The semiconductor structure includes: a substrate 100, the substrate 100 including an input region I, an output region II, and a junction region III located between the input region I and the output region II; a first electrode layer 101 located on the substrate 100 of the junction region III, the first electrode layer 101 having a third opening 110 located in the input region I and the output region II and penetrating the first electrode layer 101; a first dielectric layer 102 located on the first electrode layer 101; and a second electrode layer 103 located on the first dielectric layer 102 and also located on the substrate 100 of the input region I and the output region II, the second electrode layer 103 having a third opening 110 located in the junction region III and... A first opening 104 penetrates the second electrode layer 103; a second dielectric layer 105 is located on the second electrode layer 103; a third electrode layer 106 is located on the second dielectric layer 105 in the grounding region III, and is also located on the first electrode layer 101 at the location of the first opening 104; a first conductive plug 107 is located in the input region I and is electrically connected to the second electrode layer 103; a second conductive plug 108 is located at the location of the first opening 104 in the grounding region III and is electrically connected to the first electrode layer 101 and the third electrode layer 106; a third conductive plug 109 is located in the output region II and is electrically connected to the second electrode layer 103.

[0026] It should be noted that, since the first conductive plug 107 of input region I and the third conductive plug 109 of output region II are only electrically connected to the second electrode layer 103, and the second conductive plug 108 is used as a ground terminal, when a current signal is applied to the first conductive plug 107 of input region I, the current can be transmitted through the first conductive plug 107 of input region I to the third conductive plug 109 of output region II. That is, the current flows in and out from the second electrode layer 103, avoiding the current from passing through unnecessary paths. Therefore, the equivalent inductance of the second electrode layer 103 can be ignored, thereby reducing the equivalent inductance of the entire capacitor and thus improving the performance of the semiconductor structure.

[0027] Substrate 100 is used to provide a process platform for forming MIM capacitors.

[0028] In this embodiment, the substrate 100 includes a substrate (not shown), and the substrate material is silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0029] Input area I is used as the region for capacitor signal input.

[0030] Output area II is used as the area for capacitor signal output.

[0031] Grounding area III is used as the grounding area for capacitors.

[0032] The first electrode layer 101 is used as the electrode plate of the MIM capacitor.

[0033] In this embodiment, the first electrode layer 101 has a third opening 110 located in the input region I and the output region II respectively and penetrating the first electrode layer 101.

[0034] The third opening 110 provides space for the first conductive plug 107 and the third conductive plug 109 to form an electrical connection, while isolating the first conductive plug 107 and the third conductive plug 109 from the first electrode layer 101.

[0035] It should be noted that the third opening 110 in the first electrode layer 101 is compatible with existing processes, reducing the process difficulty of forming the first conductive plug 107 and the third conductive plug 109.

[0036] In other embodiments, the first electrode layer may not have a third opening.

[0037] In this embodiment, the material of the first electrode layer 101 is a conductive material. As an example, the material of the first electrode layer 101 includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0038] In this embodiment, the thickness of the first electrode layer 101 should not be too large or too small. If the thickness of the first electrode layer 101 is too large, its resistance will easily increase, thus affecting the transmission of high-frequency signals by the capacitor; if the thickness of the first electrode layer 101 is too small, its mechanical strength will easily decrease, making it prone to breakage or damage during operation. Therefore, in this embodiment, the thickness of the first electrode layer is 10 nanometers to 100 nanometers.

[0039] The first dielectric layer 102 serves as an insulating layer in the formation of the MIM capacitor, and is used to isolate the first electrode layer 101 and the second electrode layer 103.

[0040] In this embodiment, the material of the first dielectric layer 102 includes one or more of hafnium oxide, hafnium silicon oxide, titanium oxide, zirconium hafnium oxide, hafnium silicon nitride oxide, tantalum hafnium oxide, titanium hafnium oxide, tantalum oxide, zirconium oxide, zirconium silicon oxide, aluminum oxide, strontium titanate, and barium strontium titanate.

[0041] In this embodiment, the first dielectric layer 102 is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Selecting a high-k dielectric material is beneficial for increasing the capacitance density of the MIM capacitor. As an example, the material of the first dielectric layer 102 is hafnium oxide.

[0042] The second electrode layer 103 is used as the electrode plate of the MIM capacitor.

[0043] In this embodiment, the second electrode layer 103 has a first opening 104 located in the grounding region III and penetrating the second electrode layer 103.

[0044] The first opening 104 provides space for the second conductive plug 108 to form an electrical connection, while isolating the second conductive plug 108 from the second electrode layer 103.

[0045] In this embodiment, the bottom of the first opening 104 exposes the first dielectric layer 102, reducing the difficulty for the second conductive plug 108 to penetrate the third electrode layer 106 and the first dielectric layer 102 at the location of the first opening 104.

[0046] In this embodiment, the second electrode layer 103 is located on the first electrode layer 101 and on the base 100 at the bottom of the third opening 110, which facilitates the electrical connection of the first conductive plug 107 and the third conductive plug 109 to the second electrode layer 103.

[0047] In this embodiment, the material of the second electrode layer 103 is a conductive material. As an example, the material of the second electrode layer 103 includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0048] In this embodiment, the thickness of the second electrode layer 103 should not be too large or too small. The reasons for this are similar to those for the reasons for the thickness of the first electrode layer 101, and will not be repeated here. Therefore, in this embodiment, the thickness of the second electrode layer 103 is 10 nanometers to 100 nanometers.

[0049] The second dielectric layer 105 serves as an insulating layer in the formation of the MIM capacitor, and is used to isolate the second electrode layer 103 and the third electrode layer 106.

[0050] In this embodiment, the material of the second dielectric layer 105 is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to improve the capacitance density of the MIM capacitor.

[0051] In this embodiment, the material of the second dielectric layer 105 includes one or more of hafnium oxide, hafnium silicon oxide, titanium oxide, zirconium hafnium oxide, hafnium silicon nitride oxide, tantalum hafnium oxide, titanium hafnium oxide, tantalum oxide, zirconium oxide, zirconium silicon oxide, aluminum oxide, strontium titanate, and barium strontium titanate. As an example, the material of the second dielectric layer 105 is hafnium oxide.

[0052] The third electrode layer 106 is used as the electrode plate of the MIM capacitor.

[0053] In this embodiment, the third electrode layer 106 is located on the first electrode layer 101 at the first opening 104, which facilitates the electrical connection between the third electrode layer 106 and the second conductive plug 108.

[0054] In this embodiment, the first electrode layer 101 is located on the substrate 100 of the input region I, the grounding region III, and the output region II; the third electrode layer 106 is located on the second electrode layer 103 of the input region I, the grounding region III, and the output region II, and the third electrode layer 106 has a second opening 111 located in the input region I and the output region II respectively, and penetrating the third electrode layer 106.

[0055] It should be noted that the first electrode layer 101, the second electrode layer 103, and the third electrode layer 106 are all formed on the input region I, the grounding region III, and the output region II, which helps to increase the facing area between adjacent electrode layers of the capacitor, thereby increasing the capacitance density.

[0056] It should also be noted that the second opening 111 is used to provide space for the first conductive plug 107 and the third conductive plug 109 to form an electrical connection, while isolating the first conductive plug 107 and the third conductive plug 109 from the third electrode layer 106.

[0057] In this embodiment, the second opening 111 is located above the third opening 110 and corresponds one-to-one with the position of the third opening 110 in the input area I or output area II, which helps to reduce the difficulty of the first conductive plug 107 and the third conductive plug 109 simultaneously penetrating the third electrode layer 106 and the first electrode layer 101.

[0058] In this embodiment, the material of the third electrode layer 106 is a conductive material. As an example, the material of the third electrode layer 106 includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0059] In this embodiment, the thickness of the third electrode layer 106 should not be too large or too small. The reasons for this are similar to those for the reasons for the thickness of the first electrode layer 101, and will not be repeated here. Therefore, in this embodiment, the thickness of the third electrode layer 106 is 10 nanometers to 100 nanometers.

[0060] As an example, the first electrode layer 101, the second electrode layer 103, and the third electrode layer 106 have the same thickness.

[0061] Specifically, on the one hand, it can generate a uniform electric field among the first electrode layer 101, the second electrode layer 103, and the third electrode layer 106; on the other hand, it helps to reduce the complexity of the process.

[0062] In other embodiments, the thicknesses of the first electrode layer, the second electrode layer, and the third electrode layer may not be equal.

[0063] The first conductive plug 107 is used for electrical connection to the second electrode layer 103.

[0064] In this embodiment, the first conductive plug 107 is located at the position of the second opening 111 of the input area I, and the second opening 111 exposes part of the second electrode layer 103 of the input area I, thereby facilitating the electrical connection between the first conductive plug 107 and the second electrode layer 103 of the input area I.

[0065] In this embodiment, as Figure 4 As shown, the input area I, the grounding area III, and the output area I are arranged sequentially along the first direction Y; there are multiple first conductive plugs 107, and the multiple first conductive plugs 107 are arranged at intervals along the second direction X, the second direction X being perpendicular to the first direction Y. This facilitates the formation of first conductive plugs 107 and third conductive plugs 109 located on both sides of second conductive plugs 108, and second conductive plugs 108 serving as grounding terminals. When a current signal is applied to the first conductive plugs 107 of the input area I, it facilitates the current being transmitted through the first conductive plugs 107 of the input area I to the third conductive plugs 109 of the output area II.

[0066] The second conductive plug 108 is used to electrically connect the first electrode layer 101 and the third electrode layer 106, and also serves as a grounding terminal.

[0067] In this embodiment, the second conductive plug 108 penetrates the third electrode layer 106 and the first dielectric layer 102 at the position of the first opening 104, and is electrically connected to the first electrode layer 101 and the third electrode layer 106. That is, the first electrode layer 101 and the third electrode layer 106 share the second conductive plug 108. Accordingly, it is beneficial to reduce the number of conductive plugs, thereby increasing the area of ​​the electrode layer of the capacitor and thus improving the capacitance density.

[0068] In this embodiment, the input area I, the grounding area III, and the output area I are arranged sequentially along the first direction Y; there are multiple second conductive plugs 108, and the multiple second conductive plugs 108 are arranged at intervals along the second direction X, which is perpendicular to the first direction Y. This facilitates the formation of second conductive plugs 108 located between the first conductive plug 107 and the third conductive plug 109, and the second conductive plug 108 serves as a grounding terminal. When a current signal is applied to the first conductive plug 107 of the input area I, it facilitates the current to be transmitted through the first conductive plug 107 of the input area I to the third conductive plug 109 of the output area II.

[0069] The third conductive plug 109 is used for electrical connection to the second electrode layer 103.

[0070] In this embodiment, the third conductive plug 109 is located at the position of the second opening 111 of the output area II, and the second opening 111 exposes part of the second dielectric layer 105 of the output area II, which reduces the difficulty for the third conductive plug 109 to penetrate the second dielectric layer 105 and the second electrode layer 103 at the position of the second opening 111, thereby facilitating the electrical connection between the third conductive plug 109 and the second electrode layer 103 of the output area II.

[0071] In this embodiment, the input area I, the grounding area III, and the output area I are arranged sequentially along the first direction Y; there are multiple third conductive plugs 109, and the multiple third conductive plugs 109 are arranged at intervals along the second direction X, which is perpendicular to the first direction Y. This facilitates the formation of third conductive plugs 109 and first conductive plugs 107 located on both sides of second conductive plugs 108, and second conductive plugs 108 serving as grounding terminals. When a current signal is applied to the first conductive plug 107 of the input area I, it facilitates the current to be transmitted through the first conductive plug 107 of the input area I to the third conductive plug 109 of the output area II.

[0072] In this embodiment, the semiconductor structure further includes a bottom interconnect layer 112, which is located in the substrate 100 at the bottom of the first opening 104 and the third opening 110, respectively.

[0073] The bottom interconnect layer 112 is used as the etching stop position for forming the first conductive plug 107, the second conductive plug 108 and the third conductive plug 109.

[0074] It should be noted that, since the bottom interconnect layer 112 is located in the substrate 100 at the bottom of the third opening 110, and the bottom interconnect layer 112 is used as the etching stop position for forming the first conductive plug 107 and the third conductive plug 109, the first conductive plug 107 and the third conductive plug 109 both penetrate the second electrode layer 103 and the substrate 100 above the bottom interconnect layer 112, and are electrically connected to the corresponding bottom interconnect layer 112.

[0075] It should also be noted that, since the bottom interconnect layer 112 is located in the substrate 100 at the bottom of the first opening 104, and the bottom interconnect layer 112 is used as the etching stop position for forming the second conductive plug 108, the second conductive plug 108 penetrates the third electrode layer 106, the first electrode layer 101 and the substrate 100 above the bottom interconnect layer 112, and is electrically connected to the corresponding bottom interconnect layer 112.

[0076] In this embodiment, the semiconductor structure further includes a top interconnect layer 113, which is located on top of the first conductive plug 107, the second conductive plug 108, and the third conductive plug 109, and is electrically connected to the corresponding first conductive plug 107, second conductive plug 108, or third conductive plug 109.

[0077] The top interconnect layer 113 is used to apply voltage to the first electrode layer 101, the second electrode layer 103 and the third electrode layer 106, thereby realizing the MIM capacitor formed by the first electrode layer 101, the second electrode layer 103 and the third electrode layer 106.

[0078] In this embodiment, as Figure 4 As shown, the top interconnect layer 113 electrically connected to the first conductive plug 107 includes: a first comb tooth portion 115 extending along the first direction Y and spaced apart along the second direction X, the first comb tooth portion 115 being electrically connected to each of the first conductive plugs 107; and a first comb handle portion 114 located on the side of the first comb tooth portion 115 away from the contact area III, the first comb handle portion 114 extending along the second direction X and connecting to each of the first comb tooth portions 115.

[0079] The top interconnect layer 113, which is electrically connected to the first conductive plug 107, is arranged in the form of a first comb handle portion 114 and a plurality of first comb teeth portions 115. This arrangement is beneficial to make the voltage applied to the second electrode layer 103 of the input area I by the top interconnect layer 113 electrically connected to the first conductive plug 107 more uniform. Moreover, the comb-shaped top interconnect layer 113 electrically connected to the first conductive plug 107 is beneficial to reducing the area of ​​the metal layer.

[0080] In this embodiment, as Figure 4 As shown, the top interconnect layer 113 electrically connected to the third conductive plug 109 includes: a second comb tooth portion 116 extending along the first direction Y and spaced apart along the second direction X, the second comb tooth portion 116 being electrically connected to each of the third conductive plugs 109; and a second comb handle portion 117 located on the side of the second comb tooth portion 116 away from the contact area III, the second comb handle portion 117 extending along the second direction X and connecting to each of the second comb tooth portions 116.

[0081] The top interconnect layer 113 electrically connected to the third conductive plug 109 has a morphological arrangement of a second comb handle portion 117 and multiple second comb teeth portions 116. This arrangement facilitates a more uniform voltage distribution on the second electrode layer 103 of the output region II by the top interconnect layer 113 electrically connected to the third conductive plug 109. Furthermore, the comb-shaped top interconnect layer 113 electrically connected to the third conductive plug 109 helps reduce the metal layer area and allows space between the top interconnect layer 113 electrically connected to the third conductive plug 109 and the top interconnect layer 113 electrically connected to the first conductive plug 107. Specifically, the first comb handle portion 114 and the second comb handle portion 117 are parallel to each other, and the first comb teeth portion 115 corresponds to the second comb teeth portion 116. This allows the top interconnect layer 113 electrically connected to the third conductive plug 109 and the top interconnect layer 113 electrically connected to the first conductive plug 107 to fully utilize the formed space, resulting in a higher pattern density and saving space without mutual interference.

[0082] In this embodiment, as Figure 4As shown, the top interconnect layer 113, which is electrically connected to the second conductive plug 108, extends along the second direction X and connects each of the second conductive plugs 108. This facilitates the application of the same voltage to both the first electrode layer 101 and the third electrode layer 106 simultaneously by the top interconnect layer 113 electrically connected to the second conductive plug 108. It also facilitates the formation of mutual spaces between the top interconnect layer 113 electrically connected to the third conductive plug 109, the top interconnect layer 113 electrically connected to the first conductive plug 107, and the top interconnect layer 113 electrically connected to the second conductive plug 108. Specifically, the top interconnect layer 113 electrically connected to the second conductive plug 108, the first comb handle portion 114, and the second comb handle portion 117 are parallel to each other. This allows the top interconnect layer 113 electrically connected to the third conductive plug 109, the top interconnect layer 113 electrically connected to the first conductive plug 107, and the top interconnect layer 113 electrically connected to the second conductive plug 108 to fully utilize the formed space, resulting in a higher pattern density and saving space without mutual interference.

[0083] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 6 to 16 This is a schematic diagram of the structure corresponding to each step in an embodiment of the semiconductor structure formation method of the present invention. Specifically, Figure 16 yes Figure 15 Top view.

[0084] refer to Figure 6 A substrate 500 is provided, the substrate 500 including an input area I', an output area II', and a junction area III' located between the input area I' and the output area II'.

[0085] The substrate 500 is used to provide a process platform for forming MIM capacitors.

[0086] In this embodiment, the substrate 500 includes a substrate (not shown), and the substrate material is silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0087] Input area I' is used as the region for capacitor signal input.

[0088] Output area II' is used as the area for capacitor signal output.

[0089] Grounding area III' is used as the grounding area for capacitors.

[0090] In this embodiment, in the step of providing the substrate 500, a bottom interconnect layer 512 is formed in the substrate 500, and the bottom interconnect layer 512 is located in the input area I', the junction area III' and the output area II' respectively.

[0091] The bottom interconnect layer 512 is used as the etching stop position for forming the first conductive plug, the second conductive plug and the third conductive plug.

[0092] In this embodiment, in the step of providing the substrate 500, the input region I', the junction region III' and the output region II' are arranged sequentially along the first direction y, which is beneficial to make full use of the space area and improve the integration of the semiconductor structure.

[0093] refer to Figures 7 to 8 A first electrode layer 501 is formed on the substrate 500 of the contact area III', and the first electrode layer 501 has a third opening 510 located in the input area I' and the output area II' respectively and penetrating the first electrode layer 501.

[0094] The first electrode layer 501 is used as the electrode plate of the MIM capacitor.

[0095] The third opening 510 provides space for the first and third conductive plugs to form an electrical connection, while isolating the first and third conductive plugs from the first electrode layer 501.

[0096] In this embodiment, during the step of forming the first electrode layer 501, the third opening 510 is located above the top of the bottom interconnect layer 512.

[0097] It should be noted that the third opening 510 is located above the top of the bottom interconnect layer 512, which facilitates the subsequent electrical connection of the first conductive plug and the third conductive plug to the bottom interconnect layer 512 through the third opening 510.

[0098] In this embodiment, the first electrode layer 501 is formed on the substrate 500 of the input region I', the ground region III' and the output region II', which is beneficial to increase the area of ​​the first electrode layer 501 of the capacitor and thus improve the capacitance density.

[0099] Specifically, the step of forming the first electrode layer 501 on the substrate 500 of the input region I', the junction region III', and the output region II' includes: referencing Figure 7 A first electrode material layer 520 is formed on the substrate 500, covering the input region I', the ground region III', and the output region II'; Reference Figure 8The first electrode material layer 520 in a portion of the input region I' and output region II' is removed, and a third opening 510 is formed in the first electrode material layer 520 that penetrates the first electrode material layer 520. The remaining first electrode material layer 520 serves as the first electrode layer 501.

[0100] The first electrode material layer 520 is used to form the first electrode layer 501.

[0101] By forming a first electrode material layer 520 covering the input region I', the junction region III', and the output region II' on the substrate 500, and then removing a portion of the first electrode material layer 520 in the input region I' and the output region II', it is beneficial to improve the consistency of the thickness of the first electrode layer 501 formed on the substrate 500 in the input region I', the junction region III', and the output region II'; in addition, it is also beneficial to reduce the difficulty of forming the first electrode layer 501.

[0102] In this embodiment, the process for forming the first electrode material layer 520 includes atomic layer deposition (ALD) or physical vapor deposition (PVD). Using ALD or PVD improves the thickness uniformity of the first electrode material layer 520. In other embodiments, other deposition processes, such as chemical vapor deposition (CVD), can also be used to form the first electrode material layer.

[0103] In this embodiment, a portion of the first electrode material layer 520 in the input region I' and output region II' is removed by a dry etching process.

[0104] In this embodiment, the material of the first electrode layer 501 is a conductive material. As an example, the material of the first electrode layer 501 includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0105] In this embodiment, the thickness of the first electrode layer 501 should not be too large or too small. If the thickness of the first electrode layer 501 is too large, its resistance will easily increase, thus affecting the transmission of high-frequency signals by the capacitor. If the thickness of the first electrode layer 501 is too small, its mechanical strength will easily decrease, making it prone to breakage or damage during operation. Therefore, in this embodiment, the thickness of the first electrode layer 501 is 10 nanometers to 100 nanometers.

[0106] refer to Figure 9 A first dielectric layer 502 is formed covering the first electrode layer 501.

[0107] The first dielectric layer 502 serves as an insulating layer in the formation of the MIM capacitor, and is used to isolate the first electrode layer 501 and the second electrode layer.

[0108] In this embodiment, the first dielectric layer 502 is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to improve the capacitance density of the MIM capacitor.

[0109] In this embodiment, the material of the first dielectric layer 502 includes one or more of hafnium oxide, hafnium silicon oxide, titanium oxide, zirconium hafnium oxide, hafnium silicon nitride oxide, tantalum hafnium oxide, titanium hafnium oxide, tantalum oxide, zirconium oxide, zirconium silicon oxide, aluminum oxide, strontium titanate, and barium strontium titanate. As an example, the material of the first dielectric layer 502 is hafnium oxide.

[0110] In this embodiment, the process for forming the first dielectric layer 502 includes atomic layer deposition or chemical vapor deposition.

[0111] It should be noted that atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes have good filling performance, which allows the first dielectric layer 502 to be deposited more effectively into the third opening 510.

[0112] refer to Figures 10 to 11 A second electrode layer 503 is formed on the first dielectric layer 502. The second electrode layer 503 is also formed on the substrate 500 of the input region I' and the output region II'. The second electrode layer 503 has a first opening 504 located in the junction region III' and penetrating the second electrode layer 503.

[0113] The second electrode layer 503 is used as the electrode plate of the MIM capacitor.

[0114] The first opening 504 provides space for the second conductive plug to form an electrical connection, while isolating the second conductive plug from the second electrode layer 503.

[0115] In this embodiment, since the first electrode layer 501 has a third opening 510 that penetrates the first electrode layer 501, the second electrode layer 503 is also formed on the substrate 500 of the input region I' and the output region II'.

[0116] In this embodiment, during the step of forming the second electrode layer 503, the bottom of the first opening 504 exposes the first dielectric layer 502, which helps to reduce the difficulty of the subsequent second conductive plug penetrating the third electrode layer 503 and the first dielectric layer 502 at the position of the first opening 504.

[0117] In this embodiment, the second electrode layer 503 is formed on the first electrode layer 501 and on the first dielectric layer 502 at the bottom of the third opening 510, and the first opening 504 is located above the top of the bottom interconnect layer 512.

[0118] It should be noted that the first opening 504 is located above the top of the bottom interconnect layer 512, which facilitates the subsequent electrical connection of the second conductive plug to the bottom interconnect layer 512 through the first opening 504.

[0119] Specifically, the step of forming the second electrode layer 503 includes: referencing Figure 10 A second electrode material layer 521 covering the input region I', the ground region III', and the output region II' is formed on the first dielectric layer 501; Reference Figure 11 Remove a portion of the second electrode material layer 521 from the junction area III', and form a first opening 504 penetrating the second electrode material layer 521 in the second electrode material layer 521. The remaining second electrode material layer 521 serves as the second electrode layer 503.

[0120] The second electrode material layer 521 is used to form the second electrode layer 503.

[0121] By forming a second electrode material layer 521 covering the input region I', the junction region III', and the output region II' on the substrate 500, and then removing a portion of the second electrode material layer 521 in the input region I' and the output region II', it is beneficial to improve the consistency of the thickness of the second electrode layer 503 formed on the substrate 500 in the input region I', the junction region III', and the output region II'; in addition, it is also beneficial to reduce the difficulty of forming the second electrode layer 503.

[0122] In this embodiment, the process for forming the second electrode material layer 521 includes atomic layer deposition (ALD) or physical vapor deposition (PVD). Using ALD or PVD improves the thickness uniformity of the second electrode material layer 521, thereby improving the thickness uniformity of the second electrode layer 503. In other embodiments, other deposition processes, such as chemical vapor deposition (CVD), can also be used to form the second electrode material.

[0123] In this embodiment, the second electrode layer 503 is also formed on the substrate 500 of the input region I' and the output region II', which helps to reduce the difficulty of electrically connecting the first conductive plug and the third conductive plug to the second electrode 503 respectively; in addition, it also helps to increase the area of ​​the second electrode layer 503 of the capacitor, thereby increasing the capacitance density.

[0124] In this embodiment, the material of the second electrode layer 503 is a conductive material. As an example, the material of the second electrode layer 503 includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0125] In this embodiment, the thickness of the second electrode layer 503 should not be too large or too small. The reasons for this are similar to those for the first electrode layer 501, and therefore will not be repeated here. Therefore, in this embodiment, the thickness of the second electrode layer 503 is between 10 nanometers and 100 nanometers.

[0126] refer to Figure 12 A second dielectric layer 505 is formed covering the second electrode layer 503.

[0127] The second dielectric layer 505 serves as an insulating layer in the formation of the MIM capacitor, and is used to isolate the second electrode layer 503 and the third electrode layer.

[0128] In this embodiment, the material of the second dielectric layer 505 is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to improve the capacitance density of the MIM capacitor.

[0129] In this embodiment, the material of the second dielectric layer 505 includes one or more of hafnium oxide, hafnium silicon oxide, titanium oxide, zirconium hafnium oxide, hafnium silicon nitride oxide, tantalum hafnium oxide, titanium hafnium oxide, tantalum oxide, zirconium oxide, zirconium silicon oxide, aluminum oxide, strontium titanate, and barium strontium titanate. As an example, the material of the second dielectric layer 505 is hafnium oxide.

[0130] In this embodiment, the process for forming the second dielectric layer 505 includes atomic layer deposition or chemical vapor deposition.

[0131] It should be noted that atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes have good filling performance, which allows the second dielectric layer 505 to be deposited into the first opening 504 more effectively.

[0132] refer to Figures 13 to 14 A third electrode layer 506 is formed on the second dielectric layer 505 of the junction area III', and the third electrode layer 506 is also located on the first electrode layer 501 at the location of the first opening 504.

[0133] The third electrode layer 506 is used as the electrode plate of the MIM capacitor.

[0134] In this embodiment, the third electrode layer 506 is located on the first electrode layer 501 at the first opening 504, which reduces the difficulty of achieving electrical connection between the third electrode layer 506 and the second conductive plug.

[0135] In this embodiment, in the step of forming the third electrode layer 506, the third electrode layer 506 is located on the second electrode layer 503 of the input region I', the ground region III' and the output region II', and the third electrode layer 506 has a second opening 511 located in the input region I' and the output region II' respectively and penetrating the third electrode layer 506.

[0136] It should be noted that the first electrode layer 501, the second electrode layer 503, and the third electrode layer 506 are all formed on the input region I', the grounding region III', and the output region II', which helps to increase the facing area between adjacent electrode layers of the capacitor, thereby increasing the capacitance density.

[0137] It should also be noted that the second opening 511 is used to provide space for the first conductive plug and the third conductive plug to form an electrical connection, while isolating the first conductive plug and the third conductive plug from the third electrode layer 506.

[0138] In this embodiment, in the step of forming the third electrode layer 506, the second opening 511 is located above the third opening 510 and corresponds one-to-one with the position of the third opening 510 in the input area I' or output area II', which helps to reduce the difficulty of the first conductive plug and the third conductive plug penetrating through the third electrode layer 506 and the first electrode layer 501 at the same time.

[0139] Specifically, the third electrode layer 506 is formed on the second electrode layer 503 of the input region I', the junction region III', and the output region II', and the step of forming the third electrode layer 506 includes: referencing Figure 13 A third electrode material layer 522 is formed on the second dielectric layer 505, covering the input region I', the ground region III', and the output region II'; Reference Figure 14 The third electrode material layer 522 in a portion of the input region I' and output region II' is removed, and a second opening 511 is formed in the third electrode material layer 522, which penetrates the third electrode material layer 522. The remaining third electrode material layer 522 serves as the third electrode layer 506.

[0140] The third electrode material layer 522 is used to form the third electrode layer 506.

[0141] By forming the third electrode layer 506 on the second electrode layer 503 of the input region I', the junction region III', and the output region II', and then removing the third electrode material layer 522 in a portion of the input region I' and the output region II', it is beneficial to improve the consistency of the thickness of the third electrode layer 506 formed on the substrate 500 of the input region I', the junction region III', and the output region II'; in addition, it is also beneficial to reduce the process difficulty of forming the third electrode layer 506.

[0142] In this embodiment, the process for forming the third electrode material layer 522 includes atomic layer deposition (ALD) or physical vapor deposition (PVD). Using ALD or PVD improves the thickness uniformity of the third electrode material layer 522, thereby improving the thickness uniformity of the third electrode layer 506. In other embodiments, other deposition processes, such as chemical vapor deposition (CVD), can also be used to form the third electrode material layer.

[0143] In this embodiment, the material of the third electrode layer 506 is a conductive material. As an example, the material of the third electrode layer 506 includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0144] In this embodiment, the thickness of the third electrode layer 506 should not be too large or too small. The reasons for this are similar to those for the first electrode layer 501, and will not be repeated here. Therefore, in this embodiment, the thickness of the third electrode layer 506 is 10 nanometers to 100 nanometers.

[0145] As an example, the first electrode layer 501, the second electrode layer 503, and the third electrode layer 506 have the same thickness.

[0146] Specifically, on the one hand, it can generate a uniform electric field among the first electrode layer 501, the second electrode layer 503, and the third electrode layer 506; on the other hand, it helps to reduce the complexity of the process.

[0147] In other embodiments, the thicknesses of the first electrode layer, the second electrode layer, and the third electrode layer may not be equal.

[0148] refer to Figures 15 to 16 A first conductive plug 507 is formed in the input area I', and the first conductive plug 507 is electrically connected to the second electrode layer 503.

[0149] It should be noted that, Figure 16 yes Figure 14 Top view after the formation of the first conductive plug, the second conductive plug, the third conductive plug, and the top interconnect layer. Figure 15 yes Figure 16 Sectional view at AA3.

[0150] The first conductive plug 507 is used for electrical connection to the second electrode layer 503.

[0151] In this embodiment, in the step of forming the first conductive plug 507, the first conductive plug 507 is located at the position of the second opening 511 of the input area I', and the second opening 511 exposes part of the second electrode layer 503 of the input area I', thereby facilitating the electrical connection between the first conductive plug 507 and the second electrode layer 503 of the input area I'.

[0152] In this embodiment, reference Figure 16 In the step of forming the first conductive plug 507, there are multiple first conductive plugs 507, and the multiple first conductive plugs 507 are arranged at intervals along the second direction x, which is perpendicular to the first direction y. This facilitates the formation of the first conductive plug 507 and the third conductive plug on both sides of the second conductive plug, and the second conductive plug serves as a ground terminal. When a current signal is applied to the first conductive plug 507 of the input area I', it is beneficial for the current to be transmitted through the first conductive plug 507 of the input area I' to the third conductive plug of the output area II'.

[0153] refer to Figures 15 to 16 A second conductive plug 508 is formed at the location of the first opening 504 in the junction area III', and the second conductive plug 508 is electrically connected to the first electrode layer 501 and the third electrode layer 503.

[0154] The second conductive plug 508 is used to electrically connect the first electrode layer 501 and the third electrode layer 506, and also serves as a grounding terminal.

[0155] In this embodiment, the second conductive plug 508 penetrates the third electrode layer 506 and the first dielectric layer 502 at the position of the first opening 504, and is electrically connected to the first electrode layer 501 and the third electrode layer 506. That is, the first electrode layer 501 and the third electrode layer 506 share the second conductive plug 508. Accordingly, it is beneficial to reduce the number of conductive plugs, thereby increasing the area of ​​the electrode layer of the capacitor and thus improving the capacitance density.

[0156] In this embodiment, in the step of forming the second conductive plug 508, the second conductive plug 508 penetrates the third electrode layer 506, the first electrode layer 501 and the substrate 500 above the bottom interconnect layer 512, and is electrically connected to the bottom interconnect layer 512.

[0157] It should be noted that, since the bottom interconnect layer 512 is located in the substrate 500 of the grounding region III', and the bottom interconnect layer 512 is used as the stopping position for forming the second conductive plug 508, the second conductive plug 508 penetrates the third electrode layer 506, the first electrode layer 501, the substrate 500, the first dielectric layer 501 and the second dielectric layer 505 above the bottom interconnect layer 512, and is electrically connected to the corresponding bottom interconnect layer 512.

[0158] In this embodiment, reference Figure 16 In the step of forming the second conductive plug 508, there are multiple second conductive plugs 508, and the multiple second conductive plugs 508 are arranged at intervals along the second direction x, which is perpendicular to the first direction y. It is beneficial that the formed second conductive plug 508 is located between the first conductive plug 507 and the third conductive plug, and the second conductive plug 508 serves as a ground terminal. When a current signal is applied to the first conductive plug 507 of the input area I, it is beneficial that the current can be transmitted through the first conductive plug 507 of the input area I' to the third conductive plug of the output area II'.

[0159] refer to Figures 15 to 16 A third conductive plug 509 is formed in the output area II', and the third conductive plug 509 is electrically connected to the second electrode layer 503.

[0160] The third conductive plug 509 is used for electrical connection to the second electrode layer 503.

[0161] In this embodiment, during the step of forming the third conductive plug 509, the third conductive plug 509 is located at the position of the second opening 511 of the output region II', and the second opening 511 exposes part of the second electrode layer 503 of the output region II', thereby facilitating the electrical connection between the third conductive plug 509 and the second electrode layer 503 of the output region II'.

[0162] In this embodiment, in the step of forming the first conductive plug 507 and the third conductive plug 509, the first conductive plug 507 and the third conductive plug 509 both penetrate the second electrode layer 503 and the substrate 500 above the bottom interconnect layer 512, and are electrically connected to the bottom interconnect layer 512.

[0163] It should be noted that, since the bottom interconnect layer 112 is located in the substrate 500 of the input region I' and the output region II', and the bottom interconnect layer 512 is used as the etching stop position for forming the first conductive plug 507 and the third conductive plug 509, the first conductive plug 507 and the third conductive plug 509 both penetrate the second electrode layer 503 and the substrate 500 above the bottom interconnect layer 512, and are electrically connected to the corresponding bottom interconnect layer 512.

[0164] In this embodiment, reference Figure 16 In the step of forming the third conductive plug 509, there are multiple third conductive plugs 509, and the multiple third conductive plugs 509 are arranged at intervals along the second direction x, which is perpendicular to the first direction y. This facilitates the formation of the third conductive plug 509 and the first conductive plug 507 located on both sides of the second conductive plug 508, and the second conductive plug 508 serves as a ground terminal. When a current signal is applied to the first conductive plug 507 of the input region I', it is beneficial for the current to be transmitted through the first conductive plug 507 of the input region I' to the third conductive plug 509 of the output region II'.

[0165] In this embodiment, the first conductive plug 507, the second conductive plug 508, and the third conductive plug 509 are formed in the same step, which helps to reduce process steps and lower process costs.

[0166] It should be noted that, since the first conductive plug 507 of the input region I' and the third conductive plug 509 of the output region II' are only electrically connected to the second electrode layer 503, and the second conductive plug 508 is used as a ground terminal, when a current signal is applied to the first conductive plug 507 of the input region I', the current can be transmitted through the first conductive plug 507 of the input region I' to the third conductive plug 509 of the output region II', that is, the current flows in and out from the second electrode layer 503, avoiding the current from passing through unnecessary paths. Therefore, the equivalent inductance of the second electrode layer 503 can be ignored, thereby reducing the equivalent inductance of the entire capacitor and thus improving the performance of the semiconductor structure.

[0167] refer to Figures 15 to 16 The method for forming the semiconductor structure further includes: forming a top interconnect layer 513 on the top of the first conductive plug 507, the second conductive plug 508, and the third conductive plug 509, respectively, wherein the top interconnect layer 513 is electrically connected to the corresponding first conductive plug 507, the second conductive plug 508, or the third conductive plug 509.

[0168] The top interconnect layer 513 is used to apply voltage to the first electrode layer 501, the second electrode layer 503 and the third electrode layer 506, thereby realizing the MIM capacitor composed of the first electrode layer 501, the second electrode layer 503 and the third electrode layer 506.

[0169] In this embodiment, reference Figure 16In the step of forming the top interconnect layer 513, the top interconnect layer 513 electrically connected to the first conductive plug 507 includes: a first comb tooth portion 515, extending along the first direction y and spaced apart along the second direction x, the first comb tooth portion 515 being electrically connected to each of the first conductive plugs 507; and a first comb handle portion 514, located on the side of the first comb tooth portion 515 away from the contact area III', the first comb handle portion 514 extending along the second direction x and connected to each of the first comb tooth portions 515.

[0170] The top interconnect layer 513, which is electrically connected to the first conductive plug 507, is arranged in the form of a first comb handle portion 514 and a plurality of first comb teeth portions 515. This is beneficial to make the voltage applied to the second electrode layer 503 of the input area I' by the top interconnect layer 513 electrically connected to the first conductive plug 507 more uniform. Moreover, the comb-shaped top interconnect layer 513 electrically connected to the first conductive plug 507 is beneficial to reducing the area of ​​the metal layer.

[0171] In this embodiment, reference Figure 16 In the step of forming the top interconnect layer 513, the top interconnect layer 513 electrically connected to the third conductive plug 509 includes: a second comb tooth portion 516 extending along the first direction y and spaced apart along the second direction x, the second comb tooth portion 516 being electrically connected to each of the third conductive plugs 509; and a second comb handle portion 517 located on the side of the second comb tooth portion 516 away from the contact area III', the second comb handle portion 517 extending along the second direction x and connected to each of the second comb tooth portions 516.

[0172] The top interconnect layer 513 electrically connected to the third conductive plug 509 is arranged in the form of a second comb handle portion 517 and multiple second comb teeth portions 516. This arrangement facilitates a more uniform voltage distribution on the second electrode layer 503 of the output region II' by the top interconnect layer 513 electrically connected to the third conductive plug 509. Furthermore, the comb-shaped top interconnect layer 513 electrically connected to the third conductive plug 509 helps to reduce the metal layer area and allows space between the top interconnect layer 513 electrically connected to the third conductive plug 509 and the top interconnect layer 513 electrically connected to the first conductive plug 507. Specifically, the first comb handle portion 514 and the second comb handle portion 517 are parallel to each other, and the first comb teeth portion 515 corresponds to the second comb teeth portion 516. This allows the top interconnect layer 513 electrically connected to the third conductive plug 509 and the top interconnect layer 513 electrically connected to the first conductive plug 507 to fully utilize the formed space, resulting in a higher pattern density and saving space without mutual interference.

[0173] In this embodiment, during the step of forming the top interconnect layer 513, the top interconnect layer 513 electrically connected to the second conductive plug 508 extends along the second direction x and connects to each of the second conductive plugs 508. This facilitates the top interconnect layer 513 electrically connected to the second conductive plug 508 to simultaneously apply the same voltage to the first electrode layer 501 and the third electrode layer 506. It also facilitates the top interconnect layer 513 electrically connected to the third conductive plug 509, the top interconnect layer 513 electrically connected to the first conductive plug 507, and the top interconnect layer 513 electrically connected to the second conductive plug 508 to apply the same voltage to both the first electrode layer 501 and the third electrode layer 506. The top interconnect layers 513 electrically connected to the conductive plugs 508 leave space between each other. Specifically, the top interconnect layers 513 electrically connected to the second conductive plug 508, the first comb handle portion 514, and the second comb handle portion 517 are parallel to each other. Then, the top interconnect layers 513 electrically connected to the third conductive plug 509, the first conductive plug 507, and the second conductive plug 508 can make full use of the formed space, resulting in a higher pattern density and saving space area without mutual interference.

[0174] It should be noted that the semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0175] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including an input area, an output area, and a junction area located between the input area and the output area; A first electrode layer is located on the substrate of the grounding area, and the first electrode layer has a third opening located in the input area and the output area respectively and penetrating the first electrode layer; A first dielectric layer is located on the first electrode layer; A second electrode layer is located on the first dielectric layer and also on the substrate of the input and output regions. The second electrode layer has a first opening located in the junction area and penetrating the second electrode layer. The second dielectric layer is located on the second electrode layer; The third electrode layer is located on the second dielectric layer of the junction area and also on the first electrode layer at the first opening position; The first conductive plug is located in the input area and is electrically connected to the second electrode layer; The second conductive plug is located at the first opening of the contact area and is electrically connected to the first electrode layer and the third electrode layer. The third conductive plug is located in the output area and is electrically connected to the second electrode layer.

2. The semiconductor structure as described in claim 1, characterized in that, The bottom of the first opening exposes the first dielectric layer; The second conductive plug penetrates the third electrode layer and the first dielectric layer at the location of the first opening, and is electrically connected to the first electrode layer and the third electrode layer.

3. The semiconductor structure as described in claim 1, characterized in that, The first electrode layer is located on the substrate of the input region, the junction region, and the output region; The third electrode layer is located on the second electrode layer of the input area, the ground area and the output area. The third electrode layer has a second opening located in the input area and the output area respectively and penetrating the third electrode layer. The first conductive plug is located at the position of the second opening in the input area; The third conductive plug is located at the position of the second opening in the output area.

4. The semiconductor structure as described in claim 3, characterized in that, The second electrode layer is located on the first electrode layer and on the substrate at the bottom of the third opening; The second opening is located above the third opening, and corresponds one-to-one with the position of the third opening in the input or output area. The semiconductor structure further includes: a bottom interconnect layer, located in the substrate at the bottom of the first opening and the third opening, respectively; Both the first conductive plug and the third conductive plug penetrate the second electrode layer and the substrate above the bottom interconnect layer, and are electrically connected to the corresponding bottom interconnect layer; The second conductive plug penetrates the third electrode layer, the first electrode layer, and the substrate above the bottom interconnect layer, and is electrically connected to the corresponding bottom interconnect layer.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a top interconnect layer, which is located on top of the first conductive plug, the second conductive plug, and the third conductive plug, and is electrically connected to the corresponding first conductive plug, the second conductive plug, or the third conductive plug.

6. The semiconductor structure as described in claim 5, characterized in that, The input area, the junction area, and the output area are arranged sequentially along the first direction; The number of the first conductive plugs is multiple, and the multiple first conductive plugs are arranged at intervals along the second direction, which is perpendicular to the first direction; The top interconnect layer electrically connected to the first conductive plug includes: a first comb tooth portion extending along the first direction and spaced apart along the second direction, wherein the first comb tooth portion is electrically connected to each of the first conductive plugs; The first comb handle portion is located on the side of the first comb teeth portion away from the contact area. The first comb handle portion extends along the second direction and connects to each of the first comb teeth portions.

7. The semiconductor structure as described in claim 5, characterized in that, The input area, the junction area, and the output area are arranged sequentially along the first direction; The number of the third conductive plugs is multiple, and the multiple third conductive plugs are arranged at intervals along the second direction, which is perpendicular to the first direction; The top interconnect layer electrically connected to the third conductive plug includes: a second comb portion extending along the first direction and spaced apart along the second direction, wherein the second comb portion is electrically connected to each of the third conductive plugs; The second comb handle is located on the side of the second comb teeth away from the contact area. The second comb handle extends along the second direction and connects to each of the second comb teeth.

8. The semiconductor structure as described in claim 5, characterized in that, The input area, the junction area, and the output area are arranged sequentially along the first direction; The number of the second conductive plugs is multiple, and the multiple second conductive plugs are arranged at intervals along a second direction, which is perpendicular to the first direction; A top interconnect layer electrically connected to the second conductive plug extends along the second direction and connects each of the second conductive plugs.

9. The semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric layer includes one or more of hafnium oxide, hafnium silicon oxide, titanium oxide, hafnium zirconium oxide, hafnium silicon nitride, hafnium tantalum oxide, hafnium titanium oxide, tantalum oxide, zirconium oxide, zirconium silicon oxide, aluminum oxide, strontium titanate, and strontium barium titanate; The material of the second dielectric layer includes one or more of hafnium oxide, hafnium silicon oxide, titanium oxide, zirconium hafnium oxide, hafnium silicon nitride oxide, tantalum hafnium oxide, titanium hafnium oxide, tantalum oxide, zirconium oxide, zirconium silicon oxide, aluminum oxide, strontium titanate, and barium strontium titanate; The material of the first electrode layer includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum; The material of the second electrode layer includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum; The material of the third electrode layer includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

10. The semiconductor structure as claimed in claim 1, characterized in that, The thickness of any one of the first electrode layer, the second electrode layer, and the third electrode layer is between 10 nanometers and 100 nanometers.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an input area, an output area, and a junction area located between the input area and the output area; A first electrode layer is formed on the substrate of the contact area, and the first electrode layer has a third opening located in the input area and the output area respectively and penetrating the first electrode layer; A first dielectric layer is formed covering the first electrode layer; A second electrode layer is formed on the first dielectric layer, and the second electrode layer is also formed on the substrate of the input region and the output region. The second electrode layer has a first opening located in the ground region and penetrating the second electrode layer. A second dielectric layer is formed covering the second electrode layer; A third electrode layer is formed on the second dielectric layer of the contact area, and the third electrode layer is also located on the first electrode layer at the first opening position; A first conductive plug is formed in the input area, and the first conductive plug is electrically connected to the second electrode layer; A second conductive plug is formed at the location of the first opening in the contact area, and the second conductive plug is electrically connected to the first electrode layer and the third electrode layer. A third conductive plug is formed in the output area, and the third conductive plug is electrically connected to the second electrode layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the second electrode layer, the bottom of the first opening exposes the first dielectric layer; In the step of forming the second conductive plug, the second conductive plug penetrates the third electrode layer and the first dielectric layer at the location of the first opening, and is electrically connected to the first electrode layer and the third electrode layer.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the second electrode layer includes: forming a second electrode material layer on the first dielectric layer that covers the input region, the junction region and the output region; A portion of the second electrode material layer in the contact area is removed, and a first opening is formed in the second electrode material layer that penetrates the second electrode material layer. The remaining second electrode material layer serves as the second electrode layer.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, The first electrode layer is formed on the substrate of the input region, the junction region, and the output region; In the step of forming the third electrode layer, the third electrode layer is located on the second electrode layer of the input region, the junction region and the output region, and the third electrode layer has a second opening located in the input region and the output region respectively and penetrating the third electrode layer; In the step of forming the first conductive plug, the first conductive plug is located at the position of the second opening of the input area; In the step of forming the third conductive plug, the third conductive plug is located at the position of the second opening of the output area.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The third electrode layer is formed on the second electrode layer of the input area, the junction area, and the output area, and the step of forming the third electrode layer includes: forming a third electrode material layer covering the input area, the junction area, and the output area on the second dielectric layer; removing a portion of the third electrode material layer in the input area and the output area; forming a second opening penetrating the third electrode material layer in the third electrode material layer; and the remaining third electrode material layer serving as the third electrode layer.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of providing the substrate, a bottom interconnect layer is formed in the substrate, and the bottom interconnect layer is located in the input area, the junction area and the output area respectively; In the step of forming the first electrode layer, the third opening is located above the top of the bottom interconnect layer; The second electrode layer is formed on the first electrode layer and on the substrate at the bottom of the third opening, and the first opening is located above the top of the bottom interconnect layer; In the step of forming the third electrode layer, the second opening is located above the third opening and corresponds one-to-one with the position of the third opening in the input area or output area. In the step of forming the first conductive plug and the third conductive plug, both the first conductive plug and the third conductive plug penetrate the second electrode layer and the substrate above the bottom interconnect layer, and are electrically connected to the bottom interconnect layer; In the step of forming the second conductive plug, the second conductive plug penetrates the third electrode layer, the first electrode layer and the substrate above the bottom interconnect layer, and is electrically connected to the bottom interconnect layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The step of forming the first electrode layer on the substrate of the input region, the ground region and the output region includes: forming a first electrode material layer covering the input region, the ground region and the output region on the substrate; A portion of the first electrode material layer in the input and output regions is removed, and a third opening is formed in the first electrode material layer that penetrates the first electrode material layer. The remaining first electrode material layer serves as the first electrode layer.

18. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the semiconductor structure further includes: forming a top interconnect layer on the top of the first conductive plug, the second conductive plug, and the third conductive plug, respectively, wherein the top interconnect layer is electrically connected to the corresponding first conductive plug, the second conductive plug, or the third conductive plug.

19. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing the substrate, the input area, the junction area, and the output area are arranged sequentially along a first direction; In the step of forming the first conductive plug, there are multiple first conductive plugs, and the multiple first conductive plugs are arranged at intervals along the second direction, which is perpendicular to the first direction; In the step of forming the top interconnect layer, the top interconnect layer electrically connected to the first conductive plug includes: a first comb portion, extending along the first direction and spaced apart along the second direction, wherein the first comb portion is electrically connected to each of the first conductive plugs; The first comb handle portion is located on the side of the first comb teeth portion away from the contact area. The first comb handle portion extends along the second direction and connects to each of the first comb teeth portions.

20. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing the substrate, the input area, the junction area, and the output area are arranged sequentially along a first direction; In the step of forming the third conductive plug, there are multiple third conductive plugs, and the multiple third conductive plugs are arranged at intervals along the second direction, which is perpendicular to the first direction; In the step of forming the top interconnect layer, the top interconnect layer electrically connected to the third conductive plug includes: a second comb portion extending along the first direction and spaced apart along the second direction, wherein the second comb portion is electrically connected to each of the third conductive plugs; The second comb handle is located on the side of the second comb teeth away from the contact area. The second comb handle extends along the second direction and connects to each of the second comb teeth.

21. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing the substrate, the input area, the junction area, and the output area are arranged sequentially along a first direction; In the step of forming the second conductive plug, there are multiple second conductive plugs, and the multiple second conductive plugs are arranged at intervals along a second direction, the second direction being perpendicular to the first direction; In the step of forming the top interconnect layer, the top interconnect layer, which is electrically connected to the second conductive plug, extends along the second direction and connects each of the second conductive plugs.

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