A method of fabricating a field effect transistor and a structure

Abstract

The application discloses a manufacturing method and structure of a field effect transistor. The body region is divided into several parts, the concentration of the body region near the source region is increased, and the resistance of a parasitic transistor is reduced. The gate is extended, the current path is limited, and the opening of the parasitic transistor is prevented. The application effectively increases the avalanche resistance of the device. Meanwhile, the body region with different concentrations corresponds to the gate dielectric layer with different dielectric constants, the opening voltage is kept consistent, and the on-resistance is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, specifically a method and structure for manufacturing a field-effect transistor. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in various power systems due to their advantages such as fast switching speed, low power consumption, easy gate drive, low drive power, high input impedance, and fast frequency response. In these systems, the reliability of the device directly affects the system's stability, safety, and cost-effectiveness, thus becoming one of the important indicators for evaluating the performance of power devices.

[0003] In practical applications, when a MOSFET switches from the on state to the off state, if the load is an unclamped inductive load, the energy stored in the inductor must be released instantaneously through the power MOSFET. During this process, the device often experiences both high voltage and high current simultaneously, making it highly susceptible to failure. This failure mode is known as unclamped inductive switching (UIS) failure. Therefore, the UIS resilience of power MOSFETs is widely regarded as a key criterion for evaluating their reliability, and avalanche withstand capability is an important parameter for quantitatively characterizing UIS resilience.

[0004] To improve avalanche tolerance, the industry commonly employs increasing the body doping concentration to suppress the turn-on of parasitic bipolar transistors (BJTs). However, this method is limited by parameters such as threshold voltage and gate capacitance, resulting in relatively limited improvements and making it difficult to significantly enhance UIS (Underlying Switching) capability while meeting on-resistance and switching performance requirements. Therefore, developing a MOSFET manufacturing method that effectively improves avalanche tolerance, suppresses parasitic BJT turn-on, and does not significantly affect threshold voltage and on-resistance has become a pressing technical problem in this field. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing a field-effect transistor, comprising the following steps:

[0006] Step 1) Generate a first conductivity type semiconductor drift region on the upper surface of the substrate.

[0007] Step 2) Form a first trench in the first conductivity type semiconductor drift region and form a first gate dielectric layer in the first trench.

[0008] Step 3) Polysilicon is deposited on the first gate dielectric layer and a portion of the polysilicon is etched away to form a gate polysilicon electrode.

[0009] Step 4) Etch the first gate dielectric layer so that the first gate dielectric layer is level with the extended gate.

[0010] Step 5) Deposit the second gate dielectric layer and partially etch the second gate dielectric layer located at the edge of the first trench.

[0011] The second body region of the second conductivity type semiconductor is filled so that the second body region of the second conductivity type semiconductor is flush with the silicon surface.

[0012] Step 6) Ion implantation and push junction are performed on the side of the first conductivity type semiconductor drift region away from the substrate to form the second conductivity type first body region.

[0013] Step 7) Ion implantation and push junction are performed on the side of the second conductivity type first body region and the second conductivity type semiconductor second body region away from the first conductivity type semiconductor drift region to form the first conductivity type semiconductor source region.

[0014] Step 8) Passivate the gate polysilicon electrode and the first conductivity type semiconductor source region to form a gate-source dielectric layer.

[0015] A contact hole and a second trench are formed in a portion of the first body region of the second conductivity type. Ion implantation is performed on the second trench to form a semiconductor ohmic contact region of the second conductivity type.

[0016] Step 9) Deposit metal on the gate-source dielectric layer and the ohmic contact region of the second conductivity type semiconductor to form a source metal layer.

[0017] Metal is deposited on the lower surface of the substrate to form a drain metal layer.

[0018] Furthermore, the step of forming the first trench within the drift region of the first conductivity type semiconductor includes:

[0019] A mask layer is generated by applying a mask to the drift region of a semiconductor of the first conductivity type.

[0020] The mask layer is coated, exposed, and developed to determine the location of the first trench.

[0021] The mask layer and the first conductivity type semiconductor drift region are etched to obtain the first trench.

[0022] Furthermore, the method for forming the first gate dielectric layer in the first trench is as follows: thermal oxidation growth is performed on the first trench to form the first gate dielectric layer.

[0023] Furthermore, the doping concentration of the second body region of the second conductivity type semiconductor is greater than that of the first body region of the second conductivity type.

[0024] Furthermore, the first body region of the second conductivity type is lightly doped, while the second body region of the second conductivity type semiconductor is heavily doped.

[0025] Light doping refers to impurity concentrations on the order of 1e16cm. -3 Doping levels of 1e16cm and below, with heavy doping defined as impurity concentrations greater than 1e16cm. -3 Doping.

[0026] Furthermore, the cross-sectional shape of the gate polycrystalline silicon electrode is an inverted T-shape, with the lower part being wider than the upper part.

[0027] Furthermore, the second gate dielectric layer is a high dielectric constant dielectric layer.

[0028] Furthermore, the second gate dielectric layer is an oxide layer, and its thickness is less than that of the first gate dielectric layer.

[0029] Furthermore, the first gate dielectric layer is an oxide layer.

[0030] A field-effect transistor structure is fabricated by the method described above.

[0031] The technical effects of this invention are undeniable. By partitioning the body region, this invention increases the body region concentration near the source region, reducing the resistance of the parasitic transistor; and by extending the gate, it restricts the current path, thereby preventing the parasitic transistor from turning on. This invention effectively increases the avalanche tolerance of the device. Simultaneously, different body region concentrations correspond to gate dielectric layers with different dielectric constants, ensuring a consistent turn-on voltage and reducing on-resistance. Attached Figure Description

[0032] Figure 1 A cross-sectional view of a field-effect transistor is shown as an exemplary embodiment of the present invention;

[0033] Figure 2-14 A method for manufacturing a field-effect transistor is shown as an exemplary embodiment of the present invention;

[0034] Explanation of reference numerals in the attached figures: 1-Drain metal layer, 2-Substrate, 3-First conductivity type semiconductor drift region, 4-First bulk region, 5-Second conductivity type semiconductor ohmic contact region, 6-First conductivity type semiconductor source region, 7-Second bulk region, 8-Gate polysilicon electrode, 9-First gate dielectric layer, 10-Second gate dielectric layer, 11-Gate-source dielectric layer, 12-Source metal layer. Detailed Implementation

[0035] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.

[0036] Example 1:

[0037] A method for manufacturing a field-effect transistor includes the following steps:

[0038] Step 1 generates a first conductivity type semiconductor drift region 3 on the upper surface of substrate 2.

[0039] Step 2: A first trench is formed in the first conductivity type semiconductor drift region 3, and a first gate dielectric layer 9 is formed in the first trench.

[0040] Step 3 involves depositing polysilicon on the first gate dielectric layer 9 and etching away a portion of the polysilicon to form the gate polysilicon electrode 8.

[0041] Step 4: Etch the first gate dielectric layer 9 so that the first gate dielectric layer 9 is horizontal with the extended gate.

[0042] Step 5: Deposit the second gate dielectric layer 10 and partially etch the second gate dielectric layer 10 located at the edge of the first trench.

[0043] The second body region 7 of the second conductivity type semiconductor is filled so that the second body region 7 of the second conductivity type semiconductor is flush with the silicon surface.

[0044] Step 6 involves ion implantation and push-bonding on the side of the first conductivity type semiconductor drift region 3 away from the substrate 2 to form the second conductivity type first body region 4.

[0045] Step 7 involves ion implantation and push-junction on the side of the second conductivity type first body region 4 and the second conductivity type semiconductor second body region 7 away from the first conductivity type semiconductor drift region 3 to form the first conductivity type semiconductor source region 6.

[0046] Step 8 as follows Figure 13 As shown, passivation is performed on the gate polysilicon electrode 8 and the first conductivity type semiconductor source region 6 to form a gate-source dielectric layer 11.

[0047] A contact hole and a second trench are formed in a portion of the first body region 4 of the second conductivity type. Ion implantation is performed on the second trench to form a semiconductor ohmic contact region 5 of the second conductivity type.

[0048] Step 9 as follows Figure 14 As shown, a source metal layer 12 is formed by depositing metal on the gate-source dielectric layer 11 and the second conductivity type semiconductor ohmic contact region 5.

[0049] Metal is deposited on the lower surface of the substrate to form a drain metal layer 11.

[0050] Example 2:

[0051] A method for manufacturing a field-effect transistor, with the same technical content as in Embodiment 1, includes the step of forming a first trench within a first conductivity type semiconductor drift region 3, comprising:

[0052] A mask layer is generated by performing a masking process on the first conductivity type semiconductor drift region 3.

[0053] The mask layer is coated, exposed, and developed to determine the location of the first trench.

[0054] The mask layer and the first conductivity type semiconductor drift region are etched to obtain the first trench.

[0055] Example 3:

[0056] A method for manufacturing a field-effect transistor, with the same technical content as any one of Embodiments 1-2, wherein the method for forming a first gate dielectric layer 9 in a first trench is: thermally oxidizing the first trench to form the first gate dielectric layer 9.

[0057] Example 4:

[0058] A method for manufacturing a field-effect transistor, the technical content of which is the same as any one of embodiments 1-3, wherein the doping concentration of the second body region 7 of the second conductivity type semiconductor is greater than that of the first body region 4 of the second conductivity type.

[0059] Example 5:

[0060] A method for manufacturing a field-effect transistor, the technical content of which is the same as any one of embodiments 1-4, wherein the first body region 4 of the second conductivity type is lightly doped and the second body region 7 of the second conductivity type semiconductor is heavily doped.

[0061] Light doping refers to impurity concentrations on the order of 1e16cm. -3 Doping levels of 1e16cm and below, with heavy doping defined as impurity concentrations greater than 1e16cm. -3 Doping.

[0062] Example 6:

[0063] A method for manufacturing a field-effect transistor, the technical content of which is the same as any one of embodiments 1-5, wherein the cross-sectional shape of the gate polysilicon electrode 8 is an inverted T-shape, and the width of the lower part is greater than the width of the upper part.

[0064] Example 7:

[0065] A method for manufacturing a field-effect transistor, the technical content of which is the same as any one of embodiments 1-6, wherein the second gate dielectric layer 10 is a high dielectric constant dielectric layer.

[0066] Example 8:

[0067] A method for manufacturing a field-effect transistor, the technical content of which is the same as any one of embodiments 1-7, wherein the second gate dielectric layer 10 is an oxide layer and its thickness is less than that of the first gate dielectric layer 9.

[0068] Example 9:

[0069] A method for manufacturing a field-effect transistor, the technical content of which is the same as any one of embodiments 1-8, wherein the first gate dielectric layer 9 is an oxide layer.

[0070] Example 10:

[0071] A field-effect transistor structure is manufactured by the method described in any one of Examples 1-9.

[0072] Example 11:

[0073] A method for manufacturing a field-effect transistor includes the following steps:

[0074] A substrate is provided, the substrate including a front side and a back side disposed opposite to each other, and a first conductivity type semiconductor drift region is formed on the front side of the substrate;

[0075] A first trench is formed in the first conductivity type semiconductor drift region, and a first dielectric layer is formed in the first trench;

[0076] Polysilicon is deposited on the dielectric layer, and a portion of the polysilicon is etched away to form a gate polysilicon electrode;

[0077] Etch the first dielectric layer to make it level with the extended gate;

[0078] A high-K second dielectric layer is deposited, and a portion of the second dielectric layer at the edge of the first trench is etched.

[0079] The second body region of the semiconductor of the second conductivity type is flush with the silicon surface;

[0080] Ion implantation and push-junction are performed on the side of the first conductivity type semiconductor drift region away from the substrate to form a second conductivity type first body region;

[0081] Ion implantation and push-junction are performed on the side of the first and second body regions away from the body drift region to form a semiconductor source region of the first conductivity type.

[0082] Passivation is performed on the gate polysilicon electrode and the semiconductor source region of the first conductivity type to form an inter-gate source dielectric layer;

[0083] A contact hole and a second trench are formed in a portion of the upper region of the first body region. Ion implantation is performed on the second trench to form a semiconductor ohmic contact region of the second conductivity type.

[0084] Metal is deposited on the gate-source dielectric layer and the second conductivity type semiconductor ohmic contact region to form a source metal layer;

[0085] Metal is deposited on the back side of the substrate to form a drain metal layer;

[0086] The step of forming a first trench within the drift region of the first conductivity type semiconductor and forming an oxide layer within the first trench includes:

[0087] A mask layer is generated by performing a masking process on the drift region of the first conductivity type semiconductor.

[0088] The mask layer is coated, exposed, and developed to determine the position of the first trench;

[0089] The first trench is obtained by etching the mask layer and the first conductivity type semiconductor drift region.

[0090] The first trench is subjected to thermal oxidation growth to form the oxide layer.

[0091] Example 12:

[0092] A field-effect transistor is manufactured in the same way as in Example 11, except that the doping concentration of the second body region of the field-effect transistor is higher than that of the first body region, the first body region is lightly doped and the second body region is heavily doped.

[0093] The width of the lower portion of the gate is greater than the width of the upper portion.

[0094] The first gate dielectric layer enclosing the first body region is an oxide layer. The gate dielectric layer is a high-k dielectric layer, or an oxide layer thinner than the first dielectric layer.

[0095] The first type of conductivity semiconductor is doped with an N-type semiconductor, and the second type of conductivity semiconductor is a P-type semiconductor; or the first type of conductivity semiconductor is doped with a P-type semiconductor, and the second type of conductivity semiconductor is an N-type semiconductor.

[0096] The light doping refers to doping with an impurity concentration of 1e16cm-3 or less, and the heavy doping refers to doping with an impurity concentration greater than 1e16cm-3.

Claims

1. A method for manufacturing a field-effect transistor, characterized in that, Includes the following steps: Step 1) A first conductivity type semiconductor drift region (3) is generated on the upper surface of the substrate (2); Step 2) A first trench is formed in the first conductivity type semiconductor drift region (3), and a first gate dielectric layer (9) is formed in the first trench; Step 3) Polysilicon is deposited on the first gate dielectric layer (9), and part of the polysilicon is etched away to form a gate polysilicon electrode (8). Step 4) Etch the first gate dielectric layer (9) to keep the first gate dielectric layer (9) horizontal with the gate polysilicon electrode (8); Step 5) Deposit the second gate dielectric layer (10) and partially etch the second gate dielectric layer (10) located at the edge of the first trench to form the second body region (7) of the second conductivity type semiconductor. The second conductivity type semiconductor second body region (7) is filled so that the second conductivity type semiconductor second body region (7) is flush with the surface of the gate polysilicon electrode (8); Step 6) Ion implantation and push junction are performed on the side of the first conductivity type semiconductor drift region (3) away from the substrate (2) to form the second conductivity type first body region (4). Step 7) Ion implantation and push junction are performed on the side of the second conductivity type first body region (4) and the second conductivity type semiconductor second body region (7) away from the first conductivity type semiconductor drift region (3) to form the first conductivity type semiconductor source region (6). Step 8) Passivate the gate polysilicon electrode (8) and the first conductivity type semiconductor source region (6) to form a gate-source dielectric layer (11). A contact hole and a second trench are formed in a portion of the first body region (4) of the second conductivity type. Ion implantation is performed on the second trench to form a semiconductor ohmic contact region (5) of the second conductivity type. Step 9) Deposit metal on the gate-source dielectric layer (11) and the second conductivity type semiconductor ohmic contact region (5) to form a source metal layer (12). Metal is deposited on the lower surface of the substrate to form a drain metal layer (11).

2. A method for manufacturing a field-effect transistor according to claim 1, characterized in that, The step of forming the first trench within the first conductivity type semiconductor drift region (3) includes: A mask layer is generated by performing a masking process on the first conductivity type semiconductor drift region (3); The mask layer is coated, exposed, and developed to determine the location of the first trench; The mask layer and the first conductivity type semiconductor drift region are etched to obtain the first trench.

3. A method for manufacturing a field-effect transistor according to claim 1, characterized in that, The method for forming the first gate dielectric layer (9) in the first trench is as follows: thermal oxidation growth is performed on the first trench to form the first gate dielectric layer (9).

4. A method for manufacturing a field-effect transistor according to claim 1, characterized in that, The doping concentration of the second body region (7) of the second conductivity type semiconductor is greater than that of the first body region (4) of the second conductivity type.

5. A method for manufacturing a field-effect transistor according to claim 1, characterized in that, The first body region (4) of the second conductivity type semiconductor is lightly doped, and the second body region (7) of the second conductivity type semiconductor is heavily doped; Light doping refers to impurity concentrations on the order of 1e16cm. -3 Doping levels of 1e16cm and below, with heavy doping defined as impurity concentrations on the order of 1e16cm. -3 Doping.

6. A method for manufacturing a field-effect transistor according to claim 1, characterized in that, The cross-sectional shape of the gate polycrystalline silicon electrode (8) is an inverted T-shape, with the width of the lower part being greater than the width of the upper part.

7. A method for manufacturing a field-effect transistor according to claim 1, characterized in that, The second gate dielectric layer (10) is a high dielectric constant dielectric layer.

8. A method for manufacturing a field-effect transistor according to claim 1, characterized in that, The second gate dielectric layer (10) is an oxide layer and its thickness is less than that of the first gate dielectric layer (9).

9. A method for manufacturing a field-effect transistor according to claim 1, characterized in that, The first gate dielectric layer (9) is an oxide layer.

10. A field-effect transistor structure, characterized in that, It is manufactured by the method described in any one of claims 1-9.

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