Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, which comprises the following steps: providing a substrate; forming an epitaxial layer on one side of the substrate; forming a current spreading layer in the epitaxial layer, the current spreading layer comprises a low-concentration doped area and a high-concentration doped area arranged in sequence along a thickness direction, the high-concentration doped area is located on a side close to the substrate, and the low-concentration doped area is located on a side away from the substrate; forming a patterned first mask layer on the surface of the current spreading layer, and forming a junction field effect transistor area in the low-concentration doped area based on the first mask layer; forming a second mask layer in the first mask opening area and removing the first mask layer; forming a well area in the current spreading layer based on the second mask layer, and the junction field effect transistor area is located between adjacent well areas. The method realizes independent regulation and control of the doping of the junction field effect transistor area and the well area, avoids overlaying error, and improves the conduction performance of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are gradually replacing traditional silicon-based MOSFETs and are widely used in power electronics due to their superior performance under high voltage, high frequency, and high temperature conditions. The on-resistance Rds(on) of the device is an important parameter for measuring its conduction loss and directly affects system efficiency and heat dissipation performance.

[0003] The on-resistance of a SiC MOSFET is typically composed of multiple resistance components connected in series, including the channel resistance Rch, the accumulation layer resistance Ra, the junction field-effect transistor (JFET) region resistance Rj, the drift region resistance Re, the substrate resistance Rbd, and the contact resistances Rcs and Rcd. Among these, the JFET region resistance Rj, formed by the narrow conductive area between adjacent cells, is one of the important components affecting the device's conduction performance.

[0004] To reduce the on-resistance of devices, optimization is typically achieved by adjusting the doping concentration in each region. In existing processes, the current spread layer is usually formed by full-area implantation. The doping concentration in the JFET region is mainly determined by the epitaxial layer (EPI) concentration and the current spread layer implantation concentration, while the net doping concentration in the channel region is compensated by the EPI concentration, the current spread layer implantation, and the well region implantation.

[0005] Furthermore, in the prior art, when the doping concentration of the JFET region is optimized by adjusting the current spread layer injection parameters, the net doping distribution of the well region will inevitably change, thereby affecting the channel resistance and threshold voltage. This results in doping control coupling between the JFET region and the channel region, making it difficult to achieve independent optimization of the doping of the JFET region.

[0006] Furthermore, if patterned injection of the JFET region is used to achieve independent control, an additional photolithography step is usually required, which can easily lead to overlay errors, resulting in displacement of the injection region, affecting device performance or even causing failure.

[0007] Therefore, there is an urgent need for a semiconductor structure and its fabrication method that can achieve independent control of doping in the JFET region, reduce the resistance of the JFET region, avoid affecting the electrical characteristics of the well region, and reduce overlay errors. Summary of the Invention

[0008] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems of mutual coupling between JFET region doping and well region doping in the existing technology, which makes it difficult to control independently and the patterned implantation has overlay errors.

[0009] To achieve the above objectives, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0010] Provide a substrate of the first conductivity type;

[0011] An epitaxial layer of a first conductivity type is formed on one side of the substrate;

[0012] A current spreading layer of a first conductivity type is formed within the epitaxial layer; the current spreading layer includes a low-concentration doped region and a high-concentration doped region, the low-concentration doped region and the high-concentration doped region being sequentially disposed in the thickness direction of the substrate, the high-concentration doped region being located on the side of the current spreading layer closer to the substrate, and the low-concentration doped region being located on the side of the current spreading layer away from the substrate.

[0013] A patterned first mask layer is formed on the side of the current spreading layer away from the substrate;

[0014] Based on the patterned first mask layer, a junction field-effect transistor region of a first conductivity type is formed within the current spreading layer, and the junction field-effect transistor region is located within the low-concentration doping region;

[0015] A patterned second mask layer is formed in the opening region of the first mask layer, and the first mask layer is removed;

[0016] Based on the patterned second mask layer, a well region of a second conductivity type is formed within the current spreading layer.

[0017] In one embodiment, the junction field-effect transistor region has a preset doping depth, and the preset doping depth is not greater than the depth of the low-concentration doped region.

[0018] In one embodiment, the preset doping depth is 60% to 90% of the doping depth of the current spreading layer.

[0019] In one embodiment, forming a patterned second mask layer in the opening region of the first mask layer and removing the first mask layer includes:

[0020] A second mask material layer is formed that covers the first mask layer and fills the opening area of ​​the first mask layer;

[0021] Remove the second mask material layer from the surface of the first mask layer that is away from the substrate to obtain the second mask layer;

[0022] Remove the first mask layer.

[0023] In one embodiment, the patterned first mask layer forms a junction field-effect transistor region of a first conductivity type within the current spreading layer, including:

[0024] An ion implantation process is used to pattern and dope the current spread layer through the first mask layer to form the junction field-effect transistor region within the current spread layer.

[0025] In one embodiment, the patterned second mask layer forms a well region of a second conductivity type within the current spreading layer, including:

[0026] An ion implantation process is used to pattern and dope the current spread layer through the second mask layer to form the well region within the current spread layer.

[0027] In one embodiment, after the patterned second mask layer forms a well region of a second conductivity type within the current spreading layer, it further includes:

[0028] Remove the second mask layer.

[0029] In one embodiment, after the patterned second mask layer forms a well region of a second conductivity type within the current spreading layer, it further includes:

[0030] A source region of a first conductivity type and a contact region of a second conductivity type are formed within the well region, and the contact region is disposed adjacent to the source region.

[0031] In one embodiment, after forming a source region of a first conductivity type and a contact region of a second conductivity type within the well region, the method further includes:

[0032] A gate structure is formed on the side of the epitaxial layer away from the substrate; the gate structure includes a gate dielectric layer and a gate layer stacked sequentially.

[0033] An interlayer dielectric layer is formed covering the epitaxial layer and the gate structure. A contact hole is provided in the interlayer dielectric layer, and the bottom of the contact hole exposes the source region and the contact region.

[0034] A source metal layer is formed to fill the contact hole and cover the interlayer dielectric layer. The source metal layer is electrically connected to the source region and to the contact region.

[0035] On the other hand, this application also provides a semiconductor structure, including:

[0036] Substrate of the first conductivity type;

[0037] An epitaxial layer of the first conductivity type is located on one side of the substrate;

[0038] A current spreading layer of the first conductivity type is located within the epitaxial layer. The current spreading layer includes a low-concentration doped region and a high-concentration doped region, which are sequentially disposed in the thickness direction of the substrate. The high-concentration doped region is located on the side of the current spreading layer closer to the substrate, and the low-concentration doped region is located on the side of the current spreading layer away from the substrate.

[0039] The junction field-effect transistor region of the first conductivity type is located within the current spreading layer, and the junction field-effect transistor region is located within the low-concentration doping region;

[0040] The second conductivity type of well region is located within the current spreading layer, and the junction field-effect transistor region is located between adjacent well regions.

[0041] The aforementioned semiconductor structure and its fabrication method have the following beneficial effects: A current-spreading layer of a first conductivity type is formed within the epitaxial layer. This current-spreading layer includes low-concentration doped regions and high-concentration doped regions, which are sequentially arranged along the thickness direction of the substrate. The high-concentration doped regions are located on the side closer to the substrate, and the low-concentration doped regions are located on the side farther from the substrate. A junction field-effect transistor (JFET) region with a predetermined doping depth is formed within the current-spreading layer based on a patterned first mask layer, ensuring that the JFET region is mainly distributed within the low-concentration doped region. Furthermore, a well region is formed based on a patterned second mask layer, enabling the JFET region to... The junction field-effect transistor region is located between adjacent well regions, which allows for independent control of the doping concentration of both the junction field-effect transistor region and the well region. This effectively avoids the problem in the prior art where the doping adjustment of the junction field-effect transistor region affects the electrical characteristics and threshold voltage of the channel region, enhancing the stability of the device's conduction performance and electrical characteristics. At the same time, it optimizes the on-resistance and improves the reliability of the process. In addition, by forming a patterned second mask layer in the opening area of ​​the first mask layer, overlay errors in multiple photolithography processes are avoided, achieving precise alignment between the junction field-effect transistor region and the well region and improving the consistency of device performance. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0044] Figure 2 This is a schematic diagram of the cross-sectional structure after the epitaxial layer is formed in a semiconductor structure fabrication method provided in one embodiment;

[0045] Figure 3 This is a schematic cross-sectional view of the semiconductor structure after the current spreading layer is formed in a method for fabricating a semiconductor structure provided in one embodiment.

[0046] Figure 4 This is a schematic diagram of the cross-sectional structure of a junction field-effect transistor region formed based on a patterned first mask layer in a semiconductor structure fabrication method provided in one embodiment.

[0047] Figure 5 This is a schematic cross-sectional view of the semiconductor structure after the second mask material layer is formed in a method for fabricating a semiconductor structure provided in one embodiment.

[0048] Figure 6 This is a schematic cross-sectional view of the semiconductor structure after removing the second mask material layer located on the side of the first mask layer away from the substrate in a semiconductor structure fabrication method provided in one embodiment;

[0049] Figure 7 This is a schematic diagram of the cross-sectional structure after removing the first mask layer in a semiconductor structure fabrication method provided in one embodiment;

[0050] Figure 8 This is a schematic diagram of the cross-sectional structure after the formation of the well region in a semiconductor structure fabrication method provided in one embodiment;

[0051] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after the source region and contact region are formed in a method for fabricating a semiconductor structure provided in one embodiment.

[0052] Figure 10 This is a schematic cross-sectional view of the semiconductor structure after the gate structure is formed in a method for fabricating a semiconductor structure provided in one embodiment.

[0053] Figure 11 This is a schematic cross-sectional view of the semiconductor structure after the formation of the interlayer dielectric layer and the source metal layer in a semiconductor structure fabrication method provided in one embodiment.

[0054] Explanation of reference numerals in the attached figures:

[0055] 100-Substrate, 101-Epipolar layer, 200-Current spread layer, 201-Junction field-effect transistor region, 202-Well region, 203-Source region, 204-Contact region, 300-First mask layer, 301-Opening region, 400-Second mask layer, 401-Second mask material layer, 500-Gate structure, 501-Gate layer, 502-Gate dielectric layer, 600-Interlayer dielectric layer, 601-Contact hole, 700-Source metal layer. Detailed Implementation

[0056] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0058] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, conductivity types, and / or portions, these elements, components, areas, layers, conductivity types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, conductivity type, or portion from another element, component, area, layer, conductivity type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, conductivity type or portion discussed below may be represented as the second element, component, region, layer or portion; for example, the first conductivity type may be referred to as the second conductivity type, and similarly, the second conductivity type may be referred to as the first conductivity type; the first conductivity type and the second conductivity type are different conductivity types, for example, the first conductivity type may be P type and the second conductivity type may be N type, or the first conductivity type may be N type and the second conductivity type may be P type.

[0059] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0060] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0061] Please see Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0062] Step S1: Provide a substrate 100 of a first conductivity type;

[0063] Step S2: An epitaxial layer 101 of a first conductivity type is formed on one side of the substrate 100;

[0064] Step S3: A current spreading layer 200 of the first conductivity type is formed in the epitaxial layer 101; the current spreading layer 200 includes a low concentration doped region and a high concentration doped region, the low concentration doped region and the high concentration doped region are sequentially disposed in the thickness direction of the substrate 100, the high concentration doped region is located in the current spreading layer 200 on the side closer to the substrate 100, and the low concentration doped region is located in the current spreading layer 200 on the side away from the substrate 100.

[0065] Step S4: A patterned first mask layer 300 is formed on the side of the current spreading layer 200 away from the substrate 100;

[0066] Step S5: Based on the patterned first mask layer 300, a junction field-effect transistor region 201 of the first conductivity type is formed in the current spreading layer 200. The junction field-effect transistor region 201 has a preset doping depth, and the preset doping depth is not greater than the depth of the low concentration doped region.

[0067] Step S6: A patterned second mask layer 400 is formed in the opening region 301 of the first mask layer 300, and the first mask layer 300 is removed;

[0068] Step S7: Based on the patterned second mask layer 400, a well region 202 of the second conductivity type is formed in the current spreading layer 200, and a junction field-effect transistor region 201 is located between adjacent well regions 202.

[0069] In the above example, a current spreading layer 200 of a first conductivity type is formed within the epitaxial layer 101. The current spreading layer 200 includes a low-concentration doped region and a high-concentration doped region, which are sequentially disposed along the thickness direction of the substrate 100. The high-concentration doped region is located on the side closer to the substrate 100, and the low-concentration doped region is located on the side farther from the substrate 100. A junction field-effect transistor (JFET) region 201 with a predetermined doping depth is formed within the current spreading layer 200 based on a patterned first mask layer 300, such that the JFET region 201 is mainly distributed within the low-concentration doped region. Furthermore, a well region 202 is formed based on a patterned second mask layer 400, such that the JFET region 201 is located adjacent to the well region 202. The doping concentrations of the junction field-effect transistor region 201 and the well region 202 can be independently controlled, effectively avoiding the problem in the prior art where the doping adjustment of the junction field-effect transistor region 201 affects the electrical characteristics and threshold voltage of the channel region. This enhances the stability of the device's conduction performance and electrical characteristics, while also optimizing the on-resistance and improving the reliability of the process. Furthermore, by forming a patterned second mask layer 400 in the opening region 301 of the first mask layer 300, i.e., by forming the second mask layer 400 through a self-aligned process, the overlay error in multiple photolithography processes is avoided, achieving precise alignment between the junction field-effect transistor region 201 and the well region 202 and improving the consistency of device performance.

[0070] Specifically, step S1 is performed, providing a substrate 100 of a first conductivity type.

[0071] In one embodiment, the substrate 100 is made of silicon carbide (SiC) and serves as a mechanical support structure and current conduction path for the device. The substrate 100 is typically made of a highly doped first conductivity type semiconductor material to reduce substrate resistance, thereby reducing the on-resistance of the device and improving conductivity.

[0072] It should be noted that the first conductivity type and the second conductivity type are different conductivity types. The first conductivity type can be P-type and the second conductivity type can be N-type; or the first conductivity type can be N-type and the second conductivity type can be P-type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0073] Specifically, please refer to Figure 2 Step S2 is performed to form an epitaxial layer 101 of a first conductivity type on one side of the substrate 100.

[0074] In one embodiment, such as Figure 2 As shown, the epitaxial layer 101 is grown on the surface of the substrate 100 using a vapor phase epitaxy method. The material of the epitaxial layer 101 is consistent with that of the substrate 100, both being silicon carbide. The epitaxial layer 101 serves as the active region and voltage withstand region of the device, and its doping concentration is lower than that of the substrate 100, in order to reduce the on-resistance while ensuring the device's voltage withstand capability.

[0075] It should be noted that the thickness and doping concentration of the epitaxial layer 101 are designed according to the device's breakdown voltage level to achieve a balance between on-resistance and breakdown voltage.

[0076] Specifically, please refer to Figure 3 Step S3 is executed to form a current spreading layer 200 of the first conductivity type in the epitaxial layer 101. The current spreading layer 200 includes a low concentration doped region and a high concentration doped region. The low concentration doped region and the high concentration doped region are arranged sequentially in the thickness direction of the substrate 100. The high concentration doped region is located in the current spreading layer 200 on the side closer to the substrate 100, and the low concentration doped region is located in the current spreading layer 200 on the side away from the substrate 100.

[0077] In one embodiment, such as Figure 3 As shown, the current spreading layer 200 is used to expand the current path, reduce the on-resistance, and improve the uniformity of current distribution when the device is in the on state.

[0078] Among them, the high-concentration doped region of the current spreading layer 200 is its main functional region, which plays a dominant role in the distribution of the device's conduction current and the resistance of the junction field-effect transistor region 201, while the low-concentration doped region is mainly used to maintain charge balance and assist current spreading.

[0079] The main reason for the appearance of the aforementioned low-concentration doped region (not shown) and high-concentration doped region (not shown) is that the current spreading layer 200 forms a doping peak distribution in the depth direction, resulting in a high-concentration doped region in the deeper area. The local carrier concentration in the high-concentration doped region is significantly higher than that in the low-concentration doped region, thus preferentially forming a low-resistance conductive channel when the device is on, which has a major impact on the overall on-resistance.

[0080] Furthermore, both high-concentration and low-concentration doped regions are formed using a high-energy ion implantation process, and the doping concentration distribution is controlled by adjusting the doping concentration, implantation energy, and annealing conditions. The specific doping concentration, implantation energy, and annealing conditions can be selected based on actual conditions and are not limited here.

[0081] In one embodiment, the doping concentration of the current spreading layer 200 is higher than that of the epitaxial layer 101, so as to reduce the on-resistance while ensuring the device's withstand voltage capability.

[0082] For example, the doping depth of the current spreading layer 200 ranges from 1 μm to 2 μm. In this embodiment, the doping depth of the current spreading layer 200 ranges from 1.2 μm to 1.7 μm.

[0083] Specifically, please refer to Figure 4 Steps S4 to S5 are executed to form a patterned first mask layer 300 on the side of the current spreading layer 200 away from the substrate 100; based on the patterned first mask layer 300, a junction field-effect transistor region 201 of a first conductivity type is formed in the current spreading layer 200, and the junction field-effect transistor region 201 is located in a low concentration doped region.

[0084] In one embodiment, a patterned first mask layer 300 is formed on the side of the current spreading layer 200 away from the substrate 100, including:

[0085] A first mask material layer is deposited on the side of the current spreading layer 200 away from the substrate 100. The method of forming the first mask material layer includes, but is not limited to, chemical vapor deposition (CVD).

[0086] A patterned photoresist layer is formed on the side of the first mask material layer away from the substrate 100;

[0087] Selective etching of the first mask material layer based on the patterned photoresist layer to form the patterned first mask layer 300, wherein the etching method includes dry etching or wet etching.

[0088] In one embodiment, the material of the first mask layer 300 includes at least one of silicon nitride or silicon oxide.

[0089] In one embodiment, a junction field-effect transistor region 201 of a first conductivity type is formed within a current spreading layer 200 based on a patterned first mask layer 300, including:

[0090] An ion implantation process is used to pattern and dope the current spread layer 200 through the first mask layer 300 to form a junction field-effect transistor region 201 within the current spread layer 200. The junction field-effect transistor region 201 is used to regulate the current convergence path and reduce the on-resistance when the device is on, thereby improving the overall conduction performance of the device.

[0091] In one embodiment, the junction field-effect transistor region 201 has a preset doping depth, and the preset doping depth is not greater than the depth of the low-concentration doped region.

[0092] In one embodiment, the net doping concentration of the junction field-effect transistor region 201 is obtained by superimposing the doping of the epitaxial layer 101, the low-concentration doped region, and the junction field-effect transistor region 201 itself.

[0093] Furthermore, based on the design that the preset doping depth is no greater than the depth of the low-concentration doped region, the junction field-effect transistor region 201 is mainly located within the doping distribution range corresponding to the low-concentration doped region, thereby reducing the influence of the high-concentration doped region on the net doping distribution of the junction field-effect transistor region 201. Combined with the patterned implantation of the junction field-effect transistor region 201, independent control of the doping concentration of the junction field-effect transistor region 201 is achieved. This avoids the influence of the doping adjustment of the junction field-effect transistor region 201 on the electrical characteristics and threshold voltage of the channel region in the prior art, and achieves decoupling of the doping control of the junction field-effect transistor region 201 and the channel region.

[0094] In one embodiment, the preset doping depth is 60% to 90% of the thickness of the current spreading layer 200, for example, 0.6 μm to 1.5 μm.

[0095] Specifically, please refer to Figures 5 to 7 Step S6 is executed, in which a patterned second mask layer 400 is formed in the opening region 301 of the first mask layer 300, and the first mask layer 300 is removed.

[0096] In one embodiment, such as Figures 5 to 7 As shown, a patterned second mask layer 400 is formed in the opening region 301 of the first mask layer 300, and the removal of the first mask layer 300 includes:

[0097] A second mask material layer 401 is formed covering the first mask layer 300 and filling its patterned openings. The material of the second mask material layer 401 includes at least one of silicon oxide or silicon nitride. The method of forming the second mask material layer includes, but is not limited to, chemical vapor deposition (CVD).

[0098] The second mask material layer 401 located on the surface of the first mask layer 300 away from the substrate 100 is removed to obtain a patterned second mask layer 400. The method for removing the second mask material layer 401 includes at least one of wet etching, dry etching or chemical mechanical polishing.

[0099] Remove the first mask layer 300; the method for removing the first mask layer 300 includes at least one of wet etching, dry etching or chemical mechanical polishing.

[0100] That is, the second mask layer 400 is formed by a self-alignment process, so that the pattern of the second mask layer 400 is completely aligned with the first mask layer 300, thereby avoiding photolithography overlay errors.

[0101] Specifically, please refer to Figures 8 to 11 In step S7, based on the patterned second mask layer 400, a second conductivity type well region 202 is formed in the current extension layer 200, wherein the junction field-effect transistor region 201 is located between adjacent well regions 202.

[0102] In one embodiment, such as Figure 8 As shown, a well region 202 is formed within the current spreading layer 200 based on the patterned second mask layer 400, including:

[0103] An ion implantation process is used to pattern and dope the current spreading layer 200 through a second mask layer 400 to form a well region 202 within the current spreading layer 200. The specific doping depth and concentration can be selected according to actual conditions and are not limited here. In this embodiment, the well region 202 is formed in a low-concentration doped region. The well region 202 is used to form the channel conductive region of the device and participates in current transport and potential regulation during device conduction.

[0104] The net doping concentration of the well region 202 is compensated by the low-concentration doped regions in the epitaxial layer 101 and the current spreading layer 200, as well as the doping concentration of the well region 202 itself. Based on this structural design, the doping control of the well region 202 and the junction field-effect transistor region 201 is decoupled, thereby achieving independent control of the doping concentration of the well region 202 and the junction field-effect transistor region 201. Furthermore, the well region 202 formed based on the second mask layer 400 has high alignment accuracy, thereby improving device consistency and electrical performance stability.

[0105] In one embodiment, after forming the well region 202 within the current spreading layer 200 based on the patterned second mask layer 400, the method further includes:

[0106] Remove the second mask layer 400. The method for removing the second mask layer 400 includes at least one of dry etching, wet etching, and chemical mechanical polishing.

[0107] In one embodiment, such as Figure 9 As shown, based on the patterned second mask layer 400, after forming the well region 202 within the current spreading layer 200, the following is also included:

[0108] A source region 203 of a first conductivity type and a contact region 204 of a second conductivity type are formed in the well region 202, and the contact region 204 is disposed adjacent to the source region 203. The source region 203 is used to provide a carrier injection channel when the device is turned on, and the contact region 204 is used to form a low resistance ohmic contact with the source metal.

[0109] In one embodiment, such as Figures 10 to 11 As shown, after forming a source region 203 of a first conductivity type and a contact region 204 of a second conductivity type within the well region 202, the following is also included:

[0110] A gate structure 500 is formed on the side of the epitaxial layer 101 away from the substrate 100. The gate structure 500 includes a gate dielectric layer 502 and a gate layer 501 stacked sequentially. The gate dielectric layer 502 is located on the surface of the epitaxial layer 101 and is correspondingly disposed with respect to the well region 202. It is used to achieve electrical isolation between the gate structure and the semiconductor and to form a channel when power is applied. The gate layer 501 is located on the side of the gate dielectric layer 502 away from the epitaxial layer 101 and is used to control the channel to be turned on and off.

[0111] An interlayer dielectric layer 600 is formed on the side of the epitaxial layer 101 away from the substrate 100. A contact hole 601 is provided in the interlayer dielectric layer 600, and the bottom of the contact hole 601 exposes the source region 203 and the contact region 204.

[0112] A source metal layer 700 is formed to fill the contact hole 601 and cover the interlayer dielectric layer 600. The source metal layer 700 is electrically connected to the source region 203 and the contact region 204.

[0113] In one embodiment, the method for fabricating a semiconductor structure further includes:

[0114] A drain metal layer (not shown) is formed on the side of the substrate 100 away from the epitaxial layer 101, and the drain metal layer forms an electrical connection with the substrate 100.

[0115] Therefore, by combining self-aligned dual hard mask patterning with layered doping control to form a spatial isolation structure for the junction field-effect transistor region and the well region, independent control of the doping concentration of the junction field-effect transistor region and the well region and elimination of process overlay errors are achieved.

[0116] In one embodiment, please continue reading Figure 11 This application also provides a semiconductor structure, comprising:

[0117] The system comprises a substrate 100 of a first conductivity type, an epitaxial layer 101 of a first conductivity type, a current spreading layer 200 of a first conductivity type, a junction field-effect transistor (JFET) region 201 of a first conductivity type, and a well region 202 of a second conductivity type. The epitaxial layer 101 is located on one side of the substrate 100. The current spreading layer 200 is located within the epitaxial layer 101. The current spreading layer 200 includes a low-concentration doped region and a high-concentration doped region, which are sequentially arranged in the thickness direction of the substrate 100. The high-concentration doped region is located within the current spreading layer 200 on the side closer to the substrate 100, and the low-concentration doped region is located within the current spreading layer 200 on the side farther from the substrate 100. The JFET region 201 is located within the current spreading layer 200 and within the low-concentration doped region. The well region 202 is located within the current spreading layer 200, and the JFET region 201 is located between adjacent well regions 202.

[0118] The above semiconductor structure achieves decoupling of the doping control between the junction field-effect transistor region 201 and the well region 202 by setting a current extension layer 200 with a layered doping structure in the epitaxial layer 101 and placing the junction field-effect transistor region 201 in the low concentration doping region, thereby improving the device conduction performance and enhancing the stability of electrical characteristics.

[0119] In one embodiment, the junction field-effect transistor region 201 has a preset doping depth, and the preset doping depth is not greater than the depth of the low-concentration doped region.

[0120] In one embodiment, the preset doping depth is 50% to 90% of the doping depth of the current spreading layer 200.

[0121] In one embodiment, the semiconductor structure further includes a source region 203 of a first conductivity type and a contact region 204 of a second conductivity type, wherein the source region 203 is located within the well region 202; and the contact region 204 is located within the well region 202 and is disposed adjacent to the source region 203.

[0122] In one embodiment, the semiconductor structure further includes a gate structure 500, an interlayer dielectric layer 600, and a source metal layer 700. The gate structure 500 is located on the side of the epitaxial layer 101 away from the substrate 100. The gate structure 500 includes a gate dielectric layer 502 and a gate layer 501 stacked sequentially. The gate layer 501 is correspondingly disposed with respect to the well region 202.

[0123] The interlayer dielectric layer 600 is located on the side of the epitaxial layer 101 away from the substrate 100. The interlayer dielectric layer 600 has a contact hole 601 that penetrates the interlayer dielectric layer 600. The bottom of the contact hole 601 exposes the source region 203 and the contact region 204.

[0124] The source metal layer 700 fills the contact hole 601 and covers the interlayer dielectric layer 600, and the source metal layer 700 is electrically connected to the source region 203 and the contact region 204.

[0125] In one embodiment, the semiconductor structure further includes a drain metal layer located on the side of the substrate 100 away from the epitaxial layer 101, and the drain metal layer forms an electrical connection with the substrate 100.

[0126] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0127] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0128] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a substrate of the first conductivity type; An epitaxial layer of a first conductivity type is formed on one side of the substrate; A current spreading layer of a first conductivity type is formed within the epitaxial layer; the current spreading layer includes a low-concentration doped region and a high-concentration doped region, the low-concentration doped region and the high-concentration doped region being sequentially disposed in the thickness direction of the substrate, the high-concentration doped region being located on the side of the current spreading layer closer to the substrate, and the low-concentration doped region being located on the side of the current spreading layer away from the substrate. A patterned first mask layer is formed on the side of the current spreading layer away from the substrate; Based on the patterned first mask layer, a junction field-effect transistor region of a first conductivity type is formed within the current spreading layer, and the junction field-effect transistor region is located within the low-concentration doping region; A patterned second mask layer is formed in the opening region of the first mask layer, and the first mask layer is removed; Based on the patterned second mask layer, a well region of a second conductivity type is formed within the current spreading layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The junction field-effect transistor region has a preset doping depth, and the preset doping depth is not greater than the depth of the low-concentration doped region.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The preset doping depth is 60% to 90% of the doping depth of the current spreading layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a patterned second mask layer in the opening region of the first mask layer and removing the first mask layer includes: A second mask material layer is formed that covers the first mask layer and fills the opening area of ​​the first mask layer; Remove the second mask material layer from the surface of the first mask layer that is away from the substrate to obtain the second mask layer; Remove the first mask layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The patterned first mask layer forms a junction field-effect transistor region of a first conductivity type within the current spreading layer, including: An ion implantation process is used to pattern and dope the current spread layer through the first mask layer to form the junction field-effect transistor region within the current spread layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The patterned second mask layer forms a well region of a second conductivity type within the current spreading layer, including: An ion implantation process is used to pattern and dope the current spread layer through the second mask layer to form the well region within the current spread layer.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, After the patterned second mask layer forms a well region of a second conductivity type within the current spreading layer, it further includes: Remove the second mask layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, After the patterned second mask layer forms a well region of a second conductivity type within the current spreading layer, it further includes: A source region of a first conductivity type and a contact region of a second conductivity type are formed within the well region, and the contact region is disposed adjacent to the source region.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, After forming a source region of a first conductivity type and a contact region of a second conductivity type within the well region, the method further includes: A gate structure is formed on the side of the epitaxial layer away from the substrate; the gate structure includes a gate dielectric layer and a gate layer stacked sequentially. An interlayer dielectric layer is formed covering the epitaxial layer and the gate structure. A contact hole is provided in the interlayer dielectric layer, and the bottom of the contact hole exposes the source region and the contact region. A source metal layer is formed to fill the contact hole and cover the interlayer dielectric layer. The source metal layer is electrically connected to the source region and to the contact region.

10. A semiconductor structure, characterized in that, The semiconductor structure includes: Substrate of the first conductivity type; An epitaxial layer of the first conductivity type is located on one side of the substrate; A current spreading layer of the first conductivity type is located within the epitaxial layer. The current spreading layer includes a low-concentration doped region and a high-concentration doped region, which are sequentially disposed in the thickness direction of the substrate. The high-concentration doped region is located on the side of the current spreading layer closer to the substrate, and the low-concentration doped region is located on the side of the current spreading layer away from the substrate. The junction field-effect transistor region of the first conductivity type is located within the current spreading layer, and the junction field-effect transistor region is located within the low-concentration doping region; The second conductivity type of well region is located within the current spreading layer, and the junction field-effect transistor region is located between adjacent well regions.

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