Semiconductor structure preparation method and semiconductor structure

Abstract

The application relates to a semiconductor structure preparation method and a semiconductor structure, and relates to the technical field of integrated circuits. The method comprises the following steps: providing a substrate; based on the same target mask, sequentially forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are all N-type and are sequentially stacked in a direction away from the substrate on the top surface of the substrate; the top part of the first epitaxial layer comprises a plurality of first doped regions which are all P-type and are spaced apart along a first direction parallel to the substrate, the top part of the second epitaxial layer comprises a plurality of second doped regions which are all P-type and are spaced apart along the first direction, and the top part of the third epitaxial layer comprises a plurality of third doped regions which are all P-type and are spaced apart along the first direction; a plurality of gate structures are formed on the top surface of the third epitaxial layer and are spaced apart along the first direction, and the plurality of gate structures are located directly above the plurality of third doped regions. The device withstand voltage can be maintained, and the device loss and heat dissipation are reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the continuous development of modern electronic technology, the market has placed higher demands on the yield and performance of semiconductor devices.

[0003] Traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) typically rely primarily on epitaxial layers to support their drain-source voltage, resulting in significant turn-off and operating losses. The devices also generate considerable heat during operation, requiring more robust heat dissipation structures, which in turn increases packaging and operating costs. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure fabrication method and semiconductor structure to address the technical problems in the prior art. This method can at least utilize a P-shaped floating gate to extract electrons from the drift region during device turn-off, reduce the electron movement path, achieve rapid turn-off, form a depletion region, maintain device withstand voltage, and reduce device turn-off losses, usage losses, and heat dissipation.

[0005] In some embodiments, this application provides a method for fabricating a semiconductor structure, including:

[0006] Provide substrate;

[0007] Based on the same target photomask, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, all of which are N-type, are sequentially stacked on the top surface of the substrate in a direction away from the substrate. The top of the first epitaxial layer includes multiple first doped regions that are all P-type and are spaced apart along a first direction parallel to the substrate. The top of the second epitaxial layer includes multiple second doped regions that are all P-type and are spaced apart along the first direction. The top of the third epitaxial layer includes multiple third doped regions that are all P-type and are spaced apart along the first direction. The linear spacing between each second doped region and any two adjacent first doped regions or two third doped regions along the first direction is the same. The multiple third doped regions are located directly above the multiple first doped regions.

[0008] Multiple gate structures are formed on the top surface of the third epitaxial layer and spaced apart along the first direction. The multiple gate structures are located directly above multiple third doped regions. The dimensions of the third doped regions along the first direction are p / 4-p / 3, where p is the linear spacing between adjacent gate structures.

[0009] In the above embodiments, after forming a first epitaxial layer, all of which are N-type, on the top surface of the substrate based on the target photomask, the top of the first epitaxial layer includes a plurality of first doped regions, all of which are P-type, spaced apart along a first direction parallel to the substrate. A second epitaxial layer, all of which are N-type, is formed on the top surface of the first epitaxial layer based on the translated target photomask. The top of the second epitaxial layer includes a plurality of second doped regions, all of which are P-type, spaced apart along the first direction. The linear spacing between the second doped region and the two first doped regions adjacent to it along the first direction is the same, so as to form P-type first doped regions and P-type second doped regions that are uniformly spaced and alternately distributed along the first direction. A third epitaxial layer is formed on the top surface of the second epitaxial layer based on the target photomask. The top of this third epitaxial layer includes multiple third doped regions, all of which are P-type and spaced apart along the first direction. The linear spacing between each P-type third doped region and its two adjacent second doped regions along the first direction is the same. The multiple third doped regions are located directly above the multiple first doped regions. The linear spacing between each second doped region and its adjacent first or third doped region can be set to be equal, resulting in a uniformly spaced array of first, second, and third doped regions to form a uniform breakdown voltage or heat dissipation distribution. The P-type first, second, and third doped regions can form a P-shaped floating gate. When the device is turned on, the P-shaped floating gate is a minority carrier structure and does not participate in conduction. When the device is turned off, the P-shaped floating gate will extract electrons from the drift region to form a depletion region, maintaining the device breakdown voltage, reducing the electron movement path, achieving fast turn-off, and reducing device turn-off loss, usage loss, and heat dissipation.

[0010] Furthermore, multiple gate structures can be formed on the top surface of the third epitaxial layer based on the aforementioned target photomask, spaced apart along the first direction. By setting multiple gate structures directly above multiple third doped regions, the dimensions of the third doped regions along the first direction are p / 4-p / 3, where p is the linear spacing between adjacent gate structures. This not only avoids increasing the cost and complexity of the process due to the increase in the number of photomasks, but also utilizes the depletion region formed by the uniformly spaced array of the first, second, and third doped regions to disperse and optimize the current path, making the current distribution more uniform and avoiding local current congestion (reducing heat generation); it can also shorten the current flow distance or reduce the potential barrier in the path, thereby reducing resistance.

[0011] In some embodiments, the dimension of the first doped region along the first direction is p / 4-p / 3, and the ratio of the thickness of the first doped region to the thickness of the first epitaxial layer is 0.49-0.50.

[0012] In some embodiments, the size of the second doped region along the first direction is p / 4-p / 3; the ratio of the thickness of the second doped region to the thickness of the second epitaxial layer is 0.49-0.50.

[0013] In some embodiments, the ratio of the thickness of the third doped region to the thickness of the third epitaxial layer is 0.49-0.50.

[0014] In the above embodiments, by carefully designing the structural parameters of the P-type floating gate, low turn-off loss and low on-resistance can be obtained, while the flow path of the current inside the device can be improved (for example, the current is made to pass through the low-resistance region more concentratedly, and detours or congestion are reduced), thereby achieving a better balance between switching and conduction characteristics.

[0015] In some embodiments, forming the first epitaxial layer of type N includes:

[0016] A first initial epitaxial layer of type N with a target sheet resistance value is formed on the top surface of the substrate;

[0017] A first oxide layer is formed on the top surface of the first initial epitaxial layer;

[0018] A first patterned photoresist layer is formed on the top surface of the first oxide layer based on the target photomask. The first patterned photoresist layer includes a plurality of first opening patterns for defining a plurality of first doped regions.

[0019] Using a first patterned photoresist layer as a mask, a first ion implantation doping process is performed into a first initial epitaxial layer via a first oxide layer to form a first epitaxial layer comprising multiple first doped regions of P type; the thickness ratio of the first doped region to the thickness of the first initial epitaxial layer is 0.49-0.50.

[0020] In the above embodiments, a first ion implantation doping process is performed in the first initial epitaxial layer of the N-type having a target sheet resistance value to form a first epitaxial layer including a plurality of first doped regions of the P-type; the thickness ratio of the first doped region to the thickness of the first initial epitaxial layer is 0.49-0.50, providing drift region space for electron flow.

[0021] In some embodiments, the target sheet resistance value is 1.6 ohm / sq–2.4 ohm / sq.

[0022] In some embodiments, the ion implantation dose in the first ion implantation doping process is 1E15cm. -2 -5E16cm -2 .

[0023] In the above embodiments, by selectively implanting (usually in conjunction with a photolithographic mask) ions into a heavily doped N-type first initial epitaxial layer, a specific impurity (here, a P-type impurity, such as boron B) is injected at high energy into the first initial epitaxial layer, resulting in a first epitaxial layer "embedded" with multiple P-type regions. The energy and dose of ion implantation determine the depth and concentration of the doped regions.

[0024] In some embodiments, the photomask forming multiple second doped regions is obtained by translating the target photomask along a first direction by a first preset distance. The first preset distance is associated with the linear spacing between adjacent first doped regions along the first direction, so that the final second doped region is located at the center between two adjacent first doped regions along the first direction, thereby obtaining P-type first doped regions and P-type second doped regions that are uniformly and alternately distributed along the first direction.

[0025] In some embodiments, after forming the second epitaxial layer, an N-type third epitaxial layer is formed on the second epitaxial layer by repeating the steps of forming the first epitaxial layer, such that the plurality of third doped regions are located directly above the plurality of first doped regions, so as to obtain the first doped regions, the second doped regions, and the third doped regions arranged in a uniformly spaced array, so as to form a uniform breakdown voltage or heat dissipation distribution.

[0026] In some embodiments, forming the N-type second epitaxial layer includes:

[0027] Remove the first patterned photoresist layer and the first oxide layer;

[0028] A second initial epitaxial layer of type N with a target sheet resistance value is formed on the top surface of the first epitaxial layer;

[0029] A second oxide layer is formed on the top surface of the second initial epitaxial layer;

[0030] A second patterned photoresist layer is formed on the top surface of the second oxide layer based on the translated target photomask. The second patterned photoresist layer includes a plurality of second opening patterns for defining a plurality of second doped regions.

[0031] Using the second patterned photoresist layer as a mask, a second ion implantation doping process is performed into the second initial epitaxial layer via the second oxide layer to form a second epitaxial layer including multiple second doped regions of P type; the thickness ratio of the second doped region to the thickness of the second initial epitaxial layer is 0.49-0.50.

[0032] In some embodiments, forming a plurality of gate structures includes:

[0033] An N-type fourth initial epitaxial layer is formed on the top surface of the third epitaxial layer;

[0034] A pad oxide layer is formed on the top surface of the fourth initial epitaxial layer;

[0035] An ion implantation process is performed into the fourth initial epitaxial layer via a pad oxide layer to form a fourth epitaxial layer comprising a plurality of fourth doped regions that are spaced apart along the first direction and are all P-type.

[0036] An N-type source region is formed in the fourth doped region via a pad oxide layer;

[0037] A gate conductive material layer is formed on the top surface of the pad oxide layer;

[0038] The gate conductive material layer is patterned to obtain a plurality of gate conductive layers spaced apart along a first direction, with the plurality of gate conductive layers located directly above a plurality of source regions;

[0039] A dielectric layer is formed with its top surface flush with and higher than the top surface of the gate conductive layer, and the dielectric layer fills the gap between adjacent gate conductive layers.

[0040] The dielectric layer is patterned to obtain multiple grooves spaced apart along the first direction. The remaining dielectric layer covers the side and top surfaces of the gate conductive layer and is used to form the gate dielectric layer together with the pad oxide layer between the gate conductive layer and the fourth epitaxial layer. The grooves expose the source region directly below them. The gate dielectric layer and the gate conductive layer within its enclosing space are used to form the gate structure.

[0041] In some embodiments, after forming multiple gate structures, the method further includes: forming multiple conductive plugs within multiple grooves; and forming a source conductive layer covering the multiple conductive plugs and the remaining dielectric layer. Conductive materials (such as tungsten, titanium / titanium nitride composite layers, etc.) can be filled into the grooves to form vertical conductive connection structures, also known as "contact plugs" or "via plugs," to achieve electrical interconnection between the upper metal layer and the lower semiconductor layer.

[0042] In some embodiments, a semiconductor structure is provided, including a substrate, and a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, all of which are N-type, sequentially stacked on the substrate in a direction away from the substrate; the top of the first epitaxial layer includes a plurality of first doped regions, all of which are P-type, spaced apart along a first direction parallel to the substrate; the top of the second epitaxial layer includes a plurality of second doped regions, all of which are P-type, spaced apart along the first direction; the top of the third epitaxial layer includes a plurality of third doped regions, all of which are P-type, spaced apart along the first direction; the linear spacing between each second doped region and any two adjacent first doped regions or two adjacent third doped regions along the first direction is the same; the plurality of third doped regions are located directly above the plurality of first doped regions; wherein, the top surface of the third epitaxial layer includes a plurality of gate structures spaced apart along the first direction; the plurality of gate structures are located directly above the plurality of third doped regions; the dimension of each third doped region along the first direction is p / 4-p / 3, where p is the linear spacing between adjacent gate structures.

[0043] The above-described embodiments of this application can produce at least the following unexpected technical effects:

[0044] By setting the linear spacing between the second doped region and its adjacent first or third doped region to be equal, a uniformly spaced array of first, second, and third doped regions is obtained. The depletion region formed by this uniformly spaced array of first, second, and third doped regions disperses and optimizes the current path, resulting in a more uniform current distribution and avoiding localized current congestion (reducing heat generation). It also shortens the current flow distance or lowers the potential barrier in the path, thereby reducing resistance. The first, second, and third doped regions, all of which are P-type, can form a P-shaped floating gate. When the device is on, the P-shaped floating gate is a minority carrier structure and does not participate in conduction; when the device is off, the P-shaped floating gate extracts electrons from the drift region to form a depletion region, maintaining the device's breakdown voltage, reducing the electron movement path, achieving rapid turn-off, and reducing device turn-off losses, operating losses, and heat dissipation. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic flowchart of a semiconductor structure fabrication method provided in one embodiment of this application;

[0047] Figure 2 This is a cross-sectional schematic diagram of the structure obtained after forming the first oxide layer 13 in step S20 of one embodiment of this application;

[0048] Figure 3 This is a schematic cross-sectional view of the structure obtained after forming the first epitaxial layer in step S20 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0049] Figure 4 This is a schematic cross-sectional view of the structure obtained after removing the first patterned photoresist layer in step S20 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0050] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming the second epitaxial layer in step S20 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0051] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming the third epitaxial layer in step S20 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0052] Figure 7This is a schematic cross-sectional view of the structure obtained after forming the fourth initial epitaxial layer in step S30 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0053] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming a pad oxide layer in step S30 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0054] Figure 9 This is a schematic cross-sectional view of the structure obtained after forming the gate conductive layer in step S30 of the semiconductor structure fabrication method provided in an embodiment of this application.

[0055] Figure 10 This is a schematic cross-sectional view of the structure obtained after step S30, in the semiconductor structure fabrication method provided in one embodiment of this application, after the formation of the source conductive layer.

[0056] Figure 11 This is a schematic diagram of the drain-source current flow path during device conduction in a semiconductor structure fabrication method provided in one embodiment of this application.

[0057] Figure 12 This is a schematic diagram showing the formation of a depletion region in the P-type doped region of the epitaxial layer during device shutdown in a semiconductor structure fabrication method provided in one embodiment of this application.

[0058] Figure 13 This is a schematic diagram of the drain-source current flow path during the conduction period of the semiconductor device provided in a comparative embodiment of this application;

[0059] Figure 14 This is a schematic diagram of the drain-source current flow path during the conduction of a semiconductor device provided in another comparative embodiment of this application.

[0060] Explanation of reference numerals in the attached figures:

[0061] 11. Substrate; 121. First initial epitaxial layer; 12. First epitaxial layer; 13. First oxide layer; 14. Second epitaxial layer; 15. Third epitaxial layer; 161. Fourth initial epitaxial layer; 16. Fourth epitaxial layer; 17. Pad oxide layer; 18. Dielectric layer; 19. Gate conductive layer; PR1. First patterned photoresist layer; T1. First aperture pattern; 21. First doped region; 22. Second doped region; 23. Third doped region; 31. Fourth doped region; 32. Source region; 33. Conductive plug; 34. Source conductive layer; 35. P-type pillar. Detailed Implementation

[0062] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0064] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0065] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0066] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0067] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0068] Common high-voltage (e.g., 600V / 800V / 1000V) MOSFET devices have simple structures and low manufacturing costs. However, high-voltage MOSFETs rely primarily on epitaxial layers to support higher breakdown voltages. These epitaxial layers are typically thicker and have lower doping concentrations. High-voltage MOSFET devices face several typical challenges:

[0069] 1) Increased device size: In order to withstand higher breakdown voltage, thicker and less doped epitaxial layers are required, which increases the lateral or vertical dimensions and is not conducive to integration.

[0070] 2) Limited switching speed: Thicker epitaxial layers increase the storage effect of minority carriers, resulting in turn-off tail current and reducing the switching frequency.

[0071] 3) Increased parasitic capacitance: The depletion layer between the epitaxial layer and the substrate is wider, affecting the gate charge and capacitance, and increasing drive loss.

[0072] Based on this, this application aims to provide a semiconductor structure fabrication method and a semiconductor structure that can at least utilize a P-shaped floating gate to extract electrons from the drift region during device turn-off, reduce the electron movement path, achieve rapid turn-off, form a depletion region, maintain device withstand voltage, and reduce device turn-off loss, usage loss, and heat dissipation.

[0073] Please refer to Figure 1 In some embodiments, a method for fabricating a semiconductor structure is provided, comprising:

[0074] Step S10: Provide a substrate;

[0075] Step S20: Based on the same target photomask, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, all of which are N-type, are sequentially stacked on the top surface of the substrate in a direction away from the substrate; the top of the first epitaxial layer includes a plurality of first doped regions that are spaced apart along a first direction parallel to the substrate and are all P-type; the top of the second epitaxial layer includes a plurality of second doped regions that are spaced apart along the first direction and are all P-type; the top of the third epitaxial layer includes a plurality of third doped regions that are spaced apart along the first direction and are all P-type; the linear spacing between the second doped region and two adjacent first doped regions or two third doped regions along the first direction is the same; the plurality of third doped regions are located directly above the plurality of first doped regions.

[0076] Step S30: A plurality of gate structures are formed on the top surface of the third epitaxial layer at intervals along the first direction. The plurality of gate structures are located directly above a plurality of third doped regions. The size of the third doped region along the first direction is p / 4-p / 3, where p is the linear spacing between adjacent gate structures.

[0077] For example, please continue to refer to Figure 1After forming a first epitaxial layer, all of which are N-type, on the top surface of the substrate based on the target photomask, the top of the first epitaxial layer includes a plurality of first doped regions, all of which are P-type, spaced apart along a first direction parallel to the substrate. A second epitaxial layer, all of which are N-type, is formed on the top surface of the first epitaxial layer based on the translated target photomask. The top of the second epitaxial layer includes a plurality of second doped regions, all of which are P-type, spaced apart along the first direction. The linear spacing between the second doped region and the two first doped regions adjacent to it along the first direction is the same, so as to form P-type first doped regions and P-type second doped regions that are uniformly spaced and alternately distributed along the first direction. A third epitaxial layer is formed on the top surface of the second epitaxial layer based on the target photomask. The top of this third epitaxial layer includes multiple third doped regions, all of which are P-type and spaced apart along the first direction. The linear spacing between each P-type third doped region and its two adjacent second doped regions along the first direction is the same. The multiple third doped regions are located directly above the multiple first doped regions. The linear spacing between each second doped region and its adjacent first or third doped region can be set to be equal, resulting in a uniformly spaced array of first, second, and third doped regions to form a uniform breakdown voltage or heat dissipation distribution. The P-type first, second, and third doped regions can form a P-shaped floating gate. When the device is turned on, the P-shaped floating gate is a minority carrier structure and does not participate in conduction. When the device is turned off, the P-shaped floating gate will extract electrons from the drift region to form a depletion region, maintaining the device breakdown voltage, reducing the electron movement path, achieving fast turn-off, and reducing device turn-off loss, usage loss, and heat dissipation.

[0078] Please refer to Figure 2 In some embodiments, the substrate 11 provided in step S10 may include elemental semiconductors, compound semiconductors, wide-bandgap semiconductors, gallium nitride, silicon-on-insulator, sapphire, or combinations thereof. The substrate 11 serves as the base for the entire chip, providing support strength, and its high thermal conductivity (e.g., a silicon substrate) helps conduct heat generated by the device to the package. For vertically conductive high-voltage MOSFETs (such as VDMOS), the back side of the substrate is directly connected to the drain metal, forming the drain electrode. Current flows vertically from the source through the channel, epitaxial layer, and substrate to the drain. In typical high-voltage MOSFETs, the substrate 11 primarily serves as a low-resistance drain contact and support substrate, without actively participating in voltage withstand; its contribution to the resistance is much smaller than that of the epitaxial layer.

[0079] Please refer to Figures 2-3 In some embodiments, step S20, forming the first N-type epitaxial layer 12 includes steps S211-S214.

[0080] Step S211: Form an N-type first initial epitaxial layer 121 with a target sheet resistance value on the top surface of the substrate 11.

[0081] Please continue to refer to this. Figure 2In some embodiments, a first initial epitaxial layer 121 of N-type with a target sheet resistance value is epitaxially grown on the top surface of the substrate 11. For example, during the epitaxial growth process, a phosphorus- or arsenic-containing gas (such as PH3) can be introduced to allow dopant atoms to replace silicon lattice sites, forming N-type conductivity. The resistivity / sheet resistance value of the first initial epitaxial layer 121 can be precisely controlled by adjusting the dopant gas flow rate ratio; the thickness of the first initial epitaxial layer 121 can be controlled by controlling the epitaxial growth time, so that the target sheet resistance value is 1.6 ohm / sq–2.4 ohm / sq and the thickness is 10um–15um. For example, the target sheet resistance value of the first initial epitaxial layer 121 can be 1.6 ohm / sq, 1.8 ohm / sq, 2.0 ohm / sq, 2.2 ohm / sq, or 2.4 ohm / sq, etc. For example, the thickness of the first initial epitaxial layer 121 can be 10um, 11um, 12um, 13um, 14um, or 15um, etc.

[0082] Step S212: Form a first oxide layer 13 on the top surface of the first initial epitaxial layer 121.

[0083] For example, please continue to refer to Figure 2 When the first initial epitaxial layer 121 comprises monocrystalline silicon, a first oxide layer 13 can be formed using a thermal oxidation process. The first oxide layer 13 comprises SiO2. The thickness of the first oxide layer 13 is 100 angstroms to 500 angstroms. For example, the thickness of the first oxide layer 13 can be 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, or 500 angstroms, etc.

[0084] Step S213: A first patterned photoresist layer PR1 is formed on the top surface of the first oxide layer 13 based on the target photomask. The first patterned photoresist layer PR1 includes a plurality of first opening patterns T1 for defining a plurality of first doped regions 21.

[0085] For example, please continue to refer to Figure 3 The first patterned photoresist layer PR1 defines the area to be ion implanted (or the area to be protected), and multiple first opening patterns T1 define the lateral distribution, shape, and size parameters of the ion implantation area. The first oxide layer 13 can provide additional protection (preventing channeling effects and reducing surface damage).

[0086] Step S214: Using the first patterned photoresist layer PR1 as a mask, a first ion implantation doping process is performed into the first initial epitaxial layer 121 via the first oxide layer 13 to form a first epitaxial layer 12 including a plurality of first doped regions 21 of P type; the thickness ratio of the first doped region 21 to the thickness of the first initial epitaxial layer 121 is 0.49-0.50.

[0087] For example, please continue to refer to Figure 3A first ion implantation doping process can be used to implant P-type impurities (such as boron ions, which are commonly used) into the first initial epitaxial layer 121. The energy and dose are determined based on the target junction depth and concentration. The boron ion implantation dose is 1E15cm. -2 -5E16cm -2 For example, it can be 1E15cm -2 4E15cm -2 6E15cm -2 8E15cm -2 1E16cm -2 2E16cm -2 3E16cm -2 4E16cm -2 Or 5E16cm -2 The thickness ratio of the P-type first doped region 21 formed after diffusion to the thickness of the N-type first epitaxial layer 12 is 0.49-0.50, for example, 0.49, 0.495, or 0.50. The dimension of the first doped region 21 along the first direction is p / 4-p / 3, for example, p / 4 or p / 3, where p is the linear spacing between adjacent gate structures. After ion implantation, high-temperature annealing (e.g., 900-1100 degrees Celsius) is required to activate impurities and repair lattice damage. After annealing, these P-type first doped regions 21 form a PN junction with the surrounding N-type first epitaxial layer 12, which determines the breakdown voltage and conduction characteristics of the device.

[0088] In the above embodiments, a first ion implantation doping process is performed within the first initial epitaxial layer 121 of the N-type having a target sheet resistance value to form a first epitaxial layer 12 comprising a plurality of first doped regions 21 of the P-type. The thickness ratio of the first doped region 21 to the thickness of the first initial epitaxial layer 121 is 0.49-0.50, providing drift region space for electron flow. By selectively (typically in conjunction with a photolithographic mask) implanting ions into the heavily doped first initial epitaxial layer 121 of the N-type, a specific impurity (here, a P-type impurity, such as boron B) is injected into the first initial epitaxial layer 121 at high energy, resulting in a first epitaxial layer 12 "embedded" with a plurality of P-type regions.

[0089] Please refer to Figures 4-5 In some embodiments, step S20, forming the N-type second epitaxial layer 14 includes steps S221-S225.

[0090] Step S221: Remove the first patterned photoresist layer PR1 and the first oxide layer 13.

[0091] For example, oxygen molecules can be dissociated into oxygen free radicals under a high-frequency electric field, which react with organic matter in the first patterned photoresist layer PR1 to generate volatile products such as CO2 and H2O. Then, the first oxide layer 13 is removed by wet cleaning. For example, dilute hydrofluoric acid can be used to remove the first oxide layer 13, and the wet cleaning time is calculated based on the thickness of the first oxide layer 13. After etching, deionized water rinsing should be performed immediately to prevent HF residue from corroding the silicon surface. The first epitaxial layer 12 is monocrystalline silicon, and dilute HF has almost no corrosive effect on silicon (because the HF reaction stops after the natural oxide layer on the silicon surface is removed).

[0092] Step S222: Form a second initial epitaxial layer of type N with a target sheet resistance value on the top surface of the first epitaxial layer 12.

[0093] For example, the fabrication process of the first initial epitaxial layer 121 can be repeated to form an N-type second initial epitaxial layer (not shown) with a target sheet resistance of 1.6 ohm / sq–2.4 ohm / sq. The thickness of the second initial epitaxial layer is 10 μm–15 μm. For example, the target sheet resistance of the second initial epitaxial layer can be 1.6 ohm / sq, 1.8 ohm / sq, 2.0 ohm / sq, 2.2 ohm / sq, or 2.4 ohm / sq, etc. The thickness of the second initial epitaxial layer can be 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, or 15 μm, etc.

[0094] Step S223: Form a second oxide layer on the top surface of the second initial epitaxial layer.

[0095] For example, when the second initial epitaxial layer comprises monocrystalline silicon, a second oxide layer (not shown) can be formed using a thermal oxidation process. The second oxide layer comprises SiO2. The thickness of the second oxide layer is 100 angstroms to 500 angstroms. For example, the thickness of the second oxide layer can be 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, or 500 angstroms, etc.

[0096] Step S224: Based on the translated target photomask, a second patterned photoresist layer is formed on the top surface of the second oxide layer. The second patterned photoresist layer includes a plurality of second opening patterns for defining a plurality of second doped regions 22.

[0097] For example, the target photomask can be shifted by a first preset distance to form a second patterned photoresist layer on the top surface of the second oxide layer. Multiple second opening patterns within the second patterned photoresist layer define the lateral distribution, shape, and size parameters of the ion implantation region. The second oxide layer can provide additional protection (preventing channeling effects and reducing surface damage). The first preset distance can be half the linear spacing between adjacent first doped regions 21 along the first direction, such that the ultimately formed second doped region 22 is located at the center between two adjacent first doped regions 21 along the first direction, thus obtaining P-type first doped regions 21 and P-type second doped regions 22 uniformly and alternately distributed along the first direction.

[0098] Step S225: Using the second patterned photoresist layer as a mask, a second ion implantation doping process is performed into the second initial epitaxial layer through the second oxide layer to form a second epitaxial layer 14 including a plurality of second doped regions 22 of P type; the thickness ratio of the second doped region 22 to the thickness of the second initial epitaxial layer is 0.49-0.50.

[0099] For example, please continue to refer to Figure 5 A second ion implantation doping process can be used, using a second patterned photoresist layer as a mask, to form a plurality of P-type second doped regions 22 within the second initial epitaxial layer via a second oxide layer, resulting in a second epitaxial layer 14 comprising a plurality of second doped regions 22 uniformly spaced along a first direction. The ratio of the thickness of the second doped region 22 to the thickness of the second initial epitaxial layer can be 0.49 or 0.50.

[0100] For example, oxygen molecules can be dissociated into oxygen free radicals under a high-frequency electric field, which then react with organic matter in the second patterned photoresist layer to generate volatile products such as CO2 and H2O. The second oxide layer is then removed by wet cleaning. For instance, dilute hydrofluoric acid can be used to remove the second oxide layer.

[0101] Please refer to Figure 6 In some embodiments, in step S20, after forming the second epitaxial layer 14, an N-type third epitaxial layer 15 is formed on the second epitaxial layer 14 by repeating the step of preparing the first epitaxial layer 12, so that the plurality of third doped regions 23 are located directly above the plurality of first doped regions 21, so as to obtain the first doped regions 21, the second doped regions 22, and the third doped regions 23 arranged in a uniformly spaced array, so as to form a uniform voltage withstand or heat dissipation distribution.

[0102] Please refer to Figures 7-10 In some embodiments, step S30, forming multiple gate structures includes steps S31-S38.

[0103] Step S31: Form an N-type fourth initial epitaxial layer 161 on the top surface of the third epitaxial layer 15.

[0104] For example, please continue to refer to Figure 7 The second doped region 22 has the same linear spacing as its two adjacent first doped regions 21 or two third doped regions 23 along the first direction, i.e., linear spacing d1 = linear spacing d2 = linear spacing d3 = linear spacing d4. A fourth initial epitaxial layer 161 with a target sheet resistance of 1.6 ohm / sq–2.4 ohm / sq is epitaxially grown on the top surface of the third epitaxial layer 15. The thickness of the N-type fourth initial epitaxial layer 161 is 10um-15um. For example, the target sheet resistance of the fourth initial epitaxial layer 161 can be 1.6 ohm / sq, 1.8 ohm / sq, 2.0 ohm / sq, 2.2 ohm / sq, or 2.4 ohm / sq, etc. For example, the thickness of the fourth initial epitaxial layer 161 can be 10um, 11um, 12um, 13um, 14um, or 15um, etc.

[0105] Step S32: Form a pad oxide layer 17 on the top surface of the fourth initial epitaxial layer.

[0106] For example, please continue to refer to Figure 8 When the fourth initial epitaxial layer comprises monocrystalline silicon, a thermal oxidation process can be used to form a pad oxide layer 17. The pad oxide layer 17 comprises SiO2.

[0107] Step S33: An ion implantation process is performed into the fourth initial epitaxial layer 161 via the pad oxide layer 17 to form a fourth epitaxial layer 16 comprising a plurality of fourth doped regions 31 spaced apart along the first direction and all being P-type.

[0108] For example, please continue to refer to Figure 8 A third patterned photoresist layer (not shown) is formed on the top surface of the pad oxide layer 17. This third patterned photoresist layer includes a third opening pattern defining parameters such as the distribution, position, size, and shape of the plurality of fourth doped regions 31. Using the third patterned photoresist layer as a mask, a third ion implantation doping process is performed into the fourth initial epitaxial layer 161 via the pad oxide layer 17, resulting in a fourth epitaxial layer 16 comprising a plurality of fourth doped regions 31 spaced apart along a first direction and all being P-type. The plurality of fourth doped regions 31 are located directly above the plurality of third doped regions 23, and the orthographic projection of the third doped regions 23 onto the bottom surface of the fourth doped regions 31 lies within the bottom surface of the fourth doped regions 31.

[0109] Step S34: An N-type source region 32 is formed in the fourth doped region 31 via the pad oxide layer 17.

[0110] For example, please continue to refer to Figure 9A fourth patterned photoresist layer (not shown) is formed on the top surface of the fourth epitaxial layer 16. The fourth patterned photoresist layer includes a fourth opening pattern (not shown) for defining parameters such as the distribution, position, size, and shape of the multiple source regions 32. Using the fourth patterned photoresist layer as a mask, a fourth ion implantation doping process is performed into the fourth doped region 31 through the pad oxide layer 17 to obtain multiple source regions 32 that are spaced apart along the first direction and are all N-type. The source regions 32 are located inside the fourth doped region 31.

[0111] Step S35: Form a gate conductive material layer on the top surface of the pad oxide layer 17.

[0112] For example, please continue to refer to Figure 9 After removing the fourth patterned photoresist layer, a gate conductive material layer is formed on the top surface of the pad oxide layer 17 using a deposition process. The gate conductive material layer may include doped polysilicon.

[0113] Step S36: The gate conductive material layer is patterned to obtain a plurality of gate conductive layers 19 spaced apart along a first direction, the plurality of gate conductive layers 19 being located directly above the plurality of source regions 32.

[0114] For example, please continue to refer to Figure 9 A fifth patterned photoresist layer (not shown) is formed on the top surface of the gate conductive material layer. This fifth patterned photoresist layer includes a fifth opening pattern (not shown) for defining parameters such as the distribution, location, size, and shape of the multiple trenches. Using the fifth patterned photoresist layer as a mask, the gate conductive material layer is dry etched to obtain a gate conductive layer 19 defined by multiple trenches (not shown). The multiple trenches expose the top surfaces of multiple source regions 32.

[0115] Step S37: Form a dielectric layer 18 with its top surface flush with and higher than the top surface of the gate conductive layer 19, and fill the gap between adjacent gate conductive layers 19.

[0116] For example, please continue to refer to Figure 9 After removing the fifth patterned photoresist layer, a dielectric layer 18 can be formed by a deposition process to fill the gap between adjacent gate conductive layers 19, with the top surface of the dielectric layer 18 being higher than the top surface of the gate conductive layer 19.

[0117] Step S38: The dielectric layer 18 is patterned to obtain a plurality of grooves spaced apart along the first direction. The remaining dielectric layer 18 covers the side surface and top surface of the gate conductive layer 19 and is used to form a gate dielectric layer together with the pad oxide layer 17 between the gate conductive layer 19 and the fourth epitaxial layer 16. The grooves expose the source region 32 directly below them. The gate dielectric layer and the gate conductive layer 19 within its enclosing space are used to form a gate structure together.

[0118] For example, please continue to refer to Figure 10After planarizing the top surface of the dielectric layer 18, a sixth patterned photoresist layer (not shown) is formed on the top surface of the dielectric layer 18. The sixth patterned photoresist layer includes a sixth opening pattern (not shown) for defining parameters such as the distribution, position, size, and shape of multiple trenches. Using the sixth patterned photoresist layer as a mask, the dielectric layer 18 in the trenches is dry etched to obtain multiple trenches (not shown) spaced apart along the first direction. The trenches expose part of the top surface of the source region 32. The remaining dielectric layer 18 covers the side surface and top surface of the gate conductive layer 19. The remaining dielectric layer 18, together with the remaining pad oxide layer 17, constitutes the gate dielectric layer. The gate dielectric layer and the gate conductive layer 19 within its enclosing space constitute the gate structure.

[0119] For example, please continue to refer to Figure 10 Multiple gate structures can be formed on the top surface of the third epitaxial layer 15 based on the aforementioned target photomask, with spacing along the first direction. By setting multiple gate structures directly above multiple third doped regions 23, the dimensions of the third doped regions 23 along the first direction are p / 4-p / 3, where p is the linear spacing between adjacent gate structures. This not only avoids increasing the cost and complexity of the process due to the increase in the number of photomasks, but also utilizes the depletion region formed by the uniformly spaced array of the first doped regions 21, the second doped regions 22, and the third doped regions 23 to disperse and optimize the current path, making the current distribution more uniform and avoiding local current congestion (reducing heat generation); it can also shorten the current flow distance or reduce the potential barrier in the path, thereby reducing the resistance.

[0120] Please continue to refer to this. Figure 10 In some embodiments, after forming multiple gate structures, the method further includes:

[0121] Step S41: Form a plurality of conductive plugs 33 in a plurality of grooves;

[0122] Step S42: Form a source conductive layer 34 covering multiple conductive plugs 33 and the remaining dielectric layer 18.

[0123] For example, please continue to refer to Figure 10 Conductive materials (such as tungsten, titanium / titanium nitride composite layers, etc.) can be filled into the groove to form a vertical conductive connection structure, also known as a "contact plug" or "through-hole plug", to achieve electrical interconnection between the source conductive layer 34 and the underlying semiconductor.

[0124] Please continue to refer to this. Figure 10 In some embodiments, the size of the first doped region 21 along the first direction is p / 4-p / 3, for example, p / 3; the thickness of the first doped region 21 is 0.49-0.50 to the thickness of the first epitaxial layer 12, for example, 0.50.

[0125] Please continue to refer to this. Figure 10In some embodiments, the size of the second doped region 22 along the first direction is p / 4-p / 3, for example, p / 3; the thickness ratio of the second doped region 22 to the thickness of the second epitaxial layer 14 is 0.49-0.50, for example, 0.50.

[0126] Please continue to refer to this. Figure 10 In some embodiments, the thickness ratio of the third doped region 23 to the thickness of the third epitaxial layer 15 is 0.49-0.50, for example, 0.50.

[0127] In the above embodiments, by carefully designing the structural parameters of the P-type floating gate, low turn-off loss and low on-resistance can be obtained, while the flow path of the current inside the device can be improved (for example, the current is made to pass through the low-resistance region more concentratedly, and detours or congestion are reduced), thereby achieving a better balance between switching and conduction characteristics.

[0128] Please refer to Figures 11-12 In some embodiments, the linear spacing between the second doped region 22 and its adjacent first doped region 21 or third doped region 23 is equal, resulting in a uniformly spaced array of first doped regions 21, second doped regions 22, and third doped regions 23, forming a uniform breakdown voltage or heat dissipation distribution. The first doped region 21, second doped region 22, and third doped region 23, all being P-type, can constitute a P-shaped floating gate. When the device is turned on, the P-shaped floating gate is a minority carrier structure and does not participate in conduction. The current flowing from the drain to the source, i.e., the drain-source current Ids0, is as follows: Figure 11 As shown by the dashed line. When the device is turned off, the P-shaped floating gate draws electrons from the drift region, forming a depletion region, as shown. Figure 12 As shown in the middle circular area. Compared to Figure 13 There is no P-type doped region in the first epitaxial layer 12. Figure 11 The P-shaped floating gates arranged in a mid-space array can maintain the device's withstand voltage, reduce the electron movement path, achieve fast turn-off, and reduce device turn-off losses, usage losses, and heat dissipation. Figure 14 The P-type post 35 does not participate in conduction and occupies a large area of ​​the drift region, which leads to local concentration of drain-source current Ids1 and affects the reliability of the device.

[0129] Please continue to refer to this. Figure 10In some embodiments, a semiconductor structure is provided, including a substrate 11, and a first epitaxial layer 12, a second epitaxial layer 14, and a third epitaxial layer 15, all of which are N-type, sequentially stacked on the substrate 11 in a direction away from the substrate 11; the top of the first epitaxial layer 12 includes a plurality of first doped regions 21, all of which are P-type, spaced apart along a first direction parallel to the substrate 11; the top of the second epitaxial layer 14 includes a plurality of second doped regions 22, all of which are P-type, spaced apart along the first direction; the top of the third epitaxial layer 15 includes a plurality of third doped regions 23, all of which are P-type, spaced apart along the first direction; the second doped region 22 has the same linear spacing as any two adjacent first doped regions 21 or two adjacent third doped regions 23 along the first direction; the plurality of third doped regions 23 are located directly above the plurality of first doped regions 21; wherein, the top surface of the third epitaxial layer 15 includes a plurality of gate structures spaced apart along the first direction; the plurality of gate structures are located directly above the plurality of third doped regions 23; the size of the third doped region 23 along the first direction is p / 4-p / 3, where p is the linear spacing between adjacent gate structures.

[0130] Please continue to refer to this. Figure 10 The above-described embodiments of this application can produce at least the following unexpected technical effects:

[0131] By setting the linear spacing between the second doped region 22 and its adjacent first doped region 21 or third doped region 23 to be equal, a uniformly spaced array of first doped regions 21, second doped regions 22, and third doped regions 23 is obtained. The depletion region formed by the uniformly spaced array of first doped regions 21, second doped regions 22, and third doped regions 23 disperses and optimizes the current path, making the current distribution more uniform and avoiding local current congestion (reducing heat generation); it can also shorten the current flow distance or lower the potential barrier in the path, thereby reducing resistance. The first doped region 21, second doped region 22, and third doped region 23, all of which are P-type, can form a P-shaped floating gate. When the device is turned on, the P-shaped floating gate is a minority carrier structure and does not participate in conduction; when the device is turned off, the P-shaped floating gate extracts electrons from the drift region to form a depletion region, maintaining the device's breakdown voltage, reducing the electron movement path, achieving fast turn-off, and reducing device turn-off losses, usage losses, and heat dissipation.

[0132] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; Based on the same target photomask, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, all of which are N-type, are sequentially stacked on the top surface of the substrate in a direction away from the substrate. The top of the first epitaxial layer includes a plurality of first doped regions, all of which are P-type, spaced apart along a first direction parallel to the substrate. The top of the second epitaxial layer includes a plurality of second doped regions, all of which are P-type, spaced apart along the first direction. The top of the third epitaxial layer includes a plurality of third doped regions, all of which are P-type, spaced apart along the first direction. The linear spacing between each second doped region and any two adjacent first doped regions or two adjacent third doped regions along the first direction is the same. The plurality of third doped regions are located directly above the plurality of first doped regions. A plurality of gate structures are formed on the top surface of the third epitaxial layer at intervals along the first direction. The plurality of gate structures are located directly above the plurality of third doped regions. The dimensions of the third doped regions along the first direction are p / 4-p / 3, where p is the linear spacing between adjacent gate structures.

2. The semiconductor structure fabrication method according to claim 1, characterized in that, Includes at least one of the following features: The dimension of the first doped region along the first direction is p / 4-p / 3, and the ratio of the thickness of the first doped region to the thickness of the first epitaxial layer is 0.49-0.50; The dimension of the second doped region along the first direction is p / 4-p / 3; the ratio of the thickness of the second doped region to the thickness of the second epitaxial layer is 0.49-0.50; The ratio of the thickness of the third doped region to the thickness of the third epitaxial layer is 0.49-0.

50.

3. The semiconductor structure fabrication method according to claim 1, characterized in that, The first epitaxial layer forming the N-type includes: A first initial epitaxial layer of type N with a target sheet resistance value is formed on the top surface of the substrate; A first oxide layer is formed on the top surface of the first initial epitaxial layer; A first patterned photoresist layer is formed on the top surface of the first oxide layer based on the target photomask, and the first patterned photoresist layer includes a plurality of first opening patterns for defining the plurality of first doped regions; Using the first patterned photoresist layer as a mask, a first ion implantation doping process is performed into the first initial epitaxial layer via the first oxide layer to form a first epitaxial layer comprising a plurality of first doped regions of P type; the thickness ratio of the first doped region to the thickness of the first initial epitaxial layer is 0.49-0.

50.

4. The semiconductor structure fabrication method according to claim 1, characterized in that, The photomask forming the plurality of second doped regions is obtained by translating the target photomask along the first direction by a first preset distance, wherein the first preset distance is related to the straight-line spacing between adjacent first doped regions along the first direction.

5. The semiconductor structure fabrication method according to claim 1, characterized in that, After forming the second epitaxial layer, an N-type third epitaxial layer is formed on the second epitaxial layer by repeating the steps of preparing the first epitaxial layer.

6. The semiconductor structure fabrication method according to claim 3, characterized in that, The second epitaxial layer forming the N-type includes: Remove the first patterned photoresist layer and the first oxide layer; A second initial epitaxial layer of type N with the target sheet resistance value is formed on the top surface of the first epitaxial layer; A second oxide layer is formed on the top surface of the second initial epitaxial layer; Based on the translated target photomask, a second patterned photoresist layer is formed on the top surface of the second oxide layer, and the second patterned photoresist layer includes a plurality of second opening patterns for defining the plurality of second doped regions; Using the second patterned photoresist layer as a mask, a second ion implantation doping process is performed into the second initial epitaxial layer via the second oxide layer to form a second epitaxial layer comprising a plurality of second doped regions of P type; the thickness ratio of the second doped region to the thickness of the second initial epitaxial layer is 0.49-0.

50.

7. The semiconductor structure fabrication method according to claim 3, characterized in that, The target sheet resistance value is 1.6 ohm / sq–2.4 ohm / sq; and / or The ion implantation dose in the first ion implantation doping process is 1E15cm. -2 -5E16cm -2 .

8. The semiconductor structure fabrication method according to claim 1, characterized in that, Forming multiple gate structures includes: An N-type fourth initial epitaxial layer is formed on the top surface of the third epitaxial layer; A pad oxide layer is formed on the top surface of the fourth initial epitaxial layer; An ion implantation process is performed into the fourth initial epitaxial layer via the pad oxide layer to form a fourth epitaxial layer comprising a plurality of fourth doped regions that are spaced apart along the first direction and are all P-type. An N-type source region is formed in the fourth doped region via the pad oxide layer; A gate conductive material layer is formed on the top surface of the gasket oxide layer; The gate conductive material layer is graphically processed to obtain a plurality of gate conductive layers spaced apart along the first direction, the plurality of gate conductive layers being located directly above the plurality of source regions; A dielectric layer is formed with its top surface flush with and higher than the top surface of the gate conductive layer, and the dielectric layer fills the gap between adjacent gate conductive layers; Based on the target photomask patterning, the dielectric layer is processed to obtain a plurality of grooves spaced apart along the first direction. The remaining dielectric layer covers the side surface and top surface of the gate conductive layer, and together with the pad oxide layer between the gate conductive layer and the fourth epitaxial layer, it forms the gate dielectric layer. The grooves expose the source region directly below them. The gate dielectric layer and the gate conductive layer within its enclosing space are used to jointly form the gate structure.

9. The semiconductor structure fabrication method according to claim 8, characterized in that, After forming multiple gate structures, it also includes: Multiple conductive plugs are formed within the multiple grooves; A source conductive layer is formed covering the plurality of conductive plugs and the remaining dielectric layer.

10. A semiconductor structure, characterized in that, The system includes a substrate, and three epitaxial layers, all of type N, stacked sequentially on the substrate in a direction away from the substrate. The top of the first epitaxial layer includes a plurality of first doped regions, all of type P, spaced apart along a first direction parallel to the substrate. The top of the second epitaxial layer includes a plurality of second doped regions, all of type P, spaced apart along the first direction. The top of the third epitaxial layer includes a plurality of third doped regions, all of type P, spaced apart along the first direction. The linear spacing between each second doped region and any two adjacent first doped regions or two adjacent third doped regions along the first direction is the same. The plurality of third doped regions are located directly above the plurality of first doped regions. The top surface of the third epitaxial layer includes a plurality of gate structures spaced apart along the first direction. The plurality of gate structures are located directly above the plurality of third doped regions. The size of the third doped region along the first direction is p / 4-p / 3, where p is the linear spacing between adjacent gate structures.

Images