Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: sequentially forming a channel layer, a barrier layer and a gate cap layer doped with a p-type doping element on a substrate to obtain an intermediate semiconductor structure; placing the intermediate semiconductor structure in a first chamber, wherein the concentration of the p-type doping element in the environment of the first chamber is less than 1*10 16 cm ‑3 -2; forming a blocking layer on the side of the gate cap layer away from the barrier layer; and forming a gate metal on the side of the blocking layer away from the gate cap layer. The voltage resistance and reliability of the gate in the semiconductor device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a semiconductor device and its fabrication method. Background Technology

[0002] Semiconductor devices can include heterojunction bipolar transistors (HBTs), heterojunction field-effect transistors (HFETs), high electron mobility transistors (HEMTs), and modulation-doped FETs (MODFETs). HEMT devices can include enhancement-mode HEMTs and depletion-mode HEMTs. For example, enhancement-mode HEMTs can include p-GaN (p-type gallium nitride) gate enhancement-mode HEMTs; however, the reliability of p-GaN gate enhancement-mode HEMTs still needs further improvement. Summary of the Invention

[0003] This application addresses the shortcomings of related technologies by proposing a semiconductor device and its fabrication method to solve the problem that the reliability of the gate of semiconductor devices in related technologies still needs to be improved.

[0004] This application provides a method for fabricating a semiconductor device, comprising: A channel layer, a barrier layer, and a gate cap layer doped with p-type doped elements are sequentially formed on a substrate to obtain an intermediate semiconductor structure. The intermediate semiconductor structure is placed in a first chamber, where the concentration of p-type dopant in the environment of the first chamber is less than 1 × 10⁻⁶. 16 cm -3 ; A barrier layer is formed on the side of the gate cap layer away from the barrier layer; A gate metal is formed on the side of the barrier layer away from the gate cap layer.

[0005] This application also provides a semiconductor device, including: Substrate; A channel layer is located on one side of the substrate; A barrier layer is located on the side of the channel layer away from the substrate; A gate cap layer is located on the side of the barrier layer away from the channel layer, and the gate cap layer is doped with p-type dopant. A barrier layer is located on the side of the gate cap layer away from the barrier layer; the concentration of p-type dopant on the surface of the barrier layer away from the substrate is less than 95% of the maximum concentration of p-type dopant at various points in the gate cap layer and the barrier layer, and greater than the concentration of p-type dopant on the surface of the gate cap layer near the substrate. The gate metal is located on the side of the barrier layer away from the gate cap layer and is in contact with the barrier layer.

[0006] The beneficial effects of this application include: In this embodiment, during the fabrication process, the intermediate semiconductor structure after the formation of the gate cap layer is placed in a first chamber free of p-type dopant. This reduces the concentration of p-type dopant in the barrier layer during its formation, further reducing the concentration of p-type dopant at the interface between the barrier layer and the gate metal. This, in turn, reduces the electric field at the Schottky interface, slows down the degradation of the Schottky junction, and improves the breakdown voltage and reliability of the gate metal in the semiconductor device. For example, the concentration of p-type dopant at the interface between the barrier layer and the gate metal is lower than the maximum concentration of p-type dopant at various points in both the gate cap layer and the barrier layer.

[0007] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0009] Figure 1 The diagram shown is a schematic representation of the structure of a semiconductor device in the related technology. Figures 2a-2d The diagram shown is a schematic representation of the steps in a method for fabricating a semiconductor device according to an embodiment of this application. Figures 3a-3f The diagram shown is a schematic diagram of the steps in another method for fabricating a semiconductor device according to an embodiment of this application. Figures 4-12 The diagram shows the structure of several semiconductor devices provided in the exemplary embodiments of this application.

[0010] In the figure: 1-substrate; 2-channel layer; 3-barrier layer; 41-gate cap layer; 42-source; 43-drain; 5-gate metal; 6-barrier layer; 61-first barrier layer; 62-second barrier layer; 63-third barrier layer; 64-fourth barrier layer; 71-first transition layer; 72-second transition layer; 73-third transition layer; RC1-first chamber; RC2-second chamber; 10-p-type doped element. Detailed Implementation

[0011] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0012] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0013] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0014] Research has found that enhancement-mode HEMT devices can include p-GaN (p-type gallium nitride) gate structure enhancement-mode HEMT devices, with structures such as... Figure 1 As shown, the structure includes a substrate 1, a channel layer 2, a gate cap layer 41, and a gate metal 5, which are sequentially stacked, as well as a source 42 and a drain 43 located on both sides of the gate metal 5. When a high positive voltage is applied to the gate metal 5, a high electric field is formed at the Schottky interface between the gate cap layer 41 and the gate metal 5. After long-term high gate voltage stress, the Schottky interface will degrade, making electrons easier to tunnel through, causing a sharp increase in gate leakage current and leading to reliability problems such as breakdown failure.

[0015] The semiconductor device and its fabrication method provided in this application are intended to solve the above-mentioned technical problems in related technologies.

[0016] The semiconductor devices and their fabrication methods in the embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments may complement or combine with each other.

[0017] This application provides a method for fabricating a semiconductor device, comprising the following steps: Step 100: As Figure 2a or Figure 3a As shown, a channel layer 2, a barrier layer 3, and a gate cap layer 41 doped with p-type dopant element 10 are sequentially formed on substrate 1 to obtain an intermediate semiconductor structure. Step 200: As Figure 2b or Figure 3d As shown, the intermediate semiconductor structure is placed in the first chamber RC1, and the concentration of p-type dopant 10 in the environment of the first chamber RC1 is less than 1 × 10⁻⁶. 16 cm -3 ; Step 300: As Figure 2c or Figure 3e As shown, a barrier layer 6 is formed on the side of the first transition layer 71 away from the gate cap layer 41; Step 400: As Figure 2d or Figure 3f As shown, gate metal 5 is formed on the side of the barrier layer 6 away from the gate cap layer 41.

[0018] Compared to the process of introducing a p-type dopant source into the reaction chamber during the formation of the gate cap layer 41, the reaction chamber after the gate cap layer 41 is fabricated will have residual p-type dopant element 10. This will result in a higher concentration of p-type dopant element 10 in the barrier layer 6 when the barrier layer 6 is formed in the reaction chamber. This will further result in a higher interfacial electric field of the Schottky junction formed between the gate metal 5 and the gate cap layer 41 under forward bias, thereby limiting the forward breakdown voltage capability of the gate metal 5. In addition, a higher concentration of p-type dopant element 10 will lead to an increase in gate leakage current and reduce gate reliability. In this embodiment, during the fabrication process, the intermediate semiconductor structure after the formation of the gate cap layer 41 is placed in the first chamber RC1 without p-type dopant 10. Therefore, when forming the barrier layer 6, the concentration of p-type dopant 10 in the barrier layer 6 can be reduced. This further reduces the concentration of p-type dopant 10 at the interface between the barrier layer 6 and the gate metal 5, thereby reducing the electric field at the Schottky interface, slowing down the degradation of the Schottky junction, and improving the breakdown voltage and reliability of the gate metal 5 in the semiconductor device. For example, the concentration of p-type dopant 10 at the interface between the barrier layer 6 and the gate metal 5 is lower than the maximum concentration of p-type dopant 10 at various points in the gate cap layer 41 and the barrier layer 6.

[0019] In some embodiments, substrate 1 may comprise silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs) or other semiconductor materials, and may also comprise sapphire, silicon-on-insulator (SOI) or other suitable materials.

[0020] In some embodiments, the channel layer 2 may comprise nitrides, such as gallium nitride (GaN), aluminum nitride (AlN), or aluminum gallium nitride (Al). x Ga 1-x N, where 0 < x < 1, etc. The channel layer 2 can be gallium nitride (GaN), and the band gap of GaN is approximately 3.4 eV. In addition, a buffer layer can be disposed between the channel layer 2 and the substrate 1 to reduce the lattice mismatch between the substrate 1 and the channel layer 2.

[0021] In some embodiments, barrier layer 3 may include a group III-V compound, such as indium aluminum gallium nitride (In... a Al b Ga 1-a-b N, where a+b≤1). Further, barrier layer 3 may include the compound aluminum gallium nitride (Al₂O₃). x Ga 1-x N, where x≤1), compound indium aluminum nitrogen (In x Al 1-x N, where x < 1). The band gap of barrier layer 3 can be larger than the band gap of channel layer 2, and barrier layer 3 can be indium gallium nitride (InGaN). x Ga 1-x N, where x≤1), Al x Ga 1-x The band gap of N is approximately 3.4 to 6.2 eV.

[0022] It should be noted that due to the band difference between the channel layer 2 and the barrier layer 3, the barrier layer 3 can form a potential well for electrons, which restricts the movement of electrons in the direction perpendicular to the barrier layer 3, while allowing them to move freely in the plane of the barrier layer 3, thus forming a two-dimensional electron gas (2DEG) region.

[0023] In some embodiments, the gate cap layer 41 is made of p-GaN.

[0024] In some embodiments, the thickness of the gate cap layer 41 ranges from 10 to 100 nm. For example, the thickness of the gate cap layer 41 can be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm.

[0025] In some embodiments, the p-type dopant 10 includes Mg.

[0026] In some embodiments, the material of the gate metal 5 may include titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and its compounds (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum-copper alloys (Al-Cu)) or other suitable materials.

[0027] In some embodiments, step 100, which involves sequentially forming a channel layer 2, a barrier layer 3, and a gate cap layer 41 doped with p-type dopant element 10 on the substrate 1 to obtain an intermediate semiconductor structure, specifically includes: Step 110: Form a channel layer 2 and a barrier layer 3 sequentially on the substrate 1; Step 120: Form a gate cap layer 41 on the side of the barrier layer 3 away from the channel layer 2; wherein, the process of forming the gate cap layer 41 on the side of the barrier layer 3 away from the channel layer 2 in step 120 is carried out in the second chamber RC2, and the concentration of p-type doped elements in the second chamber RC2 is higher than the concentration of p-type doped elements in the first chamber RC1.

[0028] Step 200, placing the intermediate semiconductor structure within the first chamber RC1, includes: Step 210: As Figures 2a-2b As shown, the intermediate semiconductor structure is transferred from the second chamber RC2 to the first chamber RC1.

[0029] In this embodiment, by changing the chamber, that is, transferring the intermediate semiconductor structure from the second chamber RC2 to the first chamber RC1, the p-type dopant element 10 is eliminated in the environment during the fabrication of the barrier layer 6, thereby reducing the concentration of the p-type dopant element 10 at the Schottky interface between the barrier layer 6 and the gate metal 5, and improving the voltage withstand capability and reliability of the gate metal 5.

[0030] In some other embodiments, the fabrication process of forming the gate cap layer 41 on the side of the barrier layer 3 away from the channel layer 2 in step 120 is performed in the first chamber RC1. In this case, after forming the gate cap layer 41 on the side of the barrier layer 3 away from the channel layer 2 in step 120, the process further includes: Step 130: As Figures 3a-3b As shown, the intermediate semiconductor structure is removed from the first chamber RC1; In step 200, the intermediate semiconductor structure is placed within the first chamber RC1 (see...). Figure 3e Before that, it also includes: Step 140: As Figures 3b-3c As shown, the p-type dopant element 10 remaining in the first chamber RC1 is removed.

[0031] In this embodiment, the p-type dopant 10 can be removed by cleaning the chamber to achieve an environment free of p-type dopant 10 during the fabrication of the barrier layer 6. This reduces the concentration of p-type dopant 10 at the Schottky interface between the barrier layer 6 and the gate metal 5, thereby improving the voltage withstand capability and reliability of the gate metal 5.

[0032] In some embodiments, combined with Figure 4 The semiconductor device shown further includes, after step 400, forming the gate metal 5 on the side of the barrier layer 6 away from the gate cap layer 41: Step 500: A source 42 and a drain 43 are formed on the side of the barrier layer 3 away from the substrate 1. The source 42 and the drain 43 are both spaced apart from the gate cap layer 41, and the source 42 and the drain 43 can be disposed on opposite sides of the gate cap layer 41.

[0033] In some embodiments, the source electrode 42 may include a conductive material, which may include a metal, alloy, doped semiconductor material (e.g., doped crystalline silicon), or other suitable conductive material such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable materials. The drain electrode 43 may include a conductive material, which may include a metal, alloy, doped semiconductor material (e.g., doped crystalline silicon), or other suitable conductive material such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable materials.

[0034] In some embodiments, combined with Figure 5 The semiconductor device shown, after placing the intermediate semiconductor structure in the first chamber RC1 in step 200 and before forming the barrier layer 6 on the side of the gate cap layer 41 away from the barrier layer 3 in step 300, further includes the following steps: Step 400: A first transition layer 71 is formed on the side of the gate cap layer 41 away from the barrier layer 3, and a precursor source without p-type dopant element 10 is used to form the first transition layer 71.

[0035] In this embodiment, considering that after the gate cap layer 41 is formed, its surface is relatively rough and uneven due to doping, resulting in defects such as pits, a first transition layer 71 is applied to the surface of the gate cap layer 41 before forming the barrier layer 6. During its growth, the first transition layer 71 fills the pits and defects on the surface of the gate cap layer 41 and grows to a smooth surface. Therefore, when the barrier layer 6 is subsequently formed, it covers a relatively smooth surface on the first transition layer 71, which helps improve the crystal growth quality and form a high-quality barrier layer 6. This enhances the effect of blocking electron impacts below the gate metal 5. On the other hand, since the first transition layer 71 is not doped with p-type dopant 10, the introduction of p-type dopant 10 into the first chamber RC1 during the subsequent formation of the barrier layer 6 will not increase the concentration of p-type dopant 10 at the interface between the barrier layer 6 and the gate metal 5. Therefore, the concentration of p-type dopant 10 at the interface between the barrier layer 6 and the gate metal 5 remains low, which helps reduce the electric field.

[0036] In some embodiments, the first transition layer 71 is made of GaN. Thus, the first transition layer 71 can serve as a buffer medium to fill defects on the surface of the gate cap layer 41. Exemplarily, the first transition layer 71 is made of unintentionally doped GaN (u-GaN). Specifically, unintentionally doped GaN refers to GaN materials that are not actively doped during growth but exhibit a specific (typically n-type) conductivity type due to process and environmental factors. In other embodiments, the first transition layer 71 is made of AlGaN, with an Al content of less than or equal to 10%. In this embodiment, no new p-type dopant element 10 is introduced during the fabrication of the first transition layer 71. Exemplarily, the first transition layer 71 can be made of AlGaN with an Al content of 5%.

[0037] In some embodiments, continue to combine Figure 5 The semiconductor device shown includes a barrier layer 6 comprising a first barrier layer 61, wherein the bandgap width of the first barrier layer 61 is greater than the bandgap width of the gate cap layer 41, wherein forming the barrier layer 6 on the side of the gate cap layer 41 away from the barrier layer 3 in step 300 includes: Step 310: Form a first barrier layer 61 on the side of the gate cap layer 41 away from the barrier layer 3.

[0038] In this embodiment, the bandgap of the first barrier layer 61 is greater than the bandgap of the gate cap layer 41. Therefore, an electron barrier can be formed through the conduction band step, thereby blocking electrons and reducing gate leakage current. On the other hand, the voltage can be shared by the first barrier layer 61, resulting in a more uniform voltage distribution across the thickness of the first barrier layer 61. This significantly reduces the peak electric field at the Schottky interface and makes the electric field distribution smoother, improving the reliability of the device under high-voltage stress.

[0039] In some embodiments, the material of the first barrier layer 61 includes at least one selected from AlGaN, AlN, InGaN, and InAlN. Preferably, the material of the first barrier layer 61 includes AlGaN, and the Al content in the first barrier layer 61 is greater than or equal to 15%. For example, when the material of the first barrier layer 61 includes AlGaN with an Al content greater than or equal to 15%, the bandgap of the first barrier layer 61 is greater than or equal to 4.05 eV. When the material of the gate cap layer 41 is p-GaN, the bandgap of the gate cap layer 41 is approximately 3.4 eV.

[0040] In some embodiments, combined with Figure 6 The semiconductor device shown includes a barrier layer 6 further comprising a second transition layer 72 and a second barrier layer 62 sequentially stacked on the side of the first barrier layer 61 away from the substrate 1, wherein the band gaps of the first barrier layer 61 and the second barrier layer 62 are both greater than the band gap of the second transition layer 72; step 310, after forming the first barrier layer 61 on the side of the gate cap layer 41 away from the barrier layer 3, further includes: Step 320: A second transition layer 72 and a second barrier layer 62 are sequentially formed on the side of the first barrier layer 61 away from the gate cap layer 41.

[0041] In this embodiment, the first barrier layer 61, the second transition layer 72, and the second barrier layer 62 together constitute a "barrier-potential well-barrier" dual heterojunction structure. Since the band gap of the second transition layer 72 is smaller than that of the first barrier layer 61 and the second barrier layer 62, electrons coming from below the gate metal 5 first encounter the barrier of the first barrier layer 61, and then enter the quantum well in the second transition layer 72. Electrons may be trapped in the quantum well in the second transition layer 72 or require higher energy to escape to the second barrier layer 62. The second barrier layer 62 forms a second barrier. Electrons need to overcome two barriers to reach the gate metal 5. Therefore, the dual barrier structure can improve the effect of blocking electrons, reduce the electron impact at the interface between the gate metal 5 and the barrier layer 6, and improve reliability.

[0042] In some embodiments, the first barrier layer 61 and the second barrier layer 62 are both made of at least one of AlGaN and AlN, and the second transition layer 72 is made of GaN. Exemplarily, the first barrier layer 61 and the second barrier layer 62 are both made of AlGaN, and the second transition layer 72 is made of unintentionally doped GaN (u-GaN).

[0043] In some embodiments, the first barrier layer 61 and the second barrier layer 62 are made of the same material. Thus, the first barrier layer 61 and the second barrier layer 62 can be formed using the same manufacturing process, which simplifies the process and reduces the problem of lattice mismatch or abrupt change caused by different materials.

[0044] In some embodiments, the thickness of the second barrier layer 62 is less than the thickness of the first barrier layer 61. Therefore, when the overall thickness of the device is constant, the thickness of the second barrier layer 62 can be made relatively small, thereby preventing the second barrier layer 62 from being too thick and affecting the contact between the gate metal 5 and the barrier layer 6, thus reducing device yield. For example, the thickness of the second barrier layer 62 can be 1~10nm. The specific design can be flexibly tailored to the actual needs of the device.

[0045] Preferably, the thickness of the second barrier layer 62 is less than or equal to half the thickness of the first barrier layer 61.

[0046] In some embodiments, combined with Figure 7 The semiconductor device shown includes a third barrier layer 63 doped with an n-type dopant. Step 300, forming the barrier layer 6 on the side of the gate cap layer 41 away from the barrier layer 3, includes: Step 310': A third barrier layer 63 is formed on the side of the gate cap layer 41 away from the barrier layer 3.

[0047] In this embodiment, a pn junction is formed between the third barrier layer 63 and the gate cap layer 41. The vertical electric field distribution of the pn junction can stretch the high electric field formed by the Schottky interface in the vertical direction, thereby reducing the electric field of the Schottky interface and improving the voltage withstand capability and reliability of the gate metal 5.

[0048] In some embodiments, the material of the third barrier layer 63 includes n-GaN.

[0049] In some embodiments, combined with Figure 8 The semiconductor device shown includes a fourth barrier layer 64 located on the side of the third barrier layer 63 away from the substrate 1, wherein the bandgap width of the fourth barrier layer 64 is greater than the bandgap width of the third barrier layer 63; step 310' further includes the following after forming the third barrier layer 63 on the side of the gate cap layer 41 away from the barrier layer 3: Step 320': A fourth barrier layer 64 is formed on the side of the third barrier layer 63 away from the gate cap layer 41.

[0050] In this embodiment, an energy band difference is formed between the fourth barrier layer 64 and the third barrier layer 63. As a result, the fourth barrier layer 64 can form a potential barrier. When electrons arrive at the fourth barrier layer 64 from the third barrier layer 63, they need to cross the potential barrier of the fourth barrier layer 64 before they can enter the gate metal 5. Thus, the impact of electrons on the gate metal 5 can be blocked to a certain extent, thereby improving the reliability of the gate metal 5.

[0051] In some embodiments, the material of the fourth barrier layer 64 includes at least one of AlGaN and AlN. For example, the material of the fourth barrier layer 64 may be AlGaN.

[0052] In some embodiments, combined with Figure 9 The semiconductor device shown includes a third transition layer 73 in the barrier layer 6, which is located between the third barrier layer 63 and the fourth barrier layer 64. The material of the third transition layer 73 includes GaN. After step 310' of forming the third barrier layer 63 on the side of the gate cap layer 41 away from the barrier layer 3, and before step 320' of forming the fourth barrier layer 64 on the side of the third barrier layer 63 away from the gate cap layer 41, the following steps are also included: Step 330': A third transition layer 73 is formed on the side of the third barrier layer 63 away from the gate cap layer 41.

[0053] In this embodiment, when the third barrier layer 63 is doped with an n-type dopant, the doping process may cause defects such as roughness or even pits on its surface. The third transition layer 73 can serve as a buffer medium to fill the pits on the surface of the third barrier layer 63. Thus, a relatively flat growth surface can be provided when the fourth barrier layer 64 is formed, which is conducive to the formation of a high-quality film structure of the fourth barrier layer 64.

[0054] In some embodiments, such as Figure 10 , Figure 11 and Figure 12 As shown in any of the accompanying figures, when the barrier layer 6 includes a third barrier layer 63, the method further includes: after placing the intermediate semiconductor structure in the first chamber RC1 in step 200 and before forming the barrier layer 6 on the side of the gate cap layer 41 away from the barrier layer 3. Step 400': A first transition layer 71 is formed on the side of the gate cap layer 41 away from the barrier layer 3, and a precursor source without p-type dopant element 10 is used to form the first transition layer 71.

[0055] In this way, the gate cap layer 41, the first transition layer 71 and the third barrier layer 63 can together form a pin junction, and the first transition layer 71 can form an intrinsic layer, which can further widen the depletion region, distribute the electric field more evenly, withstand higher gate voltage swing, and have better reliability.

[0056] In some embodiments, similar to the foregoing embodiments, the material of the first transition layer 71 includes GaN; or, the material of the first transition layer 71 includes AlGaN, and the Al content in the first transition layer 71 is less than or equal to 10%.

[0057] Based on the same inventive concept, this application also provides a semiconductor structure, such as... Figures 4-12 As shown in any of the attached figures, it includes a substrate 1, a channel layer 2, a barrier layer 3, a gate cap layer 41, a barrier layer 6, and a gate metal 5.

[0058] In this configuration, the channel layer 2 is located on one side of the substrate 1; the barrier layer 3 is located on the side of the channel layer 2 away from the substrate 1; the gate cap layer 41 is located on the side of the barrier layer 3 away from the channel layer 2, and the gate cap layer 41 is doped with p-type dopant element 10; the barrier layer 6 is located on the side of the gate cap layer 41 away from the barrier layer 3; the concentration of p-type dopant element 10 on the surface of the barrier layer 6 away from the substrate 1 is less than 95% of the maximum concentration of p-type dopant element 10 at various locations in the gate cap layer 41 and the barrier layer 6, and is greater than the concentration of p-type dopant element on the surface of the gate cap layer 41 close to the substrate 10; and the gate metal 5 is located on the side of the barrier layer 6 away from the gate cap layer 41 and is in contact with the barrier layer 6.

[0059] In this embodiment, when the concentration of the p-type dopant 10 on the surface of the barrier layer 6 away from the substrate 1 is less than the maximum concentration of the p-type dopant 10 at various points in the gate cap layer 41 and the barrier layer 6, further, that is, the concentration of the p-type dopant 10 at the interface between the barrier layer 6 and the gate metal 5 is low, the electric field at the Schottky interface can be reduced, the degree of Schottky junction degradation can be slowed down, and the breakdown voltage and reliability of the gate metal 5 in the semiconductor device can be improved. Specifically, a semiconductor device with a low concentration of the p-type dopant 10 on the surface of the barrier layer 6 away from the substrate 1 can be prepared by the semiconductor device preparation method provided in the aforementioned embodiment.

[0060] It should be noted that the materials of the substrate 1, channel layer 2, barrier layer 3, gate cap layer 41, barrier layer 6, gate metal 5, source 42 and drain 43 of the semiconductor device provided in this embodiment are the same as those in the aforementioned preparation method embodiment.

[0061] In some embodiments, the concentration of the p-type dopant 10 on the surface of the barrier layer 6 away from the substrate 1 is less than 80% of the maximum concentration of the p-type dopant 10 at various locations in the gate cap layer 41 and the barrier layer 6. In this case, the concentration of the p-type dopant 10 at the interface between the barrier layer 6 and the gate metal 5 is relatively low, which is more conducive to reducing the electric field at this interface and improving device reliability. Preferably, the concentration of the p-type dopant 10 on the surface of the barrier layer 6 away from the substrate 1 is less than 50% of the maximum concentration of the p-type dopant 10 at various locations in the gate cap layer 41 and the barrier layer 6. Exemplarily, the maximum concentration of the p-type dopant 10 at various locations in the gate cap layer 41 and the barrier layer 6 ranges from 1 × 10⁻⁶. 19 cm -3 ~3×10 19 cm -3 The concentration of the p-type dopant element 10 on the surface of the barrier layer 6 away from the substrate 1 ranges from 1 × 10⁻⁶. 18 cm -3 ~5×10 18 cm -3 .

[0062] In some embodiments, secondary ion mass spectrometry (SIMS) can be used to determine the concentration of p-type dopants inside and on the surface of each film layer.

[0063] In some embodiments, the concentration of the p-type dopant 10 on the surface of the barrier layer 6 away from the substrate 1 is less than the concentration of the p-type dopant 10 on the surface of the gate cap layer 41 away from the substrate 1. In this embodiment, the concentration of the p-type dopant 10 on the surface of the gate cap layer 41 away from the substrate 1 is close to the peak concentration of the p-type dopant 10 (i.e., the maximum value of the concentration of the p-type dopant 10 at various points in the gate cap layer 41 and the barrier layer 6). Therefore, the peak concentration can be further reflected by measuring the concentration of the p-type dopant 10 on the surface of the gate cap layer 41 away from the substrate 1.

[0064] In some embodiments, the concentration of the p-type dopant 10 on the surface of the barrier layer 6 away from the substrate 1 is greater than the concentration of the p-type dopant 10 on the surface of the gate cap layer 41 near the substrate 1. Exemplarily, the concentration of the p-type dopant 10 on the surface of the gate cap layer 41 near the substrate 1 ranges from 1 × 10⁻⁶. 16 cm -3 ~5×10 16 cm -3 .

[0065] In some embodiments, the concentration of p-type dopant 10 in the barrier layer 6 gradually decreases in the direction from the substrate 1 to the barrier layer 3.

[0066] In some embodiments, the semiconductor device further includes a first transition layer 71 located between the gate cap layer 41 and the barrier layer 6. Similar to the embodiments of the aforementioned fabrication method, the first transition layer 71 can fill defects on the surface of the gate cap layer 41, improving the growth quality of the barrier layer 6.

[0067] It should be noted that the beneficial effects of the remaining embodiments of the semiconductor device are the same as those of the aforementioned preparation method, and will not be repeated hereafter.

[0068] In some embodiments, the material of the first transition layer 71 includes GaN.

[0069] In other embodiments, the first transition layer 71 is made of AlGaN, and the Al content in the first transition layer 71 is less than or equal to 10%.

[0070] In some embodiments, the p-type dopant 10 includes Mg.

[0071] In some embodiments, the barrier layer 6 includes a first barrier layer 61, the bandgap of which is greater than the bandgap of the gate cap layer 41.

[0072] In some embodiments, the material of the first barrier layer 61 includes at least one of AlGaN, AlN, InGaN, and InAlN.

[0073] In some embodiments, the material of the first barrier layer 61 includes AlGaN, and the Al content in the first barrier layer 61 is greater than or equal to 15%.

[0074] In some embodiments, the barrier layer 6 further includes a second transition layer 72 and a second barrier layer 62 sequentially stacked on the side of the first barrier layer 61 away from the substrate 1, wherein the band gap widths of the first barrier layer 61 and the second barrier layer 62 are both greater than the band gap width of the second transition layer 72.

[0075] In some embodiments, the first barrier layer 61 and the second barrier layer 62 are made of the same material.

[0076] In some embodiments, the first barrier layer 61 and the second barrier layer 62 are both made of at least one of AlGaN and AlN, and the second transition layer 72 is made of GaN.

[0077] In some embodiments, the thickness of the second barrier layer 62 is less than the thickness of the first barrier layer 61.

[0078] In some embodiments, the barrier layer 6 includes a third barrier layer 63, which is doped with an n-type dopant element.

[0079] In some embodiments, the material of the third barrier layer 63 includes n-GaN.

[0080] In some embodiments, the barrier layer 6 further includes a fourth barrier layer 64 located on the side of the third barrier layer 63 away from the substrate 1, wherein the band gap of the fourth barrier layer 64 is greater than the band gap of the third barrier layer 63.

[0081] In some embodiments, the barrier layer 6 further includes a third transition layer 73, which is located between the third barrier layer 63 and the fourth barrier layer 64, and the material of the third transition layer 73 includes GaN.

[0082] In some embodiments, the material of the fourth barrier layer 64 includes at least one of AlGaN and AlN.

[0083] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0084] The terms “center,” “upper,” “lower,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0085] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0086] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0087] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A channel layer, a barrier layer, and a gate cap layer doped with p-type doped elements are sequentially formed on a substrate to obtain an intermediate semiconductor structure. The intermediate semiconductor structure is placed in a first chamber, where the concentration of p-type dopant in the environment of the first chamber is less than 1 × 10⁻⁶. 16 cm -3 ; A barrier layer is formed on the side of the gate cap layer away from the barrier layer; A gate metal is formed on the side of the barrier layer away from the gate cap layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process of sequentially forming a channel layer, a barrier layer, and a gate cap layer doped with p-type doped elements on a substrate to obtain an intermediate semiconductor structure specifically includes: A channel layer and a barrier layer are sequentially formed on the substrate; The gate cap layer is formed on the side of the barrier layer away from the channel layer; The process of forming the gate cap layer on the side of the barrier layer away from the channel layer is carried out in a second chamber, where the concentration of p-type dopant in the second chamber is higher than that in the first chamber. The step of placing the intermediate semiconductor structure in the first chamber includes: transferring the intermediate semiconductor structure from the second chamber to the first chamber.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process of sequentially forming a channel layer, a barrier layer, and a gate cap layer doped with p-type doped elements on a substrate to obtain an intermediate semiconductor structure specifically includes: A channel layer and a barrier layer are sequentially formed on the substrate; The gate cap layer is formed on the side of the barrier layer away from the channel layer; The fabrication process of forming the gate cap layer on the side of the barrier layer away from the channel layer is carried out in the first chamber; After forming the gate cap layer on the side of the barrier layer away from the channel layer, the method further includes: Remove the intermediate semiconductor structure from the first cavity; The step of placing the intermediate semiconductor structure within the first chamber further includes: Remove any remaining p-type dopant elements from the first chamber.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of placing the intermediate semiconductor structure within the first chamber and before forming a barrier layer on the side of the gate cap layer away from the barrier layer further includes: A first transition layer is formed on the side of the gate cap layer away from the barrier layer, and the precursor source for forming the first transition layer is free of p-type doped elements.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The material of the first transition layer includes GaN; or, the material of the first transition layer includes AlGaN, and the Al content in the first transition layer is less than or equal to 10%.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The p-type doping element includes Mg.

7. The method for fabricating a semiconductor device according to any one of claims 1 to 6, characterized in that, The barrier layer includes a first barrier layer, the bandgap width of the first barrier layer being greater than the bandgap width of the gate cap layer, and forming the barrier layer on the side of the gate cap layer away from the barrier layer includes: The first barrier layer is formed on the side of the gate cap layer away from the barrier layer.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The material of the first barrier layer includes at least one of AlGaN, AlN, InGaN, and InAlN.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The first barrier layer is made of AlGaN, and the Al content in the first barrier layer is greater than or equal to 15%.

10. The method for fabricating a semiconductor device according to claim 7, characterized in that, The barrier layer further includes a second transition layer and a second barrier layer sequentially stacked on the side of the first barrier layer away from the substrate, wherein the bandgap widths of the first barrier layer and the second barrier layer are both greater than the bandgap width of the second transition layer; after forming the first barrier layer on the side of the gate cap layer away from the barrier layer, the process further includes: The second transition layer and the second barrier layer are sequentially formed on the side of the first barrier layer away from the gate cap layer.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The first barrier layer and the second barrier layer are both made of at least one of AlGaN and AlN, and the second transition layer is made of GaN.

12. The method for fabricating a semiconductor device according to claim 10, characterized in that, The thickness of the second barrier layer is less than the thickness of the first barrier layer.

13. The method for fabricating a semiconductor device according to any one of claims 1 to 6, characterized in that, The barrier layer includes a third barrier layer, the third barrier layer being doped with an n-type dopant element, and forming the barrier layer on the side of the gate cap layer away from the barrier layer includes: The third barrier layer is formed on the side of the gate cap layer away from the barrier layer.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The material of the third barrier layer includes n-GaN.

15. The method for fabricating a semiconductor device according to claim 13, characterized in that, The barrier layer further includes a fourth barrier layer located on the side of the third barrier layer away from the substrate, the bandgap width of the fourth barrier layer being greater than the bandgap width of the third barrier layer; after forming the third barrier layer on the side of the gate cap layer away from the barrier layer, the process further includes: The fourth barrier layer is formed on the side of the third barrier layer away from the gate cap layer.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, The material of the fourth barrier layer includes at least one of AlGaN and AlN.

17. The method for fabricating a semiconductor device according to claim 15, characterized in that, The barrier layer further includes a third transition layer, which is located between the third barrier layer and the fourth barrier layer, and the material of the third transition layer includes GaN; the process of forming the third barrier layer on the side of the gate cap layer away from the barrier layer and forming the fourth barrier layer on the side of the third barrier layer away from the gate cap layer further includes: The third transition layer is formed on the side of the third barrier layer away from the gate cap layer.

18. A semiconductor device, characterized in that, include: Substrate; A channel layer is located on one side of the substrate; A barrier layer is located on the side of the channel layer away from the substrate; A gate cap layer is located on the side of the barrier layer away from the channel layer, and the gate cap layer is doped with p-type dopant. A barrier layer is located on the side of the gate cap layer away from the barrier layer; the concentration of p-type dopant on the surface of the barrier layer away from the substrate is less than 95% of the maximum concentration of p-type dopant at various points in the gate cap layer and the barrier layer, and greater than the concentration of p-type dopant on the surface of the gate cap layer near the substrate. The gate metal is located on the side of the barrier layer away from the gate cap layer and is in contact with the barrier layer.

19. The semiconductor device according to claim 18, characterized in that, The concentration of p-type dopant on the side of the barrier layer away from the substrate is 80% of the maximum concentration of p-type dopant at various points in the gate cap layer and the barrier layer.

20. The semiconductor device according to claim 18, characterized in that, The semiconductor device further includes a first transition layer located between the gate cap layer and the barrier layer.

21. The semiconductor device according to claim 20, characterized in that, The material of the first transition layer includes GaN; or, the material of the first transition layer includes AlGaN, and the Al content in the first transition layer is less than or equal to 10%.

22. The semiconductor device according to claim 18, characterized in that, The p-type doping element includes Mg.

23. The semiconductor device according to any one of claims 18 to 22, characterized in that, The barrier layer includes a first barrier layer, the bandgap width of which is greater than the bandgap width of the gate cap layer.

24. The semiconductor device according to claim 23, characterized in that, The material of the first barrier layer includes at least one of AlGaN, AlN, InGaN, and InAlN.

25. The semiconductor device according to claim 24, characterized in that, The first barrier layer is made of AlGaN, and the Al content in the first barrier layer is greater than or equal to 15%.

26. The semiconductor device according to claim 23, characterized in that, The barrier layer further includes a second transition layer and a second barrier layer stacked sequentially on the side of the first barrier layer away from the substrate, wherein the bandgap widths of the first barrier layer and the second barrier layer are both greater than the bandgap width of the second transition layer.

27. The semiconductor device according to claim 26, characterized in that, The first barrier layer and the second barrier layer are made of the same material.

28. The semiconductor device according to claim 26, characterized in that, The first barrier layer and the second barrier layer are both made of at least one of AlGaN and AlN, and the second transition layer is made of GaN.

29. The semiconductor device according to claim 26, characterized in that, The thickness of the second barrier layer is less than the thickness of the first barrier layer.

30. The semiconductor device according to any one of claims 18 to 22, characterized in that, The barrier layer includes a third barrier layer, which is doped with an n-type dopant element.

31. The semiconductor device according to claim 30, characterized in that, The material of the third barrier layer includes n-GaN.

32. The semiconductor device according to claim 30, characterized in that, The barrier layer further includes a fourth barrier layer located on the side of the third barrier layer away from the substrate, wherein the bandgap width of the fourth barrier layer is greater than that of the third barrier layer.

33. The semiconductor device according to claim 32, characterized in that, The barrier layer further includes a third transition layer, which is located between the third barrier layer and the fourth barrier layer, and the material of the third transition layer includes GaN.

34. The semiconductor device according to claim 32, characterized in that, The material of the fourth barrier layer includes at least one of AlGaN and AlN.

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