Gallium nitride high electron mobility transistor

Abstract

The application discloses a gallium nitride high electron mobility transistor. The gallium nitride high electron mobility transistor comprises a substrate, a channel layer and a barrier layer arranged in sequence along a direction away from the substrate, a gate electrode arranged on a side of the barrier layer away from the substrate, a passivation layer covering the gate electrode and the barrier layer, two first electrode vias arranged on opposite sides of the gate electrode in a first direction, each first electrode via penetrating the passivation layer, and a bottom of the first electrode via extending into the barrier layer at least, the first direction being parallel to the substrate, two first conductive structures corresponding to the two first electrode vias respectively, and a first wiring layer arranged on a surface of the passivation layer away from the substrate, covering each first electrode via, and connected with the first conductive structures.

Description

Related applications

[0001] This application is a divisional application of Chinese invention patent application number 202610312630.5, filed on March 13, 2026, entitled "Gallium Nitride High Electron Mobility Transistor and its Fabrication Method Thereof". Technical Field

[0002] This invention relates to the field of semiconductor technology, and more particularly to gallium nitride high electron mobility transistors. Background Technology

[0003] Due to their high electron mobility, high breakdown voltage, and high frequency characteristics, high electron mobility transistors (HEMTs) are widely used in fields such as radio frequency communication and power electronics.

[0004] However, existing high electron mobility transistors (HEMTs) still need improvement. Summary of the Invention

[0005] The purpose of this application is to provide a gallium nitride high electron mobility transistor.

[0006] This application discloses a gallium nitride high electron mobility transistor, comprising: Substrate; A channel layer and a barrier layer are sequentially disposed along a direction away from the substrate; A gate electrode is disposed on the side of the barrier layer away from the substrate; A passivation layer covers the gate electrode and the barrier layer; Two first electrode vias are disposed on opposite sides of the gate electrode in a first direction. Each first electrode via penetrates the passivation layer, and in a direction toward the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. The first direction is parallel to the substrate. In a direction away from the substrate and perpendicular to the substrate, the cross-sectional area of ​​the first electrode via gradually increases. The two first electrode vias are a source electrode via and a drain electrode via, respectively. Two first conductive structures are filled one-to-one with the two first electrode vias. The bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. The bottom of the first conductive structure is in contact with the barrier layer to form an ohmic contact. A first wiring layer is disposed on the surface of the passivation layer away from the substrate and covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via.

[0007] In some alternative embodiments, along a direction away from the substrate, the first conductive structure includes a plurality of stacked conductive layers, the plurality of stacked conductive layers including a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate, and the resistivity of the first conductive layer being less than the resistivity of the second conductive layer.

[0008] In some alternative embodiments, the material of the first conductive layer includes aluminum.

[0009] In some alternative embodiments, the material of the second conductive layer includes tungsten.

[0010] In some alternative embodiments, the stacked plurality of conductive layers further includes a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer being used to block fluorine atoms from diffusing from the second conductive layer to the first conductive layer.

[0011] In some alternative embodiments, the material of the third conductive layer includes titanium nitride.

[0012] In some alternative embodiments, the stacked plurality of conductive layers further includes a conformally conformal fourth conductive layer covering the first electrode via, the fourth conductive layer being made of at least one of titanium and titanium nitride.

[0013] In some alternative embodiments, the fourth conductive layer forms an alloy structure with the first conductive layer.

[0014] In some alternative embodiments, the first conductive layer conformally covers the fourth conductive layer, and the third conductive layer conformally covers the first conductive layer.

[0015] In some alternative embodiments, the fourth conductive layer located on the bottom wall of the first electrode via is covered by the first conductive layer, a portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the first conductive layer, and another portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the third conductive layer.

[0016] In some alternative embodiments, the surface of the second conductive layer away from the substrate is coplanar with the surface of the passivation layer away from the substrate.

[0017] In some alternative embodiments, the first wiring layer is in contact with the second conductive layer, and the material of the first wiring layer is different from the material of the second conductive layer.

[0018] In some alternative embodiments, the material of the first wiring layer includes at least one of aluminum and copper.

[0019] In some alternative embodiments, the bottom of the first electrode via extends into the channel layer, and the bottom of the first conductive structure contacts the channel layer to form an ohmic contact.

[0020] In some alternative embodiments, the top surface of the first conductive layer is located on the side of the top surface of the barrier layer away from the substrate.

[0021] In some alternative embodiments, the gallium nitride high electron mobility transistor further includes: A second electrode via penetrates the portion of the passivation layer located above the gate electrode to expose the gate electrode; A second conductive structure fills the second electrode via, and the first wiring layer covers the second electrode via and is connected to the second conductive structure.

[0022] In some alternative embodiments, along a direction away from the substrate, the second conductive structure includes a plurality of conductive layers stacked together, wherein the plurality of conductive layers of the first conductive structure and the plurality of conductive layers of the second conductive structure are disposed in the same layer, corresponding one-to-one.

[0023] In some alternative embodiments, in the first direction, the top width of the first electrode via is greater than or equal to the top width of the second electrode via.

[0024] In some alternative embodiments, the bottom of the second electrode via extends into the gate electrode in a direction facing and perpendicular to the substrate.

[0025] In some alternative embodiments, the length of the first wiring layer covering the second electrode via is different from the length of the first wiring layer covering the first electrode via in a second direction that is parallel to the substrate and perpendicular to the first direction.

[0026] This application discloses a gallium nitride high electron mobility transistor, comprising: Substrate; A channel layer and a barrier layer are sequentially disposed along a direction away from the substrate; A gate electrode is disposed on the side of the barrier layer away from the substrate; A passivation layer covers the gate electrode and the barrier layer; Two first electrode vias are disposed on opposite sides of the gate electrode in a first direction. Each first electrode via penetrates the passivation layer, and in a direction facing the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. The first direction is parallel to the substrate. The two first electrode vias are a source electrode via and a drain electrode via, respectively. Two first conductive structures are filled one-to-one with the two first electrode vias. The bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. The bottom of the first conductive structure is in contact with the barrier layer to form an ohmic contact. The cross-sectional area of ​​the first conductive structure gradually increases in a direction away from the substrate and perpendicular to the substrate. A first wiring layer is disposed on the surface of the passivation layer away from the substrate and covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via.

[0027] In some alternative embodiments, along a direction away from the substrate, the first conductive structure includes a plurality of stacked conductive layers, the plurality of stacked conductive layers including a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate, and the resistivity of the first conductive layer being less than the resistivity of the second conductive layer.

[0028] In some alternative embodiments, the material of the first conductive layer includes aluminum.

[0029] In some alternative embodiments, the material of the second conductive layer includes tungsten.

[0030] In some alternative embodiments, the stacked plurality of conductive layers further includes a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer being used to block fluorine atoms from diffusing from the second conductive layer to the first conductive layer.

[0031] In some alternative embodiments, the material of the third conductive layer includes titanium nitride.

[0032] In some optional embodiments, the stacked plurality of conductive layers includes a fourth conductive layer, a portion of which is in direct contact with the bottom of the first electrode via, and another portion of which extends from the bottom of the first electrode via to the opening of the first electrode via and surrounds the remaining conductive layers; wherein the outer surface of the fourth conductive layer surrounding the remaining conductive layers forms the outer surface of the first conductive structure.

[0033] In some alternative embodiments, the fourth conductive layer forms an alloy structure with the first conductive layer.

[0034] In some alternative embodiments, the first conductive layer conformally covers the fourth conductive layer, and the third conductive layer conformally covers the first conductive layer.

[0035] In some alternative embodiments, the fourth conductive layer located on the bottom wall of the first electrode via is covered by the first conductive layer, a portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the first conductive layer, and another portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the third conductive layer.

[0036] In some alternative embodiments, the cross-sectional area of ​​the first electrode via gradually increases in a direction away from and perpendicular to the substrate, and the fourth conductive layer conformally covers the first electrode via.

[0037] In some alternative embodiments, the surface of the second conductive layer away from the substrate is coplanar with the surface of the passivation layer away from the substrate.

[0038] In some alternative embodiments, the first wiring layer is in contact with the second conductive layer, and the material of the first wiring layer is different from the material of the second conductive layer.

[0039] In some alternative embodiments, the material of the first wiring layer includes at least one of aluminum and copper.

[0040] In some alternative embodiments, the bottom of the first conductive structure extends into the channel layer in a direction toward and perpendicular to the substrate, and the bottom of the first conductive structure contacts the channel layer to form an ohmic contact.

[0041] In some alternative embodiments, the top surface of the first conductive layer is located on the side of the top surface of the barrier layer away from the substrate.

[0042] In some alternative embodiments, the gallium nitride high electron mobility transistor further includes: A second electrode via penetrates the portion of the passivation layer located above the gate electrode to expose the gate electrode; A second conductive structure fills the second electrode via, and the first wiring layer covers the second electrode via and is connected to the second conductive structure; in a direction facing the substrate and perpendicular to the substrate, the bottom of the second conductive structure extends into the gate electrode.

[0043] In some alternative embodiments, along a direction away from the substrate, the second conductive structure includes a plurality of conductive layers stacked together, wherein the plurality of conductive layers of the first conductive structure and the plurality of conductive layers of the second conductive structure are disposed in the same layer, corresponding one-to-one.

[0044] In some alternative embodiments, in the first direction, the top width of the first electrode via is greater than or equal to the top width of the second electrode via.

[0045] In some alternative embodiments, the length of the first wiring layer covering the second electrode via is different from the length of the first wiring layer covering the first electrode via in a second direction that is parallel to the substrate and perpendicular to the first direction.

[0046] This application discloses a gallium nitride high electron mobility transistor, comprising: Substrate; A channel layer and a barrier layer are sequentially disposed along a direction away from the substrate; A gate electrode is disposed on the side of the barrier layer away from the substrate; A passivation layer covers the gate electrode and the barrier layer; Two first electrode vias are disposed on opposite sides of the gate electrode in a first direction. Each first electrode via penetrates the passivation layer, and in a direction facing the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. The first direction is parallel to the substrate. The two first electrode vias are a source electrode via and a drain electrode via, respectively. Two first conductive structures are filled one-to-one with the two first electrode vias. The bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. The bottom of the first conductive structure is in contact with the barrier layer to form an ohmic contact. A first wiring layer is disposed on the surface of the passivation layer away from the substrate and covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via. The first conductive structure was prepared using the same deposition process.

[0047] In some alternative embodiments, along a direction away from the substrate, the first conductive structure includes a plurality of stacked conductive layers, the plurality of stacked conductive layers including a fourth conductive layer, a portion of the fourth conductive layer being in direct contact with the bottom of the first electrode via, and another portion of the fourth conductive layer extending from the bottom of the first electrode via to the opening of the first electrode via and in direct contact with the first wiring layer.

[0048] In some alternative embodiments, along a direction away from the substrate, the stacked plurality of conductive layers further include a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate, the resistivity of the first conductive layer being less than the resistivity of the second conductive layer, and the fourth conductive layer surrounding the first conductive layer and the second conductive layer.

[0049] In some alternative embodiments, the material of the first conductive layer includes aluminum.

[0050] In some alternative embodiments, the material of the second conductive layer includes tungsten.

[0051] In some alternative embodiments, the first wiring layer is in contact with the second conductive layer, and the material of the first wiring layer is different from the material of the second conductive layer.

[0052] In some alternative embodiments, the material of the first wiring layer includes at least one of aluminum and copper.

[0053] In some alternative embodiments, the material of the first wiring layer is the same as the material of the first conductive layer.

[0054] In some alternative embodiments, the fourth conductive layer forms an alloy structure with the first conductive layer.

[0055] In some alternative embodiments, the stacked plurality of conductive layers further includes a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer being used to block fluorine atoms from diffusing from the second conductive layer to the first conductive layer.

[0056] In some alternative embodiments, the material of the third conductive layer includes titanium nitride.

[0057] In some alternative embodiments, the first conductive layer conformally covers the fourth conductive layer, and the third conductive layer conformally covers the first conductive layer.

[0058] In some alternative embodiments, the fourth conductive layer located on the bottom wall of the first electrode via is covered by the first conductive layer, a portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the first conductive layer, and another portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the third conductive layer.

[0059] In some alternative embodiments, the surface of the second conductive layer away from the substrate is coplanar with the surface of the passivation layer away from the substrate.

[0060] In some alternative embodiments, the top surface of the first conductive layer is located on the side of the top surface of the barrier layer away from the substrate.

[0061] In some alternative embodiments, the gallium nitride high electron mobility transistor further includes: A second electrode via penetrates the portion of the passivation layer located above the gate electrode to expose the gate electrode; The second conductive structure fills the second electrode via, and the first wiring layer covers the second electrode via and is connected to the second conductive structure. Along the direction away from the substrate, the second conductive structure includes a plurality of conductive layers stacked together, and the plurality of conductive layers of the first conductive structure and the plurality of conductive layers of the second conductive structure are disposed in the same layer, corresponding one-to-one.

[0062] In some alternative embodiments, the bottom of the second conductive structure extends into the gate electrode in a direction facing and perpendicular to the substrate.

[0063] In some alternative embodiments, the length of the first wiring layer covering the second electrode via is different from the length of the first wiring layer covering the first electrode via in a second direction that is parallel to the substrate and perpendicular to the first direction.

[0064] In some alternative embodiments, in a direction away from and perpendicular to the substrate, at least a portion of the cross-sectional area of ​​the first electrode via monotonically increases, monotonically decreases, or remains unchanged.

[0065] In some alternative embodiments, the bottom of the first electrode via extends into the channel layer, and the bottom of the first conductive structure contacts the channel layer to form an ohmic contact.

[0066] This application discloses a gallium nitride high electron mobility transistor, comprising: Substrate; A channel layer and a barrier layer are sequentially disposed along a direction away from the substrate; A gate electrode is disposed on the side of the barrier layer away from the substrate; A passivation layer covers the gate electrode and the barrier layer; Two first electrode vias are disposed on opposite sides of the gate electrode in a first direction. Each first electrode via penetrates the passivation layer, and in a direction toward the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer; the first direction is parallel to the substrate. Two first conductive structures are filled in one-to-one with the two first electrode vias, and the bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. A first wiring layer is disposed on the surface of the passivation layer away from the substrate and covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via. The first electrode via was fabricated using the same mask.

[0067] In some alternative embodiments, the sidewall of the first electrode via is continuously provided from the bottom of the first electrode via to the opening position of the first electrode via.

[0068] In some alternative embodiments, in the first direction, the first electrode via includes two opposing sidewalls; in a direction away from the substrate and perpendicular to the substrate, the distance between the two sidewalls of at least a portion of the first electrode via monotonically increases, monotonically decreases, or remains constant.

[0069] In some alternative embodiments, the two opposing sidewalls are both inclined, and the distance between the two sidewalls gradually increases in a direction away from and perpendicular to the substrate.

[0070] In some alternative embodiments, along a direction away from the substrate, the first conductive structure includes a plurality of stacked conductive layers, the plurality of stacked conductive layers including a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate, and the resistivity of the first conductive layer being less than the resistivity of the second conductive layer.

[0071] In some alternative embodiments, the material of the first conductive layer includes aluminum.

[0072] In some alternative embodiments, the material of the second conductive layer includes tungsten.

[0073] In some alternative embodiments, the stacked plurality of conductive layers further includes a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer being used to block fluorine atoms from diffusing from the second conductive layer to the first conductive layer.

[0074] In some alternative embodiments, the material of the third conductive layer includes titanium nitride.

[0075] In some alternative embodiments, the stacked conductive layers include a fourth conductive layer, a portion of which is in direct contact with the bottom of the first electrode via, and another portion of which extends from the bottom of the first electrode via to the opening of the first electrode via and surrounds the remaining conductive layers.

[0076] In some alternative embodiments, the fourth conductive layer forms an alloy structure with the first conductive layer.

[0077] In some alternative embodiments, the first conductive layer conformally covers the fourth conductive layer, and the third conductive layer conformally covers the first conductive layer.

[0078] In some alternative embodiments, the fourth conductive layer located on the bottom wall of the first electrode via is covered by the first conductive layer, a portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the first conductive layer, and another portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the third conductive layer.

[0079] In some alternative embodiments, the surface of the second conductive layer away from the substrate is coplanar with the surface of the passivation layer away from the substrate.

[0080] In some alternative embodiments, the first wiring layer is in contact with the second conductive layer, and the material of the first wiring layer is different from the material of the second conductive layer.

[0081] In some alternative embodiments, the material of the first wiring layer includes at least one of aluminum and copper.

[0082] In some alternative embodiments, the gallium nitride high electron mobility transistor further includes: A second electrode via penetrates the portion of the passivation layer located above the gate electrode to expose the gate electrode; A second conductive structure fills the second electrode via, and the first wiring layer covers the second electrode via and is connected to the second conductive structure; in a direction facing the substrate and perpendicular to the substrate, the bottom of the second conductive structure extends into the gate electrode.

[0083] In some alternative embodiments, along a direction away from the substrate, the second conductive structure includes a plurality of conductive layers stacked together, wherein the plurality of conductive layers of the first conductive structure and the plurality of conductive layers of the second conductive structure are disposed in the same layer, corresponding one-to-one.

[0084] In some alternative embodiments, the length of the first wiring layer covering the second electrode via is different from the length of the first wiring layer covering the first electrode via in a second direction that is parallel to the substrate and perpendicular to the first direction.

[0085] In some alternative embodiments, the bottom of the first electrode via extends into the channel layer, and the bottom of the first conductive structure contacts the channel layer to form an ohmic contact.

[0086] This application discloses a gallium nitride high electron mobility transistor, comprising: Substrate; A channel layer and a barrier layer are sequentially disposed along a direction away from the substrate; A gate electrode is disposed on the side of the barrier layer away from the substrate; A passivation layer covers the gate electrode and the barrier layer; Two first electrode vias are disposed on opposite sides of the gate electrode in a first direction. Each first electrode via penetrates the passivation layer, and in a direction facing the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. The first direction is parallel to the substrate. The two first electrode vias are a source electrode via and a drain electrode via, respectively. Two first conductive structures are filled one-to-one with the two first electrode vias. The bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. The bottom of the first conductive structure is in contact with the barrier layer to form an ohmic contact. A first wiring layer is disposed on the surface of the passivation layer away from the substrate and covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via. A second electrode via penetrates the portion of the passivation layer located above the gate electrode to expose the gate electrode; A second conductive structure is formed, which fills the second electrode via, and the first wiring layer covers the second electrode via and is connected to the second conductive structure. The first conductive structure and the second conductive structure are made of the same material.

[0087] In some alternative embodiments, both the first conductive structure and the second conductive structure include a plurality of conductive layers stacked together along a direction away from the substrate, wherein the plurality of conductive layers of the first conductive structure and the plurality of conductive layers of the second conductive structure are disposed in the same layer, corresponding one-to-one.

[0088] In some alternative embodiments, the stacked plurality of conductive layers includes a first conductive layer and a second conductive layer, wherein the second conductive layer is located on the side of the first conductive layer away from the substrate, and the resistivity of the first conductive layer is less than the resistivity of the second conductive layer.

[0089] In some alternative embodiments, the material of the first conductive layer includes aluminum.

[0090] In some alternative embodiments, the material of the second conductive layer includes tungsten.

[0091] In some alternative embodiments, the stacked plurality of conductive layers further includes a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer being used to block fluorine atoms from diffusing from the second conductive layer to the first conductive layer.

[0092] In some alternative embodiments, the material of the third conductive layer includes titanium nitride.

[0093] In some alternative embodiments, the stacked plurality of conductive layers further includes a fourth conductive layer, a portion of which is disposed on the side of the first conductive layer facing the substrate, and another portion of which surrounds the remaining conductive layers.

[0094] In some alternative embodiments, the fourth conductive layer forms an alloy structure with the first conductive layer.

[0095] In some alternative embodiments, the first conductive layer conformally covers the fourth conductive layer, and the third conductive layer conformally covers the first conductive layer.

[0096] In some alternative embodiments, the fourth conductive layer located on the bottom wall of the first electrode via is covered by the first conductive layer, a portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the first conductive layer, and another portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the third conductive layer.

[0097] In some alternative embodiments, the first wiring layer is in direct contact with the second conductive layer, and the material of the first wiring layer is different from the material of the second conductive layer.

[0098] In some alternative embodiments, the material of the first wiring layer includes at least one of aluminum and copper.

[0099] In some alternative embodiments, the bottom of the second electrode via extends into the gate electrode in a direction facing and perpendicular to the substrate.

[0100] In some alternative embodiments, in the first direction, the top width of the first electrode via is greater than or equal to the top width of the second electrode via.

[0101] In some alternative embodiments, the length of the first wiring layer covering the second electrode via is different from the length of the first wiring layer covering the first electrode via in a second direction that is parallel to the substrate and perpendicular to the first direction.

[0102] In some alternative embodiments, the cross-sectional area of ​​the first electrode via gradually increases in a direction away from and perpendicular to the substrate, and the cross-sectional area of ​​the second electrode via gradually increases.

[0103] In some alternative embodiments, the surface of the second conductive layer away from the substrate is coplanar with the surface of the passivation layer away from the substrate.

[0104] In some alternative embodiments, the bottom of the first electrode via extends into the channel layer, and the bottom of the first conductive structure contacts the channel layer to form an ohmic contact.

[0105] In some alternative embodiments, the cross-sectional area of ​​the second conductive structure gradually increases in a direction away from and perpendicular to the substrate.

[0106] This application discloses a method for fabricating a gallium nitride high electron mobility transistor, comprising: Provide substrate; A channel layer and a barrier layer are formed sequentially along a direction away from the substrate; A gate electrode and a passivation layer covering the gate electrode are formed on the side of the barrier layer away from the substrate; Two first electrode vias are formed, and the two first electrode vias are disposed on opposite sides of the gate electrode in a first direction. Each first electrode via penetrates the passivation layer, and in a direction toward the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer; the first direction is parallel to the substrate; in a direction away from the substrate and perpendicular to the substrate, the cross-sectional area of ​​the first electrode via gradually increases. A first conductive structure is formed in each of the first electrode vias, and the bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. A first wiring layer is formed on the surface of the passivation layer away from the substrate. The first wiring layer covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via.

[0107] In some alternative embodiments, the first electrode via is formed using the same mask.

[0108] In some alternative embodiments, the step of forming two first electrode vias includes: Two first electrode vias and one second electrode via are formed simultaneously. The second electrode via penetrates the portion of the passivation layer located above the gate electrode to expose the gate electrode. The first wiring layer covers the second electrode via.

[0109] In some alternative embodiments, in the first direction, the top width of the first electrode via is greater than or equal to the top width of the second electrode via.

[0110] In some alternative embodiments, the length of the first wiring layer covering the second electrode via is different from the length of the first wiring layer covering the first electrode via in a second direction that is parallel to the substrate and perpendicular to the first direction.

[0111] In some alternative embodiments, the step of forming a first conductive structure within each of the first electrode vias includes: Multiple conductive material layers are formed on the passivation layer, and the multiple conductive material layers fill the first electrode via and the second electrode via. The portions of the plurality of conductive material layers located outside the first electrode via and the second electrode via are removed to form a first conductive structure within the first electrode via and a second conductive structure within the second electrode via.

[0112] In some alternative embodiments, the resistivity of the top conductive material layer among the plurality of conductive material layers is less than the resistivity of the first wiring layer.

[0113] In some alternative embodiments, the material of the first wiring layer includes at least one of aluminum and copper.

[0114] In some alternative embodiments, along a direction away from the substrate, the stacked plurality of conductive material layers include a fourth conductive material layer, a first conductive material layer, a third conductive material layer, and a second conductive material layer disposed sequentially, wherein the resistivity of the first conductive material layer is less than the resistivity of the second conductive material layer.

[0115] In some alternative embodiments, the material of the first conductive material layer includes aluminum.

[0116] In some alternative embodiments, the material of the second conductive material layer includes tungsten.

[0117] In some alternative embodiments, the third conductive material layer is used to block fluorine atoms from diffusing from the second conductive material layer to the first conductive material layer.

[0118] In some alternative embodiments, the material of the third conductive material layer includes titanium nitride.

[0119] In some alternative embodiments, the fourth conductive material layer forms an alloy structure with the first conductive material layer.

[0120] In some alternative embodiments, the fourth conductive material layer conformally covers both the first electrode via and the second electrode via.

[0121] In some alternative embodiments, the top surface of the first conductive material layer is located on the side of the top surface of the barrier layer away from the substrate.

[0122] In some alternative embodiments, the bottom of the second electrode via extends into the gate electrode in a direction facing and perpendicular to the substrate.

[0123] In some alternative embodiments, the bottom of the first electrode via extends into the channel layer, and the bottom of the first conductive structure contacts the channel layer to form an ohmic contact.

[0124] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0125] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0126] Figure 1 This is a schematic diagram showing the formation of a barrier layer in the fabrication method of the gallium nitride high electron mobility transistor of this application.

[0127] Figure 2 This is a schematic diagram showing the passivation layer after it has been formed in the method for fabricating the gallium nitride high electron mobility transistor of this application.

[0128] Figure 3A and Figure 3B This is a schematic diagram showing the formation of the first electrode via and the second electrode via in the fabrication method of the gallium nitride high electron mobility transistor of this application.

[0129] Figure 4 This is a schematic diagram showing the formation of the fourth conductive material layer in the method for fabricating the gallium nitride high electron mobility transistor of this application.

[0130] Figure 5A and Figure 5B This is a schematic diagram showing the formation of the first conductive material layer in the method for fabricating the gallium nitride high electron mobility transistor of this application.

[0131] Figure 6A and Figure 6B This is a schematic diagram showing the formation of the third conductive material layer in the method for fabricating the gallium nitride high electron mobility transistor of this application.

[0132] Figure 7A and Figure 7B This is a schematic diagram showing the formation of the second conductive material layer in the method for fabricating the gallium nitride high electron mobility transistor of this application.

[0133] Figure 8A and Figure 8B This is a schematic diagram showing the formation of the first conductive structure and the second conductive structure in the fabrication method of the gallium nitride high electron mobility transistor of this application.

[0134] Figure 9 and Figure 10 This is a schematic diagram of the gallium nitride high electron mobility transistor fabrication method of this application after the formation of the first wiring layer.

[0135] Figure 11 This is a top view of the gallium nitride high electron mobility transistor of this application.

[0136] Figure 12 This is a schematic diagram showing the connection between the gallium nitride high electron mobility transistor and the functional device of this application.

[0137] Reference numerals: 1. First conductive structure; 101. First conductive layer; 101A. First conductive material layer; 102. Second conductive layer; 102A. Second conductive material layer; 103. Third conductive layer; 103A. Third conductive material layer; 104. Fourth conductive layer; 104A. Fourth conductive material layer; 2. Second conductive structure; 3. First wiring layer; 301. First conductive block; 4. Passivation layer; 401. First passivation sublayer; 402. Second passivation sublayer; 5. Substrate; 6. Channel layer; 7. Barrier layer; 8. Gate electrode; 9. Insulating layer; 10. Second wiring layer; 11. First electrode via; 1101. Sidewall; 12. Second electrode via; 13. Functional device; X. First direction. Detailed Implementation

[0138] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0139] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0140] In related technologies, such as referring to Chinese patent application document CN113287200A, when fabricating a high electron mobility transistor (HEMT), it is first necessary to use a mask to form the ohmic contact electrode of the HEMT (in the patent application with publication number CN113287200A). Figure 1 (The source 112A and drain 112C of C) In order for the formed HEMT to be connected to other external circuits, an insulating layer covering the source and drain also needs to be formed (in patent application publication number CN113287200A). Figure 1 The passivation layer 130 of C needs to be etched to form a via that exposes the source and drain (in patent application CN113287200A). Figure 1 Contact via 132 of C), then fill the via with conductive material and form at least one wiring layer on the insulating layer (in patent application CN113287200A). Figure 1 The patterned conductive layer 134 of C is then used, and source and drain pads are designed on top of the wiring layer to connect the source and drain to other external circuits through conductive elements, wiring layers, and pads. This fabrication process is complex, and different masks are used to fabricate the ohmic contact electrodes and conductive elements in the vias, resulting in high device manufacturing costs.

[0141] To address the aforementioned problems, this application provides a method for fabricating a gallium nitride high electron mobility transistor. This method may include: Step S10, as follows Figure 1 As shown, substrate 5 is provided; Step S20: Form a channel layer 6 and a barrier layer 7 sequentially arranged along a direction away from the substrate 5; Step S30, as Figure 2 As shown, a gate electrode 8 and a passivation layer 4 covering the gate electrode 8 are formed on the side of the barrier layer 7 away from the substrate 5. Step S40, as Figure 3A and Figure 3B As shown, two first electrode vias 11 are formed. The two first electrode vias 11 are disposed on opposite sides of the gate electrode 8 in the first direction X. Each first electrode via 11 penetrates the passivation layer 4, and in the direction facing the substrate 5 and perpendicular to the substrate 5, the bottom of the first electrode via 11 extends at least into the barrier layer 7. The first direction X is parallel to the substrate 5, and the two first electrode vias 11 are the source electrode via and the drain electrode via, respectively. Step S50, as follows Figure 8A and Figure 8B As shown, a first conductive structure 1 is formed in each first electrode via 11; the bottom of the first conductive structure 1 is in direct contact with the bottom of the first electrode via 11. Step S60, as follows Figure 9 As shown, a first wiring layer 3 is formed on the surface of the passivation layer 4 away from the substrate 5. The first wiring layer 3 covers each first electrode via 11. The first wiring layer 3 is in direct contact with the top of the first conductive structure 1 and the top of the first electrode via 11.

[0142] The first wiring layer 3 mentioned above is also the metallized interconnect layer. The metallized interconnect layer connects all the sources or drains of multiple unit transistors together through the wiring arrangement, and spreads the current more evenly from the pads (such as source pads or drain pads) to the entire device working area.

[0143] This application also provides a gallium nitride high electron mobility transistor. This gallium nitride high electron mobility transistor can be fabricated using the methods described above. For example... Figure 3A and Figure 9 As shown, the gallium nitride high electron mobility transistor may include: a substrate 5; a channel layer 6 and a barrier layer 7 sequentially disposed along a direction away from the substrate 5; a gate electrode 8 disposed on the side of the barrier layer 7 away from the substrate 5; a passivation layer 4 covering the gate electrode 8 and the barrier layer 7; and two first electrode vias 11 (see...). Figure 3A The first electrode vias 11 are disposed on opposite sides of the gate electrode 8 in the first direction X, and each first electrode via 11 penetrates the passivation layer 4. In the direction facing the substrate 5 and perpendicular to the substrate 5, the bottom of the first electrode via 11 extends at least into the barrier layer 7. The two first electrode vias 11 are the source electrode via and the drain electrode via, respectively. The first direction X is parallel to the substrate 5. Two first conductive structures 1 are filled with the two first electrode vias 11 one by one. The bottom of the first conductive structure 1 is in direct contact with the bottom of the first electrode via 11. The bottom of the first conductive structure 1 is in contact with the barrier layer 7 to form an ohmic contact. A first wiring layer 3 is disposed on the surface of the passivation layer 4 away from the substrate 5 and covers each first electrode via 11. It is connected to the first conductive structure 1. The first wiring layer 3 is in direct contact with the top of the first conductive structure 1 and the top of the first electrode via 11.

[0144] Compared with related technologies, such as Figure 3A and Figure 9As shown, the first electrode via 11 extends directly from the top of the passivation layer 4 into the barrier layer 7, so that the top of the first conductive structure 1 formed in the two first electrode vias 11 directly contacts the first wiring layer 3, and the bottom of the first conductive structure 1 extends into the barrier layer 7. Thus, the two first conductive structures 1 act as the source and drain, respectively, eliminating the need for additional masks to fabricate the source and drain. In other words, in related technologies, the conductive components in the vias and the ohmic contact electrodes (source and drain) are fabricated using different masks. However, this application eliminates the process of separately fabricating the ohmic contact electrodes in related technologies. The bottom of the first conductive structure 1 extends directly into the barrier layer 7, making it easier for the bottom of the first conductive structure 1 to form a large-area ohmic contact with the barrier layer 7. This simplifies the process and reduces costs.

[0145] The following is a detailed description of each part of the embodiments of this application: like Figure 1 As shown, the substrate 5 can be a Si substrate or a SiC substrate. Si substrates or SiC have high thermal conductivity and matching lattice constants, which can improve the heat dissipation performance of the device and the quality of the heterojunction. In other embodiments, the substrate 5 can also be made of other materials.

[0146] like Figure 1 As shown, this application can grow a GaN layer on substrate 5 using a deposition process to form a channel layer 6. It should be noted that before forming the channel layer 6, this application can first form a GaN buffer layer, and then form the channel layer 6 on the GaN buffer layer. The function of the channel layer 6 is to provide a high-mobility two-dimensional electron gas (2DEG) channel. This application can grow an AlGaN layer on the channel layer 6 to form a barrier layer 7. The barrier layer 7 and the channel layer 6 form a heterojunction, inducing 2DEG through a polarization effect.

[0147] The barrier layer 7 and the channel layer 6 can also be selected from other different nitrogen-based semiconductor materials. Exemplary materials for the channel layer 6 may include, but are not limited to, nitrides or III-V compounds, such as gallium nitride, aluminum nitride, and indium nitride. Exemplary materials for the barrier layer 7 may include, but are not limited to, nitrides or III-V compounds, such as gallium nitride, aluminum nitride, indium nitride, and aluminum gallium nitride. Exemplary materials for the channel layer 6 and the barrier layer 7 can be selected such that the barrier layer 7 has a larger band gap (i.e., bandgap width) than the channel layer 6, resulting in different electron affinities and forming a heterojunction between them. For example, when the channel layer 6 is an undoped gallium nitride layer (with a band gap of approximately 3.4 eV), the barrier layer 7 can be selected as an aluminum gallium nitride layer (with a band gap of approximately 4.0 eV). A triangular potential well is generated at the interface between the channel layer 6 and the barrier layer 7, allowing electrons to accumulate in the triangular potential well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.

[0148] like Figure 2 As shown, the gate electrode 8 can be formed by a deposition process in this application. The gate electrode 8 can be strip-shaped, and its extension direction can be parallel to the substrate 5. Along the direction away from the substrate 5, the passivation layer 4 can include a first passivation sublayer 401 and a second passivation sublayer 402. The first passivation sublayer 401 and the second passivation sublayer 402 can be formed by depositing oxides (e.g., silicon oxide) or nitrides (e.g., silicon nitride) by a deposition process. The materials of the first passivation sublayer 401 and the second passivation sublayer 402 can be the same, or of course, different. The first passivation sublayer 401 can conformally cover the gate electrode 8. The thickness of the second passivation sublayer 402 can be greater than the thickness of the first passivation sublayer 401. The second passivation sublayer 402 can also be referred to as an interlayer dielectric (ILD).

[0149] like Figure 3A As shown, the first direction X is parallel to the substrate 5 and perpendicular to the extension direction of the gate electrode 8. Two first electrode vias 11 are disposed on opposite sides of the gate electrode 8 along the first direction X. The opening of each first electrode via 11 is located on the surface of the passivation layer 4 away from the substrate 5. In a direction facing and perpendicular to the substrate 5, the bottom of the first electrode via 11 extends at least into the barrier layer 7. Furthermore, the bottom of the first electrode via 11 may extend to the interface between the barrier layer 7 and the channel layer 6. The bottom of the first electrode via 11 may also extend into the channel layer 6 (see...). Figure 3BWhen the bottom of the first conductive structure 1 extends directly into the channel layer 6, the bottom of the first conductive structure 1 forms a large-area ohmic contact with the channel layer 6 and the barrier layer 7, which facilitates the transmission of 2DEG. This can effectively reduce the difficulty of depositing the first conductive structure 1 in the first electrode via 11. In other words, when the bottom of the first electrode via 11 extends directly into the channel layer 6, even if the hole depth of the first electrode via 11 is large and the bottom hole diameter is small, making it difficult to fill, or if the material properties of the first conductive structure 1 are poor and it is difficult to deposit to the bottom of the first electrode via 11, resulting in poor deposition quality of the bottom of the first conductive structure 1, the bottom of the first conductive structure 1 can still form a good ohmic contact with the channel layer 6 and the barrier layer 7. Figure 11 This is a top view of a gallium nitride high electron mobility transistor. Figure 9 and Figure 10 for Figure 11 A cross-sectional view along the AA direction. (See diagram.) Figure 11 As shown, the orthogonal projection of the first electrode via 11 on the substrate 5 can be strip-shaped, and its extension direction is perpendicular to the first direction X.

[0150] This application can use dry etching to form two first electrode vias 11. The aforementioned first electrode vias 11 are fabricated using the same mask; that is, this application uses one mask during the dry etching process to form the first electrode vias 11. In related technologies, the formation processes of connecting holes and ohmic contact electrodes use two masks. Because the first electrode vias 11 are fabricated using the same mask, the sidewalls 1101 of the first electrode vias 11 are continuously formed from the bottom of the first electrode via 11 to the opening position (top) of the first electrode via 11; that is, the sidewalls 1101 of the first electrode via 11 are continuously fabricated using a single etching process.

[0151] In one implementation, such as Figure 3A As shown, in a direction away from and perpendicular to the substrate 5, the cross-sectional area of ​​the first electrode via 11 parallel to the substrate 5 gradually increases. For example, in the first direction X, the first electrode via 11 includes two opposing sidewalls 1101, each sidewall 1101 being inclined, and the distance between the two sidewalls 1101 gradually increases along the direction away from the substrate 5, which is more conducive to forming a first conductive structure 1 with good filling quality. In another embodiment, in a direction away from and perpendicular to the substrate 5, the cross-sectional area of ​​at least a portion of the first electrode via 11 monotonically increases, monotonically decreases, or remains unchanged, that is, the distance between the two sidewalls 1101 of at least a portion of the first electrode via 11 monotonically increases, monotonically decreases, or remains unchanged. One of the two first electrode vias 11 is used to define the source region, and the other is used to define the drain region.

[0152] In addition, such as Figure 3AAs shown, during the formation of the two first electrode vias 11, this application can also simultaneously form a second electrode via 12, that is, the second electrode via 12 and the first electrode via 11 are formed using the same mask in a synchronous etching process. The orthogonal projection of the second electrode via 12 onto the substrate 5 can be strip-shaped (e.g., ...). Figure 11 As shown), and its extension direction is perpendicular to the first direction X. The depth of the second electrode via 12 is less than the depth of the first electrode via 11. The opening of the second electrode via 12 is located on the surface of the passivation layer 4 away from the substrate 5. The second electrode via 12 penetrates the portion of the passivation layer 4 above the gate electrode 8 to expose the gate electrode 8, and the orthogonal projection of the bottom of the second electrode via 12 onto the substrate 5 is located within the orthogonal projection area of ​​the gate electrode 8 onto the substrate 5. The second electrode via 12 can penetrate the second passivation sublayer 402 and the first passivation sublayer 401, and the bottom of the second electrode via 12 can extend to the top surface of the gate electrode 8. Further, the bottom of the second electrode via 12 extends into the gate electrode 8, that is, a pit is formed on the surface of the gate electrode 8 away from the substrate 5. This is because the second electrode via 12 and the first electrode via 11 are etched simultaneously, but because the depth of the second electrode via 12 is less than the depth of the first electrode via 11, the top surface of the gate electrode 8 at the bottom of the second electrode via 12 is partially etched. Furthermore, in the first direction X, the top width of the second electrode via 12 can be smaller than the top width of the first electrode via 11, that is, the width of the first electrode via 11 is larger. This setting can reduce the aspect ratio of the first electrode via 11, which has a larger depth.

[0153] like Figure 9 and Figure 10As shown, two first conductive structures 1 are filled with two first electrode vias 11 in a one-to-one correspondence. Along the direction away from the substrate 5, the first conductive structure 1 includes multiple conductive layers stacked together, including a first conductive layer 101 and a second conductive layer 102. The second conductive layer 102 is located on the side of the first conductive layer 101 away from the substrate 5. The resistivity of the first conductive layer 101 is less than that of the second conductive layer 102. For example, the material of the first conductive layer 101 may be aluminum, and the material of the second conductive layer 102 may be tungsten. This arrangement reduces ohmic contact resistance and improves the via filling performance of the first conductive structure 1 (tungsten has good filling performance). The surface of the second conductive layer 102 away from the substrate 5 is coplanar with the surface of the passivation layer 4 away from the substrate 5. The stacked conductive layers also include a third conductive layer 103 located between the first conductive layer 101 and the second conductive layer 102. The material of the third conductive layer 103 may include titanium nitride. The stacked conductive layers also include a fourth conductive layer 104. The material of the fourth conductive layer 104 includes at least one of titanium and titanium nitride. A portion of the fourth conductive layer 104 directly contacts the bottom of the first electrode via 11, while another portion extends from the bottom of the first electrode via 11 to the opening of the first electrode via 11 and contacts the first wiring layer 3, surrounding the remaining conductive layers. The outer surface of the fourth conductive layer 104 surrounding the remaining conductive layers forms the outer surface of the first conductive structure 1. This fourth conductive layer 104 can conformally cover the first electrode via 11. In a direction away from the substrate 5 and perpendicular to the substrate 5, the cross-sectional area of ​​the first conductive structure 1 gradually increases. Furthermore, the top surface of the first conductive layer 101 is located on the side of the top surface of the barrier layer 7 away from the substrate 5. This arrangement can better increase the ohmic contact area between the first conductive layer 101 and the channel layer 6 and the barrier layer 7.

[0154] like Figure 9 and Figure 10 As shown, the gallium nitride high electron mobility transistor of this application may further include a second conductive structure 2. This second conductive structure 2 fills the second electrode via 12, and the first wiring layer 3 covers the second electrode via 12 and is connected to the second conductive structure 2. The first conductive structure 1 and the second conductive structure 2 are made of the same material. For example, along the direction away from the substrate 5, both the first conductive structure 1 and the second conductive structure 2 include multiple conductive layers stacked together, with each conductive layer of the first conductive structure 1 corresponding to a different conductive layer of the second conductive structure 2. In the direction away from the substrate 5 and perpendicular to the substrate 5, the cross-sectional area of ​​the second conductive structure 2 gradually increases.

[0155] For example, the formation of the first conductive structure 1 and the second conductive structure 2 may include steps S501-S502: Step S501: A plurality of conductive material layers are formed on the passivation layer 4, and the plurality of conductive material layers fill the first electrode via 11 and the second electrode via 12. like Figure 7A and Figure 7B As shown, along the direction away from the substrate 5, the stacked conductive material layers may include a first conductive material layer 101A and a second conductive material layer 102A. Further, along the direction away from the substrate 5, the stacked conductive material layers may include a fourth conductive material layer 104A, a first conductive material layer 101A, a third conductive material layer 103A, and a second conductive material layer 102A, each conductive material layer being formed by a deposition process. Figure 3A and Figure 4 As shown, the fourth conductive material layer 104A conformally covers the first electrode via 11 and the second electrode via 12. The material of the fourth conductive material layer 104A includes at least one of titanium nitride and titanium. Figure 5A As shown, the first conductive material layer 101A conformally covers the fourth conductive material layer 104A. The material of the first conductive material layer 101A includes aluminum, which can form good ohmic contacts with semiconductor materials such as the barrier layer 7 and the channel layer 6; in another embodiment, the first conductive material layer 101A can also be selected from other metallic materials that can form good ohmic contacts with semiconductor materials such as the barrier layer 7 and the channel layer 6. For example... Figure 6A As shown, the third conductive material layer 103A conformally covers the first conductive material layer 101A. An alloy structure can be formed at the interface between the first conductive material layer 101A and the fourth conductive material layer 104A. The material of the third conductive layer 103A includes titanium nitride. In another embodiment, as... Figure 5B As shown, the first conductive material layer 101A covers the fourth conductive material layer 104A located on the bottom wall of the first electrode via 11 and a portion of the fourth conductive material layer 104A located on the side wall 1101 of the first electrode via 11; as Figure 6B As shown, the third conductive material layer 103A covers the first conductive material layer 101A and a portion of the fourth conductive material layer 104A located on the sidewall 1101 of the first electrode via 11.

[0156] like Figure 7A and Figure 7BAs shown, the third conductive material layer 103A is selected from materials that can block the diffusion of fluorine atoms. The third conductive material layer 103A is used to prevent fluorine atoms from diffusing from the second conductive material layer 102A to the first conductive material layer 101A, thereby degrading the ohmic contact performance of the first conductive material layer 101A. The material of the second conductive material layer 102A includes tungsten. Metallic tungsten can be deposited well in the first electrode via 11, thereby forming a high-quality filling structure in the first electrode via 11. This second conductive material layer 102A can be formed by chemical vapor deposition (CVD). During the CVD deposition process of the second conductive material layer 102A, tungsten-containing halides (e.g., tungsten hexafluoride) are deposited, thereby introducing halogen atoms such as fluorine atoms. The third conductive material layer 103A is placed between the first conductive material layer 101A and the second conductive material layer 102A, and fluorine atoms are essentially unable to diffuse in the third conductive material layer 103A. This arrangement can protect the first conductive material layer 101A. In addition, each of the above conductive material layers extends to form a first electrode via 11 and a second electrode via 12.

[0157] Step S502, as follows Figure 8A and Figure 8B As shown, the portions of multiple conductive material layers located outside the first electrode via 11 and the second electrode via 12 are removed to form a first conductive structure 1 in the first electrode via 11 and a second conductive structure 2 in the second electrode via 12.

[0158] This application utilizes a grinding process to remove portions of multiple conductive material layers outside the first electrode via 11 and the second electrode via 12. The remaining fourth conductive material layer 104A forms the fourth conductive layer 104, the remaining first conductive material layer 101A forms the first conductive layer 101, the remaining third conductive material layer 103A forms the third conductive layer 103, and the remaining second conductive layer 102A forms the second conductive layer 102. The surface of the second conductive layer 102 away from the substrate 5 is coplanar or flush with the surface of the passivation layer 4 away from the substrate 5. The multiple conductive layers stacked within the first electrode via 11 form the first conductive structure 1, and the multiple conductive layers stacked within the second electrode via 12 form the second conductive structure 2. As can be seen from the above, the first conductive structure 1 is prepared using the same deposition process. This means that the multiple conductive layers of the first conductive structure 1 are formed by continuous deposition. However, in related technologies, after depositing the ohmic contact electrode, an insulating layer covering the ohmic contact electrode needs to be formed, and a via is formed on the insulating layer. Then, a conductive element within the via is formed through a deposition process. Therefore, the ohmic contact electrode and the conductive element within the via are not formed by continuous deposition. Furthermore, the resistivity of the first conductive layer 101 is lower than that of the second conductive layer 102, which can achieve a lower ohmic contact resistance between the first conductive layer 101 and semiconductor materials such as the barrier layer 7 and the channel layer 6. For example, the resistivity of the first conductive layer 101, such as aluminum, can be approximately 2.82 × 10⁻⁶. -8 The resistivity of the second conductive layer 102, such as tungsten, can be approximately 5.6 × 10⁻⁶ Ω·m. -8 Approximately Ω•m (ohm-meter).

[0159] like Figure 3A and Figure 9 As shown, the first wiring layer 3 can be formed by a deposition process. The first wiring layer 3 can be in direct contact with the second conductive layer 102, and the material of the first wiring layer 3 is different from that of the second conductive layer 102. Taking the second conductive layer 102 as an example, the material of the first wiring layer 3 can include at least one of aluminum and copper. The resistivity of the first wiring layer 3 is less than that of the second conductive layer 102, that is, the resistivity of the first wiring layer 3 is less than that of the second conductive material layer 102A (the top conductive material layer among multiple conductive material layers). The first wiring layer 3 includes multiple first conductive blocks 301, each first conductive block 301 covering a first electrode via 11 and connected to the top of a first conductive structure 1, that is, the first conductive block 301 is directly formed on the top of the first conductive structure 1. The first wiring layer 3 is in direct contact with the top of the first electrode via 11, that is, the first wiring layer 3 seals the opening of the first electrode via 11.

[0160] In addition, such as Figure 12As shown, the gallium nitride high electron mobility transistor of this application also includes a functional device 13, which is disposed on the same side of the substrate 5 as the gate electrode 8. After forming the first wiring layer 3, the method of this application may further include: forming an insulating layer 9 on the side of the first wiring layer 3 away from the substrate 5, the insulating layer 9 covering the first wiring layer 3; on the side of the insulating layer 9 away from the substrate 5, a second wiring layer 10, at least one first conductive block 301 is connected to the second wiring layer 10 via a via, and the first conductive block 301 is connected to the aforementioned functional device 13 through the second wiring layer 10. The functional device 13 may also be a high electron mobility transistor (HEMT), and the first conductive block 301 may be connected to the source or drain of the functional device 13 through the second wiring layer 10.

[0161] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A gallium nitride high electron mobility transistor, characterized in that, include: Substrate; A channel layer and a barrier layer are sequentially disposed along a direction away from the substrate; A gate electrode is disposed on the side of the barrier layer away from the substrate; A passivation layer covers the gate electrode and the barrier layer; Two first electrode vias are disposed on opposite sides of the gate electrode in a first direction. Each first electrode via penetrates the passivation layer, and in a direction toward the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. The first direction is parallel to the substrate; Two first conductive structures are filled in one-to-one with the two first electrode vias, and the bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. A first wiring layer is disposed on the surface of the passivation layer away from the substrate and covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via. The first electrode via was fabricated using the same mask.

2. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The sidewalls of the first electrode via are continuously arranged from the bottom of the first electrode via to the opening position of the first electrode via.

3. The gallium nitride high electron mobility transistor according to claim 2, characterized in that, In the first direction, the first electrode via includes two opposing sidewalls; in a direction away from the substrate and perpendicular to the substrate, the distance between the two sidewalls of at least a portion of the first electrode via monotonically increases, monotonically decreases, or remains constant.

4. The gallium nitride high electron mobility transistor according to claim 3, characterized in that, The two opposing sidewalls are both inclined, and the distance between the two sidewalls gradually increases in a direction away from the substrate and perpendicular to the substrate.

5. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, Along a direction away from the substrate, the first conductive structure includes a plurality of stacked conductive layers, the plurality of stacked conductive layers including a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate, and the resistivity of the first conductive layer being less than the resistivity of the second conductive layer.

6. The gallium nitride high electron mobility transistor according to claim 5, characterized in that, The material of the first conductive layer includes aluminum.

7. The gallium nitride high electron mobility transistor according to claim 5, characterized in that, The material of the second conductive layer includes tungsten.

8. The gallium nitride high electron mobility transistor according to claim 5, characterized in that, The stacked conductive layers also include a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer being used to block fluorine atoms from diffusing from the second conductive layer to the first conductive layer.

9. The gallium nitride high electron mobility transistor according to claim 8, characterized in that, The material of the third conductive layer includes titanium nitride.

10. The gallium nitride high electron mobility transistor according to claim 8, characterized in that, The stacked conductive layers include a fourth conductive layer. Part of the fourth conductive layer is in direct contact with the bottom of the first electrode via, and another part of the fourth conductive layer extends from the bottom of the first electrode via to the opening of the first electrode via and surrounds the remaining conductive layers.

11. The gallium nitride high electron mobility transistor according to claim 10, characterized in that, The fourth conductive layer forms an alloy structure with the first conductive layer.

12. The gallium nitride high electron mobility transistor according to claim 10, characterized in that, The first conductive layer conformally covers the fourth conductive layer, and the third conductive layer conformally covers the first conductive layer.

13. The gallium nitride high electron mobility transistor according to claim 10, characterized in that, The fourth conductive layer located on the bottom wall of the first electrode via is covered by the first conductive layer, a portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the first conductive layer, and another portion of the fourth conductive layer located on the side wall of the first electrode via is covered by the third conductive layer.

14. The gallium nitride high electron mobility transistor according to claim 5, characterized in that, The surface of the second conductive layer away from the substrate is coplanar with the surface of the passivation layer away from the substrate.

15. The gallium nitride high electron mobility transistor according to claim 5, characterized in that, The first wiring layer is in contact with the second conductive layer, and the material of the first wiring layer is different from the material of the second conductive layer.

16. The gallium nitride high electron mobility transistor according to claim 15, characterized in that, The material of the first wiring layer includes at least one of aluminum and copper.

17. The gallium nitride high electron mobility transistor according to claim 10, characterized in that, The gallium nitride high electron mobility transistor also includes: A second electrode via penetrates the portion of the passivation layer located above the gate electrode to expose the gate electrode; A second conductive structure fills the second electrode via, and the first wiring layer covers the second electrode via and is connected to the second conductive structure; in a direction facing the substrate and perpendicular to the substrate, the bottom of the second conductive structure extends into the gate electrode.

18. The gallium nitride high electron mobility transistor according to claim 17, characterized in that, Along a direction away from the substrate, the second conductive structure includes a plurality of conductive layers stacked together, wherein the plurality of conductive layers of the first conductive structure and the plurality of conductive layers of the second conductive structure are disposed in the same layer, each corresponding to one of the plurality of conductive layers of the second conductive structure.

19. The gallium nitride high electron mobility transistor according to claim 17, characterized in that, In a second direction that is parallel to the substrate and perpendicular to the first direction, the length of the first wiring layer covering the second electrode via is different from the length of the first wiring layer covering the first electrode via.

20. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The bottom of the first electrode via extends into the channel layer, and the bottom of the first conductive structure contacts the channel layer to form an ohmic contact.

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