A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof, a shielding layer is formed in a current diffusion layer, then a well region and a contact region are formed between the shielding layers, after that, a gate trench is formed and a buffer layer is formed at the bottom of the gate trench, finally, a gate oxide layer and a gate polysilicon layer are formed, the buffer layer, the gate oxide layer and the current diffusion layer in the device form a similar drain voltage controlled JFET, the regulation of the shielding effect of the buffer layer is completed, the self-regulation of the Miller capacitance is realized, the lower switching loss and switching oscillation are realized, the electronic current path of the semiconductor device is narrow, the saturated peak current in the short circuit of the device is effectively limited, and the short circuit resistance of the device is significantly enhanced; the buffer layer and the shielding layer introduce a larger PN junction area, and the avalanche capability can be optimized.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the rapid development of power electronic systems towards higher efficiency, lighter weight, and higher frequency, power semiconductor devices, as core components, directly determine the overall performance of the system. Among numerous power semiconductor devices, compared to traditional silicon (Si)-based insulated-gate bipolar transistors (IGBTs), silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOS) have significant application advantages in high-voltage frequency conversion, new energy vehicles, and rail transportation due to their wide bandgap characteristics, high critical electric field, high thermal conductivity, and high saturation drift rate. Compared to Si IGBTs with the same voltage rating and specific on-resistance, the area of ​​a silicon carbide MOS chip can theoretically be reduced by 65 times. This characteristic allows for lower Miller capacitance, significantly improving the switching speed and operating frequency of the device.

[0003] Trench-gate silicon carbide MOS devices can achieve higher channel density and further reduce the specific on-resistance of the device, which has become an important development direction for future silicon carbide MOS devices. However, under high-frequency operating conditions, silicon carbide MOS devices will generate severe switching oscillations due to high switching speed and stray inductance in power electronic systems, which will eventually lead to problems such as current and voltage overshoot, additional power loss, and false turn-on, and may even directly damage the device.

[0004] To solve the aforementioned switching oscillation problem, in response to... Figure 1 The existing silicon carbide MOS devices shown typically increase the gate resistance or adjust the doping concentration of the current spreading layer to increase the Miller capacitance, thereby reducing the switching speed. Although this method can suppress oscillation to some extent, it inevitably increases the switching loss significantly, limiting the application advantages of trench gate silicon carbide MOS devices in the high-frequency field.

[0005] Therefore, how to provide a trench-type silicon carbide MOS device and its fabrication method so that the formed MOS device can simultaneously achieve the requirements of low switching oscillation, low switching loss and high robustness has become an important problem that needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device and its fabrication method to solve the problem that low switching oscillation, low switching loss and high robustness of semiconductor devices in the prior art cannot be optimized in a coordinated manner.

[0008] To achieve the above and other related objectives, the present invention provides a semiconductor device comprising:

[0009] A substrate having a first surface and a second surface disposed opposite to each other;

[0010] An epitaxial layer is disposed on the first surface of the substrate;

[0011] Multiple shielding areas, including at least a first shielding area, a second shielding area, and a third shielding area, are spaced apart in the epitaxial layer, and an epitaxial platform area is formed between adjacent first shielding areas, second shielding areas, and third shielding areas.

[0012] Gate trenches are disposed in the epitaxial platform regions on both sides of the second shielding region;

[0013] A buffer layer is disposed at the bottom of the gate trench, and the width of the buffer layer is the same as the width of the gate trench; and

[0014] The gate is located within the gate trench, and the gate is isolated from the gate trench by a gate oxide layer.

[0015] Optionally, the bottom surface of the buffer layer and the bottom surface of the second shielding area have the same depth in the epitaxial layer.

[0016] Optionally, the gate includes a first gate and a second gate, wherein the first gate is located above the second gate and the width of the second gate is smaller than the width of the first gate, the second gate is located above the buffer layer, and the bottom corner of the second gate is wrapped by the buffer layer and isolated from the buffer layer through the gate oxide layer.

[0017] Optionally, the gate trenches are symmetrically distributed about the second shielding region and the depth of the gate trenches is less than the height of the epitaxial layer.

[0018] Optionally, the semiconductor device further includes:

[0019] The well region is located within the epitaxial platform region;

[0020] The source region is located in the epitaxial platform region and above the sink region, with the top of the source region flush with the top of the epitaxial platform region;

[0021] An interlayer dielectric layer is located on the upper surface of the epitaxial layer. The interlayer dielectric layer has a plurality of contact holes that penetrate the interlayer dielectric layer and simultaneously expose the source region, the first shielding region and the third shielding region at the bottom.

[0022] A source metal layer and a drain metal layer, wherein the source metal layer is located on the interlayer dielectric layer and fills the contact hole and is electrically connected to the source region, the first shielding region and the third shielding region, and the drain metal layer is located on the second surface of the substrate.

[0023] Optionally, the first shielding region, the second shielding region, and the third shielding region have the same depth in the epitaxial layer.

[0024] This invention also provides a method for fabricating a semiconductor device, comprising the following steps:

[0025] A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other;

[0026] An epitaxial layer is formed on the first surface of the substrate;

[0027] A first shielding region, a second shielding region, and a third shielding region are formed in the epitaxial layer, and an epitaxial platform region is formed between adjacent first shielding regions, second shielding regions, and third shielding regions.

[0028] The epitaxial platform regions on both sides of the second shielding region are etched to form two gate trenches, and ion implantation is performed at the bottom of the gate trenches to form a buffer layer.

[0029] A gate oxide layer is formed on the sidewall of the gate trench, and a gate is formed in the gate trench, wherein the gate oxide layer covers the buffer layer.

[0030] Optionally, the step of forming the first shielding region, the second shielding region, and the third shielding region includes: forming a first hard mask layer on the surface of the epitaxial layer and performing a patterning process on the first hard mask layer to form a plurality of implantation regions; performing ion implantation on the epitaxial layer based on the implantation regions to form the first shielding region, the second shielding region, and the third shielding region in the epitaxial layer.

[0031] Optionally, the substrate and the epitaxial layer have a first conductivity type, and the first shielding region, the second shielding region, the third shielding region and the buffer layer have a second conductivity type.

[0032] Optionally, before forming the gate trench, the method further includes the steps of: performing ion implantation on the upper surface of the epitaxial platform region to form a well region; and performing ion implantation on the upper surface of the well region to form a source region; wherein the source region and the well region have different conductivity types.

[0033] Optionally, the method further includes the steps of: forming an interlayer dielectric layer on the surface of the epitaxial layer, and etching the interlayer dielectric layer, the source region, the first shielding region, and the third shielding region to form contact holes that expose the source region, the first shielding region, and the third shielding region; depositing metal on the interlayer dielectric layer to form a source metal layer that fills the contact holes; and depositing metal on the second surface of the substrate to form a drain metal layer.

[0034] Optionally, the step of forming the gate trench includes: etching the epitaxial platform regions on both sides of the second shielding region to form a first gate trench segment and performing ion implantation at the bottom of the first gate trench segment to form a buffer layer; etching the buffer layer at the bottom of the first gate trench segment to form a second gate trench segment, wherein the first trench segment and the second trench segment together constitute the gate trench; forming a second gate in the second gate trench segment and forming a first gate in the first gate trench segment, wherein the width of the second gate is smaller than the width of the first gate, the second gate is isolated from the buffer layer by the gate oxide layer, and the bottom corner of the second gate is wrapped by the buffer layer.

[0035] As described above, the semiconductor device and its fabrication method of the present invention first form multiple shielding regions in the epitaxial layer, then form a well region and a source region sequentially between adjacent shielding regions, then form a gate trench and a buffer layer at the bottom of the gate trench, with the width of the buffer layer equal to the width of the gate trench, and finally form a gate oxide layer and a gate in the gate trench. This makes the buffer layer, gate oxide layer and epitaxial layer in the device form a JFET similar to drain voltage control, thereby completing the regulation of the shielding effect of the buffer layer, realizing the self-regulation of Miller capacitance, and achieving lower switching losses and switching oscillations. In addition, since a stronger JFET effect is introduced between the buffer layer and the adjacent second shielding region, the conduction path of the electronic current is further compressed when the device is short-circuited. The electronic current path width of the semiconductor device of the present invention is narrower, which more effectively limits the saturation peak current when the device is short-circuited compared with the prior art, and significantly enhances the short-circuit withstand capability of the device. Furthermore, since a larger PN junction area is introduced between the buffer layer and the adjacent second shielding region, the avalanche capability is optimized. Attached Figure Description

[0036] Figure 1 The diagram shows a cross-sectional structure of a semiconductor device 10 in the prior art.

[0037] Figure 2 The diagram shown is a cross-sectional view of the semiconductor device 11 of the present invention.

[0038] Figure 3The diagram shown is a schematic cross-sectional view of another semiconductor device 12 of the present invention.

[0039] Figure 4 The diagram shown is a process flow chart of the semiconductor device fabrication method 20 of the present invention.

[0040] Figures 5 to 22 The diagram shows a cross-sectional structure of each step in the method 20 for fabricating the semiconductor device of the present invention.

[0041] Figure 23 The diagram shown is an equivalent circuit diagram of the semiconductor device of the present invention.

[0042] Figure 24 The diagram shows the electric field distribution of the semiconductor device of the present invention and the prior art under different drain voltages.

[0043] Figure 25 This diagram illustrates the relationship between the semiconductor device of the present invention and the Miller capacitance and drain voltage of the prior art.

[0044] Figure 26 The diagram shows a comparison of the electron current density distribution of the semiconductor device of the present invention and the prior art under short circuit conditions.

[0045] Figure 27 The graph shows a comparison of the short-circuit characteristics of the semiconductor device of the present invention with those of the prior art.

[0046] Component designation explanation

[0047] 101. Substrate; 111. Epitaxial layer; 1112. Drift layer; 1113. Current diffusion layer; 121. First hard mask layer; 122. Implantation region; 131. First shielding region; 132. Second shielding region; 133. Third shielding region; 151. Second hard mask layer; 161. Well region; 171. Source region; 181. Gate trench; 191. Buffer layer; 201. Gate oxide layer; 211. Gate; 2112. First gate; 2113. Second gate; 212. Interlayer dielectric layer; 213. Contact hole; 214. Source metal layer; 215. Drain metal layer; S1~S5. Steps. Detailed Implementation

[0048] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0049] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] Please see Figures 1 to 27 It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and to facilitate understanding. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms "upper," "lower," "left," "right," "middle," "first," and "second," etc., used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention.

[0051] This embodiment provides a semiconductor device 11. For example... Figure 2 As shown, the semiconductor device 11 includes: a substrate 101 having a first surface and a second surface disposed opposite to each other; an epitaxial layer 111 disposed on the first surface of the substrate 101; a plurality of shielding regions, including at least a first shielding region 131, a second shielding region 132 and a third shielding region 133, disposed at intervals in the epitaxial layer 111, and an epitaxial platform region is formed between adjacent first shielding regions 131, second shielding regions 132 and third shielding regions 133; a gate trench 181 disposed in the epitaxial platform regions on both sides of the second shielding region 132; a buffer layer 191 disposed at the bottom of the gate trench 181, and the width of the buffer layer 191 is the same as the width of the gate trench 181; and a gate 211 located in the gate trench 181, and the gate 211 is isolated from the gate trench 181 by a gate oxide layer 201.

[0052] Specifically, in this embodiment, the substrate 101 is a substrate of the first conductivity type. An epitaxial layer 111 is formed on the front side of the substrate 101. The epitaxial layer 111 can be a single-layer structure or a stacked structure. When the epitaxial layer 111 is a single-layer structure, the doping of the epitaxial layer 111 can be single-concentration doping or gradient concentration doping. When the epitaxial layer 111 is a stacked structure, the epitaxial layer 111 can include an N-type doped drift layer 1112 and a current diffusion layer 1113. The doping concentrations of the drift layer 1112 and the current diffusion layer 1113 can be the same or different. Under the premise of ensuring the performance of the semiconductor device, the shape, thickness and doping concentration of the substrate 101, the drift layer 1112 and the current diffusion layer 1113 can be selected according to the actual situation.

[0053] In this embodiment, the buffer layer 191, gate oxide layer 201, and current diffusion layer 1113 in the semiconductor device form a JFET similar to drain voltage control, thereby regulating the shielding effect of the buffer layer 191, achieving self-regulation of the Miller capacitance, and realizing lower switching losses and switching oscillations. In addition, due to the introduction of a stronger JFET effect between the buffer layer 191 and the adjacent second shielding region 132, the conduction path of the electronic current is further compressed when the device is short-circuited. The electronic current path width in the semiconductor device of this embodiment is only 0.15μm, which more effectively limits the saturation peak current of the semiconductor device when short-circuited, significantly enhancing the short-circuit withstand capability of the semiconductor device. Since the buffer layer 191 and the adjacent second shielding region 132 introduce a larger PN junction area, the hole current generated by avalanche breakdown can be extracted more effectively, suppressing the turn-on of parasitic transistors and reducing the junction temperature on the device surface, thus optimizing the avalanche capability.

[0054] It should be noted here that, as Figure 2 , Figure 3 and the following Figures 5 to 22 The diagram shows only a partial repeating unit of the formed semiconductor device. The actual semiconductor device consists of several partial repeating units as shown in the diagram.

[0055] As an example, the MOS device structure has multiple shielding regions, which are arranged laterally in the epitaxial layer 111. The depth of the shielding region is less than the height of the current diffusion layer 1113. Here, the depth refers to the vertical distance H between the top surface and the bottom surface of each shielding region.

[0056] Specifically, in this embodiment, the shielding region includes at least a first shielding region 131, a second shielding region 132, and a third shielding region 133. The first shielding region 131, the second shielding region 132, and the third shielding region 133 are all disposed in the epitaxial layer 111 at certain intervals. An epitaxial platform region is formed between adjacent first shielding regions 131, second shielding regions 132, and third shielding regions 133. The epitaxial platform region serves as a platform for the subsequent formation of the gate trench 181.

[0057] Specifically, in this embodiment, two gate trenches 181 are provided on both sides of the second shielding region 132. The gate trenches 181 are symmetrically distributed about the second shielding region 132, and the depth of the gate trenches 181 is less than the height of the current diffusion layer 1113. A buffer layer 191 is formed in the current diffusion layer 1113 at the bottom of the gate trenches 181, and the width of the buffer layer 191 is equal to the width of the gate trenches 181. The bottom surface of the buffer layer 191 and the bottom surface of the second shielding region 132 have the same depth in the epitaxial layer 111. A gate 211 is provided above the buffer layer 191, and the gate 211 is insulated from the buffer layer 191 and the epitaxial platform region by a gate oxide layer 201. In addition, the gate oxide layer 201 encapsulates the gate 211.

[0058] As an example, the gate 211 includes a first gate 2112 and a second gate 2113, wherein the first gate 2112 is located above the second gate 2113 and the width of the second gate 2113 is smaller than the width of the first gate 2112, the second gate 2113 is located above the buffer layer 191, and the bottom corner of the second gate 2113 is wrapped by the buffer layer 191 and isolated from the buffer layer 191 through the gate oxide layer 201.

[0059] Specifically, such as Figure 3 As shown, in another embodiment of the present invention, the gate trench 181 in the semiconductor device 12 includes a first gate trench 181 and a second gate trench 181. A first gate 2112 is disposed in the first gate trench 181, and a second gate 2113 is disposed in the second gate trench 181. The first gate 2112 is located above the second gate 2113, and the width of the second gate 2113 is smaller than the width of the first gate 2112. The second gate 2113 is located above the buffer layer 191, and the bottom corner of the second gate 2113 is wrapped by the buffer layer 191 and isolated from the buffer layer 191 through the gate oxide layer 201.

[0060] In another embodiment of the present invention, the semiconductor device further includes a well region 161 located in the epitaxial platform region; a source region 171 located in the epitaxial platform region and above the well region 161, the top of the source region 171 being flush with the top of the epitaxial platform region; an interlayer dielectric layer 212 located on the upper surface of the epitaxial layer 111, the interlayer dielectric layer 212 having a plurality of contact holes 213 penetrating the interlayer dielectric layer 212 and simultaneously exposing the source region 171, the first shielding region 131 and the third shielding region 133 at its bottom; a source metal layer 214 and a drain metal layer 215, wherein the source metal layer 214 is located on the interlayer dielectric layer 212 and fills the contact holes 213 and is electrically connected to the source region 171, the first shielding region 131 and the third shielding region 133, and the drain metal layer 215 is located on the second surface of the substrate 101.

[0061] Specifically, the well region 161 has a first conductivity type, and the source region 171 has a second conductivity type, wherein the first conductivity type is different from the second conductivity type. For example, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type. Specifically, the material of the interlayer dielectric layer 212 includes silicon oxide, silicon nitride, or other suitable dielectric materials. The contact hole 213 penetrates the interlayer dielectric layer 212 and extends into the source region 171, the first shielding region 131, and the third shielding region 133, forming an ohmic contact with the source region 171, the first shielding region 131, and the third shielding region 133.

[0062] Specifically, the source metal layer 214 is made of titanium, titanium nitride, silver, gold, copper, aluminum, tungsten, or other suitable conductive materials.

[0063] Specifically, the material of the drain metal layer 215 includes titanium, titanium nitride, silver, gold, copper, aluminum, tungsten, or other suitable conductive materials.

[0064] This embodiment also provides a method 20 for fabricating a semiconductor device, used to fabricate the aforementioned semiconductor device 11. For example... Figure 4 As shown, the preparation method 20 includes the following steps:

[0065] S1: A substrate 101 is provided, the substrate 101 having a first surface and a second surface disposed opposite to each other.

[0066] S2: An epitaxial layer 111 is formed on the first surface of the substrate 101.

[0067] S3: A first shielding region 131, a second shielding region 132, and a third shielding region 133 are formed in the epitaxial layer 111, and an epitaxial platform region is formed between adjacent first shielding regions 131, second shielding regions 132, and third shielding regions 133.

[0068] S4: Etch the epitaxial platform regions on both sides of the second shielding region 132 to form two gate trenches 181 and perform ion implantation at the bottom of the gate trenches 181 to form a buffer layer 191.

[0069] S5: A gate oxide layer 201 is formed on the sidewall of the gate trench 181, and a gate 211 is formed in the gate trench 181, wherein the gate oxide layer 201 covers the buffer layer 191.

[0070] In this embodiment, a first shielding region 131, a second shielding region 132, and a third shielding region 133 are first formed in the epitaxial layer 111. Then, a gate trench 181 is formed, and a buffer layer 191 is formed at the bottom of the gate trench 181, with the width of the buffer layer 191 equal to the width of the gate trench 181. Finally, a gate oxide layer 201 and a gate 211 are formed in the gate trench 181. This makes the buffer layer 191, the gate oxide layer 201, and the epitaxial layer 111 in the device form a JFET similar to drain voltage control, thereby controlling the shielding effect of the buffer layer 191, achieving self-adjustment of the Miller capacitance, and realizing lower switching losses and switching oscillations. In addition, since a stronger JFET effect is introduced between the buffer layer 191 and the adjacent second shielding region 132, the conduction path of the electronic current is further compressed when the device is short-circuited, making the electronic current path width only 0.15μm. This more effectively limits the saturation peak current when the device is short-circuited and significantly enhances the short-circuit withstand capability of the device.

[0071] The method for fabricating the semiconductor device of this embodiment will now be described in detail with reference to the accompanying drawings.

[0072] like Figure 5 As shown, steps S1 and S2 are performed first, a substrate 101 is provided, the substrate 101 has a first surface and a second surface disposed opposite to each other, and an epitaxial layer 111 is formed on the first surface of the substrate 101.

[0073] Specifically, such as Figure 5The diagram shows a cross-sectional view of the substrate 101. In this embodiment, the substrate 101 is a substrate of the first conductivity type. The substrate 101 has a first surface and a second surface disposed opposite to each other. An epitaxial layer 111 of the first conductivity type is formed on the first surface of the substrate 101. Before performing the epitaxial process, the substrate 101 is first cleaned, for example, by using a diluted acid solution to remove the natural oxide layer on the surface of the substrate 101, followed by cleaning with deionized water, and finally drying. Generally, the doping concentration of the substrate 101 and the epitaxial layer 111 decreases sequentially. While ensuring the performance of the semiconductor device, the thickness, size and doping concentration of the substrate 101 and the epitaxial layer 111 can be selected according to the actual situation.

[0074] As a preferred example, the epitaxial layer 111 can be a single-layer structure or a stacked structure. When the epitaxial layer 111 is a single-layer structure, the doping of the epitaxial layer 111 can be single-concentration doping or gradient concentration doping. When the epitaxial layer 111 is a stacked structure, the epitaxial layer 111 can include an N-type doped drift layer 1112 and a current diffusion layer 1113. The doping concentrations of the drift layer 1112 and the current diffusion layer 1113 can be the same or different. Furthermore, while ensuring the performance of the semiconductor device, the shape, thickness, and doping concentration of the substrate 101, the drift layer 1112, and the current diffusion layer 1113 can be selected according to the actual situation.

[0075] Specifically, in this embodiment, the epitaxial layer 111 includes an N-type doped drift layer 1112 and a current diffusion layer 1113 sequentially stacked on the substrate 101, such as... Figure 5 As shown, in this embodiment, the N-type doped drift layer 1112 is first formed on the substrate 101, and then ion implantation at a predetermined depth is performed on the upper surface of the N-type doped drift layer 1112 to form a current diffusion layer 1113.

[0076] like Figures 6 to 9 As shown, step S3 is then performed, in which a first shielding region 131, a second shielding region 132 and a third shielding region 133 are formed in the epitaxial layer 111, and an epitaxial platform region is formed between adjacent first shielding regions 131, second shielding regions 132 and third shielding regions 133.

[0077] As a specific example, the steps of forming the first shielding region 131, the second shielding region 132, and the third shielding region 133 include: forming a first hard mask layer 121 on the surface of the epitaxial layer 111 and performing a patterning process on the first hard mask layer 121 to form a plurality of implantation regions 122, and performing a second type of ion implantation on the epitaxial layer 111 based on the implantation regions 122 to form the first shielding region 131, the second shielding region 132, and the third shielding region 133 in the epitaxial layer 111.

[0078] Specifically, such as Figure 6 As shown, a first hard mask layer 121 is first formed on the surface of the current diffusion layer 1113, and the first hard mask layer 121 is a silicon dioxide layer; as Figure 7 As shown, the first hard mask layer 121 is patterned using photolithography and etching processes, thereby forming a plurality of injection regions 122 in the first hard mask layer 121. The bottom of the injection regions 122 exposes the current diffusion layer 1113. The methods for forming the injection regions 122 include dry etching, wet etching, or other suitable methods, such as... Figure 8 As shown, based on the patterned first hard mask layer 121, a second type of ion implantation is performed on the current diffusion layer 1113 at a preset depth in the implantation region 122 to form the first shielding region 131, the second shielding region 132, and the third shielding region 133. An epitaxial platform region is formed between adjacent first shielding regions 131, second shielding regions 132, and third shielding regions 133. The preset depth during ion implantation is less than the height of the current diffusion layer 1113, meaning that the first shielding region 131, second shielding region 132, and third shielding region 133 will not penetrate into the drift layer 1112.

[0079] Specifically, such as Figure 9 As shown, after forming the first shielding region 131, the second shielding region 132, and the third shielding region 133, it is necessary to remove the patterned first hard mask layer 121. Methods for removing the first hard mask layer 121 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods. In this embodiment, chemical mechanical polishing is preferably used to remove the patterned first hard mask layer 121.

[0080] like Figure 14 and Figure 15 As shown, step S4 is then performed to etch the epitaxial platform regions on both sides of the second shielding region 132 to form two gate trenches 181 and to perform ion implantation at the bottom of the gate trenches 181 to form a buffer layer 191.

[0081] As a specific example, before forming the gate trench 181, the method further includes the steps of: performing ion implantation on the upper surface of the epitaxial platform region to form a well region 161; and performing ion implantation on the upper surface of the well region 161 to form a source region 171; wherein the source region 171 and the well region 161 have different conductivity types.

[0082] Specifically, such as Figure 10 As shown, a second hard mask layer 151 is formed on the current diffusion layer 1113. The second hard mask layer 151 is a silicon dioxide layer. The second hard mask layer 151 is patterned using photolithography and etching processes, thereby removing the second hard mask layer 151 above the epitaxial platform region, as shown. Figure 11 As shown, based on the patterned second hard mask layer 151, ion implantation is performed to a predetermined depth on the upper surface of the epitaxial platform region to form a well region 161 in the epitaxial platform region. Then, as... Figure 12 As shown, ion implantation is performed at a predetermined depth on the upper surface of the well region 161 to form a source region 171 on the upper surface of the well region 161, wherein the source region 171 and the well region 161 have different conductivity types.

[0083] Specifically, the well region 161 has a first conductivity type, and the source region 171 has a second conductivity type, wherein the first conductivity type is different from the second conductivity type. For example, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

[0084] Specifically, such as Figure 13 As shown, after forming the well region 161 and the source region 171, the method further includes removing the patterned second hard mask layer 151. Methods for removing the second hard mask layer 151 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods. In this embodiment, chemical mechanical polishing is preferably used to remove the patterned second hard mask layer 151.

[0085] Specifically, such as Figure 14 As shown, the steps for forming the gate trench 181 are as follows: First, a patterned first shielding layer (not shown in the figure) is formed on the surface of the current diffusion layer 1113; then, based on the patterned first shielding layer, the source region 171, the well region 161, and the current diffusion layer 1113 in the epitaxial platform region on both sides of the second shielding region 132 are etched to form two gate trenches 181. The method for forming the gate trenches 181 includes dry etching, wet etching, or other suitable methods. The gate trenches 181 are symmetrically distributed about the second shielding region 132, and the depth of the gate trenches 181 is less than the height of the current diffusion layer 1113.

[0086] like Figure 15 As shown, ion implantation is performed on the current diffusion layer 1113 exposed at the bottom of the gate trench 181 to form a buffer layer 191 on the current diffusion layer 1113 at the bottom of the gate trench 181. The buffer layer 191 has a second conductivity type, and the width of the buffer layer 191 is the same as the width of the gate trench 181. Preferably, after forming the buffer layer 191 and before forming the gate oxide layer 201, a step of high-temperature annealing is further included on the semiconductor structure for which the buffer layer 191 is formed, thereby activating doped impurities and repairing lattice damage.

[0087] like Figures 16 to 18 As shown, step S5 is then performed, in which a gate oxide layer 201 is formed on the sidewall of the gate trench 181, and a gate 211 is formed in the gate trench 181, wherein the gate oxide layer 201 covers the buffer layer 191.

[0088] As a specific example, the steps of forming the gate oxide layer 201 and the gate 211 include: firstly, as... Figure 16 As shown, a gate oxide layer 201 is formed covering the sidewalls and bottom wall of the gate trench 181 and the surface of the current diffusion layer 1113. Then, polysilicon is deposited in the remaining gate trench 181 within the gate oxide layer 201 to form the gate 211. The gate 211 is insulated from the well region 161 and the source region 171 through the gate oxide layer 201. Figure 17 As shown, anisotropic etching is performed on the gate oxide layer 201 and the gate 211 on the surface of the current diffusion layer 1113, and planarization is performed on the gate oxide layer 201 and the gate 211, so that the upper surface of the gate 211 is lower than the upper surface of the source region 171. Then, as shown... Figure 18 As shown, a gate oxide layer 201 is formed again on the surface of the gate 211 to cover the gate 211.

[0089] Specifically, the gate oxide layer 201 is a high-k dielectric layer, including but not limited to silicon oxide, silicon nitride, aluminum oxide, or other suitable dielectric materials. The methods for forming the gate oxide layer 201 and the gate 211 include thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0090] Specifically, the planarization methods for the gate oxide layer 201 and the gate 211 include chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0091] In another embodiment of the invention, such as Figure 3As shown, the gate 211 includes a first gate 2112 and a second gate 2113, wherein the first gate 2112 is located above the second gate 2113 and the width of the second gate 2113 is smaller than the width of the first gate 2112, the second gate 2113 is located above the buffer layer 191, and the bottom corner of the second gate 2113 is wrapped by the buffer layer 191 and isolated from the buffer layer 191 through the gate oxide layer 201.

[0092] Specifically, the source region 171, the well region 161, and the current diffusion layer 1113 in the epitaxial platform regions on both sides of the second shielding region 132 are first etched to form a first gate trench segment, and ion implantation is performed at the bottom of the first gate trench segment to form a buffer layer 191; the buffer layer 191 at the bottom of the first gate trench segment is etched to form a second gate trench segment, such as... Figure 3 As shown, the first gate trench segment and the second gate trench segment together form a gate trench 181. Then, a gate oxide layer 201 is formed covering the sidewalls and bottom wall of the gate trench 181 and the surface of the current diffusion layer 1113. A first gate 2112 is formed in the first gate trench segment, and a second gate 2113 is formed in the second gate trench segment. The first gate 2112 and the second gate 2113 are electrically connected, and the first gate 2112 is located above the second gate 2113. The width of the second gate 2113 is smaller than the width of the first gate 2112. The second gate 2113 is located above the buffer layer 191. The bottom corner of the second gate 2113 is wrapped by the buffer layer 191 and isolated from the buffer layer 191 through the gate oxide layer 201. The steps for forming the first gate 2112 and the second gate 2113 can be referred to the foregoing content, and will not be described in detail here.

[0093] As a specific example, after forming the gate 211, the method further includes the following steps: forming an interlayer dielectric layer 212 on the surface of the epitaxial layer 111, and etching the interlayer dielectric layer 212, the source region 171, the first shielding region 131, and the third shielding region 133 to form a contact hole 213 exposing the source region 171, the first shielding region 131, and the third shielding region 133; depositing metal on the interlayer dielectric layer 212 to form a source metal layer 214 filling the contact hole 213; and depositing metal on the second surface of the substrate 101 to form a drain metal layer 215.

[0094] Specifically, such as Figure 19As shown, an interlayer dielectric layer 212 is formed on top of the source region 171 and the first shielding region 131, the second shielding region 132 and the third shielding region 133. The method for forming the interlayer dielectric layer 212 includes chemical vapor deposition, physical vapor deposition or other suitable methods. The interlayer dielectric layer 212 includes one or a combination of silicon oxide layer, silicon nitride layer, and silicon phosphate glass layer.

[0095] Specifically, such as Figure 20 As shown, a patterned photoresist masking layer is formed on the upper surface of the interlayer dielectric layer 212. Based on the patterned second masking layer, the interlayer dielectric layer 212, the source region 171, the first shielding region 131, and the third shielding region 133 are etched to form the contact hole 213. The method for forming the contact hole 213 includes dry etching, wet etching, or other suitable methods. Preferably, this embodiment uses a dry etching process to etch the interlayer dielectric layer 212, the source region 171, the first shielding region 131, and the third shielding region 133. Since dry etching has good anisotropy, it hardly increases the manufacturing cost.

[0096] Specifically, forming the second masking layer and patterning the second masking layer are conventional technical means, and will not be described in detail here.

[0097] Specifically, such as Figure 21 As shown, a source metal layer 214 is formed by depositing metal on the interlayer dielectric layer 212, and the source metal layer 214 fills the contact hole 213 and forms an ohmic contact with the source region 171, the first shielding region 131 and the third shielding region 133. The material forming the source metal layer 214 includes titanium, silver, gold, copper, aluminum, tungsten or other suitable conductive materials. The method for forming the source metal layer 214 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0098] Specifically, such as Figure 22 As shown, a drain metal layer 215 is formed by depositing metal on the second surface of the substrate 101. The material for forming the drain metal layer 215 includes titanium, silver, gold, copper, aluminum, tungsten, or other suitable conductive materials. The method for forming the drain metal layer 215 includes sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable methods.

[0099] like Figure 23 As shown, it displays the equivalent circuit diagram corresponding to the semiconductor device formed in this embodiment, by Figure 2 The cross-sectional structure diagram of the semiconductor device shown in this embodiment and Figure 23As shown in the equivalent circuit diagram, the buffer layer 191, gate oxide layer 201, and current diffusion layer 1113 in the semiconductor device can form a JFET similar to drain voltage control. The drain voltage control JFET will further control the overall electrical state of the buffer layer 191, complete the regulation of the shielding effect of the buffer layer 191, realize the self-adjustment of Miller capacitance, and achieve the purpose of synergistic optimization of switching loss and switching oscillation, that is, to achieve lower switching loss and switching oscillation.

[0100] like Figure 24 As shown, it illustrates the difference between the semiconductor device formed in this embodiment and prior art devices at different drain-source voltages V. ds A schematic diagram of the electric field distribution under the voltage between the drain (D) and the source (S), from Figure 24 It can be seen that when the drain voltage is low (drain voltage < 200V), the buffer layer 191 is not completely depleted. The buffer layer 191 is connected to the source through the first shielding region 131 and the third shielding region 133, effectively shielding the electric field lines from the drain D to the gate G, thereby reducing the coupling of gate and drain charges. When the drain voltage is high (drain voltage > 200V), the buffer layer 191 is completely depleted. At this time, the buffer layer 191 is in a floating state, which weakens its shielding effect and attracts more electric field lines from the drain to the gate, enhancing the coupling of gate and drain charges.

[0101] like Figure 25 As shown, it illustrates the relationship between the Miller capacitance and drain-source voltage between the gate and drain of the semiconductor device formed in this embodiment and the prior art device. Figure 25 As can be seen, the structure of the semiconductor device in this embodiment, by setting the structure and distribution of the buffer layer 191, the shielding region, the gate 211 and the gate oxide layer 201, achieves the following effects: in the low-voltage state, the coupling of gate and drain charges is reduced, the Miller capacitance is reduced, the switching speed is increased and the switching loss is reduced; in the high-voltage state, the coupling of gate and drain charges is enhanced, the Miller capacitance is increased, the switching speed is reduced and the switching oscillation is suppressed. This solves the problem that it is difficult to optimize the switching speed and switching oscillation in the prior art, and at the same time achieves lower switching loss and switching oscillation.

[0102] Figure 26 This is a simulation comparison of the electron current density distribution of a semiconductor device according to an embodiment of the present invention and a prior art device under short-circuit conditions. As shown in the figure, when the same drain-source voltage V of 800V is applied to both the semiconductor device of the present invention and the prior art device... dsFurthermore, under the condition of a short circuit, the electronic current conduction path width of existing technology devices is approximately 0.35 μm, while the electronic current conduction path width of the semiconductor device in this embodiment of the invention is approximately 0.15 μm. In other words, due to the stronger JFET effect introduced between the buffer layer 191 and the adjacent current diffusion layer 1113 and the second shielding region 132, the semiconductor device in this embodiment of the invention has a narrower current path during a short circuit, thereby effectively limiting the saturation peak current during a short circuit and optimizing the short-circuit capability of the semiconductor device.

[0103] Figure 27 This is a schematic diagram comparing the short-circuit characteristics of a semiconductor device according to an embodiment of the present invention and a prior art device. Generally, when the temperature of a semiconductor device reaches 1500K, the semiconductor device will be damaged. Figure 27 It can be seen that when a short circuit occurs, the current I in the device... d The temperature rises rapidly. Because the electronic current path of the semiconductor device in this embodiment of the invention is narrower, the short-circuit current of the semiconductor device in this embodiment of the invention is smaller, thus the temperature rise of the semiconductor device is relatively slower, and the short-circuit withstand time is relatively longer.

[0104] Furthermore, in the semiconductor device of this embodiment, since the buffer layer 191 and the adjacent current diffusion layer 1113 introduce a larger PN junction area, when the semiconductor device experiences non-clamped inductive load switching UIS, it can more effectively extract the hole current generated by avalanche breakdown and suppress the turn-on of parasitic transistors, thereby optimizing the avalanche capability of the semiconductor device.

[0105] In summary, the semiconductor device and its fabrication method of the present invention, by first forming multiple shielding regions in a current diffusion layer, then forming a well region and a source region in the epitaxial platform region between the shielding regions, followed by forming a gate trench and a buffer layer at the bottom of the gate trench, with the lateral width of the buffer layer equal to the lateral width of the gate trench, and finally forming a gate oxide layer and a gate in the gate trench, the buffer layer, gate oxide layer, and current diffusion layer in the semiconductor device form a JFET similar to drain voltage control, further controlling the overall electrical state of the buffer layer, completing the regulation of the shielding effect of the buffer layer, and realizing the self-adjustment of the Miller capacitance, achieves... Lower switching losses and switching oscillations are achieved. Furthermore, due to the stronger JFET effect introduced between the buffer layer, the adjacent current diffusion layer, and the second shielding region, the conduction path of electronic current is further compressed when the device is short-circuited. The electronic current conduction path width of the semiconductor device in some embodiments of the present invention is about 0.15μm, which more effectively limits the saturation peak current when the device is short-circuited compared with the prior art, and significantly enhances the short-circuit withstand capability of the device. In addition, since the buffer layer and the second shielding region introduce a larger PN junction area, the avalanche capability can be optimized, which has high industrial value.

[0106] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first surface and a second surface disposed opposite to each other; An epitaxial layer is disposed on the first surface of the substrate; Multiple shielding areas, including at least a first shielding area, a second shielding area, and a third shielding area, are spaced apart in the epitaxial layer, and an epitaxial platform area is formed between adjacent first shielding areas, second shielding areas, and third shielding areas. Gate trenches are disposed in the epitaxial platform regions on both sides of the second shielding region; A buffer layer is disposed at the bottom of the gate trench, and the width of the buffer layer is the same as the width of the gate trench; as well as The gate is located within the gate trench, and the gate is isolated from the gate trench by a gate oxide layer.

2. The semiconductor device according to claim 1, characterized in that: The bottom surface of the buffer layer and the bottom surface of the second shielding area have the same depth in the epitaxial layer.

3. The semiconductor device according to claim 1, characterized in that: The gate includes a first gate and a second gate, wherein the first gate is located above the second gate and the width of the second gate is smaller than the width of the first gate, the second gate is located above the buffer layer, and the bottom corner of the second gate is wrapped by the buffer layer and isolated from the buffer layer through the gate oxide layer.

4. The semiconductor device according to claim 1, characterized in that: The gate trenches are symmetrically distributed about the second shielding region, and the depth of the gate trenches is less than the height of the epitaxial layer.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: The well region is located within the epitaxial platform region; The source region is located within the epitaxial platform region and above the well region; An interlayer dielectric layer is located on the upper surface of the epitaxial layer. The interlayer dielectric layer has a plurality of contact holes that penetrate the interlayer dielectric layer and simultaneously expose the source region, the first shielding region and the third shielding region at the bottom. A source metal layer and a drain metal layer, wherein the source metal layer is located on the interlayer dielectric layer and fills the contact hole and is electrically connected to the source region, the first shielding region and the third shielding region, and the drain metal layer is located on the second surface of the substrate.

6. The semiconductor device according to claim 1, characterized in that: The first shielding region, the second shielding region, and the third shielding region have the same depth in the epitaxial layer.

7. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other; An epitaxial layer is formed on the first surface of the substrate; A first shielding region, a second shielding region, and a third shielding region are formed in the epitaxial layer, and an epitaxial platform region is formed between adjacent first shielding regions, second shielding regions, and third shielding regions. The epitaxial platform regions on both sides of the second shielding region are etched to form two gate trenches, and ion implantation is performed at the bottom of the gate trenches to form a buffer layer. A gate oxide layer is formed on the sidewall of the gate trench, and a gate is formed in the gate trench, wherein the gate oxide layer covers the buffer layer.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The steps for forming the first shielding area, the second shielding area, and the third shielding area include: A first hard mask layer is formed on the surface of the epitaxial layer, and the first hard mask layer is patterned to form a plurality of implantation regions; ion implantation is performed on the epitaxial layer based on the implantation regions to form the first shielding region, the second shielding region, and the third shielding region in the epitaxial layer.

9. The method for fabricating a semiconductor device according to claim 7, characterized in that: The substrate and the epitaxial layer have a first conductivity type, and the first shielding region, the second shielding region, the third shielding region and the buffer layer have a second conductivity type.

10. The method for fabricating a semiconductor device according to claim 7, characterized in that, The process further includes the following steps before forming the gate trench: Ion implantation is performed on the upper surface of the epitaxial platform region to form a trap region; Ion implantation is performed on the upper surface of the trap region to form a source region; The source region and the well region have different conductivity types.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, It also includes the following steps: An interlayer dielectric layer is formed on the surface of the epitaxial layer, and the interlayer dielectric layer, the source region, the first shielding region, and the third shielding region are etched to form contact holes that expose the source region, the first shielding region, and the third shielding region; A source metal layer is formed by depositing metal on the interlayer dielectric layer to fill the contact hole; A drain metal layer is formed by depositing metal on the second surface of the substrate.

12. The method for fabricating a semiconductor device according to claim 7, characterized in that, The step of forming the gate trench further includes: The epitaxial platform regions on both sides of the second shielding region are etched to form a first gate trench segment, and an ion implantation is performed at the bottom of the first gate trench segment to form a buffer layer. The buffer layer at the bottom of the first gate trench segment is etched to form a second gate trench segment, and the first trench segment and the second trench segment together constitute the gate trench. A second gate is formed in the second gate trench segment, and a first gate is formed in the first gate trench segment. The width of the second gate is smaller than the width of the first gate. The second gate is isolated from the buffer layer by the gate oxide layer, and the bottom corner of the second gate is wrapped by the buffer layer.

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