Semiconductor device, electronic device, and method for manufacturing semiconductor device

Abstract

The application discloses a semiconductor device, an electronic device and a preparation method of the semiconductor device. The semiconductor device comprises a substrate layer of a first conductive type, a drift layer of the first conductive type and a trench structure. The substrate layer has an upper surface. The drift layer is located on the upper surface of the substrate layer along a first direction. A transistor structure is formed in the drift layer. The transistor structure comprises a well region of a second conductive type and a source region of the first conductive type. The well region is formed in the drift layer and located on the upper surface of the drift layer. The source region is formed in the well region and located on the upper surface of the well region. The trench structure comprises a trench extending along the first direction and penetrating the source region and the well region. The bottom of the trench extends to the drift layer. A Schottky contact material is filled in the trench to form a Schottky contact with the drift layer. The device of the application can inhibit the bipolar degradation effect, improve the reliability of the semiconductor device, reduce the reverse conduction voltage drop and help reduce the switching loss.

Description

Technical Field

[0001] This invention relates to the field of vehicle technology, and in particular to a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device. Background Technology

[0002] Silicon carbide (SiC) materials are widely used in high-voltage, high-frequency, and high-efficiency power devices due to their high breakdown electric field, wide bandgap, high thermal conductivity, and excellent high-frequency performance. Among them, metal-oxide-semiconductor field-effect transistors (MOSFETs) based on silicon carbide (SiC) have broad application prospects in new energy vehicles, photovoltaic inverters, and rail transportation due to their advantages such as low conduction loss and high switching speed.

[0003] However, in practical applications, existing SiC MOSFETs require their internal parasitic body diodes to conduct under reverse freewheeling conditions. When the parasitic body diode is on, the energy released by electron-hole recombination is easily captured by basal dislocations in the epitaxial layer, leading to dislocation line slip and stacking faults. As stress accumulates over time, the stacking fault region gradually expands, causing device performance degradation, such as a significant increase in on-resistance and leakage current, i.e., a bipolar degradation effect, which limits the device's long lifespan and high reliability. Simultaneously, the parasitic body diode also suffers from high on-voltage drop and significant switching losses during reverse conduction, making it difficult to meet the application requirements of high-efficiency, high-reliability power systems. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one object of the present invention is to provide a semiconductor device that can suppress bipolar degradation effects, improve the reliability of the semiconductor device, reduce reverse conduction voltage drop, and help reduce switching losses.

[0005] The second objective of this invention is to provide an electronic device.

[0006] The third objective of this invention is to provide a method for fabricating a semiconductor device.

[0007] To achieve the above objectives, a semiconductor device according to a first aspect of the present invention includes: a substrate layer of a first conductivity type, the substrate layer having an upper surface; a drift layer of the first conductivity type, the drift layer being located on the upper surface of the substrate layer along a first direction, a transistor structure formed therein, the transistor structure including a well region of a second conductivity type and a source region of the first conductivity type, the well region being formed in the drift layer and located on the upper surface of the drift layer, the source region being formed in the well region and located on the upper surface of the well region; and a trench structure including a trench extending along the first direction and penetrating the source region and the well region, the bottom of the trench extending to the drift layer, the trench being filled with a Schottky contact material to form a Schottky contact with the drift layer.

[0008] According to an embodiment of the semiconductor device of the present invention, by filling a trench structure extending along a first direction and penetrating the source region and the well region to the drift layer with Schottky contact material, a Schottky contact is formed between the trench region and the drift layer, thereby constructing a current path dominated by Schottky barrier conduction during reverse freewheeling operation. Since the Schottky contact has a low turn-on voltage characteristic, and the trench structure shortens the electron transport path to the Schottky contact region, the current can more quickly and preferentially establish a dominant conductive channel through this low-barrier path during reverse conduction. This suppresses the conduction of parasitic diodes that traditionally rely on the well region and drift layer, reduces hole injection and electron-hole recombination processes, thereby suppressing the propagation of material defects caused by recombination and achieving the goal of suppressing bipolar degradation effects. Simultaneously, since the conduction voltage drop of the Schottky contact is lower than that of the parasitic diode, the overall voltage drop of the device is reduced during reverse conduction, thereby achieving a reduction in reverse conduction voltage drop. Furthermore, Schottky contacts are unipolar conduction mechanisms, and there is no minority carrier storage effect during switching, nor is there a reverse recovery current. Therefore, they can avoid the additional energy loss caused by carrier removal during reverse recovery, which helps to reduce switching losses and improve the overall reliability of the device.

[0009] In some embodiments, the Schottky contact material includes a semiconductor material or a metal material that forms a heterojunction Schottky contact with the drift layer.

[0010] The above-mentioned technical solution has the following advantages or beneficial effects: The heterojunction Schottky contact provides an additional unipolar conductive path for the semiconductor device, allowing carrier transport to be preferentially achieved through this interface under reverse freewheeling or specific bias conditions, thereby reducing dependence on the parasitic diode conduction path. Because this type of contact has a lower turn-on voltage and a faster carrier response speed, it helps to reduce reverse conduction voltage drop, reduce switching losses, and improve the overall reliability of the device.

[0011] In some embodiments, the Schottky contact material is the semiconductor material; the top of the trench is flush with the upper surface of the drift layer, and the semiconductor material fills the trench.

[0012] The above technical solution has the following advantages or beneficial effects: Since the trench is occupied by a completely filled semiconductor material, the region forms a through-conductive path in electrical terms, thereby providing a low-resistance transport channel for charge carriers during device operation and preferentially participating in current transport in the reverse conduction state. This helps to suppress the conduction path of the parasitic diode formed by the well region and the drift layer, thereby suppressing the bipolar degradation effect.

[0013] In some embodiments, the drift layer is a silicon carbide layer, and the semiconductor material is polycrystalline silicon.

[0014] The above technical solution has the following advantages or beneficial effects: polycrystalline silicon has good process compatibility and trench filling ability. It can maintain structural stability under high temperature process conditions. At the same time, its conductivity can be further optimized by doping control, thereby improving the current transmission capability and structural reliability of the trench region while ensuring the formation of the Schottky barrier.

[0015] In some embodiments, the Schottky contact material is the metal material; the top of the trench is flush with the upper surface of the drift layer, and the metal material fills the bottom of the trench.

[0016] The above technical solution has the following advantages or beneficial effects: Using a metallic material as the Schottky contact material within the trench, the metal-semiconductor barrier interface formed between the metal and the drift layer semiconductor material can be utilized to construct the Schottky contact. Compared to semiconductor filling materials, metallic materials have lower bulk resistivity and better carrier transport capability, thus helping to reduce the series resistance in the trench region and improve current transport efficiency.

[0017] In some embodiments, the metallic material includes a titanium / titanium nitride alloy and a tungsten plug.

[0018] In some embodiments, the semiconductor device further includes: a source metal layer located above the drift layer along the first direction, the source metal layer being connected to a Schottky contact material in the trench via a contact hole.

[0019] The above technical solution has the following advantages or beneficial effects: the source metal layer can realize the electrical connection between the external circuit and the internal source region and related conductive structures. The source metal layer can perform the functions of current collection, external lead connection, and reducing the surface wiring resistance of the device, thereby improving the device's conductivity and package connection reliability.

[0020] In some embodiments, the well region includes a first well region and a second well region, the first well region and the second well region being spaced apart along a second direction, the second direction being perpendicular to the first direction; the source region includes a first source region and a second source region, the first source region being formed within the first well region and located on the upper surface of the first well region, and the second source region being formed within the second well region and located on the upper surface of the second well region; the transistor structure further includes a JFET region, the JFET region being located between the first well region and the second well region along the second direction.

[0021] The above technical solution has the following advantages or beneficial effects: The main function of the JFET region is to provide a lateral current transition path from the source region to the drift layer 2 in the on-state of the device, so that the charge carriers are transported through the region located between the first well region and the second well region before entering the drift layer. Since this region is located at a critical position in the main current path, the width, doping concentration and resistance characteristics of the JFET region will have a significant impact on the overall on-resistance of the device.

[0022] In some embodiments, the trench structure includes: a first trench that penetrates the first source region and the first well region along the first direction; a second trench that penetrates the second source region and the second well region along the first direction; both the first trench and the second trench are filled with the Schottky contact material to form Schottky contacts with the drift layer, respectively.

[0023] The above technical solution has the following advantages or beneficial effects: the double-groove structure can increase the total Schottky contact area, reduce the current density per unit area, thereby reducing local current congestion and helping to reduce contact resistance and reverse conduction voltage drop. Simultaneously, multiple Schottky conduction paths can share the current, making the carrier distribution inside the device more uniform, reducing local heat accumulation, and improving operational stability and reliability.

[0024] In some embodiments, the semiconductor device further includes: a gate layer located along the first direction between the upper surface of the drift layer and the source metal layer, the gate layer covering the JFET region, a portion of the source region and a portion of the well region located between the first trench and the second trench; and an insulating layer located between the gate layer and the upper surface of the drift layer.

[0025] The above technical solution has the following advantages or beneficial effects: the gate layer can be used to receive external gate drive signals and control the conduction and turn-off states of the channel region through the action of electric field; the main function of the insulating layer is to prevent the gate layer from directly conducting with the underlying semiconductor region, avoid gate leakage current, and at the same time allow the gate voltage to act on the underlying semiconductor region in the form of electric field coupling.

[0026] In some embodiments, the semiconductor device further includes a dielectric layer located between the source metal layer and the upper surfaces of the gate layer and the drift layer.

[0027] The above technical solution has the following advantages or beneficial effects: the dielectric layer can form an effective electrical isolation structure between the source metal layer and the gate layer, avoiding direct electrical connection or leakage current between different potential regions.

[0028] In some embodiments, the substrate layer has a lower surface opposite the upper surface in the first direction; the semiconductor device further includes a drain metal layer located on the lower surface of the substrate layer along the first direction.

[0029] The above technical solution has the following advantages or beneficial effects: the drain metal layer is used as the current output terminal of the semiconductor device and forms an electrical connection with the internal substrate layer, thereby realizing the current transmission path between the external circuit and the internal conductive structure of the device.

[0030] To achieve the above objectives, an electronic device according to a second aspect of the present invention includes at least one semiconductor device as described in the above embodiments.

[0031] According to an embodiment of the present invention, an electronic device employing the semiconductor device described in the above embodiment fills a trench structure extending along a first direction, penetrating the source region and the well region, and extending to the drift layer with Schottky contact material, thereby forming a Schottky contact between the trench region and the drift layer. This creates a current path dominated by Schottky barrier conduction during reverse freewheeling operation. Because the Schottky contact has a low turn-on voltage characteristic, and the trench structure shortens the electron transport path to the Schottky contact region, the current can more quickly and preferentially establish a dominant conductive channel through this low-barrier path during reverse conduction. This suppresses the conduction of parasitic diodes that traditionally rely on the well region and drift layer, reduces hole injection and electron-hole recombination, and thus suppresses the propagation of material defects caused by recombination, achieving the goal of suppressing bipolar degradation effects. Simultaneously, because the forward voltage drop of the Schottky contact is lower than that of the parasitic diode, the overall voltage drop of the device is reduced during reverse conduction, thereby achieving a reduction in reverse conduction voltage drop. Furthermore, Schottky contacts are unipolar conduction mechanisms, and there is no minority carrier storage effect during switching, nor is there a reverse recovery current. Therefore, they can avoid the additional energy loss caused by carrier removal during reverse recovery, which helps to reduce switching losses and improve the overall reliability of the device.

[0032] To achieve the above objectives, a method for fabricating a semiconductor device according to a third aspect of the present invention is provided. The method is used to fabricate the semiconductor device described in the above embodiments. The method includes: fabricating a trench along a first direction, wherein the trench penetrates a source region and a well region of a transistor structure in the semiconductor device along the first direction, and the bottom of the trench extends to a drift layer of the semiconductor device, wherein the well region is formed within the drift layer and located on the upper surface of the drift layer, and the source region is formed within the well region and located on the upper surface of the well region; and filling the trench with a Schottky contact material such that the Schottky contact material forms a Schottky contact with the drift layer.

[0033] According to the semiconductor device fabrication method of the present invention, a trench structure is formed along a first direction, penetrating the source region and the well region and extending to the drift layer. Schottky contact material is filled within the trench, forming a stable Schottky contact between the trench region and the drift layer. This creates a current path dominated by Schottky barrier conduction during reverse freewheeling operation. Because the Schottky contact has a low turn-on voltage characteristic, and the trench structure shortens the electron transport path to the Schottky contact region, the current can more quickly and preferentially establish a dominant conductive channel through this low-barrier path during reverse conduction. This suppresses the conduction of parasitic diodes that traditionally rely on the well region and drift layer, reduces hole injection and electron-hole recombination, and thus suppresses the propagation of material defects caused by recombination, achieving the goal of suppressing bipolar degradation effects. Meanwhile, the Schottky contact path formed by this fabrication method has a low barrier characteristic and the trench structure shortens the carrier transport path, which reduces the equivalent series resistance during reverse conduction and thus reduces the reverse conduction voltage drop. In addition, the Schottky contact is a unipolar conduction mechanism, and there is no minority carrier storage effect during the switching process, nor is there a reverse recovery current. Therefore, it can avoid the additional energy loss caused by carrier removal during the reverse recovery process, which helps to reduce switching losses and improve the overall reliability of the device.

[0034] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0035] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of a SiC MOSFET device in the prior art; Figure 2 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention; Figure 3This is a schematic diagram of the structure of a semiconductor device according to yet another embodiment of the present invention; Figure 4 This is a schematic diagram of the layout of the internal region of a SiC MOSFET device according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a contact hole and trench structure continuously disposed in the active region according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a contact hole and trench structure according to an embodiment of the present invention, wherein the contact hole and trench structure are intermittently arranged in the active region and the spacing of the photolithographic blocking regions in the horizontal direction is less than the length of the contact hole and trench structure in the horizontal direction. Figure 7 This is a schematic diagram of a contact hole and trench structure according to an embodiment of the present invention, wherein the contact hole and trench structure are intermittently arranged in the active region and the spacing of the photolithographic blocking regions in the horizontal direction is equal to the length of the contact hole and trench structure in the horizontal direction. Figure 8 This is a schematic diagram of a contact hole and trench structure according to an embodiment of the present invention, wherein the contact hole and trench structure are intermittently arranged in the active region and the spacing of the photolithographic blocking region in the horizontal direction is greater than the length of the contact hole and trench structure in the horizontal direction. Figure 9 This is a schematic diagram of the A1-A2 cross section in the active region according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the A3-A4 section in the active region according to an embodiment of the present invention; Figure 11 This is a schematic diagram of section A5-A6 in the active region according to an embodiment of the present invention; Figure 12 This is a schematic diagram of the A7-A8 section in the active region according to an embodiment of the present invention; Figure 13 This is a block diagram of an electronic device according to an embodiment of the present invention; Figure 14 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 15 This is a schematic diagram illustrating the formation of a drift layer according to an embodiment of the present invention; Figure 16 This is a schematic diagram illustrating the formation of the well region, source region, and JFET region according to an embodiment of the present invention; Figure 17 This is a schematic diagram of the formation of a trench according to an embodiment of the present invention; Figure 18 This is a schematic diagram illustrating the formation of a dielectric layer according to an embodiment of the present invention; Figure 19This is a schematic diagram illustrating the formation of the source metal layer and the drain metal layer according to an embodiment of the present invention; Figure 20 This is a schematic diagram of the formation of a gate layer according to an embodiment of the present invention; Figure 21 This is a schematic diagram illustrating the formation of a dielectric layer according to an embodiment of the present invention; Figure 22 This is a schematic diagram of the formation of a trench according to an embodiment of the present invention.

[0036] Figure label: Existing technology: SiC MOSFET device 200'; Substrate layer 1'; drift layer 2'; well region 3'; source region 4'; source metal layer 6'; drain metal layer 11'.

[0037] This invention: 100 electronic devices; Semiconductor device 200; Substrate layer 1; Drift layer 2; Well region 3; Source region 4; Trench 5; Source metal layer 6; JFET region 7; Gate layer 8; Insulating layer 9; Dielectric layer 10; Drain metal layer 11; First well region 31; Second well region 32; First source region 41; Second source region 42; First trench 51; Second trench 52; Active region 201; Transition region 202; Termination region 203; Gate pad 204. Detailed Implementation

[0038] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0039] In the prior art, for traditional semiconductor devices, such as SiC MOSFET devices 200', such as Figure 1 As shown, in a conventional SiC MOSFET device 200', a parasitic diode can be formed between the source region 4', the well region 3', the drift layer 2', and the substrate layer 1'. In reverse freewheeling mode, electrons travel along... Figure 1 The dashed lines in the diagram converge from the drain metal layer 11' towards the area below the well region 3' until the parasitic diode turns on, while holes move along... Figure 1 The solid line in the diagram indicates that electrons and holes are injected from the source metal layer 6' to the drift layer 2'. Recombination of electrons and holes can cause stacking faults that propagate within the drift layer 2', resulting in a bipolar degradation effect. This degrades the device's electrical performance and reduces its reliability. Furthermore, parasitic diodes also exhibit high on-state voltage drop and significant switching losses during reverse conduction, making them unsuitable for high-efficiency, high-reliability power system applications.

[0040] To address the aforementioned problems, embodiments of the present invention propose a semiconductor device that can suppress bipolar degradation effects, improve the reliability of semiconductor devices, reduce reverse conduction voltage drop, and help reduce switching losses.

[0041] In some embodiments, a semiconductor device can refer to a semiconductor device structure used to realize current control, voltage modulation, or power conversion functions. It may include an integrated system composed of a substrate layer, an epitaxial layer, and functional structural units formed thereon, used to provide a low-loss current path in the on-state and achieve high voltage blocking capability in the off-state. Semiconductor devices can be applied in the field of power electronics, such as SiC MOSFETs, IGBTs (Insulated Gate Bipolar Transistors), or other power switching devices, used in systems such as new energy vehicles, photovoltaic inverters, and motor drives to achieve high-efficiency energy control and power conversion.

[0042] In some embodiments, a semiconductor device may include one or more repeating cellular structures. A cellular structure refers to a microstructural unit that constitutes the basic functional unit of the semiconductor device, arranged periodically in the planar direction of the device. Each cellular structure can independently or semi-independently perform current regulation and electric field distribution modulation functions. Multiple cellular structures, arranged in a regular pattern, form the active region of the overall device, thereby macroscopically determining the consistency of the device's electrical performance. The role of cellular structures is to ensure consistent electrical and mechanical characteristics of the device during large-area manufacturing through standardized and repeatable structural design, thereby improving the manufacturability and consistency of the device. Simultaneously, its structural parameters directly affect key performance indicators such as on-state voltage drop, switching speed, and energy loss.

[0043] The following is for reference. Figure 2 The semiconductor device of the present invention will be described using a single cell structure as an example.

[0044] Figure 2 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention, as shown below. Figure 2 As shown, the semiconductor device 200 includes: a substrate layer 1 of a first conductivity type, a drift layer 2 of a first conductivity type, and a trench structure.

[0045] In some embodiments, substrate 1 has an upper surface.

[0046] In some embodiments, substrate 1 may be a basic support structure layer of semiconductor device 200, used to support all epitaxial layer structures above it and provide overall mechanical support, while also serving as the starting substrate for device structure growth. The conductivity type and doping characteristics of substrate 1 affect the growth conditions of subsequent epitaxial layers and the electrical characteristics of the device, and are used to determine the overall distribution of the electric field inside the device and the starting conditions of the current transport path, thereby affecting the conduction characteristics and breakdown voltage of the device.

[0047] In some embodiments, the first conductivity type can be used to represent the doping conductivity type of a corresponding region in the semiconductor device 200. It can be either an N-type or a P-type conductivity type, specifically determined by the doping impurities. By introducing corresponding impurity elements into the semiconductor material to form different conductivity types, the majority carrier type in the material is changed. For example, the N-type conductivity type is formed by doping with pentavalent elements such as phosphorus (P) and arsenic (As), which generates additional free electrons as majority carriers within the material; the P-type conductivity type is formed by doping with trivalent elements such as boron (B), which generates holes as majority carriers within the material. The setting of the first conductivity type is used to uniformly define the polarity relationship of structures such as the substrate layer 1, the drift layer 2, and the source region 4, and affects the direction of the electric field distribution and the carrier transport path within the device.

[0048] In some embodiments, the drift layer 2 may be a lightly doped epitaxial layer structure formed above the substrate layer 1, used to provide the main longitudinal current transport path in the device's on-state and to withstand the high electric field distribution formed by the applied voltage in the off-state. The drift layer 2 is a lightly doped region with the same conductivity type as the substrate layer 1. Its low doping concentration gives it high breakdown voltage capability, and the device achieves a balance between conduction loss and breakdown capability through comprehensive control of resistance and electric field distribution.

[0049] In some embodiments, such as Figure 2 As shown, the drift layer 2 is located on the upper surface of the substrate layer 1 along the first direction, and a transistor structure is formed within the drift layer 2. The transistor structure is a current-regulating structural unit formed inside the drift layer, including a well region 3 of a second conductivity type and a source region 4 of a first conductivity type. The well region 3 is formed within the drift layer 2 and located on the upper surface of the drift layer 2, and the source region 4 is formed within the well region 3 and located on the upper surface of the well region 3.

[0050] In some embodiments, the second conductivity type can refer to a conductivity type opposite to the first conductivity type, used to form a doped structure with opposite polarity to the semiconductor region of the first conductivity type. For example, when the first conductivity type is N-type, the second conductivity type can be P-type; when the first conductivity type is P-type, the second conductivity type can be N-type. By setting a second conductivity type opposite to the first conductivity type, a PN junction structure can be formed inside the device to achieve functions such as channel control and electric field regulation, thereby meeting the operating requirements of the transistor structure.

[0051] In some embodiments, the well region 3 serves to form the channel control region in the transistor structure and to regulate the electric field distribution near the device surface. Together with the source region 4 and the drift layer 2, it constitutes the basic carrier control structure. The well region 3 employs a different conductivity type than the source region 4 and the drift layer 2, primarily to form a PN junction between adjacent regions to achieve current control, voltage withstand capability, and device turn-off functionality. If the well region 3, source region 4, and drift layer 2 used the same conductivity type, it would be difficult to form an effective controlled transistor structure, and it would also be detrimental to achieving stable switching operation of the device.

[0052] In some embodiments, source region 4 is a highly doped region formed within well region 3 and located on the upper surface of well region 3. Its conductivity type is the same as the first conductivity type, and it is used as the main carrier injection region when the device is turned on. By increasing the doping concentration of source region 4, the contact resistance and series resistance of this region can be reduced, thereby improving the current carrying capacity and enhancing the device's conduction performance.

[0053] In some embodiments, the trench structure includes a trench 5 extending along a first direction and penetrating the source region 4 and the well region 3, the bottom of the trench 5 extending to the drift layer 2, and the trench 5 being filled with a Schottky contact material to form a Schottky contact with the drift layer 2.

[0054] In some embodiments, the trench structure may refer to a groove-like structure formed inside the semiconductor device 200 and extending along a first direction. The trench structure serves to adjust the current transmission path and electric field distribution state inside the device, while providing a longitudinal electrical connection interface between the drift layer 2 and the upper region, enabling the device to form a conduction channel that differs from a conventional planar structure, thereby improving reverse conduction performance, reducing losses, and enhancing device reliability.

[0055] In some embodiments, when the trench 5 penetrates the source region 4 and the well region 3 and extends to the drift layer 2, and the trench is filled with a conductive material, the filling material can simultaneously form a low-resistance electrical connection path with the source region 4, the well region 3, and the drift layer 2. Because the conductive material has low internal resistance, the potential difference between the contact areas tends to decrease in the conductive state. Therefore, the source region 4, the well region 3, and the local area of ​​the drift layer in contact with the trench 5 can be approximately at the same potential. This isopotential relationship helps suppress abnormal electric field concentration in local areas and improves the uniformity of the current distribution inside the device.

[0056] In some embodiments, by forming a low-resistance connection between the source region 4, the well region 3, and a local area of ​​the drift layer, the trench region can also become a preferred conductive path, thereby improving the conductivity of the device under specific operating conditions.

[0057] In some embodiments, the trench 5 is filled with a Schottky contact material to form a Schottky contact with the drift layer 2. This is because the work function difference, band structure, and interface barrier characteristics between the Schottky contact material and the drift layer semiconductor material satisfy the conditions for forming a Schottky contact. That is, when the Schottky contact material is in direct contact with the drift layer 2, a barrier interface with rectifying characteristics can be formed at the contact interface, thereby constituting a Schottky contact. Therefore, since the bottom of the trench extends to the drift layer 2, the Schottky contact material can directly contact the surface of the drift layer, thus providing a structural basis for forming a Schottky contact.

[0058] In some embodiments, trench 5, drift layer 2, and substrate layer 1 can constitute a Schottky diode. In reverse freewheeling mode, an electron channel can be formed, allowing current to preferentially pass through the Schottky diode, bypassing the body diode formed by the trap and drift layer 2. This fundamentally eliminates the bipolar degradation triggering condition and suppresses the bipolar degradation effect. Furthermore, the Schottky diode has a lower turn-on voltage than the body diode, reducing losses during reverse conduction.

[0059] In some embodiments, the Schottky contact material within the trench 5 forms a Schottky contact with the drift layer 2, and can combine with the drift layer 2 and the substrate layer 1 to form a reverse freewheeling current path. In reverse freewheeling mode, current can preferentially be transmitted through this Schottky conduction path, thereby reducing dependence on the parasitic body diode conduction path dominated by the well region 3 and the drift layer PN junction, thus effectively suppressing the bipolar degradation effect. Simultaneously, since the Schottky diode has a lower turn-on voltage than the body diode, the on-state voltage drop and energy loss during reverse conduction can be reduced.

[0060] According to an embodiment of the semiconductor device 200 of the present invention, a Schottky contact material is filled in a trench structure extending along a first direction and penetrating the source region 4 and the well region 3 and extending to the drift layer 2, thereby forming a Schottky contact between the trench region and the drift layer 2. This constructs a current path dominated by Schottky barrier conduction during reverse freewheeling operation. Since the Schottky contact has a low turn-on voltage characteristic, and the trench structure shortens the electron transport path to the Schottky contact region, the current can more quickly and preferentially establish a dominant conductive channel through this low-barrier path during reverse conduction. This suppresses the conduction of parasitic diodes that traditionally rely on the well region 3 and the drift layer 2, reduces hole injection and electron-hole recombination processes, thereby suppressing the propagation of material defects caused by recombination and achieving the goal of suppressing bipolar degradation effects. Simultaneously, since the conduction voltage drop of the Schottky contact is lower than that of the parasitic diode, the overall voltage drop of the device is reduced during reverse conduction, thereby achieving a reduction in reverse conduction voltage drop. Furthermore, Schottky contacts are unipolar conduction mechanisms, and there is no minority carrier storage effect during switching, nor is there a reverse recovery current. Therefore, they can avoid the additional energy loss caused by carrier removal during reverse recovery, which helps to reduce switching losses and improve the overall reliability of the device.

[0061] In some embodiments, the Schottky contact material includes a semiconductor material or a metal material that forms a heterojunction Schottky contact with the drift layer 2.

[0062] In some embodiments, a heterojunction Schottky contact can refer to a barrier structure with rectifying characteristics formed at the interface by direct contact between two materials with different properties. The two materials involved in the contact have different band structures, work functions, electron affinity potentials, or carrier transport characteristics, thus generating a barrier height and a built-in electric field at the interface. This causes the carriers to exhibit different conduction characteristics under forward and reverse bias conditions, resulting in rectification behavior similar to a Schottky diode. During forward conduction, the Schottky diode is in a reverse bias state, not affecting the normal current path of the semiconductor device 200. Compared to homogeneous semiconductor contact structures, heterojunction Schottky contacts allow for adjustment of the interface barrier height, interface resistance, and carrier injection efficiency through material combination design to meet the conduction and voltage withstand performance requirements of different devices.

[0063] In some embodiments, the heterojunction Schottky contact serves to provide an additional unipolar conductive path for the semiconductor device 200, enabling carrier transport to preferentially occur through this interface under reverse freewheeling or specific bias conditions, thereby reducing dependence on the parasitic diode conduction path. Because this type of contact has a lower turn-on voltage and a faster carrier response speed, it helps to reduce reverse conduction voltage drop, decrease switching losses, and improve the overall reliability of the device.

[0064] In some embodiments, the Schottky contact material is a semiconductor material. This semiconductor material can be a conductive semiconductor material capable of filling the trench 5 and forming a heterojunction Schottky contact with the drift layer 2. It needs to possess both good conductivity and stable interface barrier characteristics with the drift layer material. When selecting a semiconductor material, factors such as thermal expansion coefficient matching, interface defect density, long-term high-temperature stability, and subsequent process compatibility can also be considered. For example, when the semiconductor device 200 is used in high-temperature, high-pressure, or high-frequency scenarios, a semiconductor material with good interface stability under thermal cycling conditions can be preferentially selected to improve the long-term reliability of the device.

[0065] In some embodiments, the top of the trench 5 is flush with the upper surface of the drift layer 2, and the trench 5 is filled with semiconductor material. Since the trench 5 is completely occupied by the semiconductor material, the region forms a through-conductive path electrically, thereby providing a low-resistance transport channel for charge carriers during device operation and preferentially participating in current transport in the reverse conduction state. This helps to suppress the conduction path of the parasitic diode formed between the well region 3 and the drift layer 2, thereby suppressing the bipolar degradation effect.

[0066] In some embodiments, the drift layer 2 is a silicon carbide layer, and the semiconductor material is polycrystalline silicon.

[0067] In some embodiments, the drift layer 2 being a silicon carbide layer can refer to the drift layer 2 being an epitaxial layer structure formed from silicon carbide (SiC) semiconductor material. Because silicon carbide material has a high breakdown electric field, a wide bandgap, and high thermal conductivity, it can maintain good electrical performance under high voltage, high temperature, and high frequency operating conditions. Therefore, setting the drift layer 2 as a silicon carbide layer can be used to achieve the electric field support capability of the device in high-voltage application scenarios and improve the overall device's withstand voltage performance and thermal stability, thus making it suitable for high power density power electronic systems.

[0068] In some embodiments, polycrystalline silicon can refer to a silicon material composed of a large number of randomly oriented micrograins, which differs structurally from monocrystalline silicon, possesses grain boundary structure characteristics, and can be formed through processes such as chemical vapor deposition. Polycrystalline silicon can be doped as needed to form a conductive polycrystalline silicon layer with specific conductivity properties. In this invention, when polycrystalline silicon is used as a Schottky contact material to fill the trench, it can form a heterojunction Schottky contact interface with the silicon carbide drift layer 2, thereby providing a low-barrier conductive channel during reverse conduction of the device. Due to the band structure difference between polycrystalline silicon and silicon carbide, this structure helps to form a Schottky barrier, thus constituting a unipolar conduction channel with a low turn-on voltage.

[0069] In some embodiments, polysilicon has good process compatibility and trench filling capability, which enables it to maintain structural stability under high temperature process conditions. At the same time, its conductivity can be further optimized by doping control, thereby improving the current transport capability and structural reliability of the trench region while ensuring the formation of the Schottky barrier.

[0070] In some embodiments, when the Schottky contact material is polycrystalline silicon, the polycrystalline silicon can be N-type doped polycrystalline silicon, and its doping concentration can be set to 1E15 atom / cm3~1E17 atom / cm3. Here, atom / cm3 refers to atoms per cubic centimeter. By controlling the doping concentration within the above range, the polycrystalline silicon can maintain good conductivity while forming suitable interface barrier characteristics with the drift layer 2, thereby facilitating the formation of a stable Schottky contact and balancing reverse conductivity, device loss, and long-term operational reliability.

[0071] In some embodiments, in addition to semiconductor materials, the Schottky contact material can also be a metallic material. Using a metallic material as the Schottky contact material within the trench 5 allows the metal-semiconductor barrier interface formed between the metal and the drift layer semiconductor material to construct the Schottky contact. Compared to semiconductor filling materials, metallic materials have lower bulk resistivity and better carrier transport capabilities, thus helping to reduce the series resistance in the trench region and improve current transport efficiency. In the reverse freewheeling state of the device, the Schottky channel formed by the metal can preferentially conduct at a lower turn-on voltage, thereby reducing the reverse conduction voltage drop and minimizing switching losses caused by minority carrier storage effects. Furthermore, metallic materials have mature deposition, via filling, and interconnection processes, which is also beneficial for device manufacturing and mass production.

[0072] In some embodiments, the metallic material includes a titanium / titanium nitride alloy and a tungsten plug. The titanium layer can serve as the interface metal in contact with the drift layer 2, improving the contact characteristics between the metal and the semiconductor and contributing to the formation of a stable Schottky barrier. The titanium nitride layer can serve as a barrier layer or adhesion layer, suppressing metal diffusion, improving interface stability, and enhancing the adhesion of subsequent metal deposition. The titanium / titanium nitride composite structure balances contact performance, thermal stability, and process reliability, making it suitable as a functional metal layer at the bottom of the trench.

[0073] In some embodiments, the tungsten plug can be a conductive metal columnar structure filled inside the trench, primarily serving to provide a low-resistance vertical conductive path and effectively fill the trench cavity. Due to tungsten's low resistivity, high melting point, and good electromigration reliability, the tungsten plug helps improve the carrier transport capability of the trench region and ensures the long-term stability of the device under high-temperature, high-current operating conditions. Furthermore, tungsten material has mature contact hole filling processes in semiconductor manufacturing, making it suitable for processing high aspect ratio structures.

[0074] In some embodiments, such as Figure 3 As shown, when the Schottky contact material is a metallic material, the top of the trench 5 is flush with the upper surface of the drift layer 2, and the metallic material fills the bottom of the trench 5.

[0075] In summary, regardless of whether the Schottky contact material is a semiconductor or a metal, the trench 5 needs to penetrate the source region 4 and the well region 3 and extend into the drift layer 2, allowing the Schottky contact material within the trench 5 to directly contact the semiconductor material in the drift layer. Only when the Schottky contact material forms a direct interface with the drift layer 2 can the basic conditions for forming a Schottky diode structure be met. If the trench 5 is insufficient in depth and only extends into the source region 4 or the well region 3, the Schottky contact material cannot contact the drift layer 2, making it difficult to form the expected Schottky conduction path.

[0076] In some embodiments, such as Figure 2 and Figure 3 As shown, the semiconductor device 200 also includes a source metal layer 6. The source metal layer 6 can be a conductive metal layer formed on the upper surface of the device, serving as the source electrode structure of the semiconductor device 200 to achieve electrical connection between external circuitry and the internal source region and related conductive structures. The source metal layer 6 can perform functions such as current collection, external lead connection, and reducing the surface wiring resistance of the device, thereby improving the device's conductivity and package connection reliability.

[0077] In some embodiments, the source metal layer 6 can be formed using a single-layer metal structure or a multi-layer composite metal structure. Its materials may include, but are not limited to: aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), tungsten (W), titanium alloys, aluminum-silicon alloys, aluminum-copper alloys, or other metallic materials with good electrical conductivity, adhesion properties, and process compatibility. Specific material selection can be adjusted based on electrical conductivity, thermal stability, process compatibility, and cost requirements.

[0078] In some embodiments, the source metal layer 6 is located above the drift layer 2 along a first direction, and the source metal layer 6 is connected to the Schottky contact material in the trench 5 through contact holes.

[0079] In some embodiments, contact holes can be formed through processes such as photolithography, etching, deposition, and filling. When the contact holes are filled with conductive material, a vertical interconnect structure can be formed, thereby reducing the contact resistance between the upper metal layer and the lower structure and improving the overall conductivity of the device.

[0080] In some embodiments, such as Figure 2 and Figure 3As shown, the well region 3 includes a first well region 31 and a second well region 32. The first well region 31 and the second well region 32 are spaced apart along a second direction, which is perpendicular to the first direction.

[0081] In some embodiments, such as Figure 2 and Figure 3 As shown, source region 4 includes a first source region 41 and a second source region 42. The first source region 41 is formed within the first well region 31 and located on the upper surface of the first well region 31, and the second source region 42 is formed within the second well region 32 and located on the upper surface of the second well region 32. The first source region 41 and the second source region 42 can be arranged symmetrically from left to right, so that when the semiconductor device 200 is turned on, charge carriers can be injected simultaneously from multiple source regions, thereby improving the overall conduction capability and improving the uniformity of current distribution.

[0082] In some embodiments, such as Figure 2 and Figure 3 As shown, the transistor structure also includes a JFET region 7, which is located between the first well region 31 and the second well region 32 along the second direction. The JFET region 7 can be a first conductivity type semiconductor region located between the first well region 31 and the second well region 32, structurally connected to the drift layer 2, and situated in a narrow channel formed between adjacent well regions. This region is called JFET region 7 because its conductivity characteristics are similar to the pinch-off channel characteristics of a junction field-effect transistor (JFET), meaning that the PN junction depletion layer formed by adjacent well regions modulates the effective conductivity width of this region.

[0083] In some embodiments, the main function of the JFET region 7 is to provide a lateral current transition path from the source region 4 to the drift layer 2 in the on-state of the device, allowing charge carriers to be transported through the region located between the first well region 31 and the second well region 32 before entering the drift layer 2. Since this region is located at a critical position in the main current path, the width, doping concentration, and resistance characteristics of the JFET region 7 will have a significant impact on the overall on-resistance of the device.

[0084] In some embodiments, the doping concentration of JFET region 7 can be higher than that of drift layer 2. Specifically, when the semiconductor device 200 is operating, the PN junction formed by well region 3 and JFET region 7 will generate a depletion layer under reverse bias conditions, which will extend into JFET region 7, thereby compressing the effective conductive channel and increasing resistance. Since the depletion layer mainly extends towards the side with lower doping concentration, by increasing the doping concentration of JFET region 7, the extent of depletion layer extension in JFET region 7 can be reduced, thereby maintaining a larger conductive cross-sectional area, reducing the resistance of JFET region, and thus reducing the overall on-resistance of the device.

[0085] In some embodiments, such as Figure 2 and Figure 3As shown, the trench structure includes a first trench 51 and a second trench 52. The first trench 51 penetrates the first source region 41 and the first well region 31 along a first direction, and the second trench 52 penetrates the second source region 42 and the second well region 32 along the first direction.

[0086] In some embodiments, both the first trench 51 and the second trench 52 are filled with Schottky contact material to form Schottky contacts with the drift layer 2, respectively. Compared to a structure with only a single trench, the dual-trench structure can increase the total Schottky contact area, reduce the current density per unit area, thereby reducing local current congestion and helping to reduce contact resistance and reverse conduction voltage drop. Simultaneously, multiple Schottky conduction paths can share the current, making the carrier distribution inside the device more uniform, reducing local heat accumulation, and improving operational stability and reliability.

[0087] In some embodiments, the first trench 51 and the second trench 52 are respectively positioned to correspond to the first source region 41, the first well region 31, the second source region 42, and the second well region 32, and can be arranged symmetrically in the second direction. This symmetrical arrangement helps to balance the electric field distribution inside the cell structure, reduce the electric field concentration problem that may be generated by a unilateral structure, thereby improving the device's breakdown voltage stability and improving the current consistency during dynamic switching.

[0088] In some embodiments, after the first trench 51 and the second trench 52 both extend to the drift layer 2 and form a Schottky contact, the current can be preferentially transmitted through the Schottky paths on both sides during reverse conduction, reducing the dependence on the conduction path of the parasitic body diode formed by the well region 3 and the drift layer 2, thereby reducing minority carrier injection, helping to suppress bipolar degradation effect, and further improving the long-term reliability of the semiconductor device 200.

[0089] In some embodiments, such as Figure 2 and Figure 3 As shown, the semiconductor device 200 also includes a gate layer 8 and an insulating layer 9.

[0090] The gate layer 8 can be used to receive external gate drive signals and control the on and off states of the channel region through the action of an electric field. The gate layer 8 can be made of polysilicon, which has good process compatibility, allowing for the formation of fine gate structures through deposition, doping, and patterning processes, and can withstand subsequent high-temperature processes. Therefore, it is widely used as the gate electrode in power semiconductor devices. Besides polysilicon, the gate layer 8 can also be formed using metal materials or metal-semiconductor composite materials, such as tungsten, titanium nitride, aluminum, copper, or combinations thereof, depending on the gate resistance, process platform, and reliability requirements.

[0091] In some embodiments, the gate layer 8 is located between the upper surface of the drift layer 2 and the source metal layer 6 along a first direction, and the gate layer 8 covers the JFET region 7, part of the source region and part of the well region located between the first trench 51 and the second trench 52.

[0092] In some embodiments, the insulating layer 9 is located between the gate layer 8 and the upper surface of the drift layer 2. The main function of the insulating layer 9 is to prevent the gate layer 8 from directly conducting with the underlying semiconductor region, thus avoiding gate leakage current, while allowing the gate voltage to act on the underlying semiconductor region in an electric field coupling manner.

[0093] In some embodiments, the insulating layer 9 can be made of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4), or other high dielectric constant insulating materials. In actual processes, the thickness and material selection of the insulating layer 9 also affect the balance between gate control capability and reliability, and therefore can be adjusted according to specific application scenarios.

[0094] In summary, the gate layer 8 and the insulating layer 9 work together to form a MOS-like gate control structure. The gate layer 8 is responsible for providing control signals, while the insulating layer 9 is responsible for electrical isolation and electric field transmission. Together, they achieve precise control of the conduction current of the semiconductor device 200, thereby meeting the requirements of low drive power consumption, high switching speed, and stable and reliable operation.

[0095] In some embodiments, such as Figure 2 and Figure 3 As shown, the semiconductor device 200 also includes a dielectric layer 10. The dielectric layer 10 may be an insulating thin film layer for electrical and structural isolation, which is disposed between the source metal layer 6 and the upper surface of the gate layer 8 and the drift layer 2, thereby forming an effective electrical isolation structure between the source metal layer 6 and the gate layer 8 to avoid direct electrical connection or leakage current between different potential regions.

[0096] In some embodiments, the material of the dielectric layer 10 can be a common semiconductor dielectric material, such as silicon dioxide, silicon nitride, or other dielectric materials with insulating properties. Alternatively, a multilayer composite dielectric structure can be adopted according to process requirements to meet different voltage levels and reliability requirements.

[0097] In some embodiments, the substrate layer 1 has a lower surface opposite to the upper surface in a first direction.

[0098] In some embodiments, the semiconductor device 200 further includes a drain metal layer 11, which is located on the lower surface of the substrate layer 1 along a first direction.

[0099] In some embodiments, the drain metal layer 11 serves as the current output terminal of the semiconductor device 200 and forms an electrical connection with the internal substrate layer 1, thereby realizing a current transmission path between the external circuit and the internal conductive structure of the device.

[0100] In some embodiments, the drain metal layer 11 may be formed of a metal material with good conductivity and process compatibility, such as aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti) or a multilayer composite metal structure thereof.

[0101] In some embodiments, when the semiconductor device 200 is a SiC MOSFET device, such as Figure 4 As shown, a SiC MOSFET device may include an active region 201, a transition region 202 between the active region 201 and the terminal region 203, a terminal region 203, and a gate pad 204.

[0102] In some embodiments, the active region 201 is the core functional region in the SiC MOSFET device that truly participates in current conduction and switching. It consists of a large number of repeating cell structures, each containing a well region 3, a source region 4, a gate channel, a JFET region 7, and a drift layer 2. Electrically, all major conduction currents (power currents from the source to the drain) are carried out through the active region 201, thus directly determining the device's key performance indicators, such as on-resistance Rds(on), current carrying capacity, switching losses, and reliability. In this invention, the active region 201 plays a particularly crucial role because the "trench structure" and the "reverse freewheeling path for replacing the body diode" are both arranged within the structure of the active region 201. Essentially, this reconstructs the reverse current path within the active region 201, thereby avoiding the bipolar degradation problem caused by the conduction of a traditional body diode.

[0103] In some embodiments, the transition region 202 between the active region 201 and the terminal region 203 is a "structural gradient region" located in the middle of the device. Its existence is to smoothly connect the high-current-density active region 201 and the high-electric-field-controlled terminal region 203 electrically and structurally. Since the active region 201 is responsible for current conduction, while the terminal region 203 is responsible for electric field passivation and edge withstand voltage control, their functions differ significantly. Direct connection between them would lead to abrupt changes in the electric field or uneven carrier distribution, resulting in localized breakdown or decreased reliability. Therefore, the transition region 202 gradually changes the doping concentration, cell density, or terminal structure parameters to ensure a smooth spatial transition of current and electric field.

[0104] In some embodiments, a gate bus may be arranged in the transition region 202, the gate bus being disposed around the active region 201 and connected to the gate pad 204, for distributing gate drive signals to the gate layer 8 of each cell structure.

[0105] In some embodiments, the termination region 203 is a structural region at the edge of the SiC MOSFET device specifically designed for electric field modulation and prevention of edge breakdown, enabling the device to operate stably at high voltages without localized electric field concentration breakdown. The termination region 203 includes structures such as junction termination extension (JTE), field plate, and guard ring. These designs work together to "flatten" the electric field distribution, transferring the maximum electric field from the edge to the internal drift layer 2, thereby improving the breakdown voltage.

[0106] In some embodiments, the gate pad 204 can refer to a metal lead for connecting the gate to external circuitry, serving as the input interface for device control signals. Its function is to introduce external driving voltage into the device, controlling the on and off of the MOS channel through the gate layer 8 and the insulating layer 9.

[0107] In some embodiments, the contact holes and trench structures in the active region 201 can be implemented in different ways, either continuously or intermittently, according to device design requirements. Specifically, Figure 5 The structure of contact holes and trenches being continuously arranged in the active region is shown. Figure 6 The structure of contact holes and trenches is shown to be intermittently arranged in the active region, and the spacing of the photolithographic blocking regions in the horizontal direction is less than the length of the contact holes and trenches in the horizontal direction. Figure 7 The structure of contact holes and trenches is shown to be discontinuously arranged in the active region, and the spacing of the photolithographic blocking regions in the horizontal direction is equal to the length of the contact holes and trenches in the horizontal direction. Figure 8 The diagram illustrates a structure in which contact holes and trenches are intermittently arranged within the active region, and where the spacing of the photolithographic blocking regions in the horizontal direction is greater than the length of the contact holes and trenches in the horizontal direction.

[0108] In some embodiments, while ensuring that the source region 4 and the well region 3 are short-circuited to achieve equipotential, different structural arrangements can be selected according to actual application requirements to adjust the conduction characteristics of the Schottky diode. Specifically, as the length of the contact hole and trench structure increases, the effective area of ​​the Schottky contact conduction region increases, resulting in a decrease in the equivalent current density during reverse conduction, thereby reducing the equivalent on-state voltage drop. Simultaneously, due to the increased area occupied by the trench structure in the active region, the effective distribution density of the MOS channel region decreases accordingly.

[0109] In some embodiments, Figures 9 to 12 Different active region cross-sectional structures are shown, using Schottky contact materials as the semiconductor material as an example. Among them, Figure 9 This is a schematic diagram of the A1-A2 section in the active region; Figure 10 This is a schematic diagram of the A3-A4 section in the active region; Figure 11 This is a schematic diagram of the A5-A6 section in the active region; Figure 12 This is a schematic diagram of the A7-A8 section in the active region.

[0110] The following is for reference. Figure 13 An electronic device according to an embodiment of the present invention is described.

[0111] Figure 13 This is a block diagram of an electronic device according to an embodiment of the present invention, such as... Figure 13 As shown, the electronic device 100 of this embodiment includes at least one semiconductor device 200 as described in the above embodiment.

[0112] In some embodiments, the electronic device 100 may include, but is not limited to, a new energy vehicle electric drive system, an on-board power supply system, a charging system, a photovoltaic inverter system, an energy storage converter system, a motor drive control system, and industrial power supply equipment.

[0113] The electronic device 100 according to an embodiment of the present invention employs the semiconductor device 200 described in the above embodiment. By filling a trench structure extending along a first direction and penetrating the source region 4 and the well region 3 to the drift layer 2 with Schottky contact material, a Schottky contact is formed between the trench region and the drift layer 2. This creates a current path dominated by Schottky barrier conduction during reverse freewheeling operation. Because the Schottky contact has a low turn-on voltage characteristic, and the trench structure shortens the electron transport path to the Schottky contact region, the current can more quickly and preferentially establish a dominant conductive channel through this low-barrier path during reverse conduction. This suppresses the conduction of parasitic diodes that traditionally rely on the well region 3 and the drift layer 2, reduces hole injection and electron-hole recombination processes, thereby suppressing the propagation of material defects caused by recombination and achieving the goal of suppressing bipolar degradation effects. Simultaneously, because the conduction voltage drop of the Schottky contact is lower than that of the parasitic diode, the overall voltage drop of the device is reduced during reverse conduction, thus achieving a reduction in reverse conduction voltage drop. Furthermore, Schottky contacts are unipolar conduction mechanisms, and there is no minority carrier storage effect during switching, nor is there a reverse recovery current. Therefore, they can avoid the additional energy loss caused by carrier removal during reverse recovery, which helps to reduce switching losses and improve the overall reliability of the device.

[0114] The following is for reference. Figure 14 A method for fabricating a semiconductor device according to an embodiment of the present invention is described. This method is used to fabricate the semiconductor device described in the above embodiment.

[0115] Figure 14 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention, such as... Figure 14 As shown, the method for fabricating a semiconductor device includes at least the following steps: S1, a trench is prepared along a first direction, wherein the trench penetrates the source region and the well region of the transistor structure in the semiconductor device along the first direction, and the bottom of the trench extends to the drift layer of the semiconductor device, wherein the well region is formed in the drift layer and located on the upper surface of the drift layer, and the source region is formed in the well region and located on the upper surface of the well region.

[0116] S2, fill the trench with Schottky contact material so that the Schottky contact material forms a Schottky contact with the drift layer.

[0117] According to the semiconductor device fabrication method of the present invention, a trench structure is formed along a first direction, penetrating the source region and the well region and extending to the drift layer. Schottky contact material is filled within the trench, forming a stable Schottky contact between the trench region and the drift layer. This creates a current path dominated by Schottky barrier conduction during reverse freewheeling operation. Because the Schottky contact has a low turn-on voltage characteristic, and the trench structure shortens the electron transport path to the Schottky contact region, the current can more quickly and preferentially establish a dominant conductive channel through this low-barrier path during reverse conduction. This suppresses the conduction of parasitic diodes that traditionally rely on the well region and drift layer, reduces hole injection and electron-hole recombination, and thus suppresses the propagation of material defects caused by recombination, achieving the goal of suppressing bipolar degradation effects. Meanwhile, the Schottky contact path formed by this fabrication method has a low barrier characteristic and the trench structure shortens the carrier transport path, which reduces the equivalent series resistance during reverse conduction and thus reduces the reverse conduction voltage drop. In addition, the Schottky contact is a unipolar conduction mechanism, and there is no minority carrier storage effect during the switching process, nor is there a reverse recovery current. Therefore, it can avoid the additional energy loss caused by carrier removal during the reverse recovery process, which helps to reduce switching losses and improve the overall reliability of the device.

[0118] In some embodiments, as Figure 2 Taking the semiconductor device 200 shown as an example, the overall fabrication process of the semiconductor device 200 according to an embodiment of the present invention is described below. The overall fabrication process of the semiconductor device 200 may include the following steps: First, an epitaxial growth process is used to form a drift layer 2 of the first conductivity type on the substrate layer 1, and the resulting structure is as follows. Figure 15 As shown.

[0119] Second, in Figure 15Based on the structure shown, a second conductivity type well region 3 is formed within the drift layer 2 using photomask lithography and ion implantation. Using a self-aligned process, after growing the spacer (sidewall) and photomask lithography, first conductivity type dopant is implanted onto the surface of the well region to form a first conductivity type source region 4. Further, using photomask lithography and ion implantation, a first conductivity type JFET region 7 is formed between adjacent well regions, resulting in the structure shown. Figure 16 As shown.

[0120] Third, in Figure 16 Based on the structure shown, a trench 5 extending along the first direction and penetrating the source region 4 and the well region 3, and extending to the drift layer 2 at the bottom, is formed by photolithography and etching processes. The resulting structure is as follows. Figure 17 As shown.

[0121] Fourth, in Figure 17 Based on the structure shown, an insulating layer 9 is grown on the device surface; subsequently, in-situ doped polysilicon is deposited to form a gate layer 8; the doping concentration is adjusted, and polysilicon is filled into the trench 5 to form a trench structure in contact with the drift layer 2, resulting in the structure shown. Figure 18 As shown.

[0122] Fifth, in Figure 18 Based on the structure shown, a dielectric layer 10 is deposited, and contact holes are formed through photolithography and etching processes, resulting in the structure shown below. Figure 19 As shown.

[0123] Sixth, in Figure 19 Based on the structure, source metal is sputtered, and a source metal layer 6 is formed by photolithography etching. A passivation layer is then deposited, followed by photolithography etching of the passivation layer. Finally, a drain metal layer 11 is deposited, forming a structure as shown below. Figure 2 The semiconductor device 200 shown.

[0124] In some embodiments, as Figure 3 Taking the semiconductor device 200 shown as an example, the overall fabrication process of the semiconductor device 200 according to an embodiment of the present invention is described below. The overall fabrication process of the semiconductor device 200 may include the following steps: First, an epitaxial growth process is used to form a drift layer 2 of the first conductivity type on the substrate layer 1, and the resulting structure is as follows. Figure 15 As shown.

[0125] Second, in Figure 15Based on the structure shown, a second conductivity type well region 3 is formed within the drift layer 2 using photomask lithography and ion implantation. Using a self-aligned process, after growing the spacer (sidewall) and photomask lithography, first conductivity type dopant is implanted onto the surface of the well region 3 to form a first conductivity type source region 4. Further, using photomask lithography and ion implantation, a first conductivity type JFET region 7 is formed between adjacent well regions, resulting in the structure shown. Figure 16 As shown.

[0126] Third, in Figure 16 Based on the structure shown, an insulating layer 9 is grown on the device surface; subsequently, in-situ doped polysilicon is deposited to form a gate layer 8, resulting in the structure shown. Figure 20 As shown.

[0127] Fourth, in Figure 20 Based on the structure shown, a dielectric layer 10 is deposited, resulting in the structure shown below. Figure 21 As shown.

[0128] Fifth, in Figure 21 Based on the structure shown, contact holes and trenches 5 are formed through photolithography and etching, resulting in the structure shown below. Figure 22 As shown.

[0129] Sixth, in Figure 22 Based on the structure shown, titanium / titanium nitride alloy and tungsten plugs are sequentially filled in, source metal is sputtered, and source metal layer 6 is formed by photolithography etching. A passivation layer is then deposited, followed by photolithography etching of the passivation layer. Finally, drain metal layer 11 is deposited, forming the structure shown. Figure 3 The semiconductor device 200 shown.

[0130] In summary, through the above-mentioned processes such as ion implantation, etching, deposition, and filling, semiconductor devices 200 with trench structures filled with semiconductor materials or trench structures filled with metal materials can be formed to meet the device performance requirements of different application scenarios.

[0131] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0132] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, include: A substrate of a first conductivity type, the substrate having an upper surface; A drift layer of a first conductivity type is located on the upper surface of the substrate layer along a first direction. A transistor structure is formed in the drift layer. The transistor structure includes a well region of a second conductivity type and a source region of the first conductivity type. The well region is formed in the drift layer and located on the upper surface of the drift layer. The source region is formed in the well region and located on the upper surface of the well region. A trench structure comprising a trench extending along a first direction and penetrating the source region and the well region, the bottom of the trench extending to the drift layer, the trench being filled with a Schottky contact material to form a Schottky contact with the drift layer.

2. The semiconductor device according to claim 1, characterized in that, The Schottky contact material includes a semiconductor material or a metal material that forms a heterojunction Schottky contact with the drift layer.

3. The semiconductor device according to claim 2, characterized in that, The Schottky contact material is the semiconductor material; The top of the trench is flush with the upper surface of the drift layer, and the semiconductor material fills the trench.

4. The semiconductor device according to claim 3, characterized in that, The drift layer is a silicon carbide layer, and the semiconductor material is polycrystalline silicon.

5. The semiconductor device according to claim 2, characterized in that, The Schottky contact material is the aforementioned metallic material; The top of the trench is flush with the upper surface of the drift layer, and the metal material fills the bottom of the trench.

6. The semiconductor device according to claim 5, characterized in that, The metallic materials include titanium / titanium nitride alloy and tungsten plugs.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A source metal layer is located above the drift layer along the first direction, and the source metal layer is connected to the Schottky contact material in the trench through a contact hole.

8. The semiconductor device according to any one of claims 7, characterized in that, The well region includes a first well region and a second well region, the first well region and the second well region are spaced apart along a second direction, the second direction being perpendicular to the first direction; The source region includes a first source region and a second source region. The first source region is formed in the first well region and located on the upper surface of the first well region, and the second source region is formed in the second well region and located on the upper surface of the second well region. The transistor structure further includes a JFET region located between the first well region and the second well region along the second direction.

9. The semiconductor device according to claim 8, characterized in that, The trench structure includes: A first trench, the first trench penetrating the first source region and the first well region along the first direction; The second trench penetrates the second source region and the second well region along the first direction; Both the first trench and the second trench are filled with the Schottky contact material to form Schottky contacts with the drift layer, respectively.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor device further includes: A gate layer is located along the first direction between the upper surface of the drift layer and the source metal layer, and the gate layer covers the JFET region, a portion of the source region, and a portion of the well region located between the first trench and the second trench; An insulating layer is located between the upper surfaces of the gate layer and the drift layer.

11. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: A dielectric layer is located between the source metal layer and the upper surfaces of the gate layer and the drift layer.

12. The semiconductor device according to any one of claims 1-11, characterized in that, The substrate layer has a lower surface opposite to the upper surface in the first direction; The semiconductor device further includes a drain metal layer located on the lower surface of the substrate along the first direction.

13. An electronic device, characterized in that, The electronic device includes at least one semiconductor device as described in any one of claims 1-12.

14. A method for fabricating a semiconductor device, characterized in that, The preparation method is used to prepare the semiconductor device according to any one of claims 1-12, and the preparation method includes: A trench is prepared along a first direction, wherein the trench penetrates the source region and the well region of the transistor structure in the semiconductor device along the first direction, and the bottom of the trench extends to the drift layer of the semiconductor device, wherein the well region is formed in the drift layer and located on the upper surface of the drift layer, and the source region is formed in the well region and located on the upper surface of the well region; The trench is filled with Schottky contact material so that the Schottky contact material forms a Schottky contact with the drift layer.

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