Method for improving metal gate fill quality

Abstract

The application provides a metal gate filling quality improvement method, which comprises the following steps: step 1: providing a substrate, wherein a gate trench is formed on the substrate, and the gate trench is obtained after removing a dummy gate layer in a gate-last process; step 2: sequentially depositing a barrier layer and a work function adjusting layer on the substrate and the sidewall and bottom of the gate trench; step 3: depositing a first TiN layer on the work function adjusting layer; step 4: filling an amorphous silicon layer into the gate trench until the gate trench is filled, and an amorphous silicon layer is formed on the surface of the substrate at the same time; after the filling is completed, the amorphous silicon layer on the surface of the substrate is removed completely through a chemical mechanical polishing process; step 5: removing the amorphous silicon layer in the gate trench; and step 6: filling a metal gate into the gate trench.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and particularly relates to a method for improving the filling quality of metal gates. Background Technology

[0002] In 28nm high-kJ metal gate (HKMG) technology, the mainstream approach still employs the gate-last technique. This process typically involves first forming an amorphous silicon dummy gate, which is then removed after source and drain fabrication. Subsequently, a work function metal (WF metal) and aluminum (Al) are sequentially filled as the gate electrode. However, in the fabrication of existing metal gate electrodes, the continuously shrinking gate length results in a large aspect ratio at the gate trench opening, making the deposition of gate electrode material into the opening extremely difficult. Due to the inherent characteristics of the deposition process, the material growth rate at the edge of the gate trench opening is often faster than at the bottom, leading to excessive buildup at the top. This can prematurely close the gate trench opening, resulting in voids at the bottom. These voids directly degrade the electrical performance of the gate electrode and the reliability of the device.

[0003] Therefore, there is an urgent need to propose an improved metal gate manufacturing method to solve the problems of poor electrical performance of the gate electrode and poor device reliability caused by poor gate trench filling effect. Summary of the Invention

[0004] This invention provides a method for improving the filling quality of metal gates, which solves the problem of voids forming at the bottom during metal gate filling and effectively improves the filling quality of metal gates.

[0005] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.

[0006] To achieve one or more of the above objectives or other objectives, the present invention provides a method for improving the filling quality of a metal gate, comprising the following steps: Step 1: providing a substrate, wherein a gate trench is formed on the substrate, the gate trench being obtained by removing a dummy gate layer in a post-gate process; Step 2: sequentially depositing a barrier layer and a work function adjustment layer on the substrate and the sidewalls and bottom of the gate trench; Step 3: depositing a first TiN layer on the work function adjustment layer; Step 4: filling the gate trench with an amorphous silicon layer until the gate trench is completely filled, while an amorphous silicon layer is simultaneously formed on the surface of the substrate, and after filling, removing the amorphous silicon layer on the surface of the substrate by a chemical mechanical polishing process; Step 5: removing the amorphous silicon layer in the gate trench; Step 6: filling the gate trench with a metal gate.

[0007] The barrier layer deposited in step 2 is a TaN layer with a thickness of 15 Å-30 Å; the work function adjustment layer deposited is a stack formed by a second TiN layer and a TiAl layer, with the second TiN layer having a thickness of 10 Å-50 Å and the TiAl layer having a thickness of 60 Å-100 Å.

[0008] The thickness of the first TiN layer deposited in step 3 is 20 Å-80 Å.

[0009] Step 4 involves removing the amorphous silicon layer from the substrate surface using a CMP process, including removing the first TiN layer, the work function adjustment layer, and the barrier layer deposited on the substrate surface using a chemical mechanical polishing process.

[0010] Step 4, filling the gate trench with the amorphous silicon layer, includes dissolving the silicon-containing precursor in toluene, preparing a spin coating solution, and using a spin coater to flow the spin coating solution into and fill the gate trench; after completing the spin coating step of the gate trench, the substrate is placed in an inert gas environment at 250℃-450℃ for heat treatment for 30min-60min.

[0011] The silicon-containing precursor includes cyclopentylsilane or polydihydrosilane; the inert gas environment is an argon environment.

[0012] The spin coater operates at a speed of 1000 rpm to 6000 rpm.

[0013] Step 4, filling the gate trench with the amorphous silicon layer, includes placing the substrate with the gate trench formed in the PECVD reaction chamber, evacuating the vacuum pressure of the reaction chamber to 10 Pa-100 Pa, introducing a mixture of silane and hydrogen gas into the reaction chamber as a reaction gas, and applying radio frequency power at a frequency of 14 MHz-15 MHz; controlling the substrate temperature at 200 ℃-300 ℃; and depositing the amorphous silicon layer until the gate trench is completely filled.

[0014] The process used to remove the amorphous silicon layer in the gate trench in step 5 is the same as the process used to remove the dummy gate layer in the gate trench in step 1.

[0015] The metal gate deposited in the gate trench consists of a Ti layer and an Al layer; the thickness of the Ti layer is 40 Å-80 Å, and the thickness of the Al layer is 1800 Å-2400 Å.

[0016] Compared with the prior art, the beneficial effects of the present invention mainly include: After forming the gate trench in the post-gate process and sequentially depositing the barrier layer, work function adjustment layer, and first TiN layer, the method of the present invention does not directly fill the metal gate. Instead, it first fills the trench with an amorphous silicon layer. The amorphous silicon layer on the substrate surface, along with the underlying first TiN layer, work function adjustment layer, and barrier layer, are removed using chemical mechanical polishing (CMP). Then, the amorphous silicon layer within the gate trench is removed using the same process as for removing the dummy gate. This results in a smoother film structure at the top edge of the gate trench, eliminating premature sealing caused by excessively fast top deposition rates. This prevents voids during subsequent metal filling (Ti / Al), significantly improving the filling quality of the metal gate and ensuring the manufacturing yield of the metal gate under advanced processes.

[0017] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a transmission electron microscope image of the gate opening structure after removing the dummy gate in the back gate process in the relevant technical field.

[0020] Figure 2 This is a schematic cross-sectional view of a substrate including a dummy gate, fabricated using a post-gate process in this invention.

[0021] Figure 3 This is a schematic cross-sectional view of the substrate in which the gate trench is formed after the dummy gate is removed by the post-gate process in this invention.

[0022] Figure 4 This is a schematic cross-sectional view of a substrate after depositing a barrier layer and a work function adjustment layer on a substrate with gate trenches.

[0023] Figure 5 This is a schematic cross-sectional view of the substrate after the first TiN layer has been deposited on the work function adjustment layer.

[0024] Figure 6 This is a schematic cross-sectional view of the substrate after an amorphous silicon layer has been deposited in the gate trench.

[0025] Figure 7 This is a schematic diagram of the cross-section of a substrate after chemical mechanical polishing.

[0026] Figure 8 This is a schematic diagram of the substrate cross-section after the amorphous silicon layer in the trench has been removed.

[0027] Figure 9 This is a schematic diagram of the substrate cross-section after the metal gate has been deposited.

[0028] In the figure: 1. Substrate; 2. Pseudo-gate; 3. SiGe trench; 4. Gate trench; 5. Barrier layer; 6. Work function adjustment layer; 7. Neck contraction region; 8. First TiN layer; 9. Amorphous silicon layer; 10. Metal gate. Detailed Implementation

[0029] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0030] Example 1 Example 1 provides a method for improving the filling quality of a metal gate, comprising the following steps: Step 1: Provide a substrate on which a gate trench is formed, the gate trench being obtained by removing the dummy gate layer in a post-gate process.

[0031] Among them, the gate-last / replacement gate process is the mainstream manufacturing solution for high dielectric constant metal gates. Compared with the gate-first process, the gate-last process forms a dummy gate (dummy poly gate) as a placeholder structure by depositing an amorphous silicon layer, and then completes the source and drain processes, deposits the interlayer dielectric layer, and removes the dummy gate to form the true gate.

[0032] Step 2: Deposit a barrier layer and a work function adjustment layer sequentially on the substrate and the sidewalls and bottom of the gate trench.

[0033] Step 3: Deposit a first TiN layer on the work function adjustment layer.

[0034] Step 4: Fill the gate trench with an amorphous silicon layer until the gate trench is completely filled. At the same time, an amorphous silicon layer is formed on the surface of the substrate. After filling, the amorphous silicon layer on the surface of the substrate is removed by chemical mechanical polishing.

[0035] Step 5: Remove the amorphous silicon layer within the gate trench.

[0036] Step 6: Fill the gate trench with a metal gate.

[0037] In Example 1, after sequentially depositing a barrier layer, a work function adjustment layer, and a first TiN layer within the gate trench formed by the back-gate process, the metal gate is not directly filled. Instead, an amorphous silicon layer is first completely filled into the trench. The amorphous silicon layer on the substrate surface, along with the first TiN layer, work function adjustment layer, and barrier layer above it, are removed using a chemical mechanical polishing process. Then, the amorphous silicon layer within the gate trench is removed using the same process as for removing the dummy gate. This flattens the film structure at the top edge of the gate trench, eliminating premature sealing caused by excessively fast top deposition rates. This prevents voids during subsequent metal filling (Ti / Al), significantly improving the filling quality of the metal gate and ensuring the manufacturing yield of the metal gate under advanced processes.

[0038] The following text, in conjunction with the appendix Figure 1-9 This application provides a detailed explanation of a method for improving the filling quality of a metal gate.

[0039] In HKMG (high dielectric metal gate) back gate processes at 28nm and below nodes, the metal gate fill quality directly affects the electrical performance and reliability of the device.

[0040] As gate dimensions gradually decrease in advanced manufacturing processes, the resulting dummy gate appearance exhibits inconsistencies between its top and bottom dimensions. After removing the dummy gate, the gate trench opening displays a large aspect ratio, and a noticeable overhang structure exists at the top of the gate trench opening. The substrate morphology after dummy gate removal is shown in the image below. Figure 1 As shown. During the subsequent barrier layer, work function adjustment layer, and metal gate filling, due to the inherent characteristics of physical vapor deposition or atomic deposition processes, the deposition rate of material at the top of the gate trench opening is significantly faster than at the bottom. Influenced by the overhanging structure at the top of the opening, the subsequently deposited material is prone to prematurely accumulating at the edge region of the opening, forming a necking contraction zone. This results in the gate trench opening region being completely closed before the bottom of the gate trench is fully filled during subsequent metal gate filling, leading to voids at the bottom of the gate trench.

[0041] To address the problems existing in the related technical field, this application provides a method for improving the filling quality of a metal gate. A barrier layer and a work function adjustment layer are sequentially deposited on a substrate forming a gate trench, and an amorphous silicon layer is filled into the gate trench. The substrate surface is then smoothed using a CMP (chemical mechanical polishing) process until the barrier layer is removed. This process can flatten the edge film structure of the gate trench opening, facilitating the subsequent filling of the metal gate.

[0042] like Figure 2-9 This application provides a method for improving the filling quality of a metal gate, comprising the following steps: Step 1: Provide a substrate 1, on which a gate trench 4 is formed. The gate trench 4 is obtained by removing the dummy gate layer in the post-gate process.

[0043] like Figure 2 As shown, the back-gate process pre-fabricates a dummy gate 2 structure on a substrate 1 with SiGe trenches 3, wherein the dummy gate 2 is obtained by depositing an amorphous silicon layer. After the dummy gate 2 is deposited, a dummy gate removal process (DPR process) is used to remove the dummy gate 2 on the substrate, forming a gate trench 4. The cross-sectional view of the formed gate trench 4 is shown below. Figure 4 As shown.

[0044] As an optional implementation, the DPR process includes planarizing the ILD layer (dielectric layer) using a CMP process to expose the top of the dummy gate 2, and removing the amorphous silicon dummy gate 2 using any one of the following methods: dry etching, wet etching, or a combination of dry and wet etching.

[0045] Taking dry etching as an example, halogen-containing gases such as Cl2, HBr, SF6, and CF4 can be used as reactants to perform plasma etching under low pressure.

[0046] As a conventional technical solution in this field, the DPR process will not be described in detail here.

[0047] Step 2: Deposit a barrier layer 5 and a work function adjustment layer 6 sequentially on the sidewalls and bottom of the substrate 1 and the gate trench 4. A cross-sectional view of the substrate 1 with the barrier layer 5 and work function adjustment layer 6 deposited is shown below. Figure 4 As shown, a neck contraction region 7 is formed at the opening region of the gate trench 4.

[0048] The barrier layer can be deposited using plasma-enhanced atomic deposition (PE-ALD). As an optional implementation, the deposited barrier layer 5 is a TaN layer (e.g., using TaCl5 or PDMAT as a precursor solution, and depositing the TaN layer using plasma-enhanced atomic deposition). The thickness of the deposited TaN layer is 15 Å–30 Å.

[0049] After the barrier layer 5 is deposited, a work function adjustment layer 6 is deposited on top of the barrier layer 5. The work function adjustment layer is a key material for work function adjustment. As an optional implementation, the work function adjustment layer in this application is a stack formed by a second TiN layer and a TiAl layer. The second TiN layer in this work function adjustment layer is a key material for work function adjustment. The thickness and uniformity of the second TiN layer directly affect the performance of the device. The deposition of the second TiN layer is obtained by combining PE-ALD and thermal ALD methods.

[0050] The deposited TiAl layer can be deposited using a self-ionization PVD process to form a high-conformity TiAl layer, and then annealed to allow the Al atoms to diffuse into TiN to form a TiAlN layer, thereby precisely adjusting the work function.

[0051] The thickness of the second TiN layer is 10 Å-50 Å, and the thickness of the TiAl layer is 60 Å-100 Å.

[0052] The deposition process of the work function adjustment layer 6 and the barrier layer 5 described above is prior art, and will not be described in detail in this application.

[0053] Step 3: Deposit a first TiN layer 8 on the work function adjustment layer 6.

[0054] The substrate structure after the deposition of the first TiN layer 8 is as follows: Figure 5 As shown, the thickness of the first deposited TiN layer is 20 Å-80 Å.

[0055] The purpose of depositing the first TiN layer 8 is that, during the removal of the amorphous silicon layer 9 in step 5, the first TiN layer 8 can serve as an etch stop layer, protecting the work function adjustment layer 6. Simultaneously, it can participate in work function adjustment and adhesion. TiN itself is a commonly used work function metal. After the deposition of metallic Ti and metallic Al (i.e., the metal gate 10) in step 6, the first TiN layer 8 can bond with the TiAi of the work function adjustment layer 6 below and the metallic Ti above, thereby participating in work function adjustment. Furthermore, the first TiN layer 8 can also act as a barrier layer, preventing aluminum atoms in the metal gate 10 from diffusing into the work function adjustment layer 6.

[0056] Step 4: Fill the gate trench 4 with an amorphous silicon layer 9 until the gate trench 4 is completely filled. Due to the overfilling process, an amorphous silicon layer 9 is simultaneously formed on the surface of the substrate 1 after the amorphous silicon layer 9 is filled. After the amorphous silicon layer 9 filling step is completed, the amorphous silicon layer 9 on the surface of the substrate 1 is then completely removed by a chemical mechanical polishing process.

[0057] In step 4, an amorphous silicon layer 9 is filled into the gate trench 4. The main purpose is to prevent the polishing slurry from entering the gate trench 4 during the subsequent CMP process, which would affect the deposition of the metal gate 10. To achieve this, the gate trench 4 needs to be filled with the amorphous silicon layer 9 as completely as possible to prevent the polishing slurry from entering. Therefore, this application uses spin coating or PECVD processes to achieve full filling of the amorphous silicon layer 9 into the gate trench 4. The specific process steps include: The spin coating process includes: dissolving a silicon-containing precursor in toluene (the silicon-containing precursor includes cyclopentylsilane or polydihydrosilane), preparing a spin coating solution, applying the spin coating solution to the surface of the substrate, and using a spin coater to flow the spin coating solution into (under the action of centrifugal force, into the gate trench 4) and fill the gate trench 4.

[0058] After completing the spin-coating step of gate trench 4, the substrate is placed in an inert gas environment at 250℃-450℃ for 30min-60min until an amorphous silicon layer is formed. This inert gas environment can be, for example, an argon environment.

[0059] As an optional implementation method, the spin coater rotates at a speed of 1000 rpm to 6000 rpm.

[0060] The PECVD process includes: placing a substrate 1 with gate trench 4 formed in it in the PECVD reaction chamber, evacuating the vacuum pressure of the reaction chamber to 10 Pa-100 Pa, introducing a mixture of silane and hydrogen gas into the reaction chamber as the reaction gas, and applying radio frequency power at a frequency of 14 MHz-15 MHz; controlling the temperature of substrate 1 to be maintained at 200 ℃-300 ℃, and depositing an amorphous silicon layer through the above steps until the gate trench 4 is completely filled.

[0061] The cross-sectional view of the substrate 1 structure after the amorphous silicon layer 9 is filled is shown below. Figure 6 As shown.

[0062] After the amorphous silicon layer 9 is filled, the remaining amorphous silicon layer 9 on the substrate 1 is removed using a CMP process, leaving only the amorphous silicon layer 9 within the gate trench 4. The CMP removal of the amorphous silicon layer 9 on the substrate surface includes completely removing the first TiN layer 8, the work function adjustment layer 6, and the barrier layer 5 deposited on the surface of the substrate 1 using a CMP process.

[0063] By excessively removing the amorphous silicon layer 9 using the CMP process (that is, removing the work function adjustment layer 6 and the barrier layer 5 on the substrate together until the interlayer dielectric layer (ILD) on the substrate is exposed), the neck shrinkage region 7 formed at the opening edge of the gate trench 4 can be completely removed (the neck shrinkage region 7 is formed after the deposition of the work function adjustment layer 6 and the barrier layer 5). This makes the opening edge of the gate trench 4 flat and unobstructed, which facilitates the subsequent filling of the metal gate 10 and improves the filling effect and filling quality.

[0064] In step 4, the amorphous silicon layer 9 on the surface of substrate 1 is removed by CMP process, resulting in the structure of substrate 1 as shown below. Figure 7 As shown.

[0065] Step 5: Remove the amorphous silicon layer 9 within the gate trench 4.

[0066] The process used to remove the amorphous silicon layer 9 within the gate trench 4 is the same as the process used to remove the dummy gate 2 within the gate trench 4 in step 1. The process for removing the dummy gate layer has already been described above and will not be repeated in detail here. Furthermore, since the process for removing the amorphous silicon layer 9 is the same as the process for removing the dummy gate 2 in step 1, the complexity of the process is reduced, and production efficiency is improved.

[0067] In step 5, the structure of substrate 1 after removing amorphous silicon layer 9 is as follows: Figure 8 As shown.

[0068] Step 6: Fill the gate trench 4 with metal gate 10.

[0069] The metal gate 1 filling the gate trench 4 is a stack of metal Ti and metal Al layers. A thin layer of metal Ti, with a thickness of 40 Å-80 Å, is first grown in the gate trench 4 using chemical vapor deposition (CVD) or physical vapor deposition (PVD). After the growth of the metal Ti layer, a thicker layer of metal aluminum, with a thickness of 1800 Å-2400 Å, is deposited on top of the metal Ti layer using PVD.

[0070] In step 6, the substrate 1 structure after depositing the metal gate 10 is as follows: Figure 9 As shown.

[0071] The above provides a detailed description of the puncture mechanism and its beverage machine provided by the present invention. Specific examples have been used to illustrate the structure and working principle of the invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for improving the filling quality of a metal gate, characterized in that, Includes the following steps: Step 1: Provide a substrate on which a gate trench is formed, the gate trench being obtained by removing the dummy gate layer in a post-gate process; Step 2: Deposit a barrier layer and a work function adjustment layer sequentially on the substrate and on the sidewalls and bottom of the gate trench; Step 3: Deposit a first TiN layer on the work function adjustment layer; Step 4: Fill the gate trench with an amorphous silicon layer until the gate trench is completely filled. At the same time, an amorphous silicon layer is formed on the surface of the substrate. After filling, the amorphous silicon layer on the surface of the substrate is removed by chemical mechanical polishing. Step 5: Remove the amorphous silicon layer within the gate trench; Step 6: Fill the gate trench with a metal gate.

2. The method for improving the filling quality of a metal gate according to claim 1, characterized in that, The barrier layer deposited in step 2 is a TaN layer with a thickness of 15 Å-30 Å; The deposited work function adjustment layer is a stack formed by a second TiN layer and a TiAl layer, wherein the thickness of the second TiN layer is 10 Å-50 Å and the thickness of the TiAl layer is 60 Å-100 Å.

3. The method for improving the filling quality of a metal gate according to claim 1, characterized in that, The thickness of the first TiN layer deposited in step 3 is 20 Å-80 Å.

4. The method for improving the filling quality of a metal gate according to claim 1, characterized in that, Step 4 involves removing the amorphous silicon layer from the substrate surface using a CMP process, including removing the first TiN layer, the work function adjustment layer, and the barrier layer deposited on the substrate surface using a chemical mechanical polishing process.

5. The method for improving the filling quality of a metal gate according to claim 1, characterized in that, Step 4, filling the gate trench with the amorphous silicon layer, includes dissolving the silicon-containing precursor in toluene, preparing a spin coating solution, and using a spin coater to flow the spin coating solution into and fill the gate trench. After completing the spin coating step of the gate trench, the substrate is heat-treated in an inert gas environment at 250℃-450℃ for 30min-60min.

6. The method for improving the filling quality of a metal gate according to claim 5, characterized in that, The silicon-containing precursor includes cyclopentylsilane or polydihydrosilane; The inert gas environment is an argon environment.

7. The method for improving the filling quality of a metal gate according to claim 6, characterized in that, The spin coater operates at a speed of 1000 rpm to 6000 rpm.

8. The method for improving the filling quality of a metal gate according to claim 1, characterized in that, Step 4, filling the gate trench with the amorphous silicon layer, includes placing the substrate with the gate trench in the PECVD reaction chamber, pumping the vacuum pressure of the reaction chamber to 10pa-100pa, introducing a mixture of silane and hydrogen into the reaction chamber as a reaction gas, and applying radio frequency power at a frequency of 14MHz-15MHz. Control the substrate temperature between 200℃ and 300℃; An amorphous silicon layer is deposited until the gate trench is completely filled.

9. The method for improving the filling quality of a metal gate according to claim 1, characterized in that, The process used to remove the amorphous silicon layer in the gate trench in step 5 is the same as the process used to remove the dummy gate layer in the gate trench in step 1.

10. The method for improving the filling quality of a metal gate according to claim 1, characterized in that, The metal gate deposited in the gate trench is a Ti layer and an Al layer. The thickness of the Ti layer is 40 Å-80 Å, and the thickness of the Al layer is 1800 Å-2400 Å.

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