Method of forming a semiconductor structure

Abstract

A method is provided, including providing a substrate including an array region and a peripheral region surrounding the array region, patterning a top portion of the substrate to form a plurality of blocks in the peripheral region and an island in the array region, depositing a first oxide layer on the substrate and covering the blocks and the island, performing a densification process on the first oxide layer, removing a top portion of the first oxide layer to form a first isolation region. The blocks and the island are separated from each other by the first isolation region. The method further includes patterning the island to form a plurality of active regions, and forming a plurality of word lines in the active regions. This method can reduce the possibility of a capacitor being shifted from an end portion of an active region, thereby improving contact resistance between the active region and the capacitor.

Description

Technical Field

[0001] This invention relates to a method for forming a semiconductor structure. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern these material layers, thereby forming circuit elements on the semiconductor substrate. As the size of semiconductor devices continues to shrink to achieve higher device density, higher performance, and lower cost, the challenge of precisely controlling device configuration has emerged. Summary of the Invention

[0003] This invention provides a method for forming a semiconductor structure. The method includes providing a substrate comprising an array region and a peripheral region surrounding the array region; patterning the top of the substrate to form a plurality of blocks in the peripheral region and islands in the array region; depositing a first oxide layer on the substrate and covering the blocks and islands; performing a densification process on the first oxide layer; and removing the top of the first oxide layer to form a first isolation region. The blocks and islands are spaced apart from each other by the first isolation region. The method further includes patterning the islands to form a plurality of active regions and forming a plurality of character lines in these active regions.

[0004] In some embodiments, a densification process is performed on the first oxide layer before these active regions are formed in the array region.

[0005] In some embodiments, depositing a first oxide layer on a substrate and covering the blocks and islands includes conformally depositing a second oxide layer on the substrate, the blocks and islands, conformally depositing a dielectric layer on the second oxide layer, and depositing the first oxide layer on the dielectric layer.

[0006] In some embodiments, removing the top of the first oxide layer to form the first isolation region includes removing the top of the second oxide layer and the top of the dielectric layer.

[0007] In some embodiments, patterning the islands to form these active regions includes forming pads on the islands, the blocks, and the first isolation region, and patterning portions of the islands and pads.

[0008] In some embodiments, the method further includes forming a second isolation zone around the active zones after the formation of the active zones.

[0009] In some embodiments, forming these character lines in these active regions includes forming a plurality of first trenches in these active regions and a plurality of second trenches in second isolation regions, conformally forming a dielectric layer along a plurality of sidewalls and bottom surfaces of these first trenches, forming a conductive layer in the bottom of these first trenches and the bottom of these second trenches, and forming a capping layer on the conductive layer.

[0010] In some embodiments, the top surface of the capping layer, the top surfaces of these active regions, and the top surface of the second isolation region are coplanar.

[0011] In some embodiments, the method further includes forming a slit, an alignment mark, a first pad, and a second pad. The slit is disposed between a peripheral region and an array region, and the alignment mark, the first pad, and the second pad are formed in the slit.

[0012] In some embodiments, alignment marks, a first pad, and a second pad are formed prior to the formation of these blocks.

[0013] In some embodiments, a second pad is used to measure a first height of these blocks, and a first pad is used to measure a second height of these active areas.

[0014] In some embodiments, the top surfaces of these blocks in the peripheral region and the top surfaces of the islands in the array region are coplanar.

[0015] This invention provides a method for forming a semiconductor structure. The method includes providing a substrate comprising an array region, a peripheral region surrounding the array region, and cleavage paths between the array region and the peripheral region. Alignment marks are formed in the cleavage paths. The method further includes patterning the top of the substrate to form a plurality of blocks in the peripheral region and islands in the array region. The method further includes depositing a first oxide layer on the substrate and covering the blocks and islands, performing a densification process on the first oxide layer, and removing the top of the first oxide layer to form isolation regions. The blocks and islands are spaced apart from each other by the isolation regions. The method further includes using a first photomask to pattern the islands to form a plurality of active regions. Before patterning the islands, the substrate and the first photomask are aligned with each other by the alignment marks. The method further includes forming a plurality of character lines in these active regions.

[0016] In some embodiments, the method further includes forming a first pad and a second pad in the cutting channel.

[0017] In some embodiments, alignment marks, a first pad, and a second pad are formed prior to the formation of these blocks.

[0018] In some embodiments, the alignment mark, the first pad, and the second pad are formed in the same process.

[0019] In some embodiments, the method further includes measuring a first height of the blocks using a second pad, and aligning the substrate with alignment marks prior to measuring the first height of the blocks.

[0020] In some embodiments, the method further includes measuring a second height of the active regions via a first pad, and aligning the substrate with alignment marks prior to measuring the second height of the active regions.

[0021] In some embodiments, forming these blocks includes using a second photomask to pattern the top of the substrate before patterning the top of the substrate. The substrate and the second photomask are aligned with each other by alignment marks.

[0022] In some embodiments, a densification process is performed on the first oxide layer before these active regions are formed in the array region.

[0023] These and other features, aspects, and advantages of the invention will be better understood with reference to the following description and the appended claims.

[0024] It should be understood that the foregoing general description and the following detailed description are by way of example and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0025] A more complete understanding of the present invention can be obtained by reading the following embodiments and the detailed description in conjunction with the accompanying drawings: Figure 1 and Figure 2 This is a perspective view of various formation stages of a method for forming a semiconductor structure according to some embodiments of the present invention.

[0026] Figure 3 This is a top view of a semiconductor structure according to some embodiments of the present invention.

[0027] Figures 4 to 7 According to some embodiments of the present invention, along Figure 2 The method of forming a semiconductor structure using line AA is shown in cross-sectional views at various formation stages.

[0028] Figure 8 This is a perspective view of various formation stages of a method for forming a semiconductor structure according to some embodiments of the present invention.

[0029] Figures 9 to 11 According to some embodiments of the present invention, along Figure 8 The method of forming a semiconductor structure using line AA is shown in cross-sectional views at various formation stages. Detailed Implementation

[0030] Embodiments of the invention will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0031] See Figure 1 , Figure 1 This is a perspective view of a method for forming a semiconductor structure according to some embodiments of the present invention at various formation stages. A substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. The substrate 100 may include elemental semiconductors, including silicon or germanium in single-crystal, polycrystalline, or amorphous forms; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium bismuthide; alloy semiconductor materials, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials; or combinations thereof. In some embodiments, the substrate 100 may have a multilayer structure, or the substrate 100 may include a multilayer compound semiconductor structure.

[0032] The substrate 100 may include an array region 102 and a peripheral region 104. The peripheral region 104 is adjacent to the array region 102. For example, the peripheral region 104 surrounds the array region 102. In some embodiments, active elements or transistors are primarily formed in the array region 102, while the peripheral region 104 is used for circuit wiring and may contain passive elements. In some embodiments, the substrate 100 comprises silicon material. Furthermore, the substrate 100 may also include a cleavage (e.g., a groove) disposed between the array region 102 and the peripheral region 104. Figure 3 (Cut track 114 in the middle).

[0033] A dielectric layer 106 is formed on the substrate 100, and a dielectric layer 108 is formed on the dielectric layer 106. In some embodiments, the dielectric layer 106 may be an oxide layer, such as silicon oxide. In some embodiments, the dielectric layer 106 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), thermal oxidation, etc. In some embodiments, the dielectric layer 108 may be a nitride layer, such as silicon nitride. In some embodiments, the dielectric layer 108 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), etc.

[0034] See Figure 2 , Figure 2This is a perspective view of a method for forming a semiconductor structure according to some embodiments of the present invention at various formation stages. A patterning process is performed on substrate 100, dielectric layer 106, and dielectric layer 108. Specifically, the top of substrate 100 is patterned to form a plurality of blocks 110 in peripheral region 104 and islands 112 in array region 102. The patterned dielectric layer 106 and patterned dielectric layer 108 remain on the blocks 110 and islands 112. In some embodiments, the top surfaces of the blocks 110 and the top surfaces of the islands 112 are coplanar. In some embodiments, substrate 100, dielectric layer 106, and dielectric layer 108 can be patterned by any suitable photolithography process. In some embodiments, substrate 100, dielectric layer 106, and dielectric layer 108 can be patterned by one or more etching processes.

[0035] See Figure 3 , Figure 3 This is a top view of a semiconductor structure according to some embodiments of the present invention. Alignment marks 116, a first pad 118, and a second pad 120 are formed in a dicing channel 114 and spaced apart from each other. In order to accurately project the circuit layout onto the desired location on the substrate 100, the substrate 100 and the photomask used in the exposure process must be aligned with each other before performing the exposure process. Alignment marks 116 may have a non-periodic pattern, which provides an identifier for alignment. Alignment marks 116 may have different geometries, such as rectangles, crosses, triangles, or combinations thereof. In some embodiments, the substrate 100 and the first photomask used to form the bulk 110 in the peripheral region 104 can be aligned with each other by alignment marks 116.

[0036] Furthermore, the first pad 118 and the second pad 120 are used to measure the height of the block 110 in the peripheral region 104 and the height of the active region (formed subsequently) in the array region 102. To accurately measure the height using the pads on the substrate 100, the substrate 100 must be aligned using alignment marks 116 before performing the measurement process. Specifically, the block 110 (e.g., Figure 2 As shown, the top surface S1 of the substrate 100 has a first height H1, and the first height H1 can be measured by the second pad 120.

[0037] In some embodiments, alignment marks 116, first pad 118, and second pad 120 may be formed prior to forming the block 110. In some embodiments, alignment marks 116, first pad 118, and second pad 120 may be formed in one or more etching processes.

[0038] See Figure 4 , Figure 4 According to some embodiments of the present invention, along Figure 2The diagram shows cross-sectional views of the method for forming a semiconductor structure using line AA at various formation stages. An oxide layer 122, a dielectric layer 124, and a dielectric layer 126 are sequentially formed on a substrate 100, a bulk 110, and an island 112. Specifically, the oxide layer 122 and the dielectric layer 124 are conformally formed along multiple sidewalls and the top surface of the bulk 110, multiple sidewalls and the top surface of the island 112, and the top surface S1 of the substrate 100. The dielectric layer 126 fills the space between the bulk 110 and the island 112 by filling the dielectric layer 124.

[0039] In some embodiments, the oxide layer 122 may be formed by any suitable deposition process, such as atomic layer deposition (ALD). In some embodiments, the dielectric layer 124 may be a liner and may be made of nitride. The dielectric layer 124 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electron beam evaporation, etc. In some embodiments, the dielectric layer 126 may be made of any suitable dielectric material. The dielectric layer 126 may be formed by spin coating.

[0040] See Figure 5 , Figure 5 According to some embodiments of the present invention, along Figure 2 The diagram shows a cross-sectional view of the method for forming a semiconductor structure along line AA at various formation stages. A densification process 128 is performed on dielectric layer 126. During densification process 128, dielectric layer 126 can be stress-relieving, and after densification process 128, dielectric layer 126 can be densified.

[0041] See Figure 6 , Figure 6 According to some embodiments of the present invention, along Figure 2 The diagram shows cross-sectional views of the method for forming the semiconductor structure along line AA at various formation stages. Excess portions of dielectric layer 108 and oxide layers 122, 124, and 126 are removed. Specifically, the tops of oxide layer 122, dielectric layer 124, dielectric layer 126, and dielectric layer 108 are removed until dielectric layer 106 is exposed. Removal can be performed using a planarization process, such as chemical mechanical planarization (CMP).

[0042] An isolation region 130 is formed between the island portion 112 and the block portion 110. Specifically, the retained portions of the oxide layer 122, the dielectric layer 124, and the dielectric layer 126 may be referred to as the isolation region 130. In some embodiments, the top surface of the dielectric layer 106 is coplanar with the top surface of the isolation region 130. In some embodiments, the isolation region 130 may be referred to as shallow trench isolation (STI).

[0043] See Figure 7 , Figure 7 According to some embodiments of the present invention, along Figure 2 The diagram shows cross-sectional views of the method for forming a semiconductor structure using line AA at various formation stages. A pad layer 132 is formed on dielectric layer 106 and isolation region 130. Pad layer 132 serves to protect the structure beneath it from subsequent patterning processes. In some embodiments, pad layer 132 can be any suitable dielectric material, such as tetraethylorthosilicate (TEOS) oxide. In some embodiments, pad layer 132 can be formed by any suitable deposition process, such as chemical vapor deposition (CVD), thermal oxidation, etc.

[0044] See Figure 8 and Figure 9 . Figure 8 This is a perspective view of various formation stages of a method for forming a semiconductor structure according to some embodiments of the present invention. Figure 9 According to some embodiments of the present invention, along Figure 8 The method of forming a semiconductor structure using line AA is shown in cross-sectional views at various formation stages.

[0045] A portion of the island 112, as well as the pads 132 and dielectric layer 106 on the island 112, are patterned. The island 112 is patterned to form a plurality of active regions 134. In order to accurately project the circuit layout onto the island 112, alignment marks 116 (such as...) must be used before performing the patterning process. Figure 3 (As shown) The substrate 100 and the second photomask used in the exposure process are aligned with each other. Since the alignment mark 116 used to form the active region 134 in the array region 102 is formed before the formation of the block 110, and the alignment of the block 110 in the peripheral region 104 can be performed by the alignment mark 116, this simplifies the design and manufacturing process of the alignment mark 116. The active regions 134 are located in the array region 102 and are spaced apart from each other by the first trench 136. The active regions 134 have a second height H2 from the bottom of the first trench 136. Specifically, the second height H2 of the active regions 134 can be measured by the first pad 118 (e.g., Figure 3 (As shown).

[0046] Since the active region 134 is formed after the densification process 128, the active region 134 has a plurality of sidewalls substantially perpendicular to the top surface S1 of the substrate 100. Performing a patterning process on portions of the pad layer 132 and the island 112 may include one or more etching operations. In some embodiments, the dielectric layer 106 and the pad layer 132 may be removed after the active region 134 is formed.

[0047] See Figure 10 , Figure 10 According to some embodiments of the present invention, along Figure 8 The diagram shows cross-sectional views of the method for forming a semiconductor structure along line AA at various formation stages. An isolation region 138 is formed in a first trench 136. The isolation region 138 is used to isolate the active regions 134 from each other. In other words, the isolation region 138 surrounds and defines the active regions 134. In some embodiments, the isolation region 138 can be formed by depositing an isolation material overfilling the first trench 136 and then removing the top of the isolation material. In some embodiments, the top surfaces of the active regions 134, 138, and 130 are coplanar.

[0048] See Figure 11 , Figure 11 According to some embodiments of the present invention, along Figure 8 The diagram shows a cross-sectional view of the method for forming a semiconductor structure of line AA at various formation stages. A plurality of word lines 150 are formed in array region 102. In some embodiments, the word lines 150 can be formed by the following steps.

[0049] First, a plurality of second trenches 140 and a plurality of third trenches 142 are formed in the active region 134 and the isolation region 138, respectively. A dielectric layer 144 is conformally formed along a plurality of sidewalls and the bottom surface of the second trenches 140. In some embodiments, the dielectric layer 144 directly contacts the active region 134. In some embodiments, the dielectric layer 144 can be formed by thermal oxidation. In some embodiments, the dielectric layer 144 may comprise silicon oxide.

[0050] Then, a conductive layer 146 is formed at the bottom of the second trench 140 and the bottom of the third trench 142. In some embodiments, the conductive layer 146 can be formed by first depositing a conductive material to fill the second trench 140 and the third trench 142, and then removing the top of the conductive material. In some embodiments, the conductive layer 146 may include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), titanium silicon nitride (TiSiN), other suitable materials, or combinations thereof.

[0051] Subsequently, a capping layer 148 is formed on the conductive layer 146 in the second trench 140 and the third trench 142. Specifically, the capping layer 148 is formed on top of the second trench 140 and the third trench 142. In some embodiments, the capping layer 148 can be formed by first depositing a dielectric material to fill the second trench 140 and the third trench 142, and then removing the top of the dielectric material. In some embodiments, the capping layer 148 may include a nitride, such as silicon nitride. In some embodiments, the top surface of the capping layer 148, the top surface of the active region 134, and the top surface of the isolation region 138 are coplanar. Character lines 150 are defined in the second trench 140 and the third trench 142.

[0052] The word lines 150 are spaced apart from each other and pass through the active regions 134. Each active region 134 in the array region 102 is traversed by two word lines 150, and each active region 134 is divided into a central portion and two end portions. Since the active regions 134 and word lines 150 are formed after performing the densification process 128, this prevents the active regions 134 and word lines 150 from experiencing stress release caused by the dielectric layer 126. In some embodiments, the top surface areas of the end portions are substantially the same.

[0053] This invention discloses a method for forming a semiconductor structure. The method includes first performing a densification process on a dielectric layer, then patterning islands to form active regions, and forming word lines through the active regions. In other words, the active regions and word lines are formed after the densification process, such that the end portions of the active regions are uniform throughout the array region and do not suffer from stress release caused by the dielectric layer during the densification process. The end portions of the formed active regions have a uniform profile throughout the active regions, thereby reducing the possibility of subsequent capacitors (not shown) shifting from the end portions of the active regions. Therefore, the contact resistance between the active regions and the subsequently formed capacitors can be improved.

[0054] Although the invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0055] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the invention falling within the appended claims.

[0056] [Symbol Explanation] 100: Substrate 102: Array area 104: Surrounding Area 106: Dielectric layer 108: Dielectric layer 110: Block 112: Island 114: Cutting Track 116: Alignment Mark 118: First Pad 120: Second pad 122: Oxide layer 124: Dielectric layer 126: Dielectric layer 128: Densification process 130: Quarantine Zone 132: Subbase 134: Active Zone 136: First trench 138: Quarantine Zone 140: Second trench 142: Third trench 144: Dielectric layer 146: Conductive layer 148: Cap layer 150: Character Line AA: Line H1: First Height H2: Second Altitude S1: Top surface.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including an array region and a peripheral region surrounding the array region; The top of the substrate is patterned to form a plurality of blocks in the peripheral region and islands in the array region; A first oxide layer is deposited on the substrate and covers the plurality of blocks and the islands; A densification process is performed on the first oxide layer; The top of the first oxide layer is removed to form a first isolation region, wherein the plurality of blocks and the island are separated from each other by the first isolation region; The island portion is patterned to form multiple active regions; as well as Multiple character lines are formed in the multiple active regions.

2. The method of claim 1, wherein the densification process is performed on the first oxide layer before the plurality of active regions are formed in the array region.

3. The method of claim 1, wherein depositing the first oxide layer on the substrate and covering the plurality of blocks and the island comprises: A second oxide layer is conformally deposited on the substrate, the plurality of blocks, and the islands; A conformally deposited dielectric layer is deposited on the second oxide layer; as well as The first oxide layer is deposited on the dielectric layer.

4. The method of claim 3, wherein removing the top of the first oxide layer to form the first isolation region comprises: Remove the top of the second oxide layer and the top of the dielectric layer.

5. The method of claim 1, wherein patterning the islands to form the plurality of active regions comprises: A cushion layer is formed on the island portion, the plurality of blocks, and the first isolation zone; as well as Pattern the island portion and a portion of the padding layer.

6. The method according to claim 1, wherein, Further includes: After the plurality of active regions are formed, a second isolation region is formed around the plurality of active regions.

7. The method of claim 6, wherein forming the plurality of character lines in the plurality of active regions comprises: Multiple first trenches are formed in the multiple active regions and multiple second trenches are formed in the second isolation region; A conformally formed dielectric layer extends along the multiple sidewalls and bottom surface of the plurality of first trenches; A conductive layer is formed at the bottom of the plurality of first trenches and at the bottom of the plurality of second trenches; as well as A capping layer is formed on the conductive layer.

8. The method of claim 7, wherein the top surface of the cover layer, the top surface of the plurality of active regions, and the top surface of the second isolation region are coplanar.

9. The method according to claim 1, wherein, Further includes: A cutting channel, an alignment mark, a first pad, and a second pad are formed, wherein the cutting channel is disposed between the peripheral region and the array region, and the alignment mark, the first pad, and the second pad are formed in the cutting channel.

10. The method of claim 9, wherein the alignment mark, the first pad, and the second pad are formed prior to the formation of the plurality of blocks.

11. The method of claim 9, wherein the second pad is used to measure a first height of the plurality of blocks, and the first pad is used to measure a second height of the plurality of active regions.

12. The method of claim 1, wherein the top surfaces of the plurality of blocks in the peripheral region and the top surfaces of the islands in the array region are coplanar.

13. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including an array region, a peripheral region surrounding the array region, and a cleaving channel between the array region and the peripheral region, wherein alignment marks are formed in the cleaving channel; The top of the substrate is patterned to form a plurality of blocks in the peripheral region and islands in the array region; A first oxide layer is deposited on the substrate and covers the plurality of blocks and the islands; A densification process is performed on the first oxide layer; The top of the first oxide layer is removed to form an isolation zone, wherein the plurality of blocks and the island are separated from each other by the isolation zone; The island is patterned using a first photomask to form a plurality of active areas, wherein the substrate and the first photomask are aligned with each other by the alignment marks before the island is patterned; as well as Multiple character lines are formed in the multiple active regions.

14. The method according to claim 13, wherein, Further includes: A first pad and a second pad are formed in the cutting channel.

15. The method of claim 14, wherein the alignment mark, the first pad, and the second pad are formed prior to the formation of the plurality of blocks.

16. The method of claim 14, wherein the alignment mark, the first pad, and the second pad are formed in the same process.

17. The method of claim 14, wherein, The method further includes measuring a first height of the plurality of blocks using the second pad, and aligning the substrate using the alignment mark before measuring the first height of the plurality of blocks.

18. The method according to claim 14, wherein, The method further includes measuring a second height of the plurality of active regions via the first pad, and aligning the substrate via the alignment mark before measuring the second height of the plurality of active regions.

19. The method of claim 13, wherein forming the plurality of blocks comprises: Before patterning the top of the substrate, a second photomask is used to pattern the top of the substrate, wherein the substrate and the second photomask are aligned with each other by the alignment marks.

20. The method of claim 13, wherein the densification process is performed on the first oxide layer before the plurality of active regions are formed in the array region.

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