Method for improving etch defects in metal gate process and semiconductor structure

Abstract

The application provides a method for improving corrosion defects in a metal gate process and a semiconductor structure, wherein a thicker characteristic is deposited at a step when a second hard mask layer is formed by a deposition process, a thicker second hard mask layer is formed at a chamfer of an isolation layer between a PMOS region and an NMOS region, and through subsequent precise control of etching thickness, the second hard mask layer of a flat area and part of the second hard mask layer at the chamfer are removed, the remaining second hard mask layer at the chamfer is reserved, the reinforcing effect of the chamfer is realized, the possibility of wet cleaning liquid seeping into the PMOS metal gate in subsequent wet cleaning of the groove is avoided, the corrosion defect problem caused by the chemical reaction between the wet cleaning liquid and the metal material such as aluminum in the traditional process is fundamentally solved, and thus the performance and reliability of the semiconductor structure are significantly improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a method and semiconductor structure for improving corrosion defects in metal gate processes. Background Technology

[0002] Advances in chip technology have not only driven the intelligent development of society but also greatly facilitated people's daily lives, making information acquisition more efficient and convenient. In early integrated circuit MOS transistors, polysilicon gates were used. However, as the size of MOS transistors continued to shrink, the traditional polysilicon gate suffered from reduced device performance due to the boron penetration effect. Furthermore, unavoidable depletion effects led to an increase in the equivalent gate dielectric layer thickness and a decrease in gate capacitance, ultimately resulting in device performance degradation. To meet the demands for higher performance, polysilicon gates are gradually being replaced by metal gates, thereby further optimizing the overall performance of the chip.

[0003] MOS transistors are further divided into PMOS and NMOS types, which differ significantly in their operating principles and electrical characteristics. Therefore, the fabrication of metal gates requires differentiated design based on the specific needs of PMOS and NMOS transistors. Currently, the industry commonly uses two methods to fabricate the metal gate structures of NMOS and PMOS transistors: The first method involves completely removing the polysilicon in the NMOS and PMOS regions, then forming metal thin film layers of different thicknesses with work function in the NMOS and PMOS regions respectively through a deposition-photolithography-etching process, and finally filling them with metal material to form the metal gate; the second method involves first removing the polysilicon in the PMOS region, filling it with metal material, and then smoothing it using a chemical mechanical polishing process, before removing the polysilicon in the NMOS region, similarly filling it with metal material, and smoothing it. However, researchers have found that in the second approach, when the polysilicon of the NMOS region is cut open, the interface at the junction of NMOS and PMOS is damaged, and a chamfer is formed at the interface. As a result, during the subsequent wet cleaning process of the cut-open NMOS region, the wet cleaning solution will penetrate into the PMOS metal gate along the chamfer and react chemically with the PMOS metal gate material, thus forming corrosion defects, which seriously affect the performance and reliability of the device.

[0004] Therefore, there is an urgent need for a method to improve corrosion defects in metal gate manufacturing processes, in order to solve the problem of corrosion defects caused by the chamfer formed at the junction of NMOS and PMOS regions.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of this invention is to provide a method and semiconductor structure for improving corrosion defects in metal gate manufacturing processes. This method addresses the problem that in existing metal gate manufacturing processes, when forming NMOS metal gates, the presence of chamfers causes wet cleaning solution to penetrate into PMOS metal gates along the chamfers and react chemically with the PMOS metal gates to form corrosion defects, thereby seriously affecting the performance and reliability of the devices.

[0007] To achieve the above objectives, the present invention provides a method for improving corrosion defects in a metal gate manufacturing process, the method comprising the following steps:

[0008] A substrate is provided in which a PMOS region and an NMOS region are formed. A PMOS metal gate and a P work function metal layer are formed in the PMOS region. An isolation layer is formed between the PMOS region and the NMOS region. Sidewalls and interlayer dielectric layers are formed on the left side of the PMOS region and the right side of the NMOS region.

[0009] A first hard mask layer and a first photoresist layer are sequentially formed on the top surface of the substrate. The first hard mask layer located on the NMOS region is removed using the first photoresist layer as a mask to expose the gate sacrificial layer in the NMOS region. The top of the isolation layer is chamfered.

[0010] A second hard mask layer is formed on the gate sacrificial layer and the first hard mask layer, wherein the thickness of the second hard mask layer at the chamfer is greater than the thickness on the first hard mask layer;

[0011] A groove is formed in the NMOS region by removing part of the second hard mask layer and the gate sacrificial layer through a etch-back process.

[0012] Metal is deposited in the groove to form an N-work function metal layer and an NMOS metal gate. A chemical mechanical polishing process is used to make the NMOS metal gate and the PMOS metal gate have flush surfaces.

[0013] Optionally, the material of the P-work function metal layer includes TiN, and the material of the N-work function metal layer includes TiAl.

[0014] Optionally, the PMOS metal gate is made of the same material as the NMOS metal gate, and the PMOS metal gate is made of aluminum.

[0015] Optionally, the material of the first hard mask layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, tantalum nitride, or titanium nitride, and the material of the second hard mask layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, tantalum nitride, or titanium nitride.

[0016] Optionally, the material of the first hard mask layer is the same as the material of the second hard mask layer.

[0017] Optionally, the thickness of the second hard mask layer ranges from 1 to 10 nm.

[0018] Optionally, the step of removing part of the second hard mask layer and the gate sacrificial layer by the etch-back process includes: removing the second hard mask layer located on the first hard mask layer and the gate sacrificial layer using a first dry etching process, at which time the part of the second hard mask layer located at the chamfer is retained; removing the gate sacrificial layer using a second dry etching process; and treating the surface of the groove to remove process residues.

[0019] Optionally, the second dry etching process selects a high selectivity etching of the gate sacrificial layer relative to the second hard mask layer.

[0020] Optionally, the material of the gate sacrificial layer includes amorphous silicon or amorphous carbon.

[0021] The present invention also provides a semiconductor structure, which is prepared by the method described above for improving corrosion defects in the metal gate process.

[0022] As described above, the method for improving corrosion defects in the metal gate fabrication process of the present invention and the semiconductor structure have the following beneficial effects: By forming a second hard mask layer at the chamfered corner of the isolation layer between the PMOS region and the NMOS region, and utilizing the characteristic of thicker deposition at the step, a thicker second hard mask layer is formed at the chamfered corner to reinforce it. Through precise control of the etching thickness in the subsequent process, it is ensured that only the second hard mask layer in the flat area is removed, while the reinforcing material at the chamfered corner is retained. This avoids the possibility of wet cleaning solution seeping into the PMOS metal gate, fundamentally solving the corrosion defect problem caused by the chemical reaction between wet cleaning solution and metal materials such as aluminum in traditional processes, thereby significantly improving the performance and reliability of the semiconductor structure. Attached Figure Description

[0023] Figure 1 The diagram shows a process flow diagram of the method for improving corrosion defects in the metal gate manufacturing process of the present invention.

[0024] Figure 2 The diagram shows a schematic of the substrate provided in the method for improving corrosion defects in the metal gate process of the present invention.

[0025] Figure 3 This is a schematic diagram of the structure after forming the first hard mask layer in the method for improving corrosion defects in the metal gate manufacturing process of the present invention.

[0026] Figure 4 The diagram shows a beveled structure formed in the method for improving corrosion defects during the metal gate manufacturing process of the present invention.

[0027] Figure 5 This is a schematic diagram of the structure after forming the second hard mask layer in the method for improving corrosion defects in the metal gate process of the present invention.

[0028] Figure 6 This is a schematic diagram of the structure after the groove is formed in the method for improving corrosion defects in the metal gate manufacturing process of the present invention.

[0029] Figure 7 The diagram shows the structure after forming an NMOS metal gate in the method for improving corrosion defects in the metal gate fabrication process of the present invention.

[0030] Component designation explanation

[0031] 10. Substrate; 11. P-work function metal layer; 12. PMOS metal gate; 13. Isolation layer; 14. Gate sacrificial layer; 151. Sidewall; 152. Interlayer dielectric layer; 16. First hard mask layer; 17. First photoresist layer; 18. Chamfer; 19. Second hard mask layer; 20. Groove; 21. N-work function metal layer; 22. NMOS metal gate; S1~S5: Steps. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0034] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0035] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0036] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] like Figure 1 As shown, this embodiment provides a method for improving corrosion defects in a metal gate manufacturing process. The method for improving corrosion defects in a metal gate manufacturing process includes the following steps:

[0038] S1: A substrate 10 is provided, in which a PMOS region and an NMOS region are formed. A PMOS metal gate 12 and a P work function metal layer 11 are formed in the PMOS region. An isolation layer 13 is formed between the PMOS region and the NMOS region. Sidewalls 151 and interlayer dielectric layers 152 are formed on the left side of the PMOS region and the right side of the NMOS region.

[0039] S2: A first hard mask layer 16 and a first photoresist layer 17 are sequentially formed on the top surface of the substrate 10. The first hard mask layer 16 located on the NMOS region is removed using the first photoresist layer 17 as a mask, exposing the gate sacrificial layer 14 in the NMOS region. A chamfered corner 18 is formed on the top of the isolation layer 13.

[0040] S3: A second hard mask layer 19 is formed on the gate sacrificial layer 14 and the first hard mask layer 16, wherein the thickness of the second hard mask layer 19 at the chamfer 18 is greater than the thickness on the first hard mask layer 16.

[0041] S4: A portion of the second hard mask layer 19 and the gate sacrificial layer 14 are removed by a back-etching process to form a groove 20 in the NMOS region;

[0042] S5: Deposit metal in the groove 20 to form an N-work function metal layer 21 and an NMOS metal gate 22, and use a chemical mechanical polishing process to make the NMOS metal gate 22 and the PMOS metal gate 12 have flush surfaces.

[0043] Here, it should be understood that the method for improving corrosion defects in the metal gate manufacturing process mentioned in this embodiment is for the post-gate process of the metal gate, but the present invention is not limited thereto. The following is a further description of the method for improving corrosion defects in the metal gate manufacturing process with reference to the accompanying drawings:

[0044] In step S1, please refer to Figure 1 and Figure 2 A substrate 10 is provided, wherein a PMOS region and an NMOS region are formed in the substrate 10, a PMOS metal gate 12 and a P work function metal layer 11 are formed in the PMOS region, an isolation layer 13 is formed between the PMOS region and the NMOS region, and sidewalls 151 and interlayer dielectric layers 152 are formed on the left side of the PMOS region and the right side of the NMOS region.

[0045] As an example, the substrate 10 may be a single-crystal, polycrystalline, or amorphous silicon substrate 10, or silicon-on-insulator (SOI), or may include other types of semiconductor materials, such as germanium, silicon carbide (SiC), or silicon-germanium (SiGe).

[0046] Specifically, in this embodiment, such as Figure 2 As shown, the substrate 10 is a common single-crystal silicon substrate, and a PMOS region and an NMOS region are formed in the substrate 10. An isolation layer 13 is formed between the PMOS region and the NMOS region. Optionally, the material of the isolation layer 13 includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride. For example, the isolation layer 13 can be a titanium nitride layer, which will not be described in detail here. Sidewalls 151 and interlayer dielectric layers 152 surrounded by sidewalls 151 are formed on the left side of the PMOS region and the right side of the NMOS region. The sidewalls 151 are in contact with the substrate 10. Optionally, the material of the sidewalls 151 includes at least one of silicon nitride and silicon dioxide. Optionally, the material of the interlayer dielectric layer 152 includes silicon oxide, silicon nitride, or other suitable dielectric materials. Specifically, in this embodiment, the material of the sidewalls 151 is silicon nitride, and the material of the interlayer dielectric layer 152 is silicon oxide.

[0047] As an example, methods for forming the P-work function metal layer 11 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0048] Specifically, in this embodiment, the P-work function metal layer 11 is made of TiN. The effective work function of the semiconductor structure is adjusted using the P-work function metal layer 11, bringing the Fermi level of the PMOS region closer to the top of the valence band of the substrate 10, thereby making the metal gate process compatible with the semiconductor process. The thickness of the P-work function metal layer 11 can be selected according to actual conditions.

[0049] like Figure 2 As shown, a PMOS metal gate 12 is formed above the P-function metal layer 11. The PMOS metal gate 12 is made of aluminum. A gate sacrificial layer 14 is filled in the NMOS region. A planarization process is performed on the top of the PMOS metal gate 12 and the top of the gate sacrificial layer 14 to obtain a flat surface, thereby helping to improve the yield of the formed semiconductor structure. Non-limiting examples of this planarization method include mechanical planarization and chemical mechanical polishing (CMP) planarization. CMP planarization is usually chosen.

[0050] In step S2, please refer to Figure 1 , Figure 3 and Figure 4 A first hard mask layer 16 and a first photoresist layer 17 are sequentially formed on the top surface of the substrate 10. The first hard mask layer 16 located on the NMOS region is removed using the first photoresist layer 17 as a mask, exposing the gate sacrificial layer 14 in the NMOS region. A chamfered corner 18 is formed on the top of the isolation layer 13.

[0051] Specifically, a first hard mask layer 16 is formed on the top surface of the substrate 10 by chemical vapor deposition of a dielectric material. The first hard mask layer 16 covers the top of the PMOS and NMOS regions and serves as a protective layer for the PMOS region during subsequent etching of the gate sacrificial layer 14 in the NMOS region. Then, a first photoresist layer 17 is formed on the first hard mask layer 16. Using the first photoresist layer 17 as a mask, a notch is formed above the NMOS region to be etched using photolithography. Figure 3 As shown, the first hard mask layer 16 above the NMOS region is etched away using a dry etching process, thereby exposing the gate sacrificial layer 14 in the NMOS region, and then the first photoresist layer 17 is removed. Here, it should be understood that, as... Figure 4As shown, when the first hard mask layer 16 is removed using a dry etching process, a portion of the gate sacrificial layer 14 and the isolation layer 13 in the NMOS region will be etched away, thereby forming a chamfer 18 on the top of the isolation layer 13. Since the gate sacrificial layer 14 needs to be etched away later, removing a portion of the gate sacrificial layer 14 at this time does not affect the subsequent process.

[0052] Specifically, the first photoresist layer 17 can be removed by ashing.

[0053] As an example, the material of the first hard mask layer 16 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, tantalum nitride, or titanium nitride. For example, the first hard mask layer 16 may be titanium nitride.

[0054] In step S3, please refer to Figure 1 and Figure 5 A second hard mask layer 19 is formed on the gate sacrificial layer 14 and the first hard mask layer 16, wherein the thickness of the second hard mask layer 19 at the chamfer 18 is greater than the thickness on the first hard mask layer 16.

[0055] Specifically, such as Figure 5 As shown, a second hard mask layer 19 is formed by depositing dielectric material again on the top surface of the gate sacrificial layer 14 and the first hard mask layer 16 using a chemical vapor deposition process. Since the chemical vapor deposition process has the characteristic of depositing a thicker layer at the step, the thickness of the second hard mask layer 19 at the chamfer 18 is greater than the thickness of the first hard mask layer 16. This means that when the second hard mask layer 19 is removed by subsequent etching, the second hard mask layer 19 located at the chamfer 18 is partially removed. The remaining second hard mask layer 19 reinforces the chamfer 18, thereby preventing the wet cleaning solution from entering the PMOS metal gate 12 through the chamfer 18 during subsequent wet cleaning. This fundamentally eliminates the problem of corrosion defects caused by the chemical reaction between the wet cleaning solution and the metal material.

[0056] As an example, the thickness of the second hard mask layer 19 ranges from 1 to 10 nm. For example, the thickness of the second hard mask layer 19 is 1 nm, 5 nm or 10 nm, so that it can both reinforce the chamfer 18 and not be too thick to increase the complexity of the subsequent removal process.

[0057] As an example, the material of the second hard mask layer 19 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, tantalum nitride, or titanium nitride, and the material of the first hard mask layer 16 is the same as that of the second hard mask layer 19. Therefore, when the first hard mask layer 16 is titanium nitride, the second hard mask layer 19 should also be titanium nitride to facilitate subsequent etching.

[0058] In step S4, please refer to Figure 1 and Figure 6 A portion of the second hard mask layer 19 and the gate sacrificial layer 14 are removed by a back-etching process, forming a groove 20 in the NMOS region.

[0059] Specifically, the step of removing part of the second hard mask layer 19 and the gate sacrificial layer 14 includes first using a first dry etching process to remove the second hard mask layer 19 located on the first hard mask layer 16 and the gate sacrificial layer 14, such as... Figure 6 As shown, at this point, a portion of the second hard mask layer 19 located at the chamfer 18 is retained, and the remaining second hard mask layer 19 reinforces the chamfer 18. Then, the second dry etching process is used to remove the gate sacrificial layer 14, and the surface of the groove 20 is treated to remove process residues. The etching gas composition, flow rate, and process conditions used in the first and second dry etching processes are well known in the art, and those skilled in the art can select and adjust them according to actual needs. Further details are not provided here.

[0060] The second dry etching process selects the gate sacrificial layer 14 for high selectivity etching relative to the second hard mask layer 19, thereby avoiding damage to the retained second hard mask layer 19, and the PMOS metal gate 12 is not etched during the second dry etching process.

[0061] Optionally, the material of the gate sacrificial layer 14 includes either amorphous silicon or amorphous carbon. For example, if the gate sacrificial layer 14 is made of amorphous silicon, after removing the gate sacrificial layer 14 using the second dry etching process to form the groove 20, the etched groove 20 must be cleaned to ensure that the amorphous silicon and process residues in the groove 20 are completely removed. Due to the presence of the aforementioned second hard mask layer 19, the wet cleaning solution cannot enter the PMOS metal gate 12 through the chamfer 18, fundamentally eliminating the problem of corrosion defects caused by the chemical reaction between the wet cleaning solution and the metal material.

[0062] In step S5, please refer to Figure 1 and Figure 7 Metal is deposited in the groove 20 to form an N-work function metal layer 21 and an NMOS metal gate 22. A chemical mechanical polishing process is used to make the NMOS metal gate 22 and the PMOS metal gate 12 have flush surfaces.

[0063] As an example, methods for forming the N-work function metal layer 21 and the NMOS metal gate 22 include sputtering, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. Specifically, in this embodiment, before depositing the NMOS metal gate 22, the N-work function metal layer 21 is first formed in the groove 20 using sputtering. In this embodiment, the material of the N-work function metal layer 21 is TiAl. The effective work function of the semiconductor structure is adjusted using the N-work function metal layer 21, so that the Fermi level of the NMOS region is close to the conduction band bottom of the substrate 10. The thickness of the N-work function metal layer 21 can be selected according to the actual situation.

[0064] Then, metal is deposited in the groove 20 to form an NMOS metal gate 22. The material of the PMOS metal gate 12 is the same as that of the NMOS metal gate 22. Finally, the remaining first hard mask layer 16 is removed by chemical mechanical polishing, so that the NMOS metal gate 22 and the PMOS metal gate 12 have flush surfaces.

[0065] In another embodiment of the invention, a semiconductor structure, such as... Figure 7 As shown, the semiconductor structure is formed using the method described above for improving corrosion defects in the metal gate process.

[0066] In summary, the method and semiconductor structure for improving corrosion defects in the metal gate fabrication process proposed in this invention utilize the characteristic of depositing a thicker second hard mask layer at the step during the deposition process. An even thicker second hard mask layer is formed at the chamfered corner of the isolation layer between the PMOS and NMOS regions. Through precise control of the subsequent etching thickness, it is ensured that the second hard mask layer in the flat area and part of the second hard mask layer at the chamfered corner are removed, while the remaining second hard mask layer at the chamfered corner is retained. This reinforces the chamfered corner and prevents the possibility of wet cleaning solution seeping into the PMOS metal gate during subsequent wet cleaning of the groove. This fundamentally solves the corrosion defect problem caused by the chemical reaction between wet cleaning solution and metal materials such as aluminum in traditional processes, thereby significantly improving the performance and reliability of the semiconductor structure. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving corrosion defects in a metal gate manufacturing process, characterized in that, The method for improving corrosion defects in the metal gate manufacturing process includes the following steps: A substrate is provided in which a PMOS region and an NMOS region are formed. A PMOS metal gate and a P work function metal layer are formed in the PMOS region. An isolation layer is formed between the PMOS region and the NMOS region. Sidewalls and interlayer dielectric layers are formed on the left side of the PMOS region and the right side of the NMOS region. A first hard mask layer and a first photoresist layer are sequentially formed on the top surface of the substrate. The first hard mask layer located on the NMOS region is removed using the first photoresist layer as a mask to expose the gate sacrificial layer in the NMOS region. The top of the isolation layer is chamfered. A second hard mask layer is formed on the gate sacrificial layer and the first hard mask layer, wherein the thickness of the second hard mask layer at the chamfer is greater than the thickness on the first hard mask layer; A groove is formed in the NMOS region by removing part of the second hard mask layer and the gate sacrificial layer through a etch-back process. Metal is deposited in the groove to form an N-work function metal layer and an NMOS metal gate. A chemical mechanical polishing process is used to make the NMOS metal gate and the PMOS metal gate have flush surfaces.

2. The method for improving corrosion defects in the metal gate manufacturing process according to claim 1, characterized in that, The material of the P-work function metal layer includes TiN, and the material of the N-work function metal layer includes TiAl.

3. The method for improving corrosion defects in the metal gate manufacturing process according to claim 1, characterized in that, The PMOS metal gate is made of the same material as the NMOS metal gate, and the PMOS metal gate is made of aluminum.

4. The method for improving corrosion defects in the metal gate manufacturing process according to claim 1, characterized in that, The material of the first hard mask layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, tantalum nitride, or titanium nitride, and the material of the second hard mask layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, tantalum nitride, or titanium nitride.

5. The method for improving corrosion defects in the metal gate manufacturing process according to claim 4, characterized in that, The material of the first hard mask layer is the same as that of the second hard mask layer.

6. The method for improving corrosion defects in the metal gate manufacturing process according to claim 4, characterized in that, The thickness of the second hard mask layer ranges from 1 to 10 nm.

7. The method for improving corrosion defects in the metal gate manufacturing process according to claim 1, characterized in that: The step of removing a portion of the second hard mask layer and the gate sacrificial layer by an etching process includes: removing the second hard mask layer located on the first hard mask layer and the gate sacrificial layer using a first dry etching process, wherein the portion of the second hard mask layer located at the chamfer is retained; removing the gate sacrificial layer using a second dry etching process; and treating the surface of the groove to remove process residues.

8. The method for improving corrosion defects in the metal gate manufacturing process according to claim 7, characterized in that, The second dry etching process selects a high selectivity etching ratio for the gate sacrificial layer relative to the second hard mask layer.

9. The method for improving corrosion defects in the metal gate manufacturing process according to claim 1, characterized in that, The material of the gate sacrificial layer includes either amorphous silicon or amorphous carbon.

10. A semiconductor structure, characterized in that, It is prepared by the method for improving corrosion defects in the metal gate manufacturing process according to any one of claims 1 to 9.

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