An SOI-LIGBT integrated with a diode and a clamp mosfet
Patent Information
- Application Number
- CN202610720982.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-25
- Publication Date
- 2026-08-21
AI Technical Summary
然而由于阳极N+区的引入，降低了导通状态下空穴的注入效率，从而导致导通压降增大，更严重的是存在Snapback电压回折现象
[0014]本发明的有益效果在于：本发明在传统LIGBT器件的基础上，在阳极处集成了二极管喝MOSFET，让器件处于一种类似MOS的阻断机制，提高了器件的耐压能力。其中二极管作为反向导通路径，摆脱了传统阳极短路LIGBT的负阻效应。
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Figure CN122622334A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device technology and relates to an SOI-LIGBT that integrates a diode and a clamping MOSFET. Background Technology
[0002] An IGBT (Insulated Gate Bipolar Transistor) is a bipolar composite power semiconductor device that combines the fast switching speed of a MOSFET with the low conduction loss of a BJT. Its development stemmed from the demand in the power electronics field for efficient, high-power switching devices. The LIGBT structure was first proposed in the mid-1980s. At that time, the power semiconductor device field was constantly exploring how to better combine the advantages of different devices to meet the performance requirements of increasingly diverse application scenarios. Early LIGBTs replaced the N+ drain region of an LDMOS with a P+ drain region, thereby introducing a PN junction at the collector. Under certain conditions, the PN junction turned on, injecting holes into the drift region to form a bipolar carrier conduction mode, significantly reducing the specific on-resistance of the device. Due to these advantages, LIGBTs are widely used in power electronics, new energy, and other fields.
[0003] Unlike LDMOS, LIGBTs lack reverse conduction capability. Therefore, in electronic circuits and smart power supplies, IGBTs are typically connected in parallel with diodes for switching, a method that struggles to improve the utilization rate per unit package area. To address this, engineers designed reverse-conducting IGBTs (RC-LIGBTs) by adding a short anode to the LIGBT's anode. However, in the traditional RC-IGBT device structure, the anode N+ and P+ regions are shorted together by the anode electrode, introducing a parasitic diode within the device, granting it reverse conduction capability. During device turn-off, the anode N+ region can directly extract electrons from the drift region, improving the device's switching speed and reducing turn-off losses. However, the introduction of the anode N+ region reduces hole injection efficiency during conduction, leading to increased on-state voltage drop and, more seriously, a snapback voltage phenomenon. When the on-current is small, the electrons injected into the NMOS flow directly out of the anode N+ region, the P+ / N-buffer junction is not turned on, the device is in unipolar mode, and the on-resistance is high. As the on-current gradually increases, the voltage drop generated by the electrons flowing through the N-buffer region below the P+ region gradually increases. When the voltage drop is greater than the built-in potential of the P+ / N-buffer junction, the P+ region begins to inject holes into the drift region, resulting in a conductivity modulation effect. The device enters bipolar mode, the resistance drops significantly, and the snapback phenomenon occurs.
[0004] To address the aforementioned problems, the present invention LIGBT is proposed. Summary of the Invention
[0005] The purpose of this invention is to provide an SOI-LIGBT device integrating a diode and a clamping MOSFET. By integrating a clamping NMOS and an integrated diode into a traditional LIGBT structure, this LIGBT achieves reverse conduction while eliminating the voltage foldback phenomenon caused by the short anode N+, ensuring good forward conduction performance. The clamping NMOS and the cathode trench gate can regulate the leakage current during forward withstand voltage, resulting in a more uniform electric field distribution and superior withstand voltage compared to traditional LIGBTs. Furthermore, the cathode of the integrated diode and the drain of the clamping NMOS are shared, improving the device's integration density.
[0006] To achieve the above objectives, the present invention provides the following technical solution:
[0007] An SOI-LIGBT device integrating a diode and a clamped MOSFET, the device comprising: a cathode trench gate 1, a cathode P+ region 2, a cathode N+ region 3, a cathode P-well region 4, a drift region 5, a silicon dioxide buried oxide layer 6, a P-type substrate region 7, an IGBT gate silicon dioxide oxide layer 8, an anode N-buffer region 9, an anode P+ region 10, an anode N+ region 11, an oxide isolation layer 12, an integrated diode P+ region 13, a clamped NMOS N1+ region 14, a clamped NMOS gate oxide layer 15, a clamped NMOS N2+ region 16, and a clamped NMOS P-base region 17.
[0008] The typical MOS region consists of a cathode trench gate 1, a cathode P+ region 2, a cathode N+ region 3, a cathode P-well region 4, a drift region 5, and an IGBT gate silicon dioxide oxide layer 8. The cathode P+ region 2 and the cathode N+ region 3 are adjacent and are located above the P-well region 4. The drift region 4 is located below the cathode P-well region 4. The IGBT gate silicon dioxide oxide layer 8 is located above the cathode N+ region 3, the cathode P-well region 4, and part of the drift region 5. The cathode trench gate 1 penetrates the cathode P-well region 4 and partially contacts the drift region 4, with its location being the same as that of the cathode.
[0009] The anode region consists of the anode P+ region 10 and the anode N-buffer region 9; the anode P+ region 10 is completely surrounded by the anode N-buffer region 9; the drift region 4 is located below the anode N-buffer region 9.
[0010] The integrated diode is composed of an integrated diode P+ region 13 and a clamped NMOS N1+ region 14. The integrated diode P+ region 13 is connected to the anode N+ region 11 through a floating electrode, and the clamped NMOS N1+ region 14 is connected to the anode collector.
[0011] The clamped NMOS is composed of clamped NMOS N1+ region 14, clamped NMOS gate oxide layer 15, clamped NMOS N2+ region 16, and clamped NMOS P-base region 17; clamped NMOS gate oxide layer 15 is connected to the anode collector, and clamped NMOS N2+ region 16 is connected to anode N+ region 11 through a floating electrode.
[0012] During reverse conduction, the current flows through the PN junction between the cathode P-well region 4 and the drift region 5, from the anode N+ region 11 to the floating electrode, and then through the floating electrode to the integrated diode P+ region 13 of the device, flowing out from the clamped NMOS N1+ region 14. The circuit is equivalent to two diodes connected in series by a wire.
[0013] In traditional LIGBTs, leakage current flows to the anode P+ region 10, causing the internal parasitic PNP to achieve an open-base region PNP blocking mechanism. The LIGBT provided by this invention, with its anode-integrated clamped NMOS, allows most of the leakage current to flow out of the clamped NMOS during forward withstand voltage testing. This prevents the parasitic PNP from entering an open-base region blocking mode, instead placing the device in a MOS-like blocking mechanism. The leakage current flows from the anode N+ region 11 to the floating electrode, then from the clamped NMOS N2+ region 16 to the clamped NMOS N1+ region 14 before flowing out again. Furthermore, during forward withstand voltage testing, the cathode trench gate 1 allows some leakage current to flow below the cathode P-well region 4, preventing electric field concentration.
[0014] The beneficial effects of this invention are as follows: Based on the traditional LIGBT device, this invention integrates a diode and a MOSFET at the anode, allowing the device to operate in a blocking mechanism similar to that of a MOSFET, thereby improving the device's voltage withstand capability. The diode, acting as a reverse conduction path, eliminates the negative resistance effect of traditional anode-short-circuited LIGBTs.
[0015] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description
[0016] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:
[0017] Figure 1This is a schematic diagram of the RFC-LIGBT (Reverse-Conducting with Floating-electrode Clamping SOI-LIGBT) device structure provided in Embodiment 1 of the present invention;
[0018] Figure 2 for Figure 1 The equivalent circuit diagram of the device is shown below;
[0019] Figure 3 This invention illustrates the effect of drift region doping on forward breakdown voltage in Embodiment 1 of the present invention, along with SSA-LIGBT, TBSA-LIGBT, and cov-LIGBT.
[0020] Figure 4 This invention provides an example of the forward conduction behavior of Example 1 of the present invention, SSA-LIGBT, TBSA-LIGBT, and cov-LIGBT at the same drift region concentration.
[0021] Figure 5 This describes the reverse conduction situation of Embodiment 1 of the present invention with SSA-LIGBT and TBSA-LIGB at the same drift region concentration.
[0022] Figure reference numerals: 1. Cathode trench gate; 2. Cathode P+ region; 3. Cathode N+ region; 4. Cathode P-well region; 5. Drift region; 6. Silicon dioxide buried oxide layer; 7. P-type substrate region; 8. IGBT gate silicon dioxide oxide layer; 9. Anode N-buffer region; 10. Anode P+ region; 11. Anode N+ region; 12. Oxide isolation layer; 13. Integrated diode P+ region; 14. Clamped NMOS N1+ region; 15. Clamped NMOS gate oxide layer; 16. Clamped NMOS N2+ region; 17. Clamped NMOS P-base region. Detailed Implementation
[0023] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0024] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.
[0025] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.
[0026] Example 1:
[0027] like Figure 1 As shown, this embodiment improves upon the traditional SOI-LIGBT device to obtain an SOI-LIGBT device that incorporates an integrated diode and a self-biased clamping MOSFET. The device includes: a cathode trench gate 1, a cathode P+ region 2, a cathode N+ region 3, a cathode P-well region 4, a drift region 5, a silicon dioxide buried oxide layer 6, a P-type substrate region 7, an IGBT gate silicon dioxide oxide layer 8, an anode N-buffer region 9, an anode P+ region 10, an anode N+ region 11, an oxide isolation layer 12, an integrated diode P+ region 13, a clamping NMOS N1+ region 14, a clamping NMOS gate oxide layer 15, a clamping NMOS N2+ region 16, and a clamping NMOS P-base region 17.
[0028] The ordinary MOS region consists of a cathode trench gate 1, a cathode P+ region 2, a cathode N+ region 3, a cathode P-well region 4, a drift region 5, and an IGBT gate silicon dioxide oxide layer 8. The cathode P+ region 2 and the cathode N+ region 3 are adjacent to each other and are located above the cathode P-well region 4. The drift region 5 is located below the cathode P-well region. The IGBT gate silicon dioxide oxide layer 8 is located above the cathode N+ region 3, the cathode P-well region 4, and part of the drift region 5.
[0029] The anode PNP transistor consists of an anode P+ region 10, an anode N-buffer region 9, a drift region 5, and a cathode P-well region 4. The anode P+ region 10 and the anode N+ region 11 are completely enclosed by the anode N-buffer region 9. The left and lower sides of the anode N-buffer region 9 are completely enclosed by the drift region 5. The lower and right sides of the cathode P-well region 4 are enclosed by the drift region 5. When forward conducting, the anode PNP transistor mainly provides a hole path.
[0030] The forward clamped NMOS consists of a P-base region 17, a clamped NMOS N1+ region 14, a clamped NMOS gate oxide layer 15, and a clamped NMOS N2+ region 16. The forward clamped NMOS region and the IGBT region are separated by an oxide isolation layer 12. The clamped NMOS N2+ region 16 is connected to the anode N+ region 11 through a floating electrode. The clamped NMOS N1+ region 14 and the clamped NMOS gate oxide layer 15 are shorted to the collector of the IGBT.
[0031] An integrated diode is integrated in the forward clamping NMOS region. An integrated diode P+ region 13 is added to the left of the clamping NMOS N1+ region 14. The cathode of this diode is shared with the drain of the forward clamping NMOS, which is the clamping NMOS N1+ region 14. The integrated diode P+ region 13 is the diode anode, which is connected to the anode N+ region 11 through a floating electrode.
[0032] This embodiment uses SENTAURUS simulation software to perform performance simulation analysis on the SOI-LIGBT device described in Example 1, analyze its mechanism, and perform electrical simulation. During the simulation, all simulation parameters of the device in Example 1 are consistent with those of SSA-LIGBT, cov-LIGBT, and TBSA-LIGBT, with a carrier lifetime of 10 μs and an ambient temperature of 300 K.
[0033] like Figure 2 The diagram shown is the equivalent circuit diagram of the device in Embodiment 1, where the IGBT is equivalent to an N-type MOSFET, an NPN transistor, and a PNP transistor. Based on this, Embodiment 1 integrates a clamping N-type MOSFET and a reverse conduction diode, and does not require additional electrical signal control, so no additional control circuit is needed in practical applications.
[0034] like Figure 3The figure shows the trend of forward breakdown voltage of Example 1 with different drift region doping as the drift region length is 20 μm. It can be seen from the curve that Example 1 and TBSA-LIGBT both obtained the optimal breakdown voltage with drift region doping of 1.7 × 10¹⁵ cm⁻³, and the forward conduction voltage drop is also in the excellent range. Therefore, 1.7 × 10¹⁵ cm⁻³ is the optimal drift region doping for Example 1.
[0035] like Figure 4 The figure shows the forward conduction performance of Example 1 with a device drift region length of 20 μm and a drift region doping concentration of 2.0 × 10¹⁵ cm⁻³, compared with that of SSA-LIGBT, cov-LIGBT, and TBSA-LIGBT. From the forward conduction curve, it can be clearly seen that Example 1 completely eliminates the negative resistance effect caused by the anode short-circuit LIGBT, while TBSA-LIGBT and SSA-LIGBT weaken the negative resistance effect through the resistance of the drift region. Example 1 greatly improves the reliability.
[0036] like Figure 5 The figure shows the reverse conduction performance of Example 1 with SSA-LIGBT and TBSA-LIGBT when the device drift region length is 10.5 μm and the drift region doping concentration is 2.0×10¹⁵ cm⁻³.
[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. An SOI-LIGBT device integrating a diode and a clamped MOSFET, comprising a cathode trench gate (1), a cathode P+ region (2), a cathode N+ region (3), a cathode P-well region (4), a drift region (5), a silicon dioxide buried oxide layer (6), a P-type substrate region (7), an IGBT gate silicon dioxide oxide layer (8), an anode N-buffer region (9), an anode P+ region (10), an anode N+ region (11), an oxide isolation layer (12), an integrated diode P+ region (13), a clamped NMOS N1+ region (14), a clamped NMOS gate oxide layer (15), a clamped NMOS N2+ region (16), and a clamped NMOS P-base region (17); The ordinary MOS region is composed of a cathode trench gate (1), a cathode P+ region (2), a cathode N+ region (3), a cathode P-well region (4), a drift region (5), and an IGBT gate silicon dioxide oxide layer (8); wherein the cathode P+ region (2) and the cathode N+ region (3) are adjacent to each other and are located above the P-well region (4); the drift region (4) is located below the cathode P-well region (4); the IGBT gate silicon dioxide oxide layer (8) is located above the cathode N+ region (3), the cathode P-well region (4), and part of the drift region (5); the cathode trench gate (1) penetrates the cathode P-well region (4) and is partially in contact with the drift region (4), and its position is the same as that of the cathode; The anode region consists of an anode P+ region (10) and an anode N-buffer region (9); the anode P+ region (10) is completely enclosed by the anode N-buffer region (9); the drift region (4) is located below the anode N-buffer region (9). The integrated diode is composed of an integrated diode P+ region (13) and a clamped NMOS N1+ region (14). The integrated diode P+ region (13) is connected to the anode N+ region (11) through a floating electrode, and the clamped NMOS N1+ region (14) is connected to the anode collector. The clamped NMOS is composed of the clamped NMOS N1+ region (14), the clamped NMOS gate oxide layer (15), the clamped NMOS N2+ region (16), and the clamped NMOS P-base region (17); the clamped NMOS gate oxide layer (15) is connected to the anode collector, and the clamped NMOS N2+ region (16) is connected to the anode N+ region (11) through a floating electrode.
2. An SOI-LIGBT device integrating a diode and a clamping MOSFET as claimed in claim 1, characterized in that... The clamping MOSFET integrates a diode, which is easy to achieve in terms of manufacturing process.
3. An SOI-LIGBT device integrating a diode and a clamping MOSFET according to claim 1 or 2, characterized in that, By connecting the P+ region (13) of the integrated diode in series with the N+ region (11) of the anode through a floating electrode, the voltage foldback phenomenon that exists in the forward operation of RC-LIGBT is eliminated.
4. An SOI-LIGBT device integrating a diode and a clamping MOSFET according to claim 1 or 2, characterized in that, Clamped MOSFETs and cathode trench gates can regulate leakage current during forward withstand voltage, resulting in a more uniform electric field distribution, avoiding electric field concentration, and improving breakdown voltage.