Integrated chip and method of forming the same

Abstract

In some embodiments, the disclosure relates to an integrated chip. The integrated chip includes a lower source / drain on a substrate, a channel on the lower source / drain, and an upper source / drain on the channel. A plurality of gate electrodes is disposed along opposite sides of the channel. The channel includes a channel material laterally surrounding an insulating core on the lower source / drain. The channel material laterally separates the insulating core from the plurality of gate electrodes.

Description

Technical Field

[0001] This invention relates to an integrated chip and a method for forming the same. Background Technology

[0002] Modern integrated circuits comprise millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., a silicon substrate). These semiconductor devices are electrically interconnected via interconnect structures. Interconnect structures include interconnect wires and interconnect vias disposed within a dielectric structure on the semiconductor substrate. By electrically coupling multiple semiconductor devices together using interconnect structures, these devices can perform the logic functions that enable the operation of the integrated circuit. Summary of the Invention

[0003] An integrated chip according to this disclosure includes: a lower source / drain electrode located on a substrate; a channel disposed on the lower source / drain electrode; an upper source / drain electrode located on the channel; and a plurality of gate electrodes disposed along opposite sides of the channel; wherein the channel includes a channel material laterally surrounding an insulating core located on the lower source / drain electrode, the channel material laterally separating the insulating core from the plurality of gate electrodes.

[0004] This disclosure discloses a method for forming an integrated chip, comprising: forming a lower source / drain contact within a lower interlayer dielectric (ILD) layer above a substrate; forming a sacrificial structure over the lower source / drain contact and the lower ILD layer; patterning the sacrificial structure to form sacrificial pillars over the lower source / drain contact; forming a plurality of gate structures over the lower ILD layer and along opposite sidewalls of the sacrificial pillars; removing the sacrificial pillars to form a channel opening between the plurality of gate structures and expose the lower source / drain contact; and forming a channel within the channel opening, wherein the channel comprises a channel material having a plurality of inner sidewalls facing opposite sides of an insulating core.

[0005] This disclosure discloses a method for forming an integrated chip, comprising: forming a lower source / drain contact within a lower interlayer dielectric (ILD) layer above a substrate; forming a sacrificial pillar above the lower source / drain contact; forming a plurality of gate structures above the lower ILD layer and along opposite sidewalls of the sacrificial pillar; removing the sacrificial pillar to form a channel opening between the plurality of gate structures; and forming a channel material within the channel opening and along a plurality of sidewalls of the plurality of gate structures, wherein the channel material includes one or more inner surfaces spaced apart from each other by a space directly above the lower source / drain contact. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. These drawings are provided to clearly illustrate relevant aspects of the embodiments. The drawings may illustrate the relationships between various structures and / or elements within the embodiments. It should be noted that these drawings are not necessarily drawn to scale. In some cases, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 Some embodiments of an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels comprising channel material surrounding an insulating core.

[0008] Figure 2 Additional embodiments of an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels comprising channel material surrounding an insulating core.

[0009] Figure 3 Additional embodiments of an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels comprising channel material surrounding an insulating core comprising channel insulating material.

[0010] Figures 4A to 4B Additional embodiments of an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels comprising channel material surrounding an insulating core, the insulating core including air gaps.

[0011] Figure 5 Additional embodiments of an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels comprising channel material surrounding an insulating core, the insulating core comprising channel insulating material and air gaps.

[0012] Figure 6 Additional embodiments of an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels comprising channel material surrounding an insulating core.

[0013] Figures 7A to 7B Some embodiments of integrated chip memory structures with vertical transistors are shown, wherein the vertical transistors have channels comprising channel material surrounding an insulating core.

[0014] Figures 8 to 17 Cross-sectional views of some embodiments of a method for forming an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels comprising channel material surrounding an insulating core comprising channel insulating material.

[0015] Figures 18 to 27Cross-sectional views of some additional embodiments of a method for forming an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels including channel material surrounding an insulating core, the insulating core including air gaps.

[0016] Figure 28 Flowcharts of some embodiments of a method for forming an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels including channel material surrounding an insulating core. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments where the first and second features are in direct contact, and can also include embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship of an element or feature as shown in the figures to other elements or features. In addition to the orientations shown in the figures, spatially relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In some embodiments, the terms “about” and / or “approximately” may be interpreted as + / - 10% or + / - 5%, while in other embodiments, the terms “about” and / or “approximately” may be interpreted as within the normal manufacturing tolerances of a given manufacturing process.

[0019] A vertical transistor (e.g., a vertical field-effect transistor, VFET) is a transistor with a channel structure extending between its source and drain regions along a direction perpendicular to the upper surface of the underlying semiconductor substrate. Vertical transistors typically have stacked source and drain regions to allow current to flow vertically. Vertical transistors enable the miniaturization of transistors, thereby increasing the density of integrated chip devices and improving the performance of integrated chips. The advantages achieved by vertical transistors can be applied to power electronics (e.g., efficiently handling higher currents and voltages), high-frequency applications (e.g., due to fast switching capabilities), and more.

[0020] However, it has been recognized that the structure and / or materials used in vertical transistors can also present challenges. For example, materials used in vertical transistors may be susceptible to higher leakage current, increased power consumption, and reduced energy efficiency. Some materials may also increase unwanted parasitic capacitance, thus limiting switching speed and high-frequency performance. Furthermore, these materials may be susceptible to thermal damage, affecting thermal stability and performance in high-power applications. These challenges may inhibit the effectiveness of vertical transistors in high-efficiency and / or low-power settings.

[0021] This disclosure relates to an integrated chip structure including a vertical transistor having a channel comprising a channel material surrounding an insulating core. In some embodiments, the integrated chip structure includes a lower source / drain above a substrate, a channel above the lower source / drain, and an upper source / drain above the channel. Multiple gate structures are arranged along opposite sides of the channel. The channel includes a channel material laterally surrounding an insulating core located above the lower source / drain. The channel material laterally separates the insulating core from the gate structures. The insulating core of the channel improves the insulation performance of the channel, thereby reducing leakage current between the lower and upper source / drain. The reduced leakage current can lower the overall power consumption of the integrated chip structure (e.g., improve overall energy efficiency).

[0022] Figure 1 Some embodiments of an integrated chip structure 100 with vertical transistors are shown, wherein the vertical transistors have channels including channel material surrounding an insulating core.

[0023] The integrated chip structure 100 includes a vertical transistor having a lower source / drain 104 vertically separated from an upper source / drain 118 via a channel 112. In some embodiments, the lower source / drain 104 may be disposed on, above, and / or within a substrate 102. One or more gate structures 106 are disposed above the lower source / drain 104 along one or more sides of the channel 112. Each of the one or more gate structures 106 includes a gate electrode 108 and a gate dielectric layer 110. The gate dielectric layer 110 separates the gate electrode 108 from the channel 112.

[0024] Channel 112 includes channel material 114 and an insulating core 116. The insulating core 116 is laterally surrounded by channel material 114 on opposite sides, thereby separating the opposite sides of the insulating core 116 from one or more gate structures 106. The insulating core 116 of channel 112 improves the insulation performance of channel 112, thus reducing the leakage current between the lower source / drain 104 and the upper source / drain 118. The reduced leakage current can reduce the overall power consumption of the integrated chip structure 100 (e.g., improve overall energy efficiency).

[0025] Furthermore, the insulating core 116 can reduce parasitic capacitance and improve the thermal performance of the channel 112. For example, the insulating core 116 can reduce parasitic capacitance between adjacent gate structures, thereby enabling faster switching speeds and improving the high-frequency performance of the vertical transistor. The insulating core 116 can also reduce heat transfer between different segments of the channel material 114, thereby improving thermal stability and ensuring better performance of the vertical transistor in high-temperature or high-power applications. Enhanced thermal stability can reduce the risk of overheating and improve device reliability and lifespan. Improvements in electrical and thermal characteristics can enable further miniaturization of electronic components and the creation of more compact and efficient electronic devices.

[0026] Figure 2 Some additional embodiments of an integrated chip structure 200 with vertical transistors are shown, wherein the vertical transistors have channels including channel material surrounding an insulating core.

[0027] The integrated chip structure 200 includes an inter-level dielectric (ILD) structure 202 disposed on a substrate 102. The ILD structure 202 comprises multiple ILD layers stacked on top of each other. Multiple vertical transistors are arranged within the ILD structure 202. The vertical transistors include multiple lower source / drain and upper source / drain electrodes separated by multiple channels 112.

[0028] In some embodiments, the plurality of lower source / drain electrodes include a plurality of lower source / drain contacts 204 disposed within the ILD structure 202, and the plurality of upper source / drain electrodes include a plurality of upper source / drain contacts 206 disposed within the ILD structure 202 above the plurality of lower source / drain contacts 204. In some embodiments (not shown), one or more conductive interconnect structures (e.g., conductive contacts, interconnect wires, and / or interconnect vias) may be configured within the ILD structure 202 between the plurality of lower source / drain contacts 204 and the substrate 102. In some embodiments, the plurality of lower source / drain contacts 204 may include source contacts, and the plurality of upper source / drain contacts 206 may include drain contacts. In other embodiments, the plurality of lower source / drain contacts 204 may include drain contacts, and the plurality of upper source / drain contacts 206 may include source contacts.

[0029] Multiple gate structures 106 are disposed within an ILD structure 202 located perpendicularly between multiple lower source / drain contacts 204 and multiple upper source / drain contacts 206. The multiple gate structures 106 are arranged along opposite sides of the multiple lower source / drain contacts 204. For example, in some embodiments, the multiple gate structures 106 may span opposite outermost walls of the multiple lower source / drain contacts 204. The multiple gate structures 106 include a gate electrode 108 and a gate dielectric layer 110 extending along multiple outer surfaces of the gate electrode 108. In some embodiments, the gate dielectric layer 110 surrounds multiple sidewalls and the bottom surface of the gate electrode 108. In some embodiments, the gate dielectric layer 110 vertically separates the multiple lower source / drain contacts 204 from the gate electrode 108.

[0030] Multiple channels 112 are vertically arranged between multiple lower source / drain contacts 204 and multiple upper source / drain contacts 206, and laterally arranged between adjacent gate structures 106. In some embodiments, a gate dielectric layer 110 laterally separates a gate electrode 108 from the multiple channels 112 arranged along opposite sides of the gate electrode 108. Each of the multiple channels 112 includes a channel material 114 and an insulating core 116. The insulating core is laterally surrounded on opposite sides by the channel material 114, thereby separating the opposite sides of the insulating core 116 from the multiple gate structures 106. In some embodiments, the multiple channels 112 may each have a width that decreases with increasing height above the substrate 102, and the multiple gate structures 106 may each have a width that increases with increasing height above the substrate 102.

[0031] Figure 3Some additional embodiments of an integrated chip structure 300 with vertical transistors are shown, wherein the vertical transistors have channels including channel material surrounding an insulating core, the insulating core including channel insulating material.

[0032] The integrated chip structure 300 includes an ILD structure 202 located on a substrate 102. The ILD structure 202 includes multiple ILD layers 202a and 202b stacked on top of each other. For example, the ILD structure 202 may include a first ILD layer 202a and a second ILD layer 202b stacked on the first ILD layer 202a. The multiple ILD layers 202a and 202b may respectively include silicon dioxide, silicon oxynitride (SiN), silicon carbonitride (SiCN), titanium oxide (TiOx), amorphous silicon (a-Si), amorphous carbon (aC), carbon-doped silicon oxide (SiCOH), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), borosilicate glass (BSG), fluorosilicate glass (FSG), undoped silicate glass (USG), and / or the like. In some embodiments, the thickness of the first ILD layer 202a may be in the range of about 1 nanometer (nm) to about 150 nm, about 50 nm to about 150 nm, or other similar values.

[0033] The ILD structure 202 includes a plurality of lower source / drain contacts 204. In some embodiments, the plurality of lower source / drain contacts 204 each include a central upper surface 205c and a peripheral upper surface 205p laterally surrounding the central upper surface 205c. The peripheral upper surface 205p is a non-zero distance 302 perpendicularly below the central upper surface 205c. The height of the plurality of lower source / drain contacts 204 along the central upper surface 205c is greater than the height along the peripheral upper surface 205p. In some embodiments, the plurality of lower source / drain contacts 204 each include a bottom surface having a first width, a top surface having a second width, and a third width perpendicularly positioned between the top and bottom surfaces. In such embodiments, the third width may be greater than the first and second widths. In some embodiments, the peripheral upper surface 205p may be substantially symmetrical with respect to the central upper surface 205c. In other embodiments, the peripheral upper surface 205p may be asymmetrical relative to the central upper surface 205c (e.g., such that the peripheral upper surface 205p along a first side of the central upper surface 205c has a larger width than the peripheral upper surface 205p along a second side of the central upper surface 205c).

[0034] Multiple lower source / drain contacts 204 may include a lower conductive filler 204C surrounded by a lower source / drain liner 204L. In some embodiments, the lower source / drain liner 204L may include one or more of molybdenum (Mo), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), aluminum (Al), chromium (Cr), nickel (Ni), tantalum (Ta), ruthenium (Ru), cobalt (Co), copper (Cu), and / or the like. In some embodiments, the lower conductive filler 204C may include one or more of molybdenum (Mo), titanium (Ti), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), nickel (Ni), tantalum (Ta), ruthenium (Ru), conductive oxides (e.g., indium oxide (InO), indium tin oxide (InSnO), etc.) and / or the like. In some embodiments, the lower conductive filler 204C and the lower source / drain liner 204L may each have a thickness in the range of about 1 nm to about 50 nm, in the range of about 10 nm to about 50 nm, or other similar values.

[0035] Multiple gate structures 106 are disposed within an ILD structure 202 above multiple lower source / drain contacts 204. The multiple gate structures 106 are arranged along opposite sides of the multiple lower source / drain contacts 204. The multiple gate structures 106 include a gate electrode 108 and a gate dielectric layer 110 extending along multiple outer surfaces of the gate electrode 108. In some embodiments, the gate dielectric layer 110 may extend along multiple sidewalls and a lower surface of the gate electrode 108. In some embodiments, the gate electrode 108 may include one or more of molybdenum (Mo), titanium (Ti), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), nickel (Ni), tantalum (Ta), ruthenium (Ru), and / or the like. In some embodiments, the gate electrode 108 may have a thickness in the range of about 1 nm to about 50 nm, in the range of about 20 nm to about 50 nm, or other similar values. In some embodiments, the gate dielectric layer 110 may include a high-k dielectric material (e.g., a material with a dielectric constant greater than about 3.9). In some embodiments, the gate dielectric layer 110 may include one or more of aluminum oxynitride (AlON), aluminum nitride (AlN), aluminum oxide (AlO), hafnium oxide (HfO2), hafnium zirconium oxide (HZO), zirconium oxide (ZrO2), indium zirconium oxide (InZrO), titanium oxide (TiOx), aluminum titanium oxide (TiAlO), tantalum oxide (Ta2O5), hafnium titanium oxide (HfTiO), europium lanthanum oxide (HfLaO), and / or the like. In some embodiments, the thickness of the gate dielectric layer 110 may be in the range of about 1 nm to about 15 nm, about 5 nm to about 10 nm, or other similar values.

[0036] Multiple channels 112 are vertically arranged above multiple lower source / drain contacts 204 and laterally arranged between adjacent gate structures 106. In some embodiments, the channels 112 may be completely confined on the central upper surface 205c of the multiple lower source / drain contacts. Each channel 112 includes an insulating core of channel material 114 and channel insulating material 304. The channel material 114 laterally surrounds the channel insulating material 304, thereby separating the channel insulating material 304 from the multiple gate structures 106. In some embodiments, the channel material 114 may include indium gallium zinc oxide (In... x Ga y Zn z O) (0≤x, y, z≤1), In x Ga y Zn zMO (where M can be Ti, Al, Ag, W, Ce, Sn and / or the like), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tungsten oxide (IWO), one or more tin-doped oxide semiconductor materials and / or the like. In some embodiments, the channel insulating material 304 may include oxide semiconductors, aluminum oxide (AlOx), silicon dioxide (SiO2), silicon oxynitride (SiON), silicon carbide (SiC), silicon nitride (SiN), silicon carbonitride (SiCN), gallium oxide (GaO), hafnium oxide (HfO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), and aluminum oxide (TiO2). x One or more of zirconium oxide (ZrO2) and / or other non-conductive materials.

[0037] In some embodiments, the plurality of channels 112 may each have a height in the range of about 10 nm to about 100 nm, in the range of about 30 nm to about 80 nm, and / or other similar values. In some embodiments, the height of the channel material 114 may be less than the height of the gate dielectric layer 110. In some embodiments, the thickness of the channel material 114 may be in the range of about 1 nm to about 10 nm, about 5 nm to about 10 nm, or other similar values. In some embodiments, the thickness of the channel material 114 may vary with the height of the channel material 114. For example, the thickness of the channel material 114 may decrease as the height of the channel material 114 increases. In some embodiments, the channel insulating material 304 may have a thickness in the range of about 5 nm to about 20 nm, in the range of about 5 nm to about 25 nm, or other similar values. In some embodiments, the thickness of the channel insulating material 304 may also vary with the height of the channel insulating material 304. For example, the thickness of the channel insulating material 304 may decrease as the height of the channel insulating material 304 increases.

[0038] Multiple upper source / drain contacts 206 are disposed within an ILD structure 202 above multiple channels 112 and multiple gate structures 106. In some embodiments, the multiple upper source / drain contacts 206 may include an upper source / drain liner 206L and an upper conductive fill 206C disposed above the upper source / drain liner 206L. In some embodiments, the upper source / drain liner 206L may include one or more of Mo, Ti, W, TaN, TiN, Ni, Ta, Ru, conductive oxides (e.g., InO, InSnO, etc.) and / or the like. In some embodiments, the upper conductive fill 206C may include one or more of Mo, Ti, TaN, TiN, W, Al, Cr, Ni, Ta, Ru, Co, Cu and / or the like. In some embodiments, the upper source / drain liner 206L and the upper conductive filler 206C may each have a thickness in the range of about 1 nm to about 50 nm, in the range of about 10 nm to about 50 nm, or other similar values.

[0039] Figure 4A Some additional embodiments of an integrated chip structure 400 with vertical transistors are shown, wherein the vertical transistors have channels including channel material surrounding an insulating core, the insulating core including air gaps.

[0040] The integrated chip structure 400 includes an ILD structure 202 located on a substrate 102. The ILD structure 202 includes multiple ILD layers 202a and 202b stacked on top of each other. For example, the ILD structure 202 may include a first ILD layer 202a and a second ILD layer 202b stacked on the first ILD layer 202a. Multiple lower source / drain contacts 204 are disposed within the first ILD layer 202a. Multiple gate structures 106 are arranged within the ILD structure 202 above the multiple lower source / drain contacts 204 and the first ILD layer 202a. The multiple gate structures 106 are arranged along opposite sides of the multiple lower source / drain contacts 204. The multiple gate structures 106 include a gate electrode 108 and a gate dielectric layer 110 extending along multiple outer surfaces of the gate electrode 108. Multiple channels 112 are vertically arranged above multiple lower source / drain contacts 204 and laterally arranged between adjacent gate structures 106. Multiple upper source / drain contacts 206 are disposed within the ILD structure 202 above the multiple channels 112 and the multiple gate structures 106.

[0041] The plurality of channels 112 include channel material 114 arranged along the sidewalls of the plurality of gate structures 106. The channel material 114 has one or more inner surfaces forming an insulating core that includes air gaps 402 within the plurality of channels 112. For example, the channel material 114 may include a plurality of inner sidewalls spaced apart from each other by spaces forming air gaps 402 directly above the plurality of lower source / drain contacts 204. The air gaps 402 are laterally separated from the plurality of gate structures 106 by the channel material 114. In some embodiments, the channel material 114 extends continuously between adjacent gate structures 106 at a first height above the substrate 102 and is discontinuous between adjacent gate structures 106 at a second height above the substrate 102, which is less than the first height. In some embodiments, the channel material 114 extends continuously at a first height above the plurality of lower source / drain contacts 204, having a first width, and extends continuously at a second height above the plurality of lower source / drain contacts 204, having a second width. In such embodiments, the first height is smaller than the second height and the first width is smaller than the second width. In some embodiments, the air gap 402 may include one or more gases, including one or more of oxygen, hydrogen, fluorinated gases (e.g., perfluorinated carbon), hydrocarbon gases, and / or the like.

[0042] In some embodiments, the channel material 114 may have a first maximum height 404, and the air gap 402 may have a second maximum height 406 that is less than the first maximum height 404. In some embodiments, the ratio of the second maximum height 406 to the first maximum height 404 may be between about 0.001 and about 0.9, between about 0.1 and about 0.9, between about 0.5 and about 0.9, or other similar values.

[0043] It should be understood that, in different embodiments, the disclosed air gaps may have different sizes and / or shapes. For example, in Figure 4A In some embodiments shown, the air gap 402 may include a tapered shape extending vertically from between multiple sidewalls of the channel material 114 to multiple lower source / drain contacts 204. In such embodiments, the air gap 402 may be formed by the multiple sidewalls of the channel material 114 and the upper surfaces of the multiple lower source / drain contacts 204. By extending the air gap 402 to the multiple lower source / drain contacts 204, the capacitance of the integrated chip structure 400 can be further reduced relative to air gaps of other shapes. In other embodiments, such as Figure 4BAs shown in cross-sectional view 408, the air gap 402 may include a teardrop shape formed by multiple sidewalls and an upper surface of the channel material 114. In such an embodiment, the air gap 402 is completely surrounded by the channel material 114. Allowing the channel material 114 to completely surround the air gap 402 simplifies the fabrication of the air gap 402.

[0044] In some embodiments, such as Figure 4B As shown in cross-sectional view 408, the lower source / drain liner 204L may further include one or more protrusions 410 formed by a sidewall of the lower source / drain liner 204L extending along one side of the plurality of gate structures 106 and located directly between the plurality of gate structures 106 and the plurality of channels 112. In some embodiments, the sidewall extends outward from the upper surface of the lower source / drain liner 204L.

[0045] Figure 5 Some additional embodiments of an integrated chip structure 500 with vertical transistors are shown, wherein the vertical transistors have channels including channel material surrounding an insulating core, the insulating core including channel insulating material and air gaps.

[0046] The integrated chip structure 500 includes an ILD structure 202 located above a substrate 102. A plurality of lower source / drain contacts 204 are disposed within the ILD structure 202. A plurality of gate structures 106 are disposed within the ILD structure 202 above the plurality of lower source / drain contacts 204. The plurality of gate structures 106 are arranged along opposite sides of the plurality of lower source / drain contacts 204. The plurality of gate structures 106 include gate electrodes 108 and gate dielectric layers 110 extending along a plurality of outer surfaces of the gate electrodes 108. A plurality of channels 112 are vertically disposed above the plurality of lower source / drain contacts 204 and laterally disposed between adjacent gate structures 106. A plurality of upper source / drain contacts 206 are disposed within the ILD structure 202 above the plurality of channels 112 and the plurality of gate structures 106.

[0047] Multiple channels 112 include channel material 114 arranged along the sidewalls of multiple gate structures 106. The channel material 114 surrounds an insulating core including channel insulating material 304 and air gaps 402. The channel insulating material 304 is arranged along one or more inner surfaces (e.g., inner sidewalls) of the channel material 114. In some embodiments, the channel insulating material 304 completely covers the multiple inner sidewalls of the channel material 114. The channel insulating material 304 has one or more inner surfaces that form air gaps 402 within the multiple channels 112. The air gaps 402 are laterally separated from the multiple gate structures 106 through the channel material 114 and the channel insulating material 304.

[0048] Figure 6 Some additional embodiments of an integrated chip structure 600 with vertical transistors are shown, wherein the vertical transistors have channels including channel material surrounding an insulating core.

[0049] The integrated chip structure 600 includes an ILD structure 202 located on a substrate 102. The ILD structure 202 includes a plurality of ILD layers 202a and 202b stacked on top of each other. For example, the ILD structure 202 may include a first ILD layer 202a and a second ILD layer 202b stacked on the first ILD layer 202a. A plurality of lower source / drain contacts 204 are disposed within the first ILD layer 202a. A dielectric layer 602 is disposed over the first ILD layer 202a and the plurality of lower source / drain contacts 204. In various embodiments, the dielectric layer 602 may include oxides (e.g., silicon dioxide), nitrides (e.g., silicon nitride, silicon oxynitride, etc.), carbides (e.g., silicon carbide, silicon carbide, etc.), and / or the like. In some embodiments, the dielectric layer 602 may extend over portions of the plurality of lower source / drain contacts 204.

[0050] A plurality of gate structures 106 are disposed above dielectric layer 602. In some embodiments, dielectric layer 602 vertically separates the plurality of gate structures 106 from a plurality of lower source / drain contacts 204. The plurality of gate structures 106 include gate electrodes 108 and gate dielectric layers 110 extending along a plurality of outer sidewalls of the gate electrodes 108. A plurality of channels 112 are vertically disposed above the plurality of lower source / drain contacts 204 and laterally disposed between adjacent gate structures 106. The plurality of channels 112 extend vertically through dielectric layer 602 to the plurality of lower source / drain contacts 204. A plurality of upper source / drain contacts 206 are disposed within an ILD structure 202 above the plurality of channels 112 and the plurality of gate structures 106.

[0051] Multiple channels 112 include channel material 114 disposed along the sidewalls of multiple gate structures 106. The channel material 114 surrounds an insulating core including channel insulating material 304 and air gaps 402. The channel insulating material 304 is disposed along one or more inner surfaces (e.g., inner sidewalls) of the channel material 114. In some embodiments, the channel insulating material 304 completely covers one or more inner surfaces (e.g., inner sidewalls) of the channel material 114. The channel insulating material 304 has one or more inner surfaces that form air gaps 402 in the multiple channels 112. The air gaps 402 are laterally separated from the multiple gate structures 106 through the channel material 114 and the channel insulating material 304.

[0052] Figures 7A to 7BSome embodiments of integrated chip memory structures with vertical transistors are shown, wherein the vertical transistors have channels comprising channel material surrounding an insulating core.

[0053] Figure 7A A schematic diagram 700 shows some embodiments of the disclosed integrated chip memory structure.

[0054] As shown in schematic diagram 700, the integrated chip structure includes a memory array comprising multiple memory cells 702a, 702b, 702c, and 702d arranged in multiple columns (extending along a first direction 708) and multiple rows (extending along a second direction 710). The multiple memory cells 702a, 702b, 702c, and 702d each include an access transistor 704 and a data storage element 706. The access transistor 704 is configured to control access to the data storage element 706. The access transistor 704 includes a gate electrode coupled to multiple word lines 712a, 712b, and 712c. The access transistor 704 also includes source / drain regions coupled to multiple bit lines 714a, 714b, and 714c.

[0055] Multiple word lines 712a, 712b, 712c and multiple bit lines 714a, 714b, 714c may also be coupled to control circuitry (e.g., a sense amplifier, a decoder, etc.) configured to selectively control access to multiple memory cells 702a, 702b, 702c, 702d. For example, in some embodiments, a write operation can be performed on the first memory cell 702a by applying a positive write voltage to the first word line 712a and the first bit line 714a. In some embodiments, a read operation can be performed on the first memory cell by applying a read voltage (e.g., a voltage less than the positive write voltage) to the first word line 712a.

[0056] Figure 7B It shows the corresponding Figure 7A A cross-sectional view 716 of some embodiments of the disclosed integrated chip memory structure is a part of the schematic diagram 700.

[0057] As shown in cross-sectional view 716, the integrated chip memory structure includes an embedded memory region 718 and a logic region 720. The embedded memory region 718 includes a plurality of memory cells 702a, 702b. The integrated chip memory structure includes an ILD structure 202 disposed on a substrate 102. In some embodiments, the ILD structure 202 includes a plurality of ILD layers stacked on top of each other. In some embodiments, adjacent ILD layers may be spaced apart from each other by an etch stop layer 730.

[0058] Embedded memory region 718 includes a plurality of gate structures 106 disposed within an ILD structure 202 between a plurality of lower source / drain contacts 204 and a plurality of upper source / drain contacts 206. In some embodiments, the plurality of lower source / drain contacts may be coupled to bit lines 714. The plurality of gate structures 106 include gate electrodes 108 and gate dielectric layers 110 extending along a plurality of outer surfaces of the gate electrodes 108. A plurality of channels 112 are disposed vertically over the plurality of lower source / drain contacts 204 and laterally between adjacent gate structures 106. The plurality of channels 112 include channel material 114 disposed along the sidewalls of the plurality of gate structures 106 and channel insulating material 304 disposed along a plurality of inner surfaces of the channel material 114. The channel insulating material 304 has one or more inner surfaces that form air gaps 402 in the plurality of channels 112.

[0059] Multiple upper source / drain contacts 206 are coupled to a data storage element 706 configured to store a first data state (e.g., logic "0") or a second data state (e.g., logic "1"). In some embodiments, the data storage element 706 may include a capacitor. In other embodiments, the data storage element 706 may include a resistive random access memory (RRAM) device, a ferroelectric random access memory (FeRAM) device, a magnetoresistive random access memory (MRAM) device, a phase change random access memory (PCRAM) device, etc.

[0060] Logic region 720 includes logic devices 722 (e.g., field-effect transistors (FETs), FinFETs, gate-all-around transistors, nanosheet transistors, and / or the like). Logic devices 722 are coupled to a plurality of overlying interconnect structures 724. In some embodiments, the edges of the memory array may include one or more sacrificial materials 726 laterally adjacent to an ILD layer 728 surrounding one or more interconnect structures 724. The one or more sacrificial materials 726 may include one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), titanium dioxide (TiOx), amorphous silicon (a-Si), amorphous carbon (aC), and / or other low-k dielectrics.

[0061] Figures 8 to 17Cross-sectional views 800-1700 show some embodiments of a method for forming an integrated chip structure with vertical transistors, wherein the vertical transistors have channels comprising channel material surrounding an insulating core, the insulating core comprising channel insulating material. Although Figures 8 to 17 The embodiments shown are described with reference to the method, but it should be understood that... Figures 8 to 17 The structure shown is not limited to the method of formation, but can exist independently of the method.

[0062] like Figure 8 As shown in cross-sectional view 800, a substrate 102 is provided. In various embodiments, the substrate 102 may include and / or may be any type of semiconductor body (e.g., silicon / CMOS block, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, and any other type of semiconductor and / or epitaxial layer formed thereon and / or otherwise associated with it.

[0063] like Figure 9 As shown in the cross-sectional view 900, a first interlayer dielectric (ILD) layer 202a is formed on the substrate 102. In some embodiments, the first ILD layer 202a may be formed by one or more deposition epitaxial processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PE-CVD), atomic layer deposition (ALD), plasma enhanced ALD (PE-ALD), thermal ALD, spin coating, metal doping, metal oxidation, sputtering, and / or similar processes). In some embodiments, the first ILD layer 202a may include silicon dioxide, silicon oxynitride (SiN), silicon carbonitride (SiCN), titanium oxide (TiOx), amorphous silicon (a-Si), amorphous carbon (aC), carbon-doped silicon oxide (SiCOH), phosphosilicate glass (PSG), borosilicate glass (BPSG), borosilicate glass (BSG), fluorosilicate glass (FSG), undoped silicate glass (USG), and / or the like. In some embodiments (not shown), one or more additional ILD layers may be disposed between the first ILD layer 202a and the substrate 102.

[0064] The first ILD layer 202a is patterned to form a plurality of lower source / drain openings 902, each formed by a plurality of sidewalls of the first ILD layer 202a. In some embodiments, the patterning process may include a photolithography process followed by an etching process to selectively expose the first ILD layer 202a to an etchant. In various embodiments, the etchant may include a dry etchant having an etching chemical substance, including fluorine substances (e.g., CF4, CHF3, C4F8, etc.) or a wet etchant including hydrofluoric acid (HF), potassium hydroxide (KOH), etc.

[0065] Multiple lower source / drain contacts 204 are formed within multiple lower source / drain openings 902. In some embodiments, the multiple lower source / drain contacts 204 can be formed by forming a lower source / drain liner 204L within the multiple lower source / drain openings 902 and over the first ILD layer 202a. In some embodiments, the lower source / drain liner 204L may include one or more of molybdenum (Mo), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), aluminum (Al), chromium (Cr), nickel (Ni), tantalum (Ta), ruthenium (Ru), cobalt (Co), copper (Cu), and / or the like. Subsequently, a lower conductive filler 204C is formed over the lower source / drain liner 204L. In some embodiments, the lower conductive filler 204C may include one or more of molybdenum (Mo), titanium (Ti), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), nickel (Ni), tantalum (Ta), ruthenium (Ru), conductive oxides (e.g., InO, InSnO, etc.), and / or the like. In some embodiments, the lower source / drain liner 204L and the lower conductive filler 204C may be formed by one or more deposition processes (e.g., PVD, CVD, PE-CVD, ALD, PE-ALD, thermal ALD, spin coating, metal doping, metal oxidation, sputtering, etc.). After the lower source / drain liner 204L and the lower conductive filler 204C are formed, a planarization process (e.g., chemical mechanical planarization (CMP)) may be performed to remove portions of the lower source / drain liner 204L and the lower conductive filler 204C above the first ILD layer 202a.

[0066] like Figure 10As shown in the cross-sectional view 1000, a sacrificial structure 1002 is formed on a first ILD layer 202a and a plurality of lower source / drain contacts 204. In some embodiments, the sacrificial structure 1002 may include a first sacrificial material 1002a and a second sacrificial material 1002b stacked on the first sacrificial material 1002a. In some embodiments, the first sacrificial material 1002a and the second sacrificial material 1002b may include one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), titanium oxide (TiOx), amorphous silicon (a-Si), amorphous carbon (aC), and / or other low-k dielectrics. The sacrificial structure 1002 may be formed by one or more deposition processes (e.g., PVD, CVD, PE-CVD, sputtering, ALD, PE-ALD, spin coating, etc.). In some embodiments, the sacrificial structure 1002 may have a thickness in the range of about 1 nm to about 150 nm, in the range of about 50 nm to about 150 nm, or other similar values.

[0067] like Figure 11 As shown in the cross-sectional view 1100, for the sacrificial structure (e.g., Figure 10 The sacrificial structure 1002 is selectively patterned to form a plurality of sacrificial pillars 1102a and 1102b on a plurality of lower source / drain contacts 204a and 204b. For example, a first sacrificial pillar 1102a is formed on a first lower source / drain contact 204a, a second sacrificial pillar 1102b is formed on a second lower source / drain contact 204b, and so on. The plurality of sacrificial pillars 1102a and 1102b are laterally spaced from each other by a plurality of gate structure openings 1104. In some embodiments, the plurality of sacrificial pillars 1102a and 1102b respectively include a first sacrificial material 1002a and a second sacrificial material 1002b. In some embodiments, portions of the lower source / drain contacts 204a and 204b may be removed, such that the lower source / drain contacts 204a and 204b each include a central upper surface 205c and a peripheral upper surface 205p that is vertically located below the central upper surface 205c and laterally surrounds the central upper surface 205c. A plurality of sacrificial pillars 1102a and 1102b are disposed above the central upper surface 205c.

[0068] In some embodiments, the sacrificial structure may be patterned according to a patterning process comprising a photolithography process forming a mask 1106 on the sacrificial structure, followed by an etching process selectively exposing the sacrificial structure to an etchant 1108 based on the mask 1106. In various embodiments, the etchant 1108 may comprise a dry etchant having an etching chemical substance, including fluorine substances (e.g., CF4, CHF3, C4F8, etc.) or a wet etchant, including hydrofluoric acid (HF), potassium hydroxide (KOH), etc.

[0069] like Figure 12 As shown in the cross-sectional view 1200, a plurality of gate structures 106 are formed within a plurality of gate structure openings 1104 and on the opposite sides of a plurality of sacrificial pillars 1102a, 1102b. The plurality of gate structures 106 can be formed by depositing a gate dielectric layer 110 within the plurality of gate structure openings 1104 and over the plurality of sacrificial pillars 1102a, 1102b. Subsequently, gate electrodes 108 can be deposited within the plurality of gate structure openings 1104 and over the gate dielectric layer 110. After the gate electrodes 108 are formed, a planarization process 1202 (e.g., CMP process) can be performed to remove portions of the gate dielectric layer 110 and gate electrodes 108 located over the plurality of sacrificial pillars 1102a, 1102b. The planarization process 1202 forms the plurality of gate structures 106.

[0070] In some embodiments, the gate dielectric layer 110 may include a high-k dielectric material. In some embodiments, the gate dielectric layer 110 may include one or more of aluminum oxynitride (AlON), aluminum nitride (AlN), aluminum oxide (AlO), hafnium oxide (HfO2), hafnium zirconium oxide (HZO), zirconium oxide (ZrO2), indium zirconium oxide (InZrO), titanium oxide (TiOx), aluminum titanium oxide (TiAlO), tantalum oxide (Ta2O5), hafnium titanium oxide (HfTiO), europium lanthanum oxide (HfLaO), and / or the like. In some embodiments, the gate electrode 108 may include one or more of molybdenum (Mo), titanium (Ti), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), nickel (Ni), tantalum (Ta), ruthenium (Ru), and / or the like. In some embodiments, the gate dielectric layer 110 and the gate electrode 108 may be formed through one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, ALD process, PE-ALD process, thermal ALD process, spin coating process, metal doping process, metal oxidation process, sputtering process, etc.).

[0071] like Figure 13 As shown in the sectional view 1300, multiple sacrificial columns (e.g., Figure 12Multiple sacrificial pillars 1102a, 1102b are removed from between adjacent gate structures 106. Removing the multiple sacrificial pillars forms multiple channel openings 1302 between the multiple gate structures 106. The multiple channel openings 1302 expose multiple lower source / drain contacts 204. In some embodiments, the multiple sacrificial pillars can be removed by exposing the multiple sacrificial pillars to etchant 1304.

[0072] like Figure 14 As shown in cross-sectional view 1400, a channel material layer 1402 is formed within a plurality of channel openings 1302 and lining the sidewalls and upper surfaces of a plurality of gate structures 106. The channel material layer 1402 includes one or more inner surfaces spaced apart from each other through a space directly above a plurality of lower source / drain contacts 204. A channel insulating material layer 1404 is subsequently formed within the plurality of channel openings 1302 and lining the plurality of sidewalls and upper surfaces of the channel material layer 1402. In some embodiments, the channel material layer 1402 may include indium gallium zinc oxide (In... x Ga y Zn z O) (0≤x, y, z≤1), In x Ga y Zn z MO (where M can be Ti, Al, Ag, W, Ce, Sn, etc.), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tungsten oxide (IWO), tin-doped oxide semiconductor materials and / or the like. In some embodiments, the channel insulating material layer 1404 may include aluminum oxide (AlOx), silicon dioxide (SiO2), silicon oxynitride (SiON), silicon carbide (SiC), silicon nitride (SiN), silicon carbonitride (SiCN), gallium oxide (GaO), hafnium oxide (HfO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), and other similar materials. x The channel material layer 1402 and / or the channel insulating material layer 1404 may be formed by one or more deposition processes (e.g., PVD, CVD, PE-CVD, ALD, PE-ALD, thermal ALD, spin coating, metal doping, metal oxidation, sputtering, etc.).

[0073] like Figure 15 As shown in the cross-sectional view 1500, a planarization process 1502 (e.g., a chemical mechanical planarization process) can be performed to remove the channel material layer (e.g.,) above the plurality of gate structures 106. Figure 14 The channel material layer 1402) and the channel insulating material layer (e.g., Figure 14The channel insulation material layer 1404 is a portion of the channel insulation material layer. The planarization process 1502 forms a plurality of channels 112 within the plurality of channel openings 1302. The plurality of channels 112 each include channel material 114 having a plurality of inner sidewalls facing opposite sides of an insulating core, the insulating core including channel insulation material 304 disposed above the lower source / drain contact 204.

[0074] like Figure 16 As shown in the cross-sectional view 1600, a second ILD layer 202b is formed over a plurality of gate structures 106, channel material 114, and channel insulating material 304. In some embodiments, the second ILD layer 202b may be formed by one or more deposition processes (e.g., PVD, CVD, PE-CVD, ALD, PE-ALD, thermal ALD, spin coating, metal doping, metal oxidation, sputtering, etc.). In some embodiments, the second ILD layer 202b may include one or more of silicon dioxide, SiON, SiN, SiCN, TiOx, a-Si, aC, SiCOH, PSG, BPSG, BSG, FSG, USG, and / or the like.

[0075] like Figure 17As shown in the cross-sectional view 1700, the second ILD layer 202b is patterned to form a plurality of upper source / drain openings 1702, each formed by a plurality of sidewalls of the second ILD layer 202b. A plurality of upper source / drain contacts 206 are formed within the plurality of upper source / drain openings 1702. In some embodiments, the plurality of upper source / drain contacts 206 can be formed by forming a plurality of upper source / drain liner layers 206L within the plurality of upper source / drain openings 1702 and over the second ILD layer 202b. In some embodiments, the upper source / drain liner layer 206L may include one or more of Mo, Ti, W, TaN, TiN, Ni, Ta, Ru, conductive oxides (e.g., InO, InSnO, etc.) and / or the like. An upper conductive fill 206C is subsequently formed over the upper source / drain liner layer 206L. In some embodiments, the upper conductive filler 206C may include one or more of Mo, Ti, TaN, TiN, W, Al, Cr, Ni, Ta, Ru, Co, Cu, and / or the like. In some embodiments, the upper source / drain liner 206L and the upper conductive filler 206C may be formed by one or more deposition processes (e.g., PVD, CVD, PE-CVD, ALD, PE-ALD, thermal ALD, spin coating, metal doping, metal oxidation, sputtering, etc.). After forming the upper source / drain liner 206L and the upper conductive filler 206C, a planarization process (e.g., CMP) may be performed to remove portions of the upper source / drain liner 206L and the upper conductive filler 206C above the second ILD layer 202b.

[0076] Figures 18 to 27 Cross-sectional views of some additional embodiments of a method for forming an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels comprising channel material surrounding an insulating core, the insulating core including air gaps. Although Figures 18 to 27 The embodiments shown are described with reference to the method, but it should be understood that... Figures 18 to 27 The structure shown is not limited to the method of formation, but can exist independently of the method.

[0077] like Figure 18 As shown in cross-sectional view 1800, a substrate 102 is provided. In various embodiments, the substrate 102 may include and / or may be any type of semiconductor body (e.g., silicon / CMOS block, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, and any other type of semiconductor and / or epitaxial layer formed thereon and / or otherwise associated with it.

[0078] like Figure 19As shown in cross-sectional view 1900, a first ILD layer 202a is formed on a substrate 102. The first ILD layer 202a is patterned to form a plurality of lower source / drain openings 902, each formed by a plurality of sidewalls of the first ILD layer 202a. In some embodiments, the patterning process may include a photolithography process followed by an etching process to selectively expose the first ILD layer 202a to an etchant 904. A plurality of lower source / drain contacts 204 are formed within the plurality of lower source / drain openings 902. In some embodiments, the plurality of lower source / drain contacts 204 may be formed by forming a lower source / drain liner 204L within the plurality of lower source / drain openings 902 and on the first ILD layer 202a. A lower conductive fill 204C is then formed on the lower source / drain liner 204L. After the lower source / drain substrate 204L and the lower conductive fill 204C are formed, a planarization process (e.g., CMP process) can be performed to remove portions of the lower source / drain substrate 204L and the lower conductive fill 204C above the first ILD layer 202a.

[0079] like Figure 20 As shown in the cross-sectional view 2000, a sacrificial structure 1002 is formed on the first ILD layer 202a and a plurality of lower source / drain contacts 204. In some embodiments, the sacrificial structure 1002 may include a first sacrificial material 1002a and a second sacrificial material 1002b stacked on the first sacrificial material 1002a.

[0080] like Figure 21 As shown in the cross-sectional view 2100, for the sacrificial structure (e.g., Figure 20 The sacrificial structure 1002 is selectively patterned to form a plurality of sacrificial pillars 1102a, 1102b on a plurality of lower source / drain contacts 204. The plurality of sacrificial pillars 1102a, 1102b are laterally spaced from each other by a plurality of gate structure openings 1104. In some embodiments, the plurality of sacrificial pillars 1102a, 1102b respectively include a first sacrificial material 1002a and a second sacrificial material 1002b. In some embodiments, portions of the plurality of lower source / drain contacts 204 may also be removed, such that the plurality of lower source / drain contacts 204 each include a central upper surface 205c and a peripheral upper surface 205p that is perpendicularly located below the central upper surface 205c and laterally surrounds the central upper surface 205c.

[0081] like Figure 22As shown in the cross-sectional view 2200, a plurality of gate structures 106 are formed within a plurality of gate structure openings 1104 and on the opposite sides of a plurality of sacrificial pillars 1102a, 1102b. The plurality of gate structures 106 can be formed by depositing a gate dielectric layer 110 within the plurality of gate structure openings 1104 and over the plurality of sacrificial pillars 1102a, 1102b. Subsequently, a gate electrode 108 can be deposited within the plurality of gate structure openings 1104 and over the gate dielectric layer 110. After the gate electrode 108 is formed, a planarization process 1202 (e.g., a CMP process) can be performed to remove portions of the gate dielectric layer 110 and the gate electrode 108 located over the plurality of sacrificial pillars 1102a, 1102b.

[0082] like Figure 23 As shown in the sectional view 2300, multiple sacrificial columns (e.g., Figure 22 Multiple sacrificial pillars (1102a, 1102b) are removed from between adjacent gate structures 106. Removing the multiple sacrificial pillars creates multiple channel openings 1302 between the multiple gate structures 106.

[0083] like Figure 24 As shown in the cross-sectional view 2400, a channel material layer 2402 is formed within a plurality of channel openings 1302 and lining the sidewalls and upper surfaces of a plurality of gate structures 106. In some embodiments, the channel material layer 2402 may include In x Ga y Zn z O (0≤x, y, z≤1), In x Ga y Zn z MO (where M can be one or more of Ti, Al, Ag, W, Ce, Sn, etc.), IGO, IZO, IWO, tin-doped oxide semiconductor materials, etc. The channel material layer 2402 has multiple inner sidewalls that are opposite to each other, thereby forming an air gap 402 above the lower source / drain contact 204.

[0084] like Figure 25 As shown in the cross-sectional view 2500, a planarization process 2502 (e.g., a CMP process) can be performed to remove the channel material layer located above the plurality of gate structures 106 (e.g., Figure 24 The channel material layer 2402 is a portion of the channel. The planarization process 2502 forms the channel 112, which includes channel material 114 having multiple inner sidewalls facing opposite sides of an air gap 402 disposed above multiple lower source / drain contacts 204.

[0085] like Figure 26As shown in cross-sectional view 2600, a second ILD layer 202b is formed over a plurality of gate structures 106 and channels 112. In some embodiments, the second ILD layer 202b may be formed through one or more deposition processes (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In some embodiments, the second ILD layer 202b may include silicon dioxide, SiON, SiN, SiCN, TiOx, a-Si, aC, SiCOH, PSG, BPSG, BSG, FSG, USG, etc.

[0086] like Figure 27 As shown in the cross-sectional view 2700, the second ILD layer 202b is patterned to form a plurality of upper source / drain openings 1702, each formed by a sidewall of the second ILD layer 202b. A plurality of upper source / drain contacts 206 are formed within the plurality of upper source / drain openings 1702. In some embodiments, the plurality of upper source / drain contacts 206 can be formed by forming a plurality of upper source / drain liner layers 206L within the plurality of upper source / drain openings 1702 and over the second ILD layer 202b. Subsequently, an upper conductive filler 206C is formed over the upper source / drain liner layers 206L. After the upper source / drain liner 206L and upper conductive fill 206C are formed, a planarization process (e.g., CMP process) can be performed to remove portions of the upper source / drain liner 206L and upper conductive fill 206C above the second ILD layer 202b.

[0087] Figure 28 Flowcharts of some embodiments of a method for forming an integrated chip structure with vertical transistors are shown, wherein the vertical transistors have channels including channel material surrounding an insulating core.

[0088] Although this document illustrates and describes method 2800 as a series of actions or events, it should be understood that the order of such actions or events shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events other than those shown and / or described herein. Furthermore, not all actions shown may be required to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or phases.

[0089] At action 2802, a lower interlayer dielectric (ILD) layer is formed on the substrate. Figure 8 A cross-sectional view 800 is shown for some embodiments corresponding to action 2802. Figure 18 A cross-sectional view 1800 is shown for some additional embodiments corresponding to action 2802.

[0090] At action 2804, multiple lower source / drain contacts are formed within the lower ILD layer. Figure 9 A cross-sectional view 900 corresponding to some embodiments of action 2804 is shown. Figure 19 A cross-sectional view 1900 is shown for some additional embodiments corresponding to action 2804.

[0091] At action 2806, a sacrificial structure is formed on top of multiple lower source / drain contacts and the lower ILD layer. Figure 10 A cross-sectional view 1000 is shown for some embodiments corresponding to action 2806. Figure 20 A cross-sectional view 2000 is shown for some additional embodiments corresponding to action 2806.

[0092] At action 2808, the sacrificial structure is patterned to form multiple sacrificial pillars on multiple lower source / drain contacts. Figure 11 A cross-sectional view 1100 is shown for some embodiments corresponding to action 2808. Figure 21 A cross-sectional view 2100 is shown for some additional embodiments corresponding to action 2808.

[0093] At action 2810, multiple gate structures are formed within multiple gate openings that separate multiple sacrificial pillars. Figure 12 A cross-sectional view 1200 is shown for some embodiments corresponding to action 2810. Figure 22 A cross-sectional view 2200 is shown for some additional embodiments corresponding to action 2810.

[0094] At action 2812, multiple sacrificial pillars are removed to form multiple channel openings between multiple gate structures. Figure 13 A cross-sectional view 1300 is shown for some embodiments corresponding to action 2812. Figure 23 A cross-sectional view 2300 is shown for some additional embodiments corresponding to action 2812.

[0095] At action 2814, channels are formed within multiple channel openings. The channels comprise channel material surrounding the insulating core. Figures 14 to 15 Cross-sectional views 1400 and 1500 are shown for some embodiments corresponding to action 2814. Figures 24 to 25 Cross-sectional views 2400 and 2500 are shown for some additional embodiments corresponding to action 2814.

[0096] At action 2816, multiple upper source / drain contacts are formed within the upper ILD layer formed above the channel and multiple gate structures. Figures 16 to 17 Cross-sectional views 1600 and 1700 are shown for some embodiments corresponding to action 2816. Figures 26 to 27 Cross-sectional views 2600 and 2700 are shown for some additional embodiments corresponding to action 2816.

[0097] Therefore, in some embodiments, this disclosure relates to an integrated chip structure having a vertical transistor having a channel having a channel material and an insulating core.

[0098] In some embodiments, this disclosure relates to an integrated chip. The integrated chip includes a lower source / drain over a substrate; a channel disposed over the lower source / drain; an upper source / drain over the channel; a plurality of gate electrodes disposed along opposite sides of the channel; and the channel includes a channel material laterally surrounding an insulating core over the lower source / drain, the channel material laterally separating the insulating core from the plurality of gate electrodes. In one embodiment, the lower source / drain includes lower source / drain contacts including a central upper surface and a peripheral upper surface perpendicularly below the central upper surface and laterally surrounding the central upper surface, the channel being located above the central upper surface. In one embodiment, the insulating core includes a dielectric material laterally contacting the channel material. In one embodiment, the insulating core includes an air gap containing gas. In one embodiment, the integrated chip further includes a gate dielectric layer extending continuously along a plurality of sidewalls and a lower surface of the plurality of gate electrodes. In one embodiment, the gate dielectric layer has a first height and the channel material has a second height less than the first height. In one embodiment, the channel material has a thickness that varies with the height of the channel material. In one embodiment, the channel material extends continuously at a first height above the lower source / drain to have a first width, and wherein the channel material extends continuously at a second height above the lower source / drain to have a second width, the first height being less than the second height and the first width being less than the second width. In one embodiment, the channel material comprises an oxide semiconductor.

[0099] In other embodiments, this disclosure relates to a method of forming an integrated chip. This method includes forming lower source / drain contacts within a lower interlayer dielectric (ILD) layer on a substrate; forming a sacrificial structure over the lower source / drain contacts and the lower ILD layer; patterning the sacrificial structure to form sacrificial pillars over the lower source / drain contacts; forming a plurality of gate structures over the lower ILD layer and along opposite sidewalls of the sacrificial pillars; removing the sacrificial pillars to form a channel opening between the plurality of gate structures and expose the lower source / drain contacts; and forming a channel within the channel opening, wherein the channel includes a channel material having a plurality of inner sidewalls facing opposite sides of an insulating core. In one embodiment, the sacrificial structure includes: a first dielectric material; and a second dielectric material disposed over the first dielectric material. In one embodiment, forming the channel includes: depositing the channel material within the channel opening, wherein the channel material lining the plurality of sidewalls and upper surface of the gate structures; and depositing a channel insulating material within the channel opening, wherein the channel insulating material lining the plurality of inner sidewalls and upper surface of the channel material. In one embodiment, forming the channel includes depositing the channel material within the channel opening, wherein the channel material includes one or more inner surfaces that form an air gap directly above the lower source / drain contact. In one embodiment, forming the plurality of gate structures includes forming a gate dielectric layer along the opposing sidewalls and upper surface of the sacrificial pillar; and forming gate electrodes along the plurality of sidewalls and above the gate dielectric layer. In one embodiment, the lower source / drain contact has a bottom surface with a first width, a top surface with a second width, and a third width perpendicular to the top surface and the bottom surface, the third width being greater than the first width and the second width. In one embodiment, the lower source / drain contact includes a central upper surface and a peripheral upper surface surrounding the central upper surface, the channel being completely confined above the central upper surface.

[0100] In some other embodiments, this disclosure relates to a method of forming an integrated chip. The method includes forming lower source / drain contacts within a lower interlayer dielectric (ILD) layer above a substrate; forming sacrificial pillars above the lower source / drain contacts; forming a plurality of gate structures above the lower ILD layer and along opposite sidewalls of the sacrificial pillars; removing the sacrificial pillars to form channel openings between the plurality of gate structures; and forming a channel material within the channel openings and along the plurality of sidewalls of the plurality of gate structures, the channel material including one or more inner surfaces spaced apart from each other by a space directly above the lower source / drain contacts. In one embodiment, the channel material extends continuously at a first height above the lower source / drain contacts between adjacent gate structures, and wherein the channel material is discontinuous at a second height above the lower source / drain contacts between the adjacent gate structures, the second height being smaller than the first height. In one embodiment, the method of forming the integrated chip further includes forming a channel insulating material along the one or more inner surfaces of the channel material. In one embodiment, the channel insulation material has one or more inner surfaces that form an air gap directly above the lower source / drain contact.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated chip, characterized in that, include: The lower source / drain is located on the substrate; The channel is arranged above the lower source / drain electrode; The upper source / drain is located above the channel; as well as Multiple gate electrodes are arranged along opposite sides of the channel; The channel comprises a channel material that laterally surrounds an insulating core located above the lower source / drain electrode, the channel material laterally separating the insulating core from the plurality of gate electrodes.

2. The integrated chip according to claim 1, characterized in that... The lower source / drain includes a lower source / drain contact, which includes a central upper surface and a peripheral upper surface that is perpendicular to the central upper surface and laterally surrounds the central upper surface. The channel is located above the central upper surface.

3. The integrated chip according to claim 1, characterized in that... The insulating core includes a dielectric material that is in lateral contact with the channel material.

4. The integrated chip according to claim 1, characterized in that... The insulating core includes an air gap containing gas.

5. A method for forming an integrated chip, characterized in that, include: The lower source / drain contacts are formed within the lower interlayer dielectric (ILD) layer above the substrate; A sacrificial structure is formed on the lower source / drain contacts and the lower ILD layer; The sacrificial structure is patterned to form a sacrificial pillar on the lower source / drain contact; Multiple gate structures are formed above the lower ILD layer and along the opposite sidewalls of the sacrificial pillar; Remove the sacrificial pillar to form a channel opening between the plurality of gate structures and expose the lower source / drain contacts; as well as A channel is formed within the channel opening, wherein the channel comprises a channel material having a plurality of inner sidewalls facing opposite sides of the insulating core.

6. The method for forming an integrated chip according to claim 5, characterized in that... Forming the channel includes: The channel material is deposited within the channel opening, wherein the channel material includes one or more inner surfaces that form an air gap directly above the lower source / drain contact.

7. The method for forming an integrated chip according to claim 5, characterized in that... The lower source / drain contact has a bottom surface with a first width, a top surface with a second width, and a third width perpendicular to the top surface and the bottom surface, the third width being greater than the first width and the second width.

8. A method for forming an integrated chip, characterized in that, include: The lower source / drain contacts are formed within the lower interlayer dielectric (ILD) layer above the substrate; A sacrificial pillar is formed on the lower source / drain contact; Multiple gate structures are formed above the lower ILD layer and along the opposite sidewalls of the sacrificial pillar; Remove the sacrificial pillar to form a channel opening between the plurality of gate structures; as well as A channel material is formed within the channel opening and along the multiple sidewalls of the plurality of gate structures, wherein the channel material includes one or more inner surfaces, the one or more inner surfaces being spaced apart from each other by a space directly above the lower source / drain contacts.

9. The method for forming an integrated chip according to claim 8, characterized in that, Also includes: A channel insulating material is formed along one or more inner surfaces of the channel material.

10. The method for forming an integrated chip according to claim 9, characterized in that... The channel insulating material has one or more inner surfaces that form an air gap directly above the lower source / drain contact.

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