A semiconductor device, a manufacturing method thereof, and a semiconductor apparatus

Abstract

The application relates to the technical field, in particular to a semiconductor device and a manufacturing method thereof and a semiconductor device, which comprises a semiconductor substrate; a first transistor and a second transistor, the first transistor and the second transistor are arranged in a vertical stack along a direction perpendicular to the surface of the semiconductor substrate, and the second transistor is located between the semiconductor substrate and the first transistor; in a cross section along a channel width direction, a first channel region of the first transistor has a first width, a second channel region of the second transistor has a second width, and the first width and the second width are not equal; a first isolation structure is arranged between the first channel region and the second channel region; in the cross section along the channel width direction, the first isolation structure is a trapezoidal structure. The application can effectively balance the driving current of the N-type transistor and the P-type transistor by independently regulating the channel width of the upper and lower transistors in the vertical stack direction, so that the switching speed of the device is more balanced, and the overall switching speed is maximized.

Description

Technical Field

[0001] This invention relates to the field of technology, and in particular to a semiconductor device and its manufacturing method, and semiconductor equipment. Background Technology

[0002] As integrated circuit manufacturing processes continue to advance to smaller technology nodes, currently reaching 2nm and below, traditional planar transistors and FinFETs are increasingly unable to meet the growing performance and integration requirements. The development of key transistor technologies is driving significant changes in transistor structure. Vertically stacked complementary transistor (CFET) technology will become the main technology route for the next generation of three-dimensional stacked transistors after the 2nm node.

[0003] In the CFET structure, NMOS and PMOS devices are integrated in a vertically stacked manner on the same active region. Control of the upper and lower layer devices is achieved through shared gates or independent gates, thereby achieving higher integration efficiency per unit area. However, this structure also brings new technical challenges.

[0004] Due to the differences in carrier physical properties, electron mobility in the channel is significantly higher than that of holes. This makes it difficult to achieve performance matching between upper and lower N / PMOS devices in a GAA CFET, which causes the rise time of the CMOS inverter to be slower than the fall time, limiting the overall speed and potentially causing timing issues.

[0005] In traditional FinFET or GAAFET processes, the performance of N / PMOS in a standard cell can be designed separately by changing the number of fins according to circuit functional requirements, thereby obtaining higher circuit characteristics. However, the CFET structure stacks N / PMOS, so the design method of changing the number of fins is no longer universal.

[0006] To address the performance matching issue of N / PMOS in CFET structures, numerous device technologies have been proposed: ① By controlling the channel crystal orientation of the upper and lower layers, the channel carrier mobility can be controlled, ultimately achieving electrical control of the N / P devices; ② By stacking heterochannel materials (germanium) with higher hole mobility, PFET performance can be improved; ③ By forming stepped stacked channels, the dimensions of the upper and lower CFET devices can be structurally designed. While these solutions provide performance control to some extent, they typically involve complex process integration schemes or impose strict restrictions on the selection of channel materials and crystal orientations. Further optimization is still possible in terms of process compatibility, process complexity, and design flexibility.

[0007] Therefore, how to achieve efficient matching of NMOS and PMOS device performance under the CFET architecture, while taking into account the feasibility of process implementation and the flexibility of design, has become a technical problem that urgently needs to be solved in the field of integrated circuit manufacturing.

[0008] In view of this, the present invention is proposed. Summary of the Invention

[0009] The purpose of this invention is to provide a semiconductor device. By independently adjusting the channel width of the upper and lower transistors in the vertical stacking direction, this invention can effectively balance the drive current of the N-type transistor and the P-type transistor, making the switching speed of the device more balanced and maximizing the overall switching speed.

[0010] In a first aspect, the present invention provides a semiconductor device, including a semiconductor substrate; A first transistor and a second transistor are stacked vertically along a direction perpendicular to the surface of the semiconductor substrate, with the second transistor located between the semiconductor substrate and the first transistor. In a cross-section along the channel width direction, the first channel region of the first transistor has a first width, and the second channel region of the second transistor has a second width, wherein the first width and the second width are not equal; A first isolation structure is disposed between the first channel region of the first transistor and the second channel region of the second transistor; In the cross-section along the width of the channel, the first isolation structure is a trapezoidal structure.

[0011] As a preferred embodiment of this technical solution, the upper width of the first isolation structure is equal to the first width, and the lower width is equal to the second width.

[0012] As a preferred embodiment of this technical solution, the first width is smaller than the second width.

[0013] In a preferred embodiment of this technical solution, the first transistor is an N-type transistor and the second transistor is a P-type transistor.

[0014] In a preferred embodiment of this technical solution, the first transistor is a P-type transistor, the second transistor is an N-type transistor, and the first width is greater than the second width.

[0015] As a preferred embodiment of this technical solution, in the cross-section along the width of the channel, the first isolation structure is an isosceles trapezoid.

[0016] Preferably in this technical solution, in a cross-section along the channel width direction, the first isolation structure is composed of at least two trapezoidal parts, wherein the included angle between the side waist and the lower base of the trapezoid located in the upper part is greater than the included angle between the side waist and the lower base of the trapezoid located in the lower part.

[0017] Preferably in this technical solution, the lower base of the trapezoid located in the upper part coincides with the upper base of the trapezoid located in the lower part.

[0018] Preferably in this technical solution, the first channel region is composed of two or more first nanowires or first nanosheets distributed at intervals in the up and down direction; the second channel region is composed of two or more second nanowires or second nanosheets distributed at intervals in the up and down direction.

[0019] Preferably in this technical solution, the first transistor includes a first gate, and the first gate surrounds the first nanowire or the first nanosheet; the second transistor includes a second gate, and the second gate surrounds the second nanowire or the second nanosheet.

[0020] Preferably in this technical solution, along the length direction of the first channel region, both sides of the first channel region are connected to the first source / drain region; Along the length direction of the second channel region, both sides of the second channel region are connected to the second source / drain region; Among them, the first source / drain region and the second source / drain region are isolated by a second isolation structure.

[0021] Preferably in this technical solution, the sidewall inclination angle θ of the trapezoid-like structure is 10 -90 o .

[0022] Preferably in this technical solution, the first width is W1, the second width is W2, wherein, W1 < W2, and 0 < (W2 - W1) / W1 ≤ 50%.

[0023] In a second aspect, the present invention also provides a method for manufacturing a semiconductor device, which specifically includes the following steps: Provide a semiconductor substrate; Form a fin stack formed by alternately stacking a channel sacrificial layer and a channel layer on the semiconductor substrate, the fin stack includes an upper fin stack and a lower fin stack, and the upper fin stack and the lower fin stack are isolated by an isolation structure sacrificial layer; Etch the upper fin stack to remove the redundant channel sacrificial layer and channel layer, and form a first transistor channel region with a first width, wherein the extension direction of the first width is consistent with the channel width direction; The isolation structure sacrificial layer is etched along the width direction of the channel to transform it into a first isolation structure. The first isolation structure is made into a trapezoidal structure in the cross section along the width direction of the channel. The upper width of the trapezoidal structure is equal to the first width, and the lower width is a second width. The first width and the second width are not equal. The lower fin stack is etched to remove excess channel sacrificial layer and channel layer, forming a second transistor channel region with the second width; Source / drain regions are formed on both sides of the first transistor channel region and the second transistor channel region; A gate trench is formed by removing the channel sacrificial layer between the first transistor channel region and the second transistor channel region, and a gate is formed in the gate trench.

[0024] As a preferred embodiment of this technical solution, the step of forming a fin stack on the semiconductor substrate by alternating stacking of a channel sacrificial layer and a channel layer includes: A lower fin stack is formed on a semiconductor substrate, an isolation structure sacrificial layer is formed on the lower fin stack, the upper fin stack is formed on another substrate, and the other substrate is bonded to the isolation structure sacrificial layer by a bonding process.

[0025] As a preferred embodiment of this technical solution, when etching the sacrificial layer of the isolation structure, the sidewall tilt angle θ of the trapezoidal structure is adjusted by controlling the etching gas ratio and radio frequency power.

[0026] As a preferred embodiment of this technical solution, the material of the sacrificial layer of the isolation structure includes silicon oxide or silicon nitride.

[0027] Thirdly, the present invention also discloses an electronic device including the above-mentioned semiconductor device, the electronic device including a smartphone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a power bank.

[0028] The semiconductor device of the present invention has at least the following beneficial effects: 1. This invention compensates for the differences in carrier mobility between transistors of different conductivity types by making the first and second transistors stacked on top of each other have different channel widths. This effectively balances the drive current of N-type and P-type transistors, making the switching speed of the device more balanced. It eliminates the "short board effect" of drive capability caused by mobility mismatch in the traditional CFET structure, and makes the rise and fall edges of the circuit equally steep, maximizing the overall switching speed. This is crucial for high-performance CPU / GPU caches, etc. 2. This invention independently controls the channel width of the upper and lower transistors in the vertical stacking direction, eliminating the need to compensate for performance differences by increasing the number of transistors or increasing the lateral dimensions as in planar structures. It can further optimize the layout and wiring space inside the cell while maintaining the high density advantage of CFET devices, thereby achieving higher logic density. 3. The first isolation structure between the first channel region and the second channel region of the present invention is configured as a trapezoidal structure. The asymmetric width structure can be better compatible with high mobility channel materials such as SiGe and stress engineering technology, thereby maximizing the improvement of carrier mobility. 4. By adjusting the width ratio of the first channel region to the second channel region, this invention can flexibly configure device structures suitable for different application scenarios such as high performance, high density, or low power consumption, creating specialized N / P width ratio cells to achieve optimal performance under this function, thus broadening the applicability of CFET devices. Attached Figure Description

[0029] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 This is a top view of the semiconductor device of the present invention; Figure 2 This is a schematic diagram of the Y-Y' cross-section of the semiconductor device of the present invention; Figure 3 This is a schematic cross-sectional view of the sacrificial piece X-X' of the present invention; Figure 4 This is a schematic cross-sectional view of the device chip of the present invention along X-X'. Figure 5 This is a schematic diagram of the X-X' cross-section of the upper fin stack formed on the sacrificial plate according to the present invention; Figure 6 This is a schematic X-X' cross-sectional view of the lower fin stack formed on the device chip according to the present invention; Figure 7 This is a schematic diagram of the flip bonding of the sacrificial wafer and the device wafer in this invention; Figure 8 This is a schematic diagram of the X-X' cross-section after the sacrificial wafer and the device wafer are bonded together according to the present invention; Figure 9 This is a schematic diagram of the X-X' cross-section of the sacrificial substrate after thinning according to the present invention; Figure 10 This is a schematic diagram of the X-X' cross-section of the present invention, which shows the deposition of a dielectric layer on the surface of the upper fin stack and the formation of a sidewall. Figure 11 This is a Y-Y' cross-sectional schematic diagram of the present invention, in which a dielectric layer is deposited on the surface of the upper fin stack to form a sidewall; Figure 12 This is a schematic diagram of the Y-Y' cross-section after the first etching step of the present invention; Figure 13 This is a schematic diagram of the Y-Y' cross-section after the second etching stage of the present invention; Figure 14 This is a schematic diagram of the Y-Y' cross-section after the third etching stage of the present invention; Figure 15 This is a schematic diagram of the Y-Y' cross-section after STI filling according to the present invention; Figure 16 This is a schematic diagram of the Y-Y' cross-section after the dummy gate stack deposition and patterning of the present invention; Figure 17 This is a schematic diagram of the X-X' cross-section after the dummy gate stack deposition and patterning of the present invention; Figure 18 This is a schematic diagram of the X-X' cross-section after the first gate sidewall has been formed according to the present invention; Figure 19 This is a schematic diagram of the X-X' cross-section after etching the fin stack of the source / drain region according to the present invention; Figure 20 This is a schematic diagram of the X-X' cross-section after etching the transverse grooves on the inner wall in this invention; Figure 21 This is a schematic diagram of the X-X' section after the inner wall of the present invention has been formed; Figure 22 This is a schematic diagram of the X-X' cross-section after the epitaxial growth of the source / drain region in this invention; Figure 23 This is a schematic diagram of the X-X' cross-section after the isolation layer medium is deposited on the source / drain region and planarized according to the present invention; Figure 24 This is a schematic diagram of the X-X' cross-section after removing the dummy gate in this invention; Figure 25 This is a schematic diagram of the Y-Y' cross-section after removing the dummy gate in this invention; Figure 26 This is a schematic diagram of the Y-Y' cross-section after the formation of the gate trench through nanosheet channel release in this invention; Figure 27 This is a schematic diagram of the X-X' cross-section after the metal grid has been formed according to the present invention; Figure 28 This is a schematic diagram of the Y-Y' cross-section after the metal grid has been formed according to the present invention; Figures 29-31 This is a schematic diagram of the interconnection process of the present invention; Figure 32This is a schematic diagram of the Y-Y' cross-section of the P on N CFET of the present invention; Figure 33 This is a schematic diagram of the Y-Y' cross-section of the N on P CFET of the present invention.

[0031] Explanation of reference numerals in the attached figures: 1: Semiconductor substrate; 2: First transistor; 3: Second transistor; 4: First isolation structure; 5: First gate sidewall; 6: Inner sidewall; 7: Sacrificial layer of isolation structure; 8: Dummy gate stack; 9: Dummy gate hard mask layer. Detailed Implementation

[0032] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they may refer to a fixed connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0035] To address the performance matching issue of N / PMOS in CFET structures, numerous device technologies have been proposed: ① By controlling the channel crystal orientation of the upper and lower layers, the channel carrier mobility can be controlled, ultimately achieving electrical control of the N / P devices; ② By stacking heterochannel materials (germanium) with higher hole mobility, PFET performance can be improved; ③ By forming stepped stacked channels, the dimensions of the upper and lower CFET devices can be structurally designed. While these solutions provide performance control to some extent, they typically involve complex process integration schemes or impose strict restrictions on the selection of channel materials and crystal orientations. Further optimization is still possible in terms of process compatibility, process complexity, and design flexibility.

[0036] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and its manufacturing method, as well as a semiconductor equipment.

[0037] In the semiconductor device provided in this embodiment of the invention, the first transistor 2 and the second transistor 3 stacked on top of each other have different channel widths, which can compensate for the differences in carrier mobility of transistors of different conductivity types, effectively balance the drive current of N-type transistors and P-type transistors, make the switching speed of the device more balanced, and improve the working performance of the semiconductor device.

[0038] In a first aspect, embodiments of the present invention provide a semiconductor device.

[0039] like Figures 1-33 As shown, the semiconductor device provided in this embodiment includes a semiconductor substrate; The first transistor 2 and the second transistor 3 are stacked vertically along a direction perpendicular to the surface of the semiconductor substrate 1, wherein the second transistor 3 is located between the semiconductor substrate 1 and the first transistor 2.

[0040] Figure 2 This is a cross-sectional view of the semiconductor device of the present invention in the Y-Y' direction, where the Y-Y' direction is the channel width direction. Figure 2 It is known that in the cross section along the channel width direction, the first channel region of the first transistor 2 has a first width, and the second channel region of the second transistor 3 has a second width. The first width and the second width are not equal. By making the stacked first transistor 2 and second transistor 3 have different channel region widths, it is possible to compensate for the difference in carrier mobility of transistors with different conductivity types.

[0041] The first isolation structure 4 is located between the first channel region and the second channel region. It can effectively isolate the upper and lower transistors electrically, prevent signal crosstalk and leakage current between the upper and lower layers, and ensure the normal function and stability of the device.

[0042] like Figure 2 As shown, in the cross-section along the channel width direction, the first isolation structure 4 is a trapezoidal structure that is symmetrical from left to right to accommodate the first channel region and the second channel region with different widths of the upper and lower transistors. In addition, the asymmetric width structure of the first isolation structure 4 can also be better compatible with high mobility channel materials such as SiGe and stress engineering technology, maximizing the improvement of carrier mobility.

[0043] Therefore, by making the first transistor 2 and the second transistor 3 stacked on top of each other have different channel widths, the present invention can compensate for the difference in carrier mobility of transistors with different conductivity types, effectively balance the drive current of N-type transistors and P-type transistors, make the switching speed of the device more balanced, eliminate the "short board effect" of drive capability caused by mobility mismatch in the traditional CFET structure, make the rise and fall edges of the circuit equally steep, maximize the overall switching speed, and achieve efficient matching of NMOS and PMOS device performance under the CFET architecture.

[0044] Based on the above technical solution, it is further preferred that the upper width of the first isolation structure 4 is equal to the first width, and the lower width of the first isolation structure 4 is equal to the second width. That is, the first gate sidewall 5 formed on both sides of the gate at the top of the first transistor 2 and the trapezoidal first isolation structure 4 can serve as a self-aligned hard mask for etching the second channel region of the second transistor 3, thereby realizing the control of the width of the second channel region.

[0045] In a specific embodiment of the present invention, the first transistor 2 is an N-type transistor and the second transistor 3 is a P-type transistor. In this case, the first width of the first channel region of the first transistor 2 is smaller than the second width of the second channel region of the second transistor 3.

[0046] In another specific embodiment of the present invention, the first transistor 2 is a P-type transistor and the second transistor 3 is an N-type transistor. In this case, the first width of the first channel region of the first transistor 2 is greater than the second width of the second channel region of the second transistor 3.

[0047] Therefore, as Figures 32-33 As shown, the present invention can flexibly design CFET structures with N-type transistors on top or P-type transistors on top, and is no longer limited to the commonly used top-N and bottom-P CFET structures.

[0048] In one specific embodiment of the present invention, the first isolation structure 4 is an isosceles trapezoid in the cross-section along the width of the channel. The isosceles trapezoidal structure is regular and has high symmetry, which makes it easy to form accurately during photolithography and etching, reducing process deviations and improving the consistency of mass production.

[0049] In another specific embodiment of the present invention, in the cross section along the width direction of the channel, the first isolation structure 4 is composed of at least two trapezoidal parts, that is, a symmetrical trapezoidal structure composed of at least two trapezoidal parts can be formed by controlling the etching process, wherein the angle between the side waist and the bottom of the upper trapezoid is greater than the angle between the side waist and the bottom of the lower trapezoid.

[0050] The combination of two trapezoidal segments with different included angles allows for segmented adjustment of isolation stiffness and electric field distribution, enabling the upper segment to adapt to low stress and the lower segment to adapt to high isolation, thus optimizing isolation performance. Furthermore, by etching multiple trapezoidal segments, the tilt angle, height, and width of each segment can be flexibly adjusted, expanding the process window and improving compatibility with different technology nodes.

[0051] Based on the above technical solution, it is further preferred that the lower base of the upper trapezoid coincides with the upper base of the lower trapezoid, that is, the lower base of the upper trapezoid is the upper base of the lower trapezoid.

[0052] The top and bottom surfaces completely overlap, which facilitates the formation of a continuous, seamless, and uninterrupted overall structure for the first isolation structure 4. This avoids leakage, noise, and reliability failure caused by interface gaps, and ensures a continuous transition of the electric field, thereby improving the device switching speed and signal integrity.

[0053] Based on the above technical solution, more preferably, the first channel region is composed of two or more first nanowires or first nanosheets spaced vertically apart; the second channel region is composed of two or more second nanowires or second nanosheets spaced vertically apart. Multilayer nanowires / nanosheets can significantly increase the effective channel width within the same device area, improving conduction current and meeting the requirements of high-performance circuits. Furthermore, multilayer nanowires / nanosheets are a standard structure for 2nm and below processes, highly compatible with GAA and CFET processes, facilitating device miniaturization and integration.

[0054] More preferably, based on the above technical solution, the first transistor 2 includes a first gate surrounding a first nanowire or a first nanosheet; the second transistor 3 includes a second gate surrounding a second nanowire or a second nanosheet. The gate-ring structure makes the gate's control of the channel more uniform and efficient, significantly improving the switching speed and current-to-switching ratio.

[0055] On the basis of the above technical solution, more preferably, along the length direction of the first channel region, the two sides of the first channel region are connected to the first source / drain region; along the length direction of the second channel region, the two sides of the second channel region are connected to the second source / drain region; wherein, the first source / drain region and the second source / drain region are isolated by a second isolation structure. The second isolation structure effectively separates the upper and lower source / drain regions, reduces the vertical parasitic capacitance, improves the circuit operating frequency, and at the same time avoids leakage, crosstalk, and coupling between the source and drain of the upper and lower devices, ensuring the independent operation of the N-type transistor and the P-type transistor. On the basis of the above technical solution, further preferably, a trapezoid-like structure with different θ angles can be formed by adjusting the etching process.

[0056] Further preferably, the sidewall inclination angle θ of the trapezoid-like structure is 10-90 o .

[0057] On the basis of the above technical solution, further preferably, by adjusting the width ratio of the first channel region to the second channel region, a device structure suitable for different application scenarios such as high performance, high density, or low power consumption can be flexibly configured, creating a unit with a specialized N / P width ratio, making it optimal under this function, and broadening the application range of the CFET device.

[0058] Further preferably, the first width is W1, the second width is W2, wherein, W1 < W2, and 0 < (W2 - W1) / W1 ≤ 50%.

[0059] On the basis of the above technical solution, further preferably, the materials of the first isolation structure 4 and the second isolation structure include silicon oxide or silicon nitride.

[0060] In the second aspect, this embodiment provides a method for manufacturing a semiconductor device. The structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the present invention embodiment is the same as the structure of the semiconductor device provided in the first aspect. Therefore, the beneficial effects of the second aspect and its various implementation manners in the present invention embodiment can refer to the analysis of the beneficial effects in the first aspect and its various implementation manners, and will not be elaborated here.

[0061] The following will be based on Figure 3-31 the cross-sectional views of the operations shown, to describe the manufacturing process. Specifically, the method for manufacturing the semiconductor device includes the following steps: First, as Figure 1-9 [ shown, provide a semiconductor substrate 1. In this embodiment, a device wafer and a sacrificial wafer can be provided respectively; For example, a lower fin stack formed by alternating stacks of channel sacrificial layers and channel layers is formed on a device wafer, and an upper fin stack formed by alternating stacks of channel sacrificial layers and channel layers is formed on a sacrificial wafer. Then, an isolation structure sacrificial layer 7 is formed above the lower fin stack or above the upper fin stack. The sacrificial wafer formed by the upper fin stack is further bonded to the device wafer formed by the lower fin stack through a bonding process. At this time, the upper fin stack of the sacrificial wafer and the lower fin stack of the device wafer are isolated by the isolation structure sacrificial layer 7. The present invention does not strictly limit the steps of forming a fin stack formed by alternating stacking of a channel sacrificial layer and a channel layer on a semiconductor substrate 1. The isolation structure sacrificial layer 7 can be embedded between the upper fin stack and the lower fin stack using the above-described wafer bonding integration or other monolithic integration methods. In order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above.

[0062] For example, the device wafer and the sacrificial wafer can be substrates made of any semiconductor material such as silicon, silicon germanium, or germanium.

[0063] For example, the device wafer and the sacrificial wafer can also be substrates made of insulating materials such as silicon oxide or ceramic.

[0064] For example, when both the first transistor 2 and the second transistor 3 are gate-around transistors, the materials of the channel sacrificial layer and the channel layer included in the upper fin stack and the lower fin stack can be the same to reduce the limitation of the epitaxial critical thickness and improve the formation quality of the semiconductor device; of course, the materials of the two can also be different.

[0065] For example, the material of the isolation structure sacrificial layer 7 includes silicon oxide or silicon nitride.

[0066] After completing the above wafer bonding process, an initial structure with vertically stacked fins is formed.

[0067] Next, the upper fin stack is etched to form a first transistor 2 channel region with a first width, wherein the extension direction of the first width is consistent with the channel width direction.

[0068] Specifically, such as Figure 10-11 As shown, a dielectric layer (such as silicon nitride SiN) is deposited on the exposed upper fin stack surface; further, through anisotropic etching, dielectric sidewalls perpendicular to the silicon surface are retained to form sidewalls, which provide lateral hard mask support for subsequent three-stage etching, ensuring the self-alignment characteristics of subsequent etching processes.

[0069] Based on the above, further, such as Figure 12As shown, using the sidewall as a mask, the upper fin stack is etched (i.e., the first stage of etching) to remove excess superlattice layers, forming the first transistor 2 channel region with a first width. At this point, the upper fin has been formed, with a fixed width of W1, and the width direction is consistent with the channel width direction.

[0070] Next, as Figure 13 As shown, the isolation structure sacrificial layer 7 is etched downward along the channel width direction (second stage etching), and the tilt angle is adjusted by using etching process parameters (gas ratio, radio frequency power) to transform it into the first isolation structure 4, and the first isolation structure 4 has a trapezoidal structure in the cross section along the channel width direction.

[0071] For example, in the cross section along the width of the channel, the first isolation structure 4 is an isosceles trapezoid, which has a regular structure, high symmetry, and is easy to form precisely during photolithography and etching.

[0072] Specifically, the sidewall tilt angle θ of the isosceles trapezoidal structure can be adjusted by controlling the etching gas ratio and radio frequency power.

[0073] For example, in the cross section along the width of the channel, the first isolation structure 4 can also be a trapezoidal structure composed of multiple trapezoidal segments. The trapezoidal first isolation structure 4 can segmentally adjust the isolation stiffness and electric field distribution, so that the upper part adapts to low stress and the lower part adapts to high isolation, thereby achieving optimal isolation performance.

[0074] Specifically, the sidewall tilt angle, height, and width of each trapezoid can be precisely controlled by dynamically adjusting the etching gas ratio, RF power, bias power, and chamber pressure in stages. Through parameter smoothing transition, the lower base of the upper trapezoid and the upper base of the lower trapezoid can be completely overlapped, forming a continuous, gapless multi-segment trapezoidal structure. This ultimately achieves precise matching of the widths of the upper and lower transistor channels, while ensuring the electrical isolation performance and mechanical stability of the first isolation structure 4.

[0075] Next, as Figure 14 As shown, using the first isolation structure 4 and the sidewall of the trapezoidal structure formed above as a composite mask, the lower fin stack is etched (third stage etching) to remove the excess channel sacrificial layer and channel layer, forming the second transistor 3 channel region with the second width.

[0076] At this point, the lower fins have been formed. Since the lower width of the first isolation structure 4 is W2, the width of the channel region of the second transistor 3 can be fixed at W2. Similarly, the width direction here is consistent with the channel width direction.

[0077] Through the above three etching processes, the final structure exhibits an asymmetric width where the first width W1 is less than the second width W2, perfectly solving the technical problem of mismatched mobility between N-type and P-type transistors.

[0078] Next, source / drain regions are formed on both sides of the channel region of the first transistor 2 and the channel region of the second transistor 3.

[0079] Specifically, such as Figure 15 As shown, shallow trench isolation material (such as silicon oxide) is filled in the source / drain regions and chemically mechanically polished to achieve lateral isolation between transistors, providing a flat substrate for subsequent gate deposition and metal interconnect processes.

[0080] Based on the above, further, such as Figure 16-17 As shown, an oxide layer and polysilicon (or amorphous silicon) are sequentially deposited above the shallow trench isolation region, and CMP is performed. Then, a dummy gate hard mask layer 9 is deposited. Then, the amorphous or polysilicon dummy gate is anisotropically etched and stopped at the top of the upper fin stack. After etching, only the dummy gate hard mask layer 9 above the dummy gate structure is retained, and the source / drain regions are fully exposed.

[0081] Based on the above, further, such as Figure 18 As shown, the first gate sidewall dielectric (such as SiCNO) is deposited on both sides of the dummy gate structure by atomic layer deposition process, and then the first gate sidewall dielectric in the horizontal direction is etched to retain only the dielectric of the dummy gate and the sidewall of the dummy gate hard mask layer 9, thus forming the first gate sidewall 5.

[0082] Based on the above, further, such as Figure 19 As shown, using the dummy gate hard mask layer 9 and the first gate sidewall dielectric as masks, the fin stack of the first source / drain region and the second source / drain region is etched by anisotropic etching process.

[0083] Based on the above, further, such as Figure 20 As shown, isotropic etching is used to precisely etch the inner wall cavity, forming a controllable transverse groove; then, following conventional methods, such as... Figure 21 As shown, the inner wall medium is deposited and etched to form the inner wall 6, exposing the channel material.

[0084] Based on the above, further, such as Figure 22 As shown, source / drain regions are epitaxially grown using methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, or combinations thereof. The source / drain regions can also be doped simultaneously. For example, for a P-type FET, the source / drain region material is boron-doped SiGe (SiGe:B), and for an N-type FET, the source / drain region material is phosphorus-doped silicon (Si:P). After forming the source / drain regions, an isolation layer dielectric is deposited on the source / drain regions, and the isolation layer dielectric is chemically and mechanically polished to planarize it, thus obtaining the isolation layer.

[0085] Based on the above, such as Figure 23 As shown, the fake gate hard mask layer 9 is further removed to expose the fake gate layer.

[0086] Based on the above, such as Figure 24-25 As shown, the dummy gate is further removed.

[0087] Based on the above, such as Figure 26 As shown, the first transistor channel region and the channel sacrificial layer in the first transistor channel region are further selectively etched to form a gate trench, providing space for subsequent metal gate filling.

[0088] Based on the above, such as Figure 27-28 As shown, a high-k metal gate is deposited and CMP is performed to form a metal gate surrounding the channel layer.

[0089] Based on the above, such as Figures 29-31 As shown, further processes such as front-end interconnect, back-end interconnect, and rear-side interconnect are carried out to realize the electrical connection between various parts inside the device and between the device and external circuits, transmit the electrical signals of the device to the required places, and build a complete integrated circuit system. This part of the process can refer to the existing technology and will not be described in detail here.

[0090] Example 3 This embodiment provides an electronic device including the above-described semiconductor devices. The electronic device includes a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0091] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0092] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be effectively combined.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising a semiconductor substrate; A first transistor and a second transistor, the first transistor and the second transistor are stacked vertically in a direction perpendicular to the surface of the semiconductor substrate, and the second transistor is located between the semiconductor substrate and the first transistor; In a cross-section along the channel width direction, a first channel region of the first transistor has a first width, a second channel region of the second transistor has a second width, and the first width is not equal to the second width; A first isolation structure is provided between the first channel region of the first transistor and the second channel region of the second transistor; In a cross-section along the channel width direction, the first isolation structure is a trapezoid-like structure.

2. The semiconductor device according to claim 1, characterized in that, The upper width of the first isolation structure is equal to the first width, and the lower width is equal to the second width.

3. The semiconductor device according to claim 2, characterized in that, The first width is less than the second width.

4. The semiconductor device according to claim 3, characterized in that, The first transistor is an N-type transistor, and the second transistor is a P-type transistor.

5. The semiconductor device according to claim 2, characterized in that, The first transistor is a P-type transistor, the second transistor is an N-type transistor, and the first width is greater than the second width.

6. The semiconductor device according to claim 2, characterized in that, In a cross-section along the channel width direction, the first isolation structure is an isosceles trapezoid.

7. The semiconductor device according to claim 2, characterized in that, In a cross-section along the channel width direction, the first isolation structure is composed of at least two trapezoidal parts, wherein the included angle between the side waist and the lower base of the trapezoid located in the upper part is greater than the included angle between the side waist and the lower base of the trapezoid located in the lower part.

8. The semiconductor device according to claim 7, characterized in that, The lower base of the trapezoid located in the upper part coincides with the upper base of the trapezoid located in the lower part.

9. The semiconductor device according to claim 1, characterized in that, The first channel region is composed of two or more first nanowires or first nanosheets distributed at intervals up and down; the second channel region is composed of two or more second nanowires or second nanosheets distributed at intervals up and down.

10. The semiconductor device according to claim 9, characterized in that, The first transistor includes a first gate that surrounds the first nanowire or the first nanosheet; the second transistor includes a second gate that surrounds the second nanowire or the second nanosheet.

11. The semiconductor device according to claim 9, characterized in that, Along the length direction of the first channel region, both sides of the first channel region are connected to a first source / drain region; Along the length direction of the second channel region, both sides of the second channel region are connected to a second source / drain region; Wherein, the first source / drain region and the second source / drain region are isolated by a second isolation structure.

12. The semiconductor device according to any one of claims 1-11, characterized in that, The sidewall inclination angle θ of the trapezoidal structure is 10°. o -90 o .

13. The semiconductor device according to any one of claims 1-11, characterized in that, The first width is W1, the second width is W2, wherein, W1 < W2, and 0 < (W2 - W1) / W1 ≤ 50%.

14. A method for fabricating a semiconductor device, characterized in that, Including the following steps: Providing a semiconductor substrate; Forming a fin stack formed by alternately stacking a channel sacrificial layer and a channel layer on the semiconductor substrate, the fin stack includes an upper fin stack and a lower fin stack, and the upper fin stack and the lower fin stack are isolated by an isolation structure sacrificial layer; Etching the upper fin stack to remove the redundant channel sacrificial layer and channel layer, and forming a first transistor channel region having a first width, wherein the extending direction of the first width is consistent with the channel width direction; The isolation structure sacrificial layer is etched along the width direction of the channel to transform it into a first isolation structure. The first isolation structure is made into a trapezoidal structure in the cross section along the width direction of the channel. The upper width of the trapezoidal structure is equal to the first width, and the lower width is the second width. The first width and the second width are not equal. The lower fin stack is etched to remove excess channel sacrificial layer and channel layer, forming a second transistor channel region with the second width; Source / drain regions are formed on both sides of the first transistor channel region and the second transistor channel region; A gate trench is formed by removing the channel sacrificial layer between the first transistor channel region and the second transistor channel region, and a gate is formed in the gate trench.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The step of forming a fin stack on the semiconductor substrate, consisting of alternating stacks of a channel sacrificial layer and a channel layer, includes: The lower fin stack is formed on a semiconductor substrate, the isolation structure sacrificial layer is formed on the lower fin stack, the upper fin stack is formed on another substrate, and the other substrate is bonded to the isolation structure sacrificial layer by a bonding process.

16. The method for fabricating a semiconductor device according to claim 14, characterized in that, When etching the sacrificial layer of the isolation structure, the sidewall tilt angle θ of the trapezoidal structure is adjusted by controlling the etching gas ratio and radio frequency power.

17. The method for fabricating a semiconductor device according to claim 14, characterized in that, The material of the sacrificial layer of the isolation structure includes silicon oxide or silicon nitride.

18. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 1-13; Electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

Images