Array substrate, preparation method thereof and display panel

Abstract

The embodiment of the specification provides an array substrate, in which a planarization layer comprises a plurality of thinning regions and a first through hole penetrating through the thinning regions in the thinning regions. Thus, when the first through hole is formed, the thinning regions with a smaller thickness can be used as a basis, which is beneficial to accurately form the first through hole with a smaller size, thereby meeting the display requirements of a high-resolution display panel and improving the display effect of the display panel. Specifically, the thinner thinning regions can improve the etching selectivity when the first through hole is formed by etching. The etching selectivity refers to the etching rate ratio of the etching target material to the mask material. When the planarization layer is etched, the high-resolution photoresist as the protection of the mask is more effective, can better protect the part that needs to be reserved, ensures the accuracy of the opening, and can more accurately define the shape and size of the first through hole, so that the first through hole with a size meeting the requirements can be accurately formed.

Description

Technical Field

[0001] This specification relates to the field of display technology, specifically to display panel technology within the field of display technology, and more specifically to an array substrate and its preparation method, and a display panel. Background Technology

[0002] As living standards continue to improve, users have increasingly higher requirements for the display effects of various electronic product display panels. It is necessary to continuously improve the display effects of display panels to meet users' growing demands for display quality. Summary of the Invention

[0003] This specification provides a display panel and its manufacturing method, as well as an electronic device, to improve the display effect of the display panel.

[0004] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0005] In a first aspect, an array substrate is provided, comprising:

[0006] Substrate;

[0007] A planarization layer located on one side of the substrate, the planarization layer comprising: a plurality of thinning regions and a first via located in the thinning regions and penetrating the thinning regions.

[0008] In conjunction with the first aspect, in some embodiments of the first aspect, the planarization layer further includes: a plurality of main planarization regions surrounding the thinning region, the thickness of the main planarization regions being greater than the thickness of the thinning region.

[0009] In conjunction with the first aspect, in some embodiments of the first aspect, the thinning region includes a ramp region and a sub-flat region;

[0010] The slope area is located between the sub-flat area and the main flat area, and the sub-flat area is arranged around the first through hole;

[0011] In the slope region, the thickness of the planarization layer gradually decreases along a first direction; the first direction includes the direction from the main planarization region to the sub-planarization region.

[0012] In conjunction with the first aspect, in some embodiments of the first aspect, the array substrate further includes:

[0013] An electrode layer located between the substrate and the planarization layer, wherein the first via exposes at least a portion of the electrode layer;

[0014] Optionally, the electrode layer includes a plurality of first electrodes, and the first via exposes at least a portion of the first electrodes;

[0015] Optionally, the first electrode includes an anode;

[0016] Optionally, it further includes a light-emitting material layer filling the first through-hole.

[0017] Secondly, a method for fabricating an array substrate is provided, comprising:

[0018] Provide substrate;

[0019] A planarization layer is formed on one side of the substrate, the planarization layer comprising: a plurality of thinning regions and a first via located in the thinning regions and penetrating the thinning regions.

[0020] In conjunction with the second aspect, in some embodiments of the first aspect, forming a planarization layer on one side of the substrate includes:

[0021] A flat material layer of uniform thickness is formed on one side of the substrate;

[0022] Multiple thinning zones are formed in the flat material layer;

[0023] In the thinning region, a first through-hole is formed penetrating the thinning region;

[0024] Optionally, the planar material layer includes a polyimide layer, an acrylic layer, or a siloxane layer.

[0025] In conjunction with the second aspect, in some embodiments of the first aspect, forming a plurality of thinning zones in the flat material layer includes:

[0026] A first photoresist layer is formed on the surface of the flat material layer;

[0027] Using a partially transparent photomask as a mask, the first photoresist layer is exposed and developed to etch the first photoresist layer to form a first patterned layer;

[0028] Using the first patterned layer as a mask, the planar material layer is thinned to form a plurality of thinned regions in the planar material layer;

[0029] Optionally, the partially transparent mask may include a grayscale mask or a halftone mask.

[0030] In conjunction with the second aspect, in some embodiments of the first aspect, forming the first through-hole penetrating the thinning region in the thinning region includes:

[0031] A second photoresist layer is formed covering the planar material layer;

[0032] The second photoresist layer is patterned to form a plurality of second vias, the second vias exposing a portion of the thinned region;

[0033] Using the patterned second photoresist layer as a mask, the planar material layer is etched to form the first through-hole penetrating the thinned region in the thinned region;

[0034] Optionally, etching the planar material layer includes:

[0035] The planar material layer is etched using a dry etching process.

[0036] In conjunction with the second aspect, in some embodiments of the first aspect, the step of forming a planarization layer on the substrate side further includes:

[0037] An electrode layer is formed on one side of the substrate;

[0038] The first via exposes at least a portion of the electrode layer;

[0039] Optionally, the electrode layer includes a first electrode, and the first via exposes at least a portion of the first electrode.

[0040] Thirdly, an electronic device is provided, including a display panel as described in any of the above embodiments.

[0041] As can be seen from the above technical solution, in the array substrate provided in the embodiments of this specification, the planarization layer includes multiple thinning regions and a first via hole located in the thinning regions and penetrating the thinning regions. Thus, when forming the first via hole, it can be based on the thinner thinning regions, which is beneficial for accurately forming a smaller-sized first via hole, thereby meeting the display requirements of high-resolution display panels and improving the display effect of the display panel. Specifically, the thinner thinning regions can improve the etching selectivity when etching to form the first via hole. Etching selectivity refers to the etching rate ratio of the target material to the mask material. When the planarization layer is thinner, the high-resolution photoresist acts more effectively as a mask during etching, better protecting the parts that need to be retained, ensuring the accuracy of the opening, and more precisely defining the shape and size of the first via hole, thereby accurately forming a first via hole with the required size. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0043] Figure 1 A top view of an array substrate provided for one embodiment of this specification;

[0044] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure along line AA';

[0045] Figure 3 A cross-sectional structural diagram of an array substrate provided for one embodiment of this specification;

[0046] Figure 4 A cross-sectional view of another array substrate provided for one embodiment of this specification;

[0047] Figure 5 A schematic diagram of the structure of a display panel provided for one embodiment of this specification;

[0048] Figure 6 A schematic cross-sectional view of a substrate provided for one embodiment of this specification;

[0049] Figure 7 A schematic flowchart illustrating a method for fabricating an array substrate according to one embodiment of this specification;

[0050] Figure 8 A schematic diagram illustrating the fabrication process of an array substrate according to one embodiment of this specification;

[0051] Figure 9 This is a schematic diagram illustrating the preparation process of a planarization layer according to one embodiment of this specification.

[0052] Explanation of reference numerals in the attached figures

[0053] 10-Substrate; 20-Functional film layer; 30-Planarization layer; 30'-Planarization material layer; 40-Electrode layer; 31-Thinning region; 32-First via; 33-Main planarization region; 34-Slope region; 35-Sub-planarization region; 11-Polyimide film layer; 12-Inorganic film layer; 100-Display panel. Detailed Implementation

[0054] Unless otherwise defined, the technical or scientific terms used in the embodiments of this specification shall have the ordinary meaning understood by one of ordinary skill in the art to which this specification pertains. The terms "first," "second," and similar terms used in the embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to avoid confusion of constituent elements.

[0055] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0056] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0057] Overview

[0058] With the continuous development of display technology, users have increasingly higher requirements for the display effects of various electronic devices, and high-resolution display panels can bring excellent display effects. However, with the continuous increase in resolution, researchers in related fields are facing new challenges. Taking AMOLED (Active-Matrix Organic Light-Emitting Diode) display panels as an example, research has found that it is currently impossible to create small-sized vias in the planarization layer (PLN), thus limiting the development of high-resolution array substrates and display panels.

[0059] Research has revealed that the materials currently used to form planarization layers are mostly organic materials, and the photoresist used as a mask when forming vias is also an organic polymer. This means that the photoresist is consumed as the etching process progresses. Since the planarization layer is usually quite thick and the etching process takes a long time, the photoresist's masking effect is poor. It cannot effectively protect the parts that do not need to be etched, resulting in poor etching selectivity during via etching and failing to meet the requirements for forming small-sized vias.

[0060] To solve this problem, the inventors discovered that when forming the planarization layer, the area where the first via needs to be formed can be thinned first to form a thinned region, and then etching can be performed in the thinned region to form the first via through the thinned region. In this process, because a thinning region is pre-formed, the thickness of the thinning region is relatively small. Therefore, when etching the thinned region to form the first via, the thinner region helps to improve the etching rate and etching selectivity of the first via, thereby improving the masking effect of the photoresist. This is because in etching processes such as dry etching, the etching rate is positively correlated with the thickness of the material to be etched. Thinner materials require less time to etch under the same conditions, thus allowing for more precise control of the etching depth and size. Furthermore, the thinning region can improve etching selectivity, which refers to the ratio of the etching rate of the target material to the etching rate of the mask material. When the planarization layer is thinner, the high-resolution photoresist acts more effectively as a mask during etching, better protecting the parts that need to be preserved, ensuring the accuracy of the opening, and enabling a more precise definition of the shape and size of the first via, thus allowing for the precise formation of a first via with the required dimensions. Furthermore, when etching a thinner region to form the first via, the etching process parameters (such as etching gas, power, time, etc.) can be adjusted more precisely, thereby achieving the accurate formation of a smaller-sized first via.

[0061] Based on the above concept, this specification provides an array substrate and a method for fabricating the same. The array substrate and the method for fabricating the same provided in this specification will be described exemplarily below with reference to the accompanying drawings.

[0062] Exemplary methods

[0063] One embodiment of this specification provides an array substrate, such as Figure 1 and Figure 2 As shown, it includes:

[0064] Substrate 10;

[0065] A planarization layer 30 is located on one side of the substrate 10. The planarization layer 30 includes a plurality of thinning regions 31 and a first through-hole 32 located in the thinning regions 31 and penetrating the thinning regions 31.

[0066] Figure 1 A top view of the array substrate structure is shown. Figure 2 It shows Figure 1 The cross-sectional structure diagram along line AA' shows that, in addition to the substrate 10 and the planarization layer 30, the display panel may also include other film layer structures. For clarity, Figure 1 and Figure 2The planarization layer 30 on the side opposite to the substrate 10 and the film structure filling the first via 32 are not shown in the figure. In some embodiments, such as Figure 2 As shown, the substrate 10 and the planarization layer 30 may further include functional film layers 20 for forming structures such as thin film transistor (TFT) arrays. These functional film layers 20 may include multiple metal layers and dielectric layers located between the metal layers. These dielectric layers may include inorganic insulating layers. In some embodiments, the first via 32 may be referred to as a pixel via. The first via 32 may be used to fill a light-emitting material layer. Therefore, the size of the first via 32 determines the resolution of the array substrate to a certain extent.

[0067] In this embodiment, when forming the planarization layer 30, the area of ​​the planarization layer 30 where the first via 32 is to be formed can be thinned first to form a thinned region 31, and then etching can be performed in the thinned region 31 to form the first via 32 that penetrates the thinned region 31. In this process, since the thinning region 31 is pre-formed, its thickness is relatively small. Therefore, when etching the thinning region 31 to form the first via 32, the thinner thinning region 31 helps to improve the etching rate and etching selectivity of the first via 32, thereby improving the masking effect of the photoresist. This is because in etching processes such as dry etching, the etching rate is positively correlated with the thickness of the material to be etched. Thinner materials require less time to etch under the same conditions, so the etching depth and size can be controlled more precisely. In addition, the thinning region 31 can improve the etching selectivity. Etching selectivity refers to the etching rate ratio of the target material to the mask material. When the planarization layer 30 is etched, the high-resolution photoresist acts more effectively as a mask, better protecting the parts that need to be retained, ensuring the accuracy of the opening, and more precisely defining the shape and size of the first via 32, thereby accurately forming the first via 32 with the required size. Furthermore, when etching the thinner thinning region 31 to form the first through hole 32, the etching process parameters (such as etching gas, power, time, etc.) can be adjusted more precisely, thereby achieving the precise formation of a smaller first through hole 32.

[0068] In one implementation, such as Figure 3 As shown, the planarization layer 30 further includes a plurality of main planarization regions 33 surrounding the thinning region 31, wherein the thickness H1 of the main planarization region 33 is greater than the thickness H2 of the thinning region 31.

[0069] In this embodiment, the main flattening region 33 may be disposed around the thinning region 31, and the thickness of the main flattening region 33 may be relatively thick to provide a flat area for the film layer to be formed subsequently. Meanwhile, the thickness of the thinning region 31 may be relatively thin to provide higher etching selectivity when forming the first via 32, thereby meeting the requirement for forming a smaller-sized first via 32.

[0070] In one implementation, such as Figure 4 As shown, the thinning region 31 includes a slope region 34 and a sub-flat region 35;

[0071] The slope area 34 is located between the sub-flat area 35 and the main flat area 33, and the sub-flat area 35 is arranged around the first through hole 32;

[0072] In the slope region 34, the thickness of the planarization layer 30 gradually decreases along a first direction; the first direction includes the direction from the main planarization region 33 to the sub-planarization region 35.

[0073] exist Figure 4 In the diagram, the arrow in DR1 indicates the first direction. In this embodiment, a slope region 34 and a sub-flat region 35 can be provided in the thinning region 31. The slope region 34 includes a slope extending from the main flat region 33 to the sub-flat region 35. This slope can reduce the angle of the film layers subsequently covered on it, reducing the probability of these film layers breaking due to excessively steep angles in the slope region 34, which is beneficial to improving the reliability of the array substrate.

[0074] In one implementation, reference Figures 2-4 The array substrate further includes an electrode layer 40 located between the substrate 10 and the planarization layer 30, wherein the first via 32 exposes at least a portion of the electrode layer 40.

[0075] Optionally, the electrode layer 40 includes a plurality of first electrodes, and the first through-hole 32 exposes at least a portion of the first electrodes;

[0076] Optionally, the first electrode includes an anode;

[0077] Optionally, it also includes a light-emitting material layer filling the first through-hole 32.

[0078] In this embodiment, an electrode layer 40 may be disposed between the substrate 10 and the planarization layer 30. The electrode layer 40 may include a plurality of first electrodes, and the first electrodes may include an anode. In this way, the smaller size of the first via 32 can improve the resolution of the array substrate.

[0079] Exemplary display panels and electronic devices

[0080] like Figure 5 As shown, one embodiment of this specification also provides a display panel 100, including an array substrate as described in any of the above embodiments.

[0081] In some embodiments, the display panel 100 may also include film layer structures such as a thin film encapsulation (TFE) layer, but this specification does not limit this.

[0082] In one embodiment of this specification, an electronic device is also provided, including a display panel 100 as described in any of the above embodiments.

[0083] The display panel 100 and electronic device provided in the embodiments of this specification include an array substrate as described in any of the above embodiments. In this array substrate, the planarization layer 30 includes a plurality of thinning regions 31 and a first via 32 penetrating the thinning regions 31. Thus, when forming the first via 32, it can be based on the thinner thinning regions 31, which is beneficial for accurately forming the smaller size of the first via 32, thereby meeting the display requirements of the high-resolution display panel and improving the display effect of the display panel. Specifically, the thinner thinning regions 31 can improve the etching selectivity when etching to form the first via 32. Etching selectivity refers to the etching rate ratio of the target material to the mask material. When the planarization layer 30 is thinner, the high-resolution photoresist acts more effectively as a mask during etching, which can better protect the parts that need to be retained, ensure the accuracy of the opening, and more accurately define the shape and size of the first via 32, thereby accurately forming the first via 32 with the required size.

[0084] Exemplary methods

[0085] In one embodiment of this specification, a method for fabricating an array substrate is also provided, such as... Figure 6 As shown, it includes:

[0086] S601: Provides substrate 10;

[0087] Optionally, the substrate 10 includes, but is not limited to, a flexible substrate 10 and a non-flexible substrate 10, wherein the flexible substrate 10 includes, but is not limited to, a polyimide (PI) substrate 10. In some embodiments, reference is made to... Figure 7The polyimide substrate 10 can be a composite substrate 10, which may include a stacked structure of a double-layer polyimide film layer 11 and an inorganic film layer 12. The inorganic film layer 12 may include a silicon dioxide layer or a silicon nitride layer, etc., and may be located between the two polyimide film layers. In this composite substrate 10, the polyimide film layer has good flexibility, enabling the array substrate or display panel to maintain structural integrity when bent and folded, making it suitable for flexible display applications. The inorganic film layer typically has high mechanical strength, providing additional support, enhancing the overall mechanical properties of the composite substrate 10, and reducing the risk of damage during manufacturing and use. The non-flexible substrate 10 may include a glass substrate 10, etc. This specification does not limit this; the specific choice depends on the actual situation.

[0088] S602: A planarization layer 30 is formed on one side of the substrate 10. The planarization layer 30 includes a plurality of thinning regions 31 and a first through-hole 32 located in the thinning regions 31 and penetrating the thinning regions 31.

[0089] refer to Figure 8 , Figure 8 This diagram illustrates the process of forming a planarization layer 30 on substrate 10. In some embodiments, such as Figure 8 As shown, before forming the planarization layer 30, the step of forming an electrode layer 40 on one side of the substrate 10 may be included. Optionally, the first via 32 exposes at least a portion of the electrode layer 40; alternatively, the electrode layer 40 includes a first electrode, and the first via 32 exposes at least a portion of the first electrode.

[0090] In one implementation, reference Figure 9 , Figure 9 The feasible process for forming a planarization layer 30 on one side of the substrate 10 is shown, specifically including:

[0091] A flat material layer 30' of uniform thickness is formed on one side of the substrate 10;

[0092] Multiple thinning zones 31 are formed in the flat material layer 30';

[0093] In the thinning region 31, a first through hole 32 is formed that penetrates the thinning region 31;

[0094] Optionally, the planar material layer 30' includes: a polyimide layer, an acrylic layer, or a siloxane layer.

[0095] In this embodiment, when forming the planarization layer 30, the area of ​​the planarization material layer 30' where the first through hole 32 is to be formed can be thinned first to form a thinned region 31, and then etching can be performed in the thinned region 31 to form the first through hole 32 penetrating the thinned region 31. In this process, since the thinning region 31 is pre-formed, its thickness is relatively small. Therefore, when etching the thinning region 31 to form the first via 32, the thinner thinning region 31 helps to improve the etching rate and etching selectivity of the first via 32, thereby improving the masking effect of the photoresist. This is because in etching processes such as dry etching, the etching rate is positively correlated with the thickness of the material to be etched. Thinner materials require less time to etch under the same conditions, so the etching depth and size can be controlled more precisely. In addition, the thinning region 31 can improve the etching selectivity. Etching selectivity refers to the etching rate ratio of the target material to the mask material. When the planarization layer 30 is etched, the high-resolution photoresist acts more effectively as a mask, better protecting the parts that need to be retained, ensuring the accuracy of the opening, and more precisely defining the shape and size of the first via 32, thereby accurately forming the first via 32 with the required size. Furthermore, when etching the thinner thinning region 31 to form the first through hole 32, the etching process parameters (such as etching gas, power, time, etc.) can be adjusted more precisely, thereby achieving the precise formation of a smaller first through hole 32.

[0096] Optionally, forming a plurality of thinning regions 31 in the flat material layer 30' includes:

[0097] A first photoresist layer is formed on the surface of the planar material layer 30';

[0098] Using a partially transparent photomask as a mask, the first photoresist layer is exposed and developed to etch the first photoresist layer to form a first patterned layer;

[0099] Using the first patterned layer as a mask, the planar material layer 30' is thinned to form a plurality of thinned regions 31 in the planar material layer 30'.

[0100] Optionally, the partially transparent mask may include a grayscale mask or a halftone mask.

[0101] In this embodiment, a partially transmissive mask is used as a mask to expose and develop the first photoresist layer into a first patterned layer of varying thickness. The first patterned layer is thinner in the thinning region 31, so that when the planar material layer 30' is subsequently thinned, the photoresist on the thinning region 31 can be quickly etched away, thereby achieving the purpose of etching and thinning the planar material layer 30' in the thinning region 31.

[0102] Partially transparent masks are distinguished from fully transparent masks. Fully transparent masks, including ILD (Interlayer Dielectric) masks, have completely transparent openings. Partially transparent masks, on the other hand, achieve different grayscale levels or partial exposure effects by allowing only partial light transmission, making them suitable for processes requiring fine pattern control. Gray masks can achieve multiple grayscale levels, with transmittance varying from completely transparent to completely opaque. This multi-level grayscale characteristic allows for very fine pattern control. Halftone masks have a fixed translucency, with transmittance between completely transparent and completely opaque. This fixed translucency makes them suitable for applications requiring partial exposure and intermediate grayscale effects.

[0103] In one embodiment, forming the first through-hole 32 penetrating the thinning region 31 in the thinning region 31 includes:

[0104] A second photoresist layer is formed covering the planar material layer 30';

[0105] The second photoresist layer is patterned to form a plurality of second vias, the second vias exposing a portion of the thinned region 31;

[0106] Using the patterned second photoresist layer as a mask, the planar material layer 30' is etched to form the first through-hole 32 penetrating the thinning region 31 in the thinning region 31;

[0107] Optionally, etching the planar material layer 30' includes:

[0108] The planar material layer 30' is etched using a dry etching process.

[0109] Dry etching achieves high-precision pattern transfer by precisely controlling etching parameters (such as etching gas, power, pressure, and temperature). This allows the etching process to precisely follow the pattern of the mask, forming very small and uniform holes. Dry etching enables high-resolution pattern definition and is suitable for fabricating holes with dimensions at the micrometer or even nanometer scale. For example, dry etching techniques such as plasma etching and reactive ion etching (RIE) can achieve etching of first vias 32 smaller than 3 micrometers in the thinned region 31, and even reach the submicrometer level.

[0110] Dry etching typically exhibits anisotropic properties, meaning that etching primarily occurs along the vertical direction, with very little undercut. This results in vias with very steep sidewalls, allowing the via shape and size to more closely approximate design values ​​and reducing dimensional deviations. Anisotropic etching allows for precise control of the via shape, ensuring that the depth-to-diameter ratio (aspect ratio) meets design requirements, which is crucial for high-density integrated micro / nano structures.

[0111] In summary, in the method for fabricating the array substrate provided in this embodiment, when forming the planarization layer 30, the area of ​​the planarization layer 30 where the first via 32 is to be formed can be thinned first to form a thinned region 31, and then etching can be performed in the thinned region 31 to form the first via 32 penetrating the thinned region 31. In this process, since the thinning region 31 is pre-formed, its thickness is relatively small. Therefore, when etching the thinning region 31 to form the first via 32, the thinner thinning region 31 helps to improve the etching rate and etching selectivity of the first via 32, thereby improving the masking effect of the photoresist. This is because in etching processes such as dry etching, the etching rate is positively correlated with the thickness of the material to be etched. Thinner materials require less time to etch under the same conditions, so the etching depth and size can be controlled more precisely. In addition, the thinning region 31 can improve the etching selectivity. Etching selectivity refers to the etching rate ratio of the target material to the mask material. When the planarization layer 30 is etched, the high-resolution photoresist acts more effectively as a mask, better protecting the parts that need to be retained, ensuring the accuracy of the opening, and more precisely defining the shape and size of the first via 32, thereby accurately forming the first via 32 with the required size. Furthermore, when etching the thinner thinning region 31 to form the first through hole 32, the etching process parameters (such as etching gas, power, time, etc.) can be adjusted more precisely, thereby achieving the precise formation of a smaller first through hole 32.

[0112] In one embodiment, the electronic device provided in any embodiment of this specification may be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user device. By way of example and not limitation, the terminal device may be a mobile phone, tablet computer, computer with wireless transceiver capabilities, virtual reality (VR) terminal device, augmented reality (AR) terminal device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical care, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc.

[0113] Electronic devices can also be network devices, which can be any device with wireless transceiver capabilities. These devices include, but are not limited to: evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), base transceiver station (BTS), home base station (e.g., home evolved node B, or home node B, HNB), building base band unit (BBU), access point (AP), wireless relay node, wireless backhaul node, transmission point (TP), or transmission and reception point (TRP) in a wireless fidelity (WIFI) system. They can also be gNBs in 5G, such as NR, or transmission points (TRPs or TPs), one or a group of antenna panels (including multiple antenna panels) of a base station in a 5G system, or network nodes constituting a gNB or transmission point, such as BBUs or distributed units (DUs).

[0114] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] The embodiments described above are merely illustrative of several implementation methods outlined in this specification. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the solutions provided in this specification. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection for this patent should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, include: Substrate; A planarization layer located on one side of the substrate, the planarization layer comprising: a plurality of thinning regions and a first via located in the thinning regions and penetrating the thinning regions.

2. The array substrate according to claim 1, characterized in that, The planarization layer further includes a plurality of main planarization regions surrounding the thinning region, wherein the thickness of the main planarization regions is greater than the thickness of the thinning region.

3. The array substrate according to claim 2, characterized in that, The thinning zone includes a sloping zone and a sub-flat zone; The slope area is located between the sub-flat area and the main flat area, and the sub-flat area is arranged around the first through hole; In the slope region, the thickness of the planarization layer gradually decreases along a first direction; the first direction includes the direction from the main planarization region to the sub-planarization region.

4. The array substrate according to claim 1, characterized in that, Also includes: An electrode layer located between the substrate and the planarization layer, wherein the first via exposes at least a portion of the electrode layer; Optionally, the electrode layer includes a plurality of first electrodes, and the first via exposes at least a portion of the first electrodes; Optionally, the first electrode includes an anode; Optionally, it further includes a light-emitting material layer filling the first through-hole.

5. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 4.

6. A method for fabricating an array substrate, characterized in that, include: Provide substrate; A planarization layer is formed on one side of the substrate, the planarization layer comprising: a plurality of thinning regions and a first via located in the thinning regions and penetrating the thinning regions.

7. The method according to claim 6, characterized in that, The step of forming a planarization layer on one side of the substrate includes: A flat material layer of uniform thickness is formed on one side of the substrate; Multiple thinning zones are formed in the flat material layer; In the thinning region, a first through-hole is formed penetrating the thinning region; Optionally, the planar material layer includes a polyimide layer, an acrylic layer, or a siloxane layer.

8. The method according to claim 7, characterized in that, The formation of multiple thinning zones in the flat material layer includes: A first photoresist layer is formed on the surface of the flat material layer; Using a partially transparent photomask as a mask, the first photoresist layer is exposed and developed to etch the first photoresist layer to form a first patterned layer; Using the first patterned layer as a mask, the planar material layer is thinned to form a plurality of thinned regions in the planar material layer; Optionally, the partially transparent mask may include a grayscale mask or a halftone mask.

9. The method according to claim 7, characterized in that, The first through-hole formed in the thinning region includes: A second photoresist layer is formed covering the planar material layer; The second photoresist layer is patterned to form a plurality of second vias, the second vias exposing a portion of the thinned region; Using the patterned second photoresist layer as a mask, the planar material layer is etched to form the first through-hole penetrating the thinned region in the thinned region; Optionally, etching the planar material layer includes: The planar material layer is etched using a dry etching process.

10. The method according to claim 6, characterized in that, The process before forming the planarization layer on one side of the substrate further includes: An electrode layer is formed on one side of the substrate; The first via exposes at least a portion of the electrode layer; Optionally, the electrode layer includes a first electrode, and the first via exposes at least a portion of the first electrode.

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