Electronic device

Abstract

An electronic device can include a base layer including an active area and a peripheral area; pixels in the active area, each of the pixels including a pixel circuit; a repair pixel circuit in the peripheral area; a data line connected to the pixels; and a repair line connected to the repair pixel circuit and extending to the active area. A portion of the repair line can overlap the data line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0021274, filed on February 19, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure described herein relate to pixel-based electronic devices with improved reliability. Background Technology

[0004] A display panel included in an electronic device comprises multiple pixels and drivers (e.g., scan drivers and data drivers) that control the multiple pixels. Each of the multiple pixels includes a display element and a pixel driver that controls the display element. The pixel driver may include multiple transistors and at least one capacitor organically connected to each other. Data lines connected to the pixels need to be shielded to prevent coupling to adjacent conductive patterns. Summary of the Invention

[0005] Embodiments of this disclosure provide an electronic device including pixels that has improved reliability by utilizing repair lines in the construction of shielding data lines.

[0006] According to one or more embodiments, an electronic device may include: a substrate layer including an effective region and a peripheral region; pixels in the effective region, each pixel including pixel circuitry; repair pixel circuitry in the peripheral region; a data line connected to the pixel; and a repair line connected to the repair pixel circuitry and extending into the effective region. A portion of the repair line may overlap with the data line. Attached Figure Description

[0007] The above and other objects and features of this disclosure will become apparent from the detailed description of its embodiments with reference to the accompanying drawings.

[0008] Figure 1A It is a block diagram of an electronic device according to one or more embodiments.

[0009] Figure 1B The illustrations are schematic diagrams of electronic devices according to various embodiments.

[0010] Figure 2A This is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0011] Figure 2B This is a perspective view of a curved electronic device according to one or more embodiments of the present disclosure.

[0012] Figure 2CThis is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure.

[0013] Figure 3A This is a plan view of an electronic device according to one or more embodiments of the present disclosure.

[0014] Figure 3B This is a repair pixel and an equivalent circuit diagram of the pixel according to one or more embodiments of the present disclosure.

[0015] Figure 4 This is an enlarged plan view of the display area according to one or more embodiments of the present disclosure.

[0016] Figure 5 It is a plan view of the stacking order of conductive patterns included in a unit pixel according to one or more embodiments of the present disclosure.

[0017] Figure 6 It is along Figure 5 The cross-sectional view taken from line I-I'.

[0018] Figures 7A to 7F This is a plan view illustrating the stacking order of layers of conductive patterns included in unit pixels of various patterns according to one or more embodiments of the present disclosure. Detailed Implementation

[0019] In the specification, the statement that the first component (or area, layer, part, etc.) is "on" the second component, "connected" to the second component, or "linked" to the second component means that the first component is directly on the second component, directly connected to or linked to the second component, or that the third component is located between them.

[0020] The same reference numerals refer to the same parts. Furthermore, in the drawings, for the sake of the effectiveness of the description of the technical content, the thickness, scale, and dimensions of the parts are exaggerated. The term "and / or" includes one or more combinations of the associated elements defined in each of them.

[0021] Although the terms “first,” “second,” etc., may be used to describe various components, these components should not be construed as being limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope and spirit of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The articles “a,” “an,” and “the / described” are singular because they have a single referent, but the use of the singular forms in the specification should not preclude the existence of more than one referent.

[0022] Furthermore, the terms "below," "under," "above," and "above" are used to describe the relevance of the components illustrated in the accompanying drawings. These terms are relative concepts and are described relative to the directions indicated in the drawings.

[0023] It will be understood that the terms “comprising,” “including,” and “having,” etc., specify the presence of the features, numbers, steps, operations, elements, or components or combinations thereof described in the specification, without excluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, or components or combinations thereof.

[0024] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0025] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0026] Figure 1A It is a block diagram of an electronic device according to one or more embodiments. Figure 1B The illustrations are schematic diagrams of electronic devices according to various embodiments.

[0027] Figure 1A This is a block diagram of an electronic device according to one or more embodiments. Reference Figure 1A An electronic device 10 according to one or more embodiments may include a display module (e.g., a display panel or display component) 11, a processor 12, a memory 13, and a power module 14.

[0028] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0029] Data and / or instructions required to operate the processor 12 or display module 11 can be stored in the memory 13. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the provided signals and output image information through the display screen.

[0030] The power module 14 may include a power module (e.g., a power circuit) such as a power adapter or battery device (e.g., a battery pack) and a power conversion module (e.g., a power conversion circuit such as a DC-DC converter or an AC-DC converter) that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0031] At least one of the components of the electronic device 10 described above may be included in the display device according to the embodiments described above. Furthermore, some of the individual modules functionally included in a single module may be included in the display device, while others may be provided separately from the display device. For example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices in the electronic device 10 besides the display device.

[0032] Figure 1B The illustrations are schematic diagrams of electronic devices according to various embodiments.

[0033] refer to Figure 1B The various electronic devices applied to the display device according to the embodiments may include not only electronic devices for displaying images (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) that include display modules, as well as electronic devices 10_3 for vehicles (such as central information displays disposed in dashboards, central instrument panels, and dashboards for vehicles, and rearview mirror displays).

[0034] The display device / display panel according to one or more embodiments can be applied to various electronic devices. The electronic device according to one or more embodiments includes the display device / display panel described above, and may further include modules or devices having additional functions in addition to the functions of the display device / display panel.

[0035] In the following description, the electronic devices described in the accompanying drawings can be applied to embodiments of the electronic devices described above.

[0036] Figure 2A This is a perspective view of an electronic device according to one or more embodiments of the present disclosure. Figure 2B This is a perspective view of a curved electronic device according to one or more embodiments of the present disclosure. Figure 2C This is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure.

[0037] An electronic device ED according to one or more embodiments may include a display surface DP-IS. The display surface DP-IS may be parallel to a surface defined by a first direction DR1 and a second direction DR2. The normal direction of the display surface DP-IS (i.e., the thickness direction of the display panel DP) represents a third direction DR3. The front (or upper) and rear (or lower) surfaces of the layers or cells described later are divided by the third direction DR3.

[0038] Electronic devices (EDs) may include a display area (DA) and a non-display area (NDA). Pixels range from PX11 to PXnm (see...). Figure 3A ) is set in the display area DA, and pixels PX11 to PXnm (see Figure 3A The non-display area NDA is not located within the display surface DP-IS. The non-display area NDA is defined along the periphery of the display surface DP-IS. The non-display area NDA may surround the display surface DA. In one or more embodiments of this disclosure, the non-display area NDA may be omitted, or it may be located only on one side of the display surface DA.

[0039] refer to Figure 2B According to one or more embodiments, the electronic device ED-1 can be bent along the first direction DR1 relative to a virtual axis AX extending in the second direction DR2. However, this disclosure is not limited thereto, and the electronic device ED-1 can be bent relative to a plurality of axes extending in the first direction DR1 or in different directions.

[0040] According to one or more embodiments, electronic devices ED and ED-1 can be rollable, foldable, or sliding electronic devices. In this case, electronic devices ED and ED-1 have flexible characteristics and can be folded or rolled up by a hinge member or a rolling member included in the housing. Accordingly, electronic devices ED and ED-1 may include a curved display surface DP-IS or a three-dimensional display surface DP-IS. The three-dimensional display surface DP-IS may include multiple display areas indicating different directions. Electronic devices ED and ED-1 may correspond to the electronic device 10 illustrated in FIG. 1.

[0041] According to one or more embodiments, unit pixels PXUs arranged along a first direction DR1 and a second direction DR2 can be disposed on a display surface DP-IS. A unit pixel PXU may include at least two pixels PX11 to PXnm that generate source light (see...). Figure 3A ).

[0042] Including pixels PX11 to PXnm in a single pixel unit PXU (reference) Figure 3AThe size, shape, and arrangement of the emitting area of ​​each of the pixels included in the unit pixel PXU are not limited to any one type. For example, the emitting area sizes of the pixels included in the unit pixel PXU can be different from each other. In addition, each emitting area can have a circular or polygonal shape on the plane.

[0043] refer to Figure 2C The electronic device ED and electronic device ED-1 according to the present disclosure may include a display panel DP, a window panel WD disposed on the display panel DP, and a light control layer OSL disposed between the display panel DP and the window panel WD.

[0044] The display panel DP includes a substrate layer BS, a circuit element layer DP-CL disposed on the substrate layer BS, a display element layer DP-OLED, and a packaging layer TFE. The display panel DP may further include functional layers such as anti-reflective layers and refractive index adjustment layers. The circuit element layer DP-CL includes at least multiple insulating layers and circuit elements. The substrate layer BS may include a display area DA (or active area) and a non-display area NDA (or peripheral area). The insulating layers, described below, may include organic layers and / or inorganic layers.

[0045] The substrate layer BS may include a synthetic resin film. The synthetic resin film may include a thermosetting resin. Specifically, the synthetic resin film may include at least one of acrylate resins, methacrylate resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. Furthermore, the substrate layer BS may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate, etc.

[0046] Insulating, semiconductor, and conductive layers are formed in the circuit element layer DP-CL using processes such as coating and deposition. Subsequently, the insulating, semiconductor, and conductive layers can be selectively patterned using photolithography and etching processes. These processes form semiconductor patterns, conductive patterns, and signal lines. Patterns arranged on the same layer are formed using the same process.

[0047] The circuit element layer DP-CL includes connections to pixels PX11 to PXnm (see...) Figure 3A The driving lines or signal lines of the display element layer (DP-OLED) can include scan lines, data lines, and power lines for controlling the operation of each pixel. The display element layer of a DP-OLED can include the light-emitting element OLED (see [link to OLED display layer]). Figure 6 ) and the pixel-defining film PDL used to define and separate the emission regions of each OLED light-emitting element (see Figure 6 ).

[0048] The encapsulation layer TFE can be placed on the display element layer DP-OLED to protect the light-emitting element OLED (see...). Figure 6The encapsulation layer TFE can include an inorganic layer and an organic layer disposed between the inorganic layers. The inorganic layer can protect the light-emitting element OLED (see [link to encapsulation layer]). Figure 6 The organic layer protects the light-emitting element OLED from moisture and oxygen, and also protects it from the effects of moisture and oxygen. Figure 6 It is protected from foreign objects such as dust particles.

[0049] The light control layer OSL may include the ability to convert from pixel PX11 to PXnm (see Figure 3A The light control pattern is a light-controlled pattern that determines the optical properties of the source light generated. The light control pattern may include quantum dots that convert the wavelength of the emitted light, and may include color filters that selectively transmit light of a specific wavelength.

[0050] A window panel (WD) can be mounted on a display panel (DP) and can transmit the image provided by the display panel (DP) to the outside. The window panel (WD) can act as a protective outermost layer for viewing images through it. The window panel (WD) can be divided into sections such as... Figure 2A The diagram illustrates the display surface DP-IS, which includes the display area DA and the non-display area NDA. The boundary between the display area DA and the non-display area NDA can be defined by a border pattern that is positioned below the window panel WD and absorbs light.

[0051] A window panel (WD) may include a base layer and functional layers disposed on the base layer. The functional layers may include protective layers and anti-fingerprint layers, etc. The base layer of the window panel (WD) may be formed of glass, sapphire, or plastic.

[0052] Figure 3A This is a plan view of an electronic device according to one or more embodiments of the present disclosure. Figure 3B This is a repair pixel and an equivalent circuit diagram of the pixel according to one or more embodiments of the present disclosure.

[0053] refer to Figure 3A The electronic device ED may include a display panel DP, a first gate driver GDC1 and a second gate driver GDC2, a data driver DDC, and a control circuit TC.

[0054] The control circuit TC controls the driving of the first gate driver GDC1, the second gate driver GDC2, and the data driver DDC. The control circuit TC generates image data RGB by converting the data format of the input image signal to match the interface specification of the data driver DDC. The control circuit TC outputs the image data RGB along with various control signals DCS, GCS1, and GCS2.

[0055] The first gate driver GDC1 receives a first gate control signal GCS1 from the control circuit TC, and the second gate driver GDC2 receives a second gate control signal GCS2 from the control circuit TC. The first gate control signal GCS1 may include a start signal for initiating the operation of the first gate driver GDC1 and a clock signal for determining when to output a signal, etc., and the second gate control signal GCS2 may include a start signal for initiating the operation of the second gate driver GDC2 and a clock signal for determining when to output a signal, etc.

[0056] The first gate driver GDC1 and the second gate driver GDC2 output multiple scan signals to multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn, which will be described later. Among the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn, the first set of scan lines GWL1 to GWLn can be referred to as write scan lines. Among the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn, the second set of scan lines GRL1 to GRLn can be referred to as reference scan lines. Among the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn, the third set of scan lines GIL1 to GILn can be referred to as initialization scan lines.

[0057] In addition, at least one of the first gate driver GDC1 and the second gate driver GDC2 generates a plurality of transmit control signals and outputs them to a plurality of transmit signal lines EL1 to ELn.

[0058] The data driver DDC receives the data control signal DCS and the image data RGB from the control circuit TC. The data driver DDC converts the image data RGB into a data signal and outputs the data signal to multiple data lines DL1 to DLm, which will be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data RGB. The data driver DDC can be a component included in a driver chip.

[0059] The display panel DP includes multiple scan lines GWL1 to GWLn, GRL1 to GRLn and GIL1 to GILn, multiple transmit signal lines EL1 to ELn, multiple data lines DL1 to DLm and multiple pixels PX.

[0060] Multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn extend along a first direction DR1 and are arranged along a second direction DR2 perpendicular to the first direction DR1. Each of the multiple transmit signal lines EL1 to ELn can be arranged parallel to a corresponding scan line among the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn. Multiple data lines DL1 to DLm intersect with the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn to insulate them.

[0061] Each of the multiple pixels PX is connected to a corresponding one of the multiple scan lines GWL1 to GWLn, GRL1 to GRLn and GIL1 to GILn, a corresponding one of the multiple transmit signal lines EL1 to ELn, and a corresponding one of the multiple data lines DL1 to DLm.

[0062] The display panel DP receives a first power voltage ELVDD and a second power voltage ELVSS. The first power voltage ELVDD can be supplied to multiple pixels PX via a first power line PL1. The second power voltage ELVSS can be supplied to multiple pixels PX via a second power line PL2 disposed on the display panel DP.

[0063] The display panel DP can further receive the initialization voltage Vint, the first reference voltage Vref1, and the second reference voltage Vref2. The initialization voltage Vint, the first reference voltage Vref1, and the second reference voltage Vref2 can be received via the initialization line VL and the first voltage line VL1 and the second voltage line VL2, respectively (see...). Figure 3B () is provided to multiple pixels PX.

[0064] Figure 3B The diagram shows connections to write scan lines GWL1 to GWLn (see...) Figure 3A The i-th write scan line GWLi and data lines DL1 to DLm provided in the i-th write scan signal GWi are shown in (see Figure 3A The pixel PXij provides the data signal DS on the j-th data line DLj. Pixel PXij is connected to reference scan lines GRL1 to GRLn (see...). Figure 3A The i-th reference scan line GRLi provides the i-th reference scan signal GRi and is connected to the initialization scan lines GIL1 to GILn (see...). Figure 3A The i-th initialization signal Gli is provided in the i-th initialization scan line GILi.

[0065] Pixel PXij may include a pixel circuit (or pixel driving circuit) PXC and a light-emitting element OLED electrically connected to the pixel circuit PXC. In one or more embodiments, the pixel circuit PXC may include six transistors (hereinafter, first transistor T1 to sixth transistor T6) and three capacitors (hereinafter, first capacitor C1, second capacitor C2, and third capacitor C3). In one or more embodiments, the first transistor T1 to sixth transistor T6 may be transistors of a first type (e.g., N-type). In one or more embodiments of this disclosure, at least one of the first transistors T1 to sixth transistor T6 may be omitted from pixel PXij, or additional transistors may be further included in pixel PXij.

[0066] According to one or more embodiments, each of the first transistor T1 and the second transistor T2 may include two gates (e.g., an upper gate and a lower gate). Furthermore, at least one of the first transistor T1 and the second transistor T2 may include only one gate.

[0067] In one or more embodiments, the first transistor T1 may be referred to as a driving transistor, and the second transistor T2 may be referred to as a switching transistor. The node to which the first transistor T1 and the light-emitting element OLED are connected may be referred to as a first node ND1, and the node to which the first transistor T1 and the second transistor T2 are connected may be referred to as a second node ND2.

[0068] The light-emitting element OLED includes a first electrode electrically connected to a first node ND1, a second electrode connected to a second power line PL2 receiving a second power voltage ELVSS, and an emitting layer disposed between the first electrode and the second electrode. A detailed description of the light-emitting element OLED will follow later.

[0069] A first transistor T1 is electrically connected between a first power line PL1 receiving a first power voltage ELVDD and a first node ND1. The first transistor T1 may include a source S1, a drain D1, a semiconductor region connected to the first node ND1, and a gate G1 electrically connected to a second node ND2. According to one or more embodiments, the first transistor T1 may further include a lower gate electrically connected to the gate G1. In this specification, the "source / drain / semiconductor region" included in the transistor may be a region obtained by dividing a "semiconductor pattern" along the region.

[0070] The second transistor T2 is electrically connected between the j-th data line DLj and the second node ND2. The second transistor T2 may include a source S2 connected to the second node ND2, a drain D2 connected to the j-th data line DLj, a semiconductor region, and a gate G2 connected to the i-th write scan line GWLi. According to one or more embodiments, the second transistor T2 may further include a lower gate electrically connected to the gate G2.

[0071] The third transistor T3 is electrically connected between the second node ND2 and the first voltage line VL1 receiving the first reference voltage Vref1. The third transistor T3 may include a drain D3 connected to the second node ND2, a source S3 connected to the first voltage line VL1, a semiconductor region, and a gate G3 connected to the i-th reference scan line GRLi. According to one or more embodiments, the third transistor T3 may further include a lower gate electrically connected to the gate G3.

[0072] The fourth transistor T4 is electrically connected to the initialization line VL, which receives the initialization voltage Vint, and the light-emitting element OLED. The fourth transistor T4 may include a drain D4 connected to the first electrode of the light-emitting element OLED, a source S4 connected to the initialization line VL, a semiconductor region, and a gate G4 connected to the i-th initialization scan line GILi. According to one or more embodiments, the fourth transistor T4 may further include a lower gate electrically connected to the gate G4.

[0073] The fifth transistor T5 is electrically connected between the first power line PL1 and the drain D1 of the first transistor T1. In one or more embodiments, the fifth transistor T5 may include a drain D5 connected to the first power line PL1, a source S5 connected to the drain D1 of the first transistor T1, a semiconductor region, and a gate G5 connected to the i-th first transmit signal line ELi that provides the i-th first transmit signal EMi. The fifth transistor T5 may further include a lower gate electrically connected to the gate G5.

[0074] The sixth transistor T6 is electrically connected between the first node ND1 and the light-emitting element OLED. In one or more embodiments, the sixth transistor T6 may include a drain D6 connected to the first node ND1, a source S6 connected to the first electrode of the light-emitting element OLED, a semiconductor region, and a gate G6 connected to the i-th second emission signal line ELBi that provides the i-th second emission signal EMBi. The sixth transistor T6 may further include a lower gate electrically connected to the gate G6.

[0075] The first capacitor C1 is electrically connected between the first node ND1 and the second node ND2. The first capacitor C1 includes a first-1 capacitor pattern E1-1 connected to the first node ND1 and a first-2 capacitor pattern E1-2 connected to the second node ND2.

[0076] The second capacitor C2 is electrically connected between the second voltage line VL2 and the first node ND1. The second capacitor C2 includes a 2-1 capacitor pattern E2-1 connected to the first node ND1 and a 2-2 capacitor pattern E2-2 connected to the second voltage line VL2.

[0077] The third capacitor C3 is electrically connected between the first electrode and the second electrode of the OLED. The third capacitor C3 includes a first capacitor pattern E3-1 connected to the first electrode of the OLED and a second capacitor pattern E3-2 connected to the second electrode of the OLED.

[0078] According to one or more embodiments, any one of the first to third capacitors C1, C2 and C3 may be omitted.

[0079] The display panel DP according to this disclosure may include pixels PXij disposed in the display area DA (or effective area) and repair pixels PXij_a disposed in the non-display area NDA (or peripheral area). The repair pixel PXij_a may include a repair pixel circuit (or pixel driver) PXC_a and a light-emitting element OLED electrically connected to the repair pixel circuit PXC_a. The repair pixel circuit PXC_a included in the repair pixel PXij_a and the pixel circuit PXC included in the pixel PXij may have the same structure. For example, the repair pixel circuit PXC_a may also include the first transistor T1 to the sixth transistor T6 described above and the first capacitor to the third capacitor C1, C2, and C3. Although the transistors included in the pixel circuit may have the same structure as the transistors in the repair pixel circuit, for clarity, they may be referred to differently, such that the transistors in the pixel circuit are called pixel transistors, and the transistors in the repair pixel circuit are called repair transistors. According to one or more embodiments, the repair pixel PXij_a may not include the light-emitting element OLED and may only include the repair pixel circuit PXC_a disposed in the non-display area NDA, and this disclosure is not limited to any one embodiment.

[0080] The repair pixel PXij_a can be configured to drive the OLED of the defective pixel PXij by connecting it to the repair pixel circuit PXC_a. This connection is made when a defect is detected in any of the pixel circuits PXC during testing of the pixel PXij set in the display area DA. Defects such as dark spots may occur in the defective pixel PXij.

[0081] The repair pixel PXij_a can be set in the non-display area NDA and can be connected to the defective pixel PXij in the display area DA via the repair line RP.

[0082] When a defect occurs in any of the pixel circuits (PXCs), the connection between the OLED and the defective PXC may be physically or electrically broken. More specifically, the break may occur between the first electrode of the OLED and the drain D4 of the fourth transistor T4, or between the first electrode of the OLED and the source S6 of the sixth transistor T6. Accordingly, the defective PXC may not be driven.

[0083] Subsequently, the first electrode of the disconnected OLED light-emitting element can be reconnected to the drain D4 of the fourth transistor T4 or the source S6 of the sixth transistor T6 of the repair pixel PXij_a via the repair line RP. Accordingly, the disconnected OLED light-emitting element can be normally driven by the repair pixel circuit PXC_a, which has the same structure as the previous pixel circuit PXC.

[0084] According to this disclosure, it is possible to repair defective pixels (e.g., pixels with dark spots) detected during the testing process by including a repair pixel circuit PXC_a disposed in the non-display area NDA. Accordingly, it is possible to provide electronic devices with improved reliability and process yield.

[0085] Figure 4 This is an enlarged plan view of the display area according to one or more embodiments of the present disclosure. The first to third pixels PX-R, PX-G, and PX-B, described below, can be compared with... Figures 3A to 3B The pixels PX and PXij described in the text correspond to each other.

[0086] refer to Figure 4The display area DA (or effective area) may include emitting areas PXA-R, PXA-G, and PXA-B, and a non-emitting area NPXA. Source light formed in the first pixel PX-R can be provided to the first emitting area PXA-R, source light formed in the second pixel PX-G can be provided to the second emitting area PXA-G, and source light formed in the third pixel PX-B can be provided to the third emitting area PXA-B. Each of the first to third emitting areas PXA-R, PXA-G, and PXA-B can be coupled to a pixel-defined film PDL (see [link to pixel definition]). Figure 6 The non-emitting region NPXA corresponds to the opening PDL-OP in the first to third emitting regions PXA-R, PXA-G, and PXA-B. The non-emitting region NPXA can be located between the first and third emitting regions PXA-R, PXA-G, and PXA-B. The non-emitting region NPXA can be associated with the pixel-defining film PDL (see [link to relevant documentation]). Figure 6 The non-emission zone NPXA can be located around the first to third emission zones PXA-R, PXA-G, and PXA-B.

[0087] exist Figure 4 For ease of description, the first electrode AE ​​(see [reference needed]) is included in the first to third pixels PX-R, PX-G, and PX-B. Figure 6 The shape of the pixel (represented by dashed lines) is called the first to third pixels PX-R, PX-G, and PX-B.

[0088] Each of the first to third pixels PX-R, PX-G, and PX-B includes a pixel circuit PXC (see reference). Figure 3B ) and the light-emitting element OLED connected to the pixel circuit PXC (reference) Figure 3B ), and the light-emitting element OLED (reference) Figure 3B (This can produce source light of the same color. For example, the source light can be blue. This is achieved by using an OLED (see...) light-emitting element...) Figure 3B The generated source light can be included in Figure 2C The light control pattern in the OSL light control layer described in the text is converted into any one of red, green, and blue.

[0089] The converted light can be emitted through the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B. When the light passes through the optical control layer OSL, red light can be provided to the first emission region PXA-R, green light can be provided to the second emission region PXA-G, and blue light can be provided to the third emission region PXA-B. However, this disclosure is not limited to this, and the source light generated by the first to third pixels PX-R, PX-G, and PX-B can have different colors.

[0090] According to one or more embodiments, the first transmission region PXA-R and the third transmission region PXA-B are arranged in the same row, and the second transmission region PXA-G is arranged in a different row from the first transmission region PXA-R and the third transmission region PXA-B. For example, the first transmission region PXA-R and the third transmission region PXA-B may be spaced apart from each other in the first direction DR1, and the second transmission region PXA-G may be spaced apart from the first transmission region PXA-R and the third transmission region PXA-B in the diagonal direction of the first direction DR1 and the second direction DR2.

[0091] According to one or more embodiments, the area of ​​the first transmission region PXA-R can be smaller than the area of ​​the second transmission region PXA-G, and can be larger than the area of ​​the third transmission region PXA-B.

[0092] In one or more embodiments, as an example, a first transmission area PXA-R, a second transmission area PXA-G, and a third transmission area PXA-B with a square shape are illustrated, but the arrangement and size of the transmission areas are not limited thereto.

[0093] Figure 4 The arrangement of the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B in the unit pixel PXU illustrated in the figure is merely an example, and this disclosure is not limited thereto. For example, the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B can be arranged along the first direction DR1 and can be set in the same row. Furthermore, the arrangement of the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B in each of the unit pixels PXU does not necessarily have to be the same.

[0094] Figure 5 It is a plan view of the stacking order of conductive patterns included in a unit pixel according to one or more embodiments of the present disclosure. Figure 6 It is along Figure 5 The cross-sectional view taken from line I-I'. Figures 7A to 7F This is a plan view illustrating the stacking order of layers of conductive patterns included in unit pixels of various patterns according to one or more embodiments of the present disclosure.

[0095] refer to Figure 5 A unit pixel PXU can include the first to third pixels PX-R, PX-G, and PX-B (see...) Figure 4 Each of the first to third pixels, PX-R, PX-G, and PX-B, may include... Figure 3BThe pixel circuit PXC and the light-emitting element OLED are described in the figure. The first to third pixels PX-R, PX-G and PX-B can be connected to the first power line PL1 and the second power line PL2, the scan lines GWL, GRL and GIL, the data lines DL-R, DL-G and DL-B, the initialization line VL, the first voltage line VL1 and the second voltage line VL2, and the first transmit signal line EL and the second transmit signal line ELB.

[0096] exist Figure 5 In the image, only the repair line RP and the data lines DL-R, DL-G, and DL-B are shaded.

[0097] According to this disclosure, a portion of the repair line RP may overlap with data lines DL-R, DL-G, and DL-B. Data lines DL-R, DL-G, and DL-B may overlap with... Figure 3A and Figure 3B This corresponds to any one of the data lines DL1 to DLm described in the text.

[0098] The repair line RP may include a first portion P1-P and second portions P2-R, P2-G, and P2-B. The first portion P1-P may extend along a first direction DR1, and each of the second portions P2-R, P2-G, and P2-B may protrude from the first portion P1-P along a second direction DR2. The first portion P1-P and the second portions P2-R, P2-G, and P2-B are an integral pattern formed by the same process, but for ease of description, they will be described separately.

[0099] refer to Figure 6 According to one or more embodiments, a display panel DP may include a substrate layer BS, a circuit element layer DP-CL disposed on the substrate layer BS, a display element layer DP-OLED, and an encapsulation layer TFE. For example... Figure 2C As described herein, the electronic device ED may include an optical control layer OSL and a window panel WD disposed on a display panel DP.

[0100] A circuit element layer DP-CL is disposed on a substrate layer BS. The circuit element layer DP-CL may include a first insulating layer INS1 to a sixth insulating layer INS6 disposed on the substrate layer BS, and conductive patterns P2-R, E2-R1, E2-R2, AC2, GT, PC, DL-R, PL1-V, and VL1-V disposed between the first insulating layer INS1 to the sixth insulating layer INS6. According to one or more embodiments, each of the first insulating layer INS1 to the fourth insulating layer INS4 may be provided as an inorganic layer. The first insulating layer INS1 to the fourth insulating layer INS4 may be provided as a single inorganic layer, or may be provided as a multilayer comprising different inorganic layers, and this disclosure is not limited to any one embodiment.

[0101] The fifth insulating layer INS5 may include a first inorganic layer INS5-1 and a first organic layer INS5-2. The sixth insulating layer INS6 may include a first inorganic layer INS6-1 and a first organic layer INS6-2. The conductive patterns P2-R, E2-R1, E2-R2, AC2, PC, DL-R, PL1-V, and VL1-V disposed between the first insulating layers INS1 to the sixth insulating layer INS6 will be described later.

[0102] The display element layer of DP-OLED may include a pixel-defining film (PDL) and a light-emitting element (OLED). The pixel-defining film (PDL) defines and... Figure 4 The corresponding opening PDL-OP in each of the launch regions PXA-R, PXA-G, and PXA-B described in the document. Figure 6 The light-emitting element OLED shown in the diagram can be included Figure 4 The first pixel, PX-R, is described in the diagram. The description of the light-emitting element OLED can be applied to pixels PX-R, PX-G, and PX-B.

[0103] According to one or more embodiments, the pixel-defined film (PDL) may have light-absorbing properties. For example, the pixel-defined film (PDL) may be black. The pixel-defined film (PDL) may include a black colorant. The black colorant may include black dyes and black pigments. The black colorant may include carbon black, metals such as chromium, or oxides thereof. According to one or more embodiments, the pixel-defined film (PDL) may correspond to a light-shielding pattern having light-shielding properties.

[0104] An OLED light-emitting element may include a first electrode AE, a second electrode CE, and a common layer CL disposed between the first electrode AE ​​and the second electrode CE.

[0105] The first electrode AE ​​of the OLED light-emitting element can be disposed on the sixth insulating layer INS6. The second electrode CE can be disposed on the first electrode AE. A common layer CL can be disposed between the first electrode AE ​​and the second electrode CE. The common layer CL may include an emission layer containing organic material, a hole control layer disposed between the first electrode AE ​​and the emission layer, and an electron control layer disposed between the emission layer and the second electrode CE. The hole control layer may include a hole transport layer and a hole injection layer. The electron control layer may include an electron transport layer and an electron injection layer. According to one or more embodiments, the common layer CL and the second electrode CE may be a common layer provided as an integral pattern formed together on the first to third pixels PX-R, PX-G, and PX-B.

[0106] The encapsulation layer TFE can cover the display element layer DP-OLED. The encapsulation layer TFE can comprise organic or inorganic materials. The encapsulation layer TFE can have a multilayer structure in which repeated inorganic / organic layers are present. In one or more embodiments, the encapsulation layer TFE can comprise a first inorganic layer, an organic layer, and a second inorganic layer stacked in sequence. The first and second inorganic layers can protect the light-emitting element OLED from external moisture, and the organic layer can prevent stamping defects in the light-emitting element OLED due to foreign matter introduced during the manufacturing process.

[0107] The first and second inorganic layers may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc. Each of the first and second inorganic layers may have a multilayer structure. The organic layer may include an acrylic organic layer, but this disclosure is not limited thereto. The inorganic layer can protect the OLED light-emitting element from moisture and oxygen, and the organic layer can protect the OLED light-emitting element from foreign matter such as dust particles.

[0108] Figure 2C The optical control layer OSL described herein can be disposed on the encapsulation layer TFE. The optical control layer OSL can be disposed between the encapsulation layer TFE and the window panel WD. The rear surface of the window panel WD can provide a substrate surface on which components including the optical control layer OSL are formed.

[0109] The optical control layer (OSL) according to one or more embodiments may include a color filter layer disposed on the rear surface of the window panel (WD). The color filter layer may include a first color filter that transmits a first light, a second color filter that transmits a second light, and a third color filter that transmits source light. In one or more embodiments, the first color filter may be a red filter, the second color filter may be a green filter, and the third color filter may be a blue filter.

[0110] Each of the first to third color filters includes a polymeric photosensitive resin and a colorant. The first color filter may include a red colorant, the second color filter may include a green colorant, and the third color filter may include a blue colorant. The first color filter may include a red pigment or a red dye, the second color filter may include a green pigment or a green dye, and the third color filter may include a blue pigment or a blue dye.

[0111] The first through third color filters can be set to correspond to the above references respectively. Figure 4 The first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B are described as corresponding. That is, each of the first to third color filters can overlap with the opening PDL-OP of the corresponding pixel-defined film PDL.

[0112] According to one or more embodiments, at least two of the first to third color filters may be stacked on the pixel-defining film (PDL). The at least two color filters are configured to overlap each other on a third direction (DR3) that is the thickness direction, to distinguish the boundary between adjacent emission regions.

[0113] According to one or more embodiments, each of the first to third light control patterns comprising quantum dots may be disposed on the first to third color filters. It may further include a capping layer sealing the first to third color filters and a dam defining the boundaries of the first to third light control patterns. The dam may overlap with a pixel-defining film (PDL).

[0114] According to one or more embodiments, a low-refractive-index layer may be disposed between the first and third color filters. The low-refractive-index layer may include at least one inorganic layer. For example, the low-refractive-index layer may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride, or a transparent metal film. However, the embodiments are not limited thereto, and the low-refractive-index layer may include an organic film. For example, the low-refractive-index layer may have a structure in which multiple hollow particles are dispersed in an organic polymer resin. The low-refractive-index layer may include a single layer or multiple layers.

[0115] The layer structure of any one of the first to third pixels PX-R, PX-G, and PX-B described below can also be applied to the repaired pixel PXij_a described above, and its repeated description will be omitted.

[0116] refer to Figure 5 , Figure 6 and Figure 7A The first conductive layer CML1 can be disposed on the substrate layer BS and can be covered by the first insulating layer INS1.

[0117] The first conductive layer CML1 includes a repair line RP, and is included in the first capacitor C1 (see...). Figure 3B The first-1 capacitor pattern E1-1 in the first-1 capacitor pattern E1-1 corresponds to the first-1 patterns E1-R1, E1-G1 and E1-B1, and is included in the second capacitor C2 (see Figure 3B The second-1 capacitor pattern E2-1 corresponds to the second-1 patterns E2-R1, E2-G1 and E2-B1, and the second-1 voltage line VL2-H is included in the second voltage line VL2.

[0118] Patterns E2-R1, E2-G1, and E2-B1 in section 2-1, as well as voltage line VL2-H in section 2-1, are integral patterns formed using the same process, but for ease of description, they will be described separately.

[0119] The repair line RP may include a first portion P1-P and second portions P2-R, P2-G, and P2-B. The first portion P1-P may extend along a first direction DR1, and each of the second portions P2-R, P2-G, and P2-B may protrude from the first portion P1-P along a second direction DR2. The first portion P1-P and the second portions P2-R, P2-G, and P2-B are an integral pattern formed by the same process, but for ease of description, they will be described separately.

[0120] Patterns E1-R1, E1-G1, and E1-B1 of the first-1 pattern can be spaced apart from each other in the first direction DR1. Patterns E2-R1, E2-G1, and E2-B1 of the second-1 pattern can be set between patterns E1-R1, E1-G1, and E1-B1 of the first-1 pattern and the first part P1-P.

[0121] Voltage line VL2-H 2-1 can connect two adjacent patterns E2-1, E2-R1, E2-G1, and E2-B1, and can surround the ends of the second portions P2-R, P2-G, and P2-B. Voltage line VL2-H 2-1 can be connected to patterns E2-R1, E2-G1, and E2-B1 and can define a pattern.

[0122] Among patterns E2-R1, E2-G1, and E2-B1, pattern E2-G1, which is located at its center, may include a protruding pattern EP protruding along the second direction DR2. The protruding pattern EP may be connected to a connecting protruding pattern PP included in the fourth conductive layer CML4.

[0123] refer to Figure 5 , Figure 6 and Figure 7B The second conductive layer CML2 can be disposed on the first insulating layer INS1 and can be covered by the second insulating layer INS2.

[0124] The second conductive layer CML2 includes a write scan line GWL, a first voltage line VL1-H included in the first voltage line VL1, and a first capacitor C1 (see...). Figure 3B The first and second capacitor patterns E1-R2, E1-G2, and E1-B2 corresponding to the first and second capacitor patterns E1-2 in the first and second capacitors, and included in the second capacitor C2 (see Figure 3B The second-2 capacitor pattern E2-2 corresponds to the second-2 patterns E2-R2, E2-G2 and E2-B2, the first-1 power line PL1-H included in the first power line PL1, the first-1 initialization line VL-H included in the initialization line VL, and the second-1 power line PL2-H included in the second power line PL2.

[0125] The write scan line GWL, the first-1 voltage line VL1-H, the first-1 power line PL1-H, the first-1 initialization line VL-H, and the second-1 power line PL2-H can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2.

[0126] In patterns E1-R2, E1-G2, and E1-B2 of the first and second series, and patterns E2-R2, E2-G2, and E2-B2 of the second series, patterns E1-R2 and E2-R2 of the first and second series can be integral patterns formed by the same process; patterns E1-G2 and E2-G2 of the first and second series can be integral patterns formed by the same process; and patterns E1-B2 and E2-B2 of the first and second series can be integral patterns formed by the same process. Patterns E1-R2 and E2-R2 of the first and second series can be connected to each other and define a single pattern; patterns E1-G2 and E2-G2 of the first and second series can be connected to each other and define a single pattern; and patterns E1-B2 and E2-B2 of the first and second series can be connected to each other and define a single pattern. Patterns 1-2 E1-R2 and 2-2 E2-R2, patterns 1-2 E1-G2 and 2-2 E2-G2, and patterns 1-2 E1-B2 and 2-2 E2-B2 can be between voltage line VL1-H and power line PL1-H and can be spaced apart from each other along the first direction DR1.

[0127] Patterns 1-2 E1-R2 and 1-1 E1-R1 can overlap each other to define the area included in the first pixel PX-R (see...). Figure 4 The first capacitor C1 in ) (see Figure 3B Patterns 1-2 E1-G2 and 1-1 E1-G1 can overlap each other to define the area included in the second pixel PX-G (see...). Figure 4 The first capacitor C1 in ) (see Figure 3B ), and patterns 1-2 E1-B2 and 1-1 E1-B1 can overlap each other to define the area included in the third pixel PX-B (see Figure 4 The first capacitor C1 in ) (see Figure 3B ).

[0128] Pattern 2-2 E2-R2 and pattern 2-1 E2-R1 may overlap each other to define the area included in the first pixel PX-R (see Figure 4 The second capacitor C2 in ) (see Figure 3B Patterns 2-2 E2-G2 and 2-1 E2-G1 can overlap each other to define the area included in the second pixel PX-G (see...). Figure 4The second capacitor C2 in ) (see Figure 3B ), and patterns 2-2 E2-B2 and 2-1 E2-B1 can overlap each other to define the area included in the third pixel PX-B (see Figure 4 The second capacitor C2 in ) (see Figure 3B ).

[0129] refer to Figure 5 , Figure 6 and Figure 7C The third conductive layer CML3 can be disposed on the second insulating layer INS2 and can be covered by the third insulating layer INS3.

[0130] The third conductive layer CML3 may include components contained in Figure 3B The semiconductor patterns AC1, AC2, and AC3 in the first transistor T1 to the sixth transistor T6 described herein. Each of the first pixel to the third pixel PX-R, PX-G, and PX-B may include three semiconductor patterns AC1, AC2, and AC3. The semiconductor patterns AC1, AC2, and AC3 may be divided into “source / drain / semiconductor regions” included in the first transistor T1 to the sixth transistor T6 for each region.

[0131] refer to Figure 5 , Figure 6 and Figure 7D The fourth conductive layer CML4 can be disposed on the third insulating layer INS3 and can be covered by the fourth insulating layer INS4. Figure 7D The diagram illustrates a contact hole CNT that is defined simultaneously through at least one of the first insulating layer INS1 to the third insulating layer INS3.

[0132] The fourth conductive layer CML4 may include a reference scan line GRL, a first transmit signal line EL, a second transmit signal line ELB, an initialization scan line GIL, a connecting protrusion pattern PP, and gate patterns GT-R1, GT-R2, GT-G1, GT-G2, GT-B1, and GT-B2.

[0133] Each of the reference scan line GRL, the first transmit signal line EL, the second transmit signal line ELB, and the initialization scan line GIL can extend along the first direction DR1 and can be arranged along the second direction DR2.

[0134] The gate patterns GT-R1, GT-R2, GT-G1, GT-G2, GT-B1, and GT-B2 can be disposed between the reference scan line GRL and the first transmit signal line EL. The first pixel PX-R can include two gate patterns GT-R1 and GT-R2, the second pixel PX-G can include two gate patterns GT-G1 and GT-G2, and the third pixel PX-B can include two gate patterns GT-B1 and GT-B2. Figure 6 The grid pattern GT shown in the figure can be any one of the grid patterns GT-R1, GT-R2, GT-G1, GT-G2, GT-B1, and GT-B2.

[0135] The portion of the pattern included in the fourth conductive layer CML4 that overlaps with the semiconductor patterns AC1, AC2 and AC3 included in the third conductive layer CML3 can be defined as the gate included in the first transistor T1 to the sixth transistor T6.

[0136] The portion of the first semiconductor pattern AC1 that overlaps with the reference scan line GRL can be defined as the gate G3 of the third transistor T3. The portion of the first semiconductor pattern AC1 that overlaps with the first gate patterns GT-R1, GT-G1, and GT-B1 can be defined as the gate G2 of the second transistor T2.

[0137] The portion of the second semiconductor pattern AC2 that overlaps with the second gate patterns GT-R2, GT-G2, and GT-B2 can be defined as the gate G1 of the first transistor T1. The portion of the second semiconductor pattern AC2 that overlaps with the first transmit signal line EL can be defined as the gate G5 of the fifth transistor T5.

[0138] The portion of the third semiconductor pattern AC3 that overlaps with the second transmit signal line ELB can be defined as the gate G6 of the sixth transistor T6. The portion of the third semiconductor pattern AC3 that overlaps with the initialization scan line GIL can be defined as the gate G4 of the fourth transistor T4.

[0139] One end of the connecting protruding pattern PP can be connected to the protruding pattern EP of the first conductive layer CML1 through the contact hole CNT, and the opposite end of the connecting protruding pattern PP can be connected to the seventh connecting pattern P7 included in the fifth conductive layer CML5 through the contact hole CNT.

[0140] refer to Figure 5 , Figure 6 and Figure 7E The fifth conductive layer CML5 can be disposed on the fourth insulating layer INS4 and can be covered by the fifth insulating layer INS5.

[0141] The fifth conductive layer CML5 may include the first data lines to the third data lines DL-R, DL-G and DL-B, as well as the connecting patterns PC and P1 to P8 that connect the patterns disposed in different conductive layers.

[0142] The first to third data lines DL-R, DL-G, and DL-B can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Each of the first to third pixels PX-R, PX-G, and PX-B can include connection patterns PC and P1 to P8 disposed between two data lines disposed adjacent to each other along the first direction DR1.

[0143] Each of the first to third data lines DL-R, DL-G, and DL-B can be connected to the first semiconductor pattern AC1 via contact hole CNT. Accordingly, each of the first to third data lines DL-R, DL-G, and DL-B can be connected to the second transistor T2.

[0144] The first connection pattern P1 can connect the write scan line GWL and a portion of the first semiconductor pattern AC1 through the contact hole CNT.

[0145] The second connection pattern P2 can connect the first voltage line VL1-H and another part of the first semiconductor pattern AC1 through the contact hole CNT.

[0146] The third connection pattern P3 can connect the second gate patterns GT-R2, GT-G2, and GT-B2, as well as another part of the first semiconductor pattern AC1, through the contact hole CNT.

[0147] The fourth connection pattern P4 can connect the first-1 power line PL1-H and another part of the second semiconductor pattern AC2 through the contact hole CNT.

[0148] The fifth connection pattern P5 can connect another part of the second semiconductor pattern AC2 and the second bridging pattern B2 included in the sixth conductive layer CML6 through the contact hole CNT.

[0149] The sixth connection pattern P6 can connect the first initialization line VL-H and a portion of the third semiconductor pattern AC3 through the contact hole CNT.

[0150] The seventh connection pattern P7 can connect the connection protrusion pattern PP and the voltage line VL2-V included in the sixth conductive layer CML6 through the contact hole CNT.

[0151] The eighth connection pattern P8 can connect the second-1 electric line PL2-H and the second-2 electric line PL2-V of the sixth conductive layer CML6 through the contact hole CNT.

[0152] The connecting pattern PC can be connected to the first bridging pattern B1 included in the sixth conductive layer CML6 via the contact hole CNT.

[0153] According to this disclosure, the second voltage line VL2 may include a second-first voltage line VL2-H and a second-second voltage line VL2-V. The second-first voltage line VL2-H and the second-second voltage line VL2-V can be connected to each other via a protruding pattern EP, a connecting protruding pattern PP, and a seventh connecting pattern P7. Because the second voltage line VL2 has a double-wire structure disposed on different layers, the resistance of the second voltage line VL2 can be reduced.

[0154] refer to Figure 5 , Figure 6 and Figure 7F The sixth conductive layer CML6 can be disposed on the fifth insulating layer INS5 and can be covered by the sixth insulating layer INS6.

[0155] The sixth conductive layer CML6 may include the first-second electric power line PL1-V included in the first electric power line PL1, the first-second initialization line VL-V included in the initialization line VL, the first bridging pattern B1 and the second bridging pattern B2, the first-second voltage line VL1-V included in the first voltage line VL1, the second-second voltage line VL2-V included in the second voltage line VL2, and the second-second electric power line PL2-V included in the second electric power line PL2.

[0156] The first-second electric power line PL1-V, the first-second initialization line VL-V, the first-second voltage line VL1-V, the second-second voltage line VL2-V, and the second-second electric power line PL2-V can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The first bridging pattern B1 and the second bridging pattern B2 can be included in each of the first to third pixels PX-R, PX-G, and PX-B, and can be spaced apart from each other along the second direction DR2 between the first-second initialization line VL-V and the first-second voltage line VL1-V.

[0157] The first-second power line PL1-V can be connected to the first-first power line PL1-H via the fourth connection pattern P4. Accordingly, because the first power line PL1 has a double-wire structure disposed on a different layer, the resistance of the first power line PL1 can be reduced.

[0158] Initialization line VL-V (1-2) can be connected to initialization line VL-H (1-1) via the fourth connection pattern P4. Accordingly, because initialization line VL has a double-wire structure disposed on different layers, the resistance of initialization line VL can be reduced.

[0159] Voltage line VL1-V (first-second voltage line) can be connected to voltage line VL1-H (first-first voltage line) via the second connection pattern P2. Because voltage line VL1 has a double-wire structure on a different layer, its resistance can be reduced. Voltage line VL2-V (second-second voltage line) can be connected to voltage line VL2-H (second-first voltage line) via the seventh connection pattern P7. Because voltage line VL2 has a double-wire structure on a different layer, its resistance can be reduced.

[0160] The second-2 power line PL2-V can be connected to the second-1 power line PL2-H via the eighth connection pattern P8. Accordingly, the second power line PL2, having a double-wire structure disposed on a different layer, can exhibit reduced resistance.

[0161] The first bridging pattern B1 can be connected to the connecting pattern PC via contact hole CNT, and the second bridging pattern B2 can be connected to the fifth connecting pattern P5 via contact hole CNT. The second bridging pattern B2 can be connected to the light-emitting element OLED (see...). Figure 3B The first electrode AE ​​in ) (see Figure 6 ).

[0162] According to this disclosure, the second portions P2-R, P2-G, and P2-B of the repair line RP included in the first conductive layer CML1 can overlap with the data lines DL-R, DL-G, and DL-B. This is because the repair line RP is independent of the data lines included in the pixel circuit PXC (see reference ). Figure 3B The lines in the data lines RP and DL-R, DL-G, and DL-B are repaired so that the coupling between the repair line RP and the data lines DL-R, DL-G, and DL-B can be maintained without affecting pixel PXij (see reference). Figure 3B The operation of the device is described. According to this disclosure, signal distortion caused by coupling to the power lines can be prevented or mitigated by shielding the data lines DL-R, DL-G, and DL-B with a repair line RP. Accordingly, it is possible to provide electronic devices with improved reliability.

[0163] In one or more embodiments of this disclosure, the electronic device may include: a substrate layer including an effective region and a peripheral region; pixels, each in the effective region including pixel circuitry; repair pixel circuitry in the peripheral region; data lines connected to the pixels; and repair lines connected to the repair pixel circuitry and extending into the effective region. A portion of the repair lines may overlap with the data lines.

[0164] The data cable can be arranged along a first direction, and the repair line can include: a first portion extending along the first direction; and a second portion protruding from the first portion along a second direction intersecting the first direction. Each of the second portions can overlap with the data cable.

[0165] The repair pixel circuit may include a repair transistor, and the pixel transistor may have the same structure as the repair transistor.

[0166] In any of the pixels, the connection between the light-emitting element and the pixel transistor may be broken.

[0167] The connection between the light-emitting element and the pixel transistor can be rewired via repair lines.

[0168] The electronic device may include: a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer on a substrate layer; and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer between the first conductive layer and the sixth conductive layer, and a first electric field line, a second electric field line, an initialization line, a first voltage line, a second voltage line, a write scan line, a reference scan line, an initialization scan line, a first transmit signal line, and a second transmit signal line may be connected to a pixel transistor and a repair transistor.

[0169] The first conductive layer may be directly on the substrate and may be covered by the first insulating layer. The first conductive layer may include a repair line, a first-1 capacitor pattern between the second portions, a second-1 capacitor pattern between the first-1 capacitor pattern and the first portion, and a second-1 voltage line connected to the second-1 capacitor pattern and defining a pattern.

[0170] The second conductive layer may be on the first insulating layer and may be covered by the second insulating layer. The second conductive layer may include: a second-1 electric field line that may be arranged along a second direction and each extending along a first direction; a write scan line; a first-1 voltage line of a first voltage line; a first initialization line of the first electric field line and an initialization line; and capacitor electrodes, between the first-1 voltage line and the first-1 electric field line, and spaced apart from each other along the first direction.

[0171] Each of the capacitor electrodes may include a first-second capacitor pattern and a second-second capacitor pattern connected to each other and defining a pattern, wherein the first-second capacitor pattern overlaps with the first-second capacitor pattern to form a first capacitor, and wherein the second-second capacitor pattern overlaps with the second-second capacitor pattern to form a second capacitor.

[0172] The third conductive layer may be on and covered by the second insulating layer, and the third conductive layer may include a semiconductor pattern contained in each of the pixel transistor and the repair transistor.

[0173] The fourth conductive layer may be on the third insulating layer and may be covered by the fourth insulating layer. The fourth conductive layer may include: a reference scan line, a first transmit signal line, a second transmit signal line, and an initialization scan line that may be arranged along a second direction and each extend along a first direction; and gates, a portion of each of the gates overlapping the semiconductor layer and included in each of the pixel transistor and the repair transistor.

[0174] The fifth conductive layer can be disposed on the fourth insulating layer and can be covered by the fifth insulating layer, and the fifth conductive layer can include data lines and connection patterns that connect different conductive layers.

[0175] The sixth conductive layer may be on the fifth insulating layer and may be covered by the sixth insulating layer. The sixth conductive layer may include first-second electric field lines of first electric field lines that may be arranged along a first direction and each extending along a second direction, second initialization lines of initialization lines, first-second voltage lines of first voltage lines, second-second voltage lines of second voltage lines, and second-second electric field lines of second electric field lines.

[0176] The first-2 electric power line, the second-2 electric power line, the first-2 voltage line, the second-2 voltage line, and the second initialization line can be connected to the first-1 electric power line, the second-1 electric power line, the first-1 voltage line, the second-1 voltage line, and the first initialization line respectively through contact holes passing through the first insulation layer to the fifth insulation layer, so as to form the first electric power line, the second electric power line, the first voltage line, the second voltage line, and the initialization line.

[0177] The pixel circuit may include a light-emitting element. The light-emitting element may include a first electrode, a second electrode, and a common layer between the first electrode and the second electrode, and the common layer may include an emitting layer.

[0178] The effective area may include emitting areas and non-emitting areas. In the emitting area, three emitting areas that can be directly adjacent to each other can be defined as a unit pixel. The effective area may include multiple unit pixels, including a unit pixel, and the multiple unit pixels can be arranged along a first direction and a second direction that intersect each other.

[0179] The three emission zones correspond to the first emission zone, the second emission zone, and the third emission zone. The first emission zone can be configured to emit red light, the second emission zone can be configured to emit green light, and the third emission zone can be configured to emit blue light. The size of the first emission zone can be smaller than the size of the second emission zone and larger than the size of the third emission zone.

[0180] The first launch area and the third launch area may be spaced apart from each other along a first direction, and the second launch area may be spaced apart from each of the first launch area and the third launch area along a diagonal direction of the first direction and the second direction.

[0181] The pixel circuit may include a light-emitting element, and the electronic device may further include an encapsulation layer covering the light-emitting element.

[0182] The electronic device may further include: a light control pattern on an encapsulation layer, configured to convert the optical properties of source light generated in a light-emitting element, and including quantum dots; and a color filter on the light control pattern.

[0183] According to one or more embodiments of this disclosure, since the data line is partially shielded by the repair line, signal distortion due to coupling to the power line can be prevented. Accordingly, it is possible to provide electronic devices with improved reliability.

[0184] Although one or more embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications and substitutions may be made without departing from the scope and spirit of this disclosure as disclosed in the appended claims.

[0185] Accordingly, the scope of this disclosure should not be limited to the content described in the detailed description of the specification, but should be defined by the claims.

Claims

1. An electronic device comprising: The basal layer includes the effective area and the peripheral area; Each of the pixels in the effective area includes pixel circuitry; Repair the pixel circuitry in the peripheral region; A data cable is connected to the pixel; as well as The repair line connects to the repair pixel circuit and extends into the effective area. A portion of the repair line overlaps with the data line.

2. The electronic device according to claim 1, wherein, The data line is arranged along a first direction, and wherein the repair line includes: The first part extends along the first direction; and The second part protrudes from the first part along a second direction intersecting the first direction, and Each of the second parts overlaps with the data line.

3. The electronic device according to claim 1, wherein, The repair pixel circuit includes a repair transistor, and the pixel circuit includes a pixel transistor, and the pixel transistor has the same structure as the repair transistor.

4. The electronic device according to claim 1, wherein, In any of the pixels, the connection between the light-emitting element and the pixel transistor is broken.

5. The electronic device according to claim 4, wherein, The connection between the light-emitting element and the pixel transistor is rewired via the repair line.

6. The electronic device according to claim 2, wherein, The repair pixel circuit includes a repair transistor, and the pixel circuit includes a pixel transistor. The electronic device includes: A first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer are disposed on the substrate layer, and A first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer are located between the first conductive layer and the sixth conductive layer; and The first power line, the second power line, the initialization line, the first voltage line, the second voltage line, the write scan line, the reference scan line, the initialization scan line, the first transmit signal line, and the second transmit signal line are connected to the pixel transistor and the repair transistor.

7. The electronic device according to claim 6, wherein, The first conductive layer is directly on the substrate layer and is covered by the first insulating layer, and The first conductive layer includes the repair line, a first-1 capacitor pattern between the second portion, a second-1 capacitor pattern between the first-1 capacitor pattern and the first portion, and a second voltage line connected to the second voltage line and defining a pattern.

8. The electronic device according to claim 7, wherein, The second conductive layer is on top of and covered by the first insulating layer, and The second conductive layer includes: The second-1st power line of the second power line arranged along the second direction and each extending along the first direction, the write scan line, the first-1st voltage line of the first voltage line, the first-1st power line of the first power line, and the first initialization line of the initialization line; and The capacitor electrodes are spaced apart from each other between the first-1 voltage line and the first-1 electric line and along the first direction.

9. The electronic device according to claim 8, wherein, Each of the capacitor electrodes includes a first-second capacitor pattern and a second-second capacitor pattern that are connected to each other and define a pattern. Wherein, the first-1 capacitor pattern overlaps with the first-2 capacitor pattern to form a first capacitor, and The second-1 capacitor pattern overlaps with the second-2 capacitor pattern to form a second capacitor.

10. The electronic device according to claim 8, wherein, The third conductive layer is on top of and covered by the second insulating layer, and The third conductive layer includes a semiconductor pattern contained in each of the pixel transistor and the repair transistor.

11. The electronic device according to claim 9, wherein, The fourth conductive layer is on the third insulating layer and is covered by the fourth insulating layer, and The fourth conductive layer includes: The reference scan line, the first transmit signal line, the second transmit signal line, and the initialization scan line, arranged along the second direction and each extending along the first direction; and A gate, a portion of each of the gates overlaps with a semiconductor layer and is included in each of the pixel transistor and the repair transistor.

12. The electronic device according to claim 10, wherein, The fifth conductive layer is disposed on the fourth insulating layer and is covered by the fifth insulating layer, and The fifth conductive layer includes the data line and a connection pattern that connects the different conductive layers.

13. The electronic device according to claim 11, wherein, The sixth conductive layer is on the fifth insulating layer and is covered by the sixth insulating layer, and The sixth conductive layer includes a first-2 electric field line of the first electric field line arranged along the first direction and each extending along the second direction, a second initialization line of the initialization line, a first-2 voltage line of the first voltage line, a second-2 voltage line of the second voltage line, and a second-2 electric field line of the second electric field line.

14. The electronic device according to claim 13, wherein, The first-2 electric power line, the second-2 electric power line, the first-2 voltage line, the second-2 voltage line, and the second initialization line are respectively connected to the first-1 electric power line, the second-1 electric power line, the first-1 voltage line, the second-1 voltage line, and the first initialization line through contact holes passing through the first insulation layer to the fifth insulation layer, to form the first electric power line, the second electric power line, the first voltage line, the second voltage line, and the initialization line.

15. The electronic device according to claim 1, wherein, The pixel circuit includes a light-emitting element, and The light-emitting element includes a first electrode, a second electrode, and a common layer between the first electrode and the second electrode. The common layer includes the emission layer.

16. The electronic device according to claim 1, wherein, The effective area includes the emission area and the non-emission area. In the emission region, three emission regions that are directly adjacent to each other are defined as a unit pixel, and The effective area includes multiple unit pixels, including the single unit pixel, and the multiple unit pixels are arranged along a first direction and a second direction that intersect each other.

17. The electronic device according to claim 16, wherein, The three launch zones correspond to the first launch zone, the second launch zone, and the third launch zone. Wherein, the first emitting region is configured to emit red light, the second emitting region is configured to emit green light, and the third emitting region is configured to emit blue light, and The size of the first transmission region is smaller than the size of the second transmission region but larger than the size of the third transmission region.

18. The electronic device according to claim 17, wherein, The first emission region and the third emission region are spaced apart from each other along the first direction, and The second emission region is spaced apart from each of the first emission region and the third emission region along the diagonal direction of the first direction and the second direction.

19. The electronic device according to claim 1, wherein, The pixel circuit includes a light-emitting element, and the electronic device further includes: An encapsulation layer covers the light-emitting element.

20. The electronic device of claim 19, further comprising: A light control pattern, on the encapsulation layer, is configured to convert the optical properties of the source light generated in the light-emitting element, and includes quantum dots; as well as Color filters on the light control pattern.

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