Semiconductor layout pattern and method of manufacturing the same

Abstract

A semiconductor layout pattern and a method of fabricating the same are disclosed. The semiconductor layout pattern includes a substrate having a plurality of ternary content addressable memory (TCAM) cells. Layouts of at least two of the TCAM cells are mirror-symmetrical to each other along a symmetry axis. Each of the TCAM cells includes a plurality of transistors. The substrate includes a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged in an X direction. A first gate structure of the plurality of gate structures is connected to a search line SLB, and a second gate structure of the plurality of gate structures is not connected to the search line SLB. The first gate structure and the second gate structure are arranged in parallel. The first gate structure does not overlap the symmetry axis, and the second gate structure overlaps the symmetry axis.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a layout pattern of a Content Addressable Memory (CAM) and a method for manufacturing the same. Background Technology

[0002] Generally, when performing digital data operations, the amount of data to be processed is enormous. Furthermore, some applications (such as network routers) require large amounts of dynamically updated stored data, which cannot be pre-sorted, making real-time data retrieval difficult. To effectively accelerate data retrieval for this large and randomly stored data, Content Addressable Memory (CAM) is used to solve various search problems. CAM (also known as associative memory) acts like a giant lookup table, finding the address of a matching keyword based on the input keyword. This is achieved through a special hardware architecture design that allows the keyword to be searched to be compared simultaneously with the data stored in the CAM, outputting the address of the data matching the input keyword. The data associated with the keyword can then be found using the address found by the CAM.

[0003] Content-addressable memory (CAM) can include binary CAM (BCAM) and tri-state CAM (TCAM). In BCAM, each bit has two states, 0 or 1, while in TCAM, each bit has three states: 0, 1, and a "don't care" state. This third state characteristic of TCAM enables it to perform both exact match lookups and fuzzy match lookups. Summary of the Invention

[0004] This invention provides a semiconductor layout pattern comprising a substrate on which a plurality of tri-state content addressable memory (TCAM) cells are included, wherein at least two TCAM cells are mirror-symmetrical about each other along an axis of symmetry, and each TCAM cell includes a plurality of transistors. The substrate includes a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged in an X direction, wherein some of the gate structures span the fin structures and constitute the plurality of transistors of the TCAM cell, wherein the plurality of gate structures includes a first gate structure connected to a search line SLB and a second gate structure not connected to the search line SLB, wherein the first gate structure and the second gate structure are arranged in parallel, and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

[0005] The present invention also provides a method for fabricating a semiconductor layout pattern, comprising providing a substrate and forming a plurality of ternary content addressable memory (TCAM) cells on the substrate, wherein at least two TCAM cells are mirror-symmetrical about each other along an axis of symmetry, wherein each TCAM cell includes a plurality of transistors, the substrate includes a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged in an X direction, wherein some of the gate structures cross the fin structures and constitute the plurality of transistors of the TCAM cell, wherein the plurality of gate structures includes a first gate structure connected to a search line SLB and a second gate structure not connected to the search line SLB, wherein the first gate structure and the second gate structure are arranged in parallel and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

[0006] The present invention is characterized in that, when two Tri-State Content Addressable Memory Cells (TCAMs) are arranged on a substrate, if the gate structure is directly divided at the junction of the two TCAMs with a continuous strip cutting pattern, uneven pattern density is likely to occur. To solve this problem, in the present invention, the cutting area at the junction of the two TCAMs is divided into multiple segments, arranged in an alternating manner in, for example, a rhomboid shape. In this way, the gate structure after cutting will be more uniformly distributed, which is beneficial to improving the overall quality of the semiconductor device. In addition, the present invention connects the first metal layer, which is prone to coupling effects, to the voltage source through the upper contact plug to avoid the occurrence of coupling effects. Furthermore, in some embodiments of the present invention, in addition to forming fin structures, multiple dummy fin structures are also formed and distributed next to the fin structures, which can improve the pattern uniformity of the overall layout. Attached Figure Description

[0007] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0008] Figure 1 This is a schematic diagram of the circuit pattern of the tri-state content addressable memory in the first embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of the layout pattern of a tri-state content-addressable memory cell in the first embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of the side-by-side layout of two tri-state content-addressable memory cells in the first embodiment of the present invention;

[0011] Figure 4 , Figure 5 and Figure 6 This is a schematic diagram of the side-by-side layout of two tri-state content-addressable memory cells in the second embodiment of the present invention;

[0012] Figure 7 for Figure 6 The cross-sectional view obtained along section line B-B' emphasizes the contact plug, the first metal layer, and the relationship between the contact plug and the first metal layer;

[0013] Figure 8 For the corresponding Figure 4 The cross-sectional view obtained by section line A-A' in the figure emphasizes the relationship between the base, fin structure and dummy fin structure.

[0014] Symbol Explanation

[0015] 6T-SRAM1: Six-transistor static random access memory

[0016] 6T-SRAM2: Six-transistor static random access memory

[0017] 10: Base

[0018] BL: Bitline

[0019] BLB: Line

[0020] C1, C2, C3, C4: Cutting areas

[0021] CL: Comparison Logic Circuit

[0022] DF: Virtual fin structure

[0023] F: Fin-like structure

[0024] G: Gate structure

[0025] G1: Gate structure (first gate structure)

[0026] G2: Gate structure (first gate structure)

[0027] G3: Gate structure

[0028] G4: Gate structure

[0029] G5: Gate structure (third gate structure)

[0030] I: Axis of symmetry

[0031] INV1: First Inverter

[0032] INV2: Second Inverter

[0033] INV3: Third Inverter

[0034] INV4: Fourth Inverter

[0035] M1: First metal layer

[0036] M1-1: First metallic wire

[0037] M1-2: Second metal wire

[0038] M1-3: Third metal wire

[0039] M2: Second metal layer

[0040] MD: Conductive layer

[0041] MP: Conductive layer

[0042] ML: Matching line

[0043] N1: Storage node

[0044] N2: Storage Node

[0045] PU1: First pull-up transistor

[0046] PU2: Second pull-up transistor

[0047] PU3: Third pull-up transistor

[0048] PU4: Fourth pull-up transistor

[0049] PD1: First pull-down transistor

[0050] PD2: Second pull-down transistor

[0051] PD3: Third pull-down transistor

[0052] PD4: Fourth pull-down transistor

[0053] PG1: First transfer gate transistor

[0054] PG2: Second transfer gate transistor

[0055] PG3: Third transfer gate transistor

[0056] PG4: Fourth Transfer Gate Transistor

[0057] SL: Search Line

[0058] SLB: Search Line

[0059] T1: First transistor

[0060] T2: Second transistor

[0061] T3: Third transistor

[0062] T4: Fourth transistor

[0063] TCAM: Tri-state Content Addressable Memory

[0064] TCAM2: Tri-state Content Addressable Memory

[0065] V0: Contact plug

[0066] V1: Contact plug

[0067] Vcc: Voltage source

[0068] Vss: Voltage source

[0069] WL1: Wordline

[0070] WL2: Wordline Detailed Implementation

[0071] Although this document discusses specific configurations and arrangements, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0072] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0073] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context) as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a plural combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or to convey a plural usage, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for the presence of additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0074] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosed content of this case should be interpreted in the broadest possible sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “above” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0075] Furthermore, for ease of description, as illustrated in the accompanying drawings, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein may be interpreted accordingly.

[0076] As used herein, the term "substrate" refers to the material on which layers of material are subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0077] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0078] In this embodiment, a ternary content-addressable memory (TCAM) is first disclosed, which includes two six-transistor static random access memories (6T-SRAMs) each consisting of six transistors, and a comparator logic circuit consisting of four transistors. For more details, please refer to... Figure 1 , Figure 1 The diagram illustrates a circuit pattern of a three-state content-addressable memory according to a first embodiment of the present invention. For example... Figure 1As shown, a tri-state content-addressable memory (TCAM) of the present invention is composed of two six-transistor cells (six-transistor static random access memory) 6T-SRAM1 and 6T-SRAM2, and a comparison logic circuit CL. The six-transistor cell 6T-SRAM1 includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass-gate transistor PG1, and a second pass-gate transistor PG2. The six-transistor cell 6T-SRAM2 includes a third pull-up transistor PU3, a fourth pull-up transistor PU4, a third pull-down transistor PD3, a fourth pull-down transistor PD4, a third pass-gate transistor PG3, and a fourth pass-gate transistor PG4. The comparison logic circuit CL includes two interconnected first transistors T1 and T2, and two interconnected third transistors T3 and T4. The first pull-up transistor PU1 and the first pull-down transistor PD1 form a first inverter INV1, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form a second inverter INV2. The first inverter INV1 and the second inverter INV2 form a latch circuit, allowing data to be latched to storage nodes N1 and N2. Similarly, the third pull-up transistor PU3 and the third pull-down transistor PD3 form a third inverter INV3, and the fourth pull-up transistor PU4 and the fourth pull-down transistor PD4 form a fourth inverter INV4. The third inverter INV3 and the fourth inverter INV4 form a latch circuit, allowing data to be latched to storage nodes N1 and N2.

[0079] Taking a six-transistor unit 6T-SRAM1 as an example, the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first transmission gate transistor PG1, and the second transmission gate transistor PG2 together constitute a six-transistor static random access memory (6T-SRAM). Furthermore, the first pull-up transistor PU1 and the second pull-up transistor PU2 serve as active loads; they can also be replaced by ordinary resistors as pull-up elements, in which case it becomes a four-transistor static random access memory (4T-SRAM). In this embodiment, one source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc (not shown), and one source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss (not shown). The six-transistor unit 6T-SRAM2 has similar features and connection methods to the above-mentioned six-transistor unit 6T-SRAM1; please refer to [reference needed]. Figure 1 I will not repeat the details here.

[0080] Generally speaking, the first pull-up transistor PU1, the second pull-up transistor PU2, the third pull-up transistor PU3, and the fourth pull-up transistor PU4 of a 6T-SRAM memory cell are composed of P-type metal oxide semiconductor (PMOS) transistors, while the first pull-down transistor PD1, the second pull-down transistor PD2, the third pull-down transistor PD3, the fourth pull-down transistor PD4, the first transfer gate transistor PG1, the second transfer gate transistor PG2, the third transfer gate transistor PG3, and the fourth transfer gate transistor PG4 are composed of N-type metal oxide semiconductor (NMOS) transistors.

[0081] Taking a six-transistor cell 6T-SRAM1 as an example, at memory node N1, the gates of the first pull-down transistor PD1 and the first pull-up transistor PU1, and the drains of the second pull-down transistor PD2, the second pull-up transistor PU2, and the first transmission gate transistor PG1 are electrically connected. Similarly, at memory node N2, the gates of the second pull-down transistor PD2 and the second pull-up transistor PU2, and the drains of the first pull-down transistor PD1, the first pull-up transistor PU1, and the first transmission gate transistor PG1 are electrically connected. The six-transistor cell 6T-SRAM2 has similar characteristics and connection methods to the above-described six-transistor cell 6T-SRAM1, which can be referred to... Figure 1This will not be repeated here. As for the gates of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 in the six-transistor cell 6T-SRAM1, they are coupled to word line WL1. The gates of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 in the six-transistor cell 6T-SRAM2 are coupled to word line WL2. The sources of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 are coupled to the corresponding bit line BLB and bit line BL, respectively.

[0082] like Figure 1 As shown, in this embodiment, the gate of the second transistor T2 is connected to the storage node N2 of the 6T-SRAM, meaning the gate of the second transistor T2 is connected to the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2. The second transistor T2 is connected in series with the first transistor T1, meaning the drain of the second transistor T2 is connected to the source of the first transistor T1. The drain of the first transistor T1 is connected to a voltage source (e.g., a voltage source Vss), and the gate of the first transistor T1 is connected to a search line SLB. The source of the second transistor T2 is connected to a match line ML.

[0083] On the other hand, the connection methods of the third transistor T3 and the fourth transistor T4 are similar to and symmetrical to those of the first transistor T1 and the second transistor T2, respectively. The gate of the third transistor T3 is connected to the storage node N2 of the 6T-SRAM2, meaning that the gate of the third transistor T3 is connected to the gates of the fourth pull-up transistor PU4 and the fourth pull-down transistor PD4. The fourth transistor T4 is connected in series with the third transistor T3, meaning that the drain of the fourth transistor T4 is connected to the source of the third transistor T3. The drain of the fourth transistor T4 is connected to a voltage source (e.g., a voltage source Vss), and the gate of the fourth transistor T4 is connected to the search line SL. The source of the third transistor T3 is connected to the matching line ML.

[0084] The 6T-SRAM described above can be used as a signal storage unit in a tri-state content-addressable memory (TPM). The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4, which are connected to the 6T-SRAM, are used as the comparison logic circuit for the TPM. In other words, a TPM in this embodiment is composed of two 6T-SRAMs and four other transistors.

[0085] In practice, the matching line ML can be pre-charged to a high potential. Then, the search lines SL and SLB can be supplied with either a high or low potential to turn on or off the first transistor T1 and the fourth transistor T4. This allows the signals from the search lines SL and SLB to be compared with the signals previously stored in the 6T-SRAM. For example, a high potential can be defined as signal 1, and a low potential as signal 0. Depending on the application, the signals of the search lines SL and SLB can be set to (0, 1), (1, 0), or (0, 0). Signals (0, 1) or (1, 0) are compared with the signals stored in the 6T-SRAM at memory node N1. If the comparison matches, the electrical signal of the matching line ML remains high; otherwise, if the comparison does not match, the electrical signal of the matching line ML drops from high to low. Additionally, the signal (0, 0) represents a "don't care" state, allowing for fuzzy comparison. The above circuitry constitutes the Tri-State Content Addressable Memory (TCAM) described in this invention. Other related technologies concerning the principles and logic comparison methods of content addressable memory are existing technologies in this field and will not be elaborated upon here.

[0086] Figure 2 The diagram illustrates the layout pattern of a tri-state content-addressable memory cell according to a first embodiment of the present invention. For example... Figure 2 As shown, in order to form tri-state content-addressable memory cells in each region, multiple fin structures F, multiple gate structures G (e.g., polysilicon gates, but not limited to these), and multiple conductive layers are formed on the substrate 10. Figure 2 The conductive layer overlapping with the gate structure G is defined as MP, while the conductive layer not overlapping with the gate structure G is defined as MD. The conductive layers MP and MD can be made of the same material, such as metals like tungsten, cobalt, copper, aluminum, gold, silver, etc., but are not limited to these. Both conductive layers MP and MD function as connecting elements. Therefore, in some embodiments, conductive layers MP and MD can be considered as the same layer structure. Additionally, a contact plug V0 is included to connect the gate structure G or the conductive layers MP / MD to other signal sources, such as wires from other layers or bit lines BL / BLB, word lines WL1 / WL2, search lines SL / SLB, match lines ML, voltage sources Vcc / Vss, etc.

[0087] In some embodiments of the present invention, the fin structure F may be replaced by a diffusion region; the fin structure F will still be used as an example for the following description. The gate structure G spans the fin structure F and is combined to form the aforementioned transistors, including a first pull-up transistor PU1, a second pull-up transistor PU2, a third pull-up transistor PU3, a fourth pull-up transistor PU4, a first pull-down transistor PD1, a second pull-down transistor PD2, a third pull-down transistor PD3, a fourth pull-down transistor PD4, a first transmission gate transistor PG1, a second transmission gate transistor PG2, a third transmission gate transistor PG3, a fourth transmission gate transistor PG4, a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Each transistor can be electrically connected to a signal source via subsequently formed metal wires or contact structures, such as bit lines BL / BLB, word lines WL1 / WL2, search lines SL / SLB, and matching lines ML. For clarity of description in the accompanying drawings, Figure 2 In the layout diagrams of various embodiments of the present invention, the names of transistors or connected signal sources are directly marked at the corresponding positions in the layout diagram to indicate that a specific transistor is formed at that position, or that the position is connected to a specific signal source.

[0088] When two or more tri-state addressable memory cells (TCAMs) are arranged adjacently, reference can be made. Figure 2 and Figure 3 As shown. Figure 3 The diagram illustrates a side-by-side layout of two tri-state content-addressable memory cells according to a first embodiment of the present invention. Figure 3 The left half contains the same as Figure 2 The three-state content-addressable memory (TCAM) cells are identical, while the right half contains another TCAM2, where TCAM and TCAM2 are mirror images of each other along the axis of symmetry I. The three-state content-addressable memory cells TCAM and TCAM2 have approximately symmetrical circuit patterns. For simplicity, these symmetrical components will not be described again.

[0089] like Figure 3As shown, tri-state content-addressable memory cells TCAM and TCAM2 are arranged side by side, but the gate structure G at the axis of symmetry I is cut off. In this way, TCAM and TCAM2 are electrically insulated from each other, and can be considered as two independent components. More specifically, after the fabrication process of the gate structure G, multiple continuous strip-shaped gate structures are formed. These continuous strip-shaped structures can then be cut into multiple separate gate structures using, for example, an etching process, thus separating the tri-state content-addressable memory cells TCAM and TCAM2.

[0090] However, the applicant discovered that cutting multiple gate structures G at the point of overlap with the axis of symmetry I (i.e., along the Y direction) in the aforementioned gate cutting step would lead to two problems. One is that the cutting pattern extends along the longitudinal direction (Y direction) and cuts multiple gate structures G. However, since the length of the cutting pattern in the Y direction is relatively long, its width in the X direction also needs to be maintained at a certain value. Otherwise, if the aspect ratio of the cutting pattern is too high, it is easy for the cutting pattern to break during exposure, resulting in incomplete cutting of the gate structures G. The other problem is that between two adjacent TCAMs, all the gate structures G are cut along the axis of symmetry I, which can easily lead to uneven pattern density, affecting the quality of subsequent components.

[0091] To address the above two issues, in other embodiments of the present invention, an improved layout pattern for a tri-state content-addressable memory cell and its fabrication method are provided, as detailed below. Figures 4 to 8 The circuit diagram is the same as in the above embodiment and can be referred to. Figure 1 As shown. The following will describe different embodiments of the present invention. For the sake of simplicity, the description will focus on the differences between the embodiments, without repeating the similarities. Furthermore, identical elements in the embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.

[0092] Figure 4 , Figure 5 and Figure 6 The diagram illustrates a side-by-side layout of two tri-state content-addressable memory cells in a second embodiment of the present invention. (See diagram for example.) Figure 4As shown, this embodiment also includes two adjacent tri-state content-addressable memory cells TCAM and TCAM2, which are mirror images of each other along the axis of symmetry I. The difference from the previous embodiment is that, on the axis of symmetry I between TCAM and TCAM2, not all gate structures G are cut off at the axis of symmetry I; rather, a portion of the gate structures G are cut off at the axis of symmetry I, while the remaining portion are not. More specifically, as... Figure 4 As shown, it is possible to Figure 4 Among the multiple gate structures G, gate structures G1, G2, G3, and G4 are defined. Gate structures G1-G4 all belong to gate structure G. Gate structures G1 and G4 are connected to the search line SL / SLB via contact plug V0, while gate structures G2 and G3 are not connected to other components and can be considered as dummy gate structures. In this embodiment, gate structures G1, G2, G3, and G4 partially overlap each other in the Y direction. In this embodiment, gate structures G1 and G4 do not overlap with the axis of symmetry I, while gate structures G2 and G3 are not cut off at the axis of symmetry I; therefore, gate structures G2 and G3 overlap with the axis of symmetry I. In other words, the difference between this embodiment and the above embodiment is that, when performing the gate structure cutting step, not all gate structures G overlapping with the axis of symmetry I are cut off. Instead, a portion of the gate structures G overlapping with the axis of symmetry I are cut off in an interlaced manner, and the other portion of the gate structures G is not cut off at the axis of symmetry I.

[0093] Furthermore, you can refer to Figure 4 The cutting regions C1, C2, C3, and C4 are outlined with dashed lines. Regions C1-C4 represent the areas where the gate structure G is cut; in other words, the gate structure G located within regions C1-C4 will be removed. This can be seen from... Figure 4 As can be seen, the four adjacent cutting regions C1-C4 are arranged in an alternating manner to form a diamond-like shape. Therefore, the cuts that cut the gate structure G will also be distributed in a diamond-like manner.

[0094] In this embodiment, because the cutting regions C1-C4 are arranged in a rhomboid pattern, compared to the above... Figure 3In this embodiment, regarding the aspect ratio of the elongated cutting regions extending along the entire axis of symmetry I, the aspect ratio of each cutting region C1-C4 is relatively small. This allows the width of each cutting region C1-C4 to be reduced accordingly, which better avoids incomplete exposure due to excessively large aspect ratios, thus preventing the gate structure G from being cut accurately. Furthermore, since the cutting regions C1-C4 are more uniformly distributed, the density uniformity of the overall semiconductor layout pattern can also be improved.

[0095] Please refer to the following. Figure 5 and Figure 6 After forming the aforementioned fin structure F, gate structure G, conductive layer MP, conductive layer MD, and contact plug V0, subsequent patterns such as the first metal layer M1, contact plug V1, and second metal layer M2 are formed on top of them. Here, the first metal layer M1 and the second metal layer M2 can connect different components on the same layer (on the XY plane), while the contact plugs V0 and V1 are mainly used to connect components between different layers in the vertical direction (perpendicular to the XY plane). For clearer illustration in the figures, Figure 5 and Figure 6 The signal sources connected to the metal wires are marked next to the first metal layer M1 and the second metal layer M2, such as bit lines BL / BLB, word lines WL1 / WL2, search lines SL / SLB, matching lines ML, voltage sources Vcc / Vss, etc.

[0096] The materials of the first metal layer M1, the second metal layer M2, the contact plug V0, and the contact plug V1 are, for example, highly conductive metals such as tungsten, cobalt, copper, aluminum, gold, and silver, but are not limited to these. To simplify the pattern design of the photomask, such as... Figures 5-6 As shown, Figure 5 The first metal layer M1 formed contains multiple metal patterns, most of which extend along the Y direction, while Figure 6 The second metal layer M2 contains multiple metal patterns, most of which extend along the X direction. It is also understood that although patterned layers such as the first metal layer M1 and the second metal layer M2 are shown in this embodiment, in some embodiments the semiconductor layout pattern may also include more stacked metal layers and metal plugs, such as the third metal layer M3 (not shown), the fourth metal layer M4 (not shown), contact plug V2 (not shown), and contact plug V3 (not shown), which are also within the scope of this invention.

[0097] It is worth noting that, please refer to Figure 5The first metal layer M1 contains multiple metal patterns extending along the Y direction. The metal pattern overlapping the axis of symmetry I is defined as the first metal conductor M1-1, and the metal patterns adjacent to the first metal conductor M1-1 on the left and right are defined as the second metal conductor M1-2 and the third metal conductor M1-3, respectively. In this embodiment, the first metal conductor M1-1 is not connected to the lower contact plug V0, but the second metal conductor M1-2 and the third metal conductor M1-3 are both connected to the lower contact plug V0. Thus, when the circuit is on, the low-potential first metal conductor M1-1 is located between the two high-potential second metal conductors M1-2 and the third metal conductor M1-3. The applicant has found that this configuration is prone to coupling effects. Specifically, the high-potential metal conductors generate an electric field that affects the low-potential metal conductors, causing signal interference problems such as noise.

[0098] Another feature of the present invention is that, in order to solve the above-mentioned coupling effect problem, in this embodiment, the first metal wire M1-1 is connected to the second metal layer M2 through the upper contact plug V1, and then connected to the voltage source Vss, while the first metal wire M1-1 is not connected to the contact plug V0. See also... Figure 6 and Figure 7 ,in Figure 7 Draw Figure 6 The cross-sectional view obtained along section line B-B' is used to clearly illustrate the features of this embodiment. Figure 7 The drawing mainly shows the contact plug V0, the first metal layer M1, and the relationship between the contact plug V1 and the first metal layer M2; other components are omitted and not shown. Additionally, Figure 7 A portion of the contact plugs V0, indicated by dashed lines, are located below the first metal layer M1. This means that although these contact plugs V0 do not pass through the cross-sectional direction B-B', they are located outside the cross-sectional line B-B' and are electrically connected to the first metal layer M1. Figure 7 It can be seen that the first metal wire M1-1 is located between the second metal wire M1-2 and the third metal wire M1-3. The second metal wire M1-2 and the third metal wire M1-3 are both connected to the lower contact plug V0 to the search line SLB. The lower part of the second metal wire M1-1 does not contain the contact plug V0, but is electrically connected to the second metal layer M2 through the upper contact plug V1, and is connected to the voltage source Vss.

[0099] In summary, in this embodiment, one method to solve the coupling problem is to ground the first metal wire M1-1 or connect it to a fixed voltage source (such as Vss). However, the second metal wires M1-2 and the third metal wires M1-3 on both sides of the first metal wire M1-1 are already connected to the contact plug V0. Therefore, connecting the first metal wire M1-1 to the voltage source Vss from the lower contact plug V0 would occupy additional space. Therefore, in this embodiment, electrically connecting the first metal wire M1-1 to the voltage source Vss through the upper contact plug V1 can effectively solve the above-mentioned coupling effect without occupying additional space.

[0100] Furthermore, another feature of the present invention is described in reference to... Figure 8 . Figure 8 For the corresponding Figure 4 The cross-sectional view obtained by section line A-A' in the figure is shown in order to clearly illustrate the features of this embodiment. Figure 8 The main focus is on the relationship between the base, the fin-like structure, and the dummy fin-like structure; other components are omitted and not shown. For example... Figure 8 As shown, when forming the fin structure, to avoid uneven pattern density in the semiconductor layout—for example, areas with fin structures having higher pattern density and areas without fin structures having lower pattern density—in some embodiments of the present invention, multiple dummy fin structures DF can be formed simultaneously on the substrate 10 while forming the fin structure F on the substrate 10. From the cross-sectional view, the width and height of the dummy fin structures DF are preferably smaller than the width and height of the fin structure F. In the present invention, the purpose of forming the dummy fin structures DF is to make the overall pattern more uniform and avoid the aforementioned problem of uneven pattern density. In subsequent steps, the dummy fin structures DF may be retained on the substrate 10, meaning that the gate structure G, in addition to spanning the fin structure F, also spans the dummy fin structures DF. Alternatively, in other embodiments, the dummy fin structures DF may be removed, which is also within the scope of the present invention.

[0101] Based on the above description and accompanying drawings, the present invention provides a semiconductor layout pattern comprising a substrate 10, on which a plurality of tri-state content addressable memory (TCAM) cells are included, wherein at least two TCAM cells (TCAM1, TCAM2) are mirror-symmetrically arranged along a symmetry axis I, wherein each TCAM cell includes a plurality of transistors, and the substrate 10 includes a plurality of fin structures F arranged in a Y direction and a plurality of gate structures G arranged in an X direction, wherein some of the gate structures G span the fin structures F and constitute the plurality of transistors of the TCAM cell, wherein the plurality of gate structures G includes a first gate structure G1 connected to a search line SLB and a second gate structure G2 not connected to the search line SLB, wherein the first gate structure G1 and the second gate structure G2 are arranged in parallel, and the first gate structure G1 does not overlap with the symmetry axis I, while the second gate structure G2 overlaps with the symmetry axis I.

[0102] In some embodiments of the present invention, an extension direction of the symmetry axis I is parallel to an extension direction of each fin structure (both extending along the Y direction), and the extension direction of the symmetry axis I is perpendicular to an extension direction of each gate structure G (the gate structure G extends along the X direction).

[0103] In some embodiments of the present invention, each TCAM unit includes a plurality of transistors, including two six-transistor layout patterns (6T-SRAM1 and 6T-SRAM2) and a comparison logic circuit CL. Each six-transistor layout pattern includes: a first pull-up transistor (PU1) and a first pull-down transistor (PD1) forming a first inverter (INV1); a second pull-up transistor (PU2) and a second pull-down transistor (PD2) forming a second inverter (INV2); a first access transistor (PG1) and a second access transistor (PG2) connecting the first inverter and the second inverter. The comparison logic circuit CL includes a first transistor T1 and a second transistor T2 connected in series, and a third transistor T3 and a fourth transistor T4 connected in series. The gate structure of the second transistor T2 is connected to the gate structure of the second pull-down transistor (PD2).

[0104] In some embodiments of the present invention, the first gate structure G1 spans a portion of the fin structure F and forms the first transistor T1, and the second gate structure G2 does not span the fin structure.

[0105] In some embodiments of the present invention, the plurality of gate structures G further include a third gate structure (such as...). Figure 4The third gate structure G5 spans the fin structure F and forms the second transistor T2, wherein the third gate structure G5 and the second gate structure G2 are aligned with each other in the X direction.

[0106] In some embodiments of the present invention, the layout pattern includes a first metal layer (M1) containing a plurality of metal wires, and a first metal wire M1-1 contained in the first metal layer (M1) overlaps with the axis of symmetry, and a second metal wire M1-2 contained in the first metal layer (M1) is electrically connected to a first gate structure G1 through a zero-layer contact plug (V0), wherein, from a cross-sectional view, the zero-layer contact plug (V0) is located below the second metal wire M1-2.

[0107] In some embodiments of the present invention, the first metal wire M1-1 is electrically connected to a second metal layer (M2) through a first layer contact plug (V1) and connected to a voltage source (Vss).

[0108] In some embodiments of the present invention, as viewed in a cross-sectional view, the first layer of contact plugs (V1) is located above the first metal wire M1-1, and there is no contact plug V0 directly below the first metal wire M1-1 (e.g., Figure 7 (As shown).

[0109] In some embodiments of the present invention, the first metal wire M1-1 and the second metal wire M1-2 are parallel to each other, the first metal wire M1-1 and the second metal wire M1-2 are adjacent to each other, and an extension direction of the first metal wire M1-1 is parallel to an extension direction of the axis of symmetry I.

[0110] In some embodiments of the present invention, a plurality of dummy fin structures DF are located on the substrate 10, and some of the dummy fin structures DF are located between the fin structures F, wherein the width and height of the dummy fin structures DF are smaller than the width and height of the fin structures F.

[0111] The present invention also provides a method for fabricating a semiconductor layout pattern, comprising providing a substrate 10, forming a plurality of ternary content addressable memory (TCAM) cells on the substrate 10, wherein the layout of at least two TCAM cells is mirror-symmetrical to each other along a symmetry axis I, wherein each TCAM cell includes a plurality of transistors, the substrate 10 includes a plurality of fin structures F arranged in a Y direction and a plurality of gate structures G arranged in an X direction, wherein some of the gate structures G span the fin structures F and constitute the plurality of transistors of the TCAM cell, wherein the plurality of gate structures G includes a first gate structure G1 connected to a search line SLB and a second gate structure G2 not connected to the search line SLB, wherein the first gate structure G1 and the second gate structure G2 are arranged in parallel, and the first gate structure G1 does not overlap with the symmetry axis I, while the second gate structure G2 overlaps with the symmetry axis I.

[0112] In some embodiments of the present invention, an extension direction of the symmetry axis I is parallel to an extension direction of each fin structure (both extending along the Y direction), and the extension direction of the symmetry axis I is perpendicular to an extension direction of each gate structure G (the gate structure G extends along the X direction).

[0113] In some embodiments of the present invention, each TCAM unit includes a plurality of transistors, including two six-transistor layout patterns (6T-SRAM1 and 6T-SRAM2) and a comparison logic circuit CL. Each six-transistor layout pattern includes: a first pull-up transistor (PU1) and a first pull-down transistor (PD1) forming a first inverter (INV1); a second pull-up transistor (PU2) and a second pull-down transistor (PD2) forming a second inverter (INV2); a first access transistor (PG1) and a second access transistor (PG2) connecting the first inverter and the second inverter. The comparison logic circuit CL includes a first transistor T1 and a second transistor T2 connected in series, and a third transistor T3 and a fourth transistor T4 connected in series. The gate structure of the second transistor T2 is connected to the gate structure of the second pull-down transistor (PD2).

[0114] In some embodiments of the present invention, the first gate structure G1 spans a portion of the fin structure F and forms the first transistor T1, and the second gate structure G2 does not span the fin structure.

[0115] In some embodiments of the present invention, the plurality of gate structures G further include a third gate structure (such as...). Figure 4The third gate structure G5 spans the fin structure F and forms the second transistor T2, wherein the third gate structure G5 and the second gate structure G2 are aligned with each other in the X direction.

[0116] In some embodiments of the present invention, a first metal layer (M1) is formed that includes a plurality of metal wires, and a first metal wire M1-1 included in the first metal layer (M1) overlaps with the axis of symmetry, and a second metal wire M1-2 included in the first metal layer (M1) is electrically connected to a first gate structure G1 through a zero-layer contact plug (V0), wherein, from a cross-sectional view, the zero-layer contact plug (V0) is located below the second metal wire M1-2.

[0117] In some embodiments of the present invention, the first metal wire M1-1 is electrically connected to a second metal layer (M2) through a first layer contact plug (V1) and connected to a voltage source (Vss).

[0118] In some embodiments of the present invention, as viewed in a cross-sectional view, the first layer of contact plugs (V1) is located above the first metal wire M1-1, and there is no contact plug V0 directly below the first metal wire M1-1 (e.g., Figure 7 (As shown).

[0119] In some embodiments of the present invention, the first metal wire M1-1 and the second metal wire M1-2 are parallel to each other, the first metal wire M1-1 and the second metal wire M1-2 are adjacent to each other, and an extension direction of the first metal wire M1-1 is parallel to an extension direction of the axis of symmetry I.

[0120] In some embodiments of the present invention, a plurality of dummy fin structures DF are formed on the substrate 10, and some of the dummy fin structures DF are located between the fin structures F, wherein the width and height of the dummy fin structures DF are smaller than the width and height of the fin structures F.

[0121] In summary, the key feature of this invention is that when two Tri-State Content Addressable Memory Cells (TCAMs) are arranged on a substrate, if the gate structure is directly divided with a continuous strip cutting pattern at the junction of the two TCAMs, uneven pattern density can easily occur. To solve this problem, in this invention, the cutting area at the junction of the two TCAMs is divided into multiple segments, arranged in an alternating manner, for example, in a diamond shape. This results in a more uniform distribution of the cut gate structure, thus improving the overall quality of the semiconductor device. Furthermore, this invention connects the first metal layer, which is prone to coupling effects, to the voltage source via upper contact plugs to avoid coupling effects. Additionally, in some embodiments of this invention, besides forming fin-like structures, multiple dummy fin-like structures are also formed and distributed beside the fin-like structures, thereby improving the pattern uniformity of the overall layout.

[0122] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor layout pattern, comprising: A substrate containing a plurality of ternary content addressable memory (TCAM) cells, wherein the layout of at least two TCAM cells is mirror-symmetrical about each other along an axis of symmetry. Each TCAM unit includes multiple transistors, and the substrate includes multiple fin structures arranged in the Y direction and multiple gate structures arranged in the X direction, wherein some of the gate structures span the fin structures and constitute the multiple transistors of the TCAM unit; and The plurality of gate structures include a first gate structure connected to the search line SLB and a second gate structure not connected to the search line SLB. The first gate structure and the second gate structure are arranged in parallel, and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

2. The semiconductor layout pattern of claim 1, wherein the extension direction of the axis of symmetry is parallel to the extension direction of each of the fin structures, and the extension direction of the axis of symmetry is perpendicular to the extension direction of each of the gate structures.

3. The semiconductor layout pattern as claimed in claim 1, wherein each of the TCAM units includes a plurality of transistors comprising a comparator logic circuit and two six-transistor layout patterns, wherein each six-transistor layout pattern comprises: The first pull-up transistor (PU1) and the first pull-down transistor (PD1) form the first inverter (INV1), the second pull-up transistor (PU2) and the second pull-down transistor (PD2) form the second inverter (INV2), and the first access transistor (PG1) and the second access transistor (PG2) are connected to the first inverter and the second inverter. The comparison logic circuit includes a first transistor T1 and a second transistor T2 connected in series, and a third transistor T3 and a fourth transistor T4 connected in series, wherein the gate structure of the second transistor T2 is connected to the gate structure of the second pull-down transistor (PD2).

4. The semiconductor layout pattern as claimed in claim 3, wherein the first gate structure spans a portion of the fin structure and constitutes the first transistor T1, and the second gate structure does not span the fin structure.

5. The semiconductor layout pattern of claim 1, wherein the plurality of gate structures further includes a third gate structure that spans the fin structure and forms the second transistor T2, wherein the third gate structure and the second gate structure are aligned with each other in the X direction.

6. The semiconductor layout pattern of claim 1, wherein the layout pattern includes a first metal layer (M1) including a plurality of metal wires, and the first metal wires included in the first metal layer (M1) overlap with the axis of symmetry, and the second metal wires included in the first metal layer (M1) are electrically connected to the first gate structure through a zero-layer contact plug (V0), wherein, in cross-sectional view, the zero-layer contact plug (V0) is located below the second metal wires.

7. The semiconductor layout pattern of claim 6, wherein the first metal wire is electrically connected to the second metal layer (M2) via a first contact plug (V1) and is connected to a voltage source (Vss).

8. The semiconductor layout pattern of claim 7, wherein, in cross-sectional view, the first layer contact plug (V1) is located above the first metal conductor, and there is no contact plug directly below the first metal conductor.

9. The semiconductor layout pattern of claim 6, wherein the first metal wire and the second metal wire are parallel to each other, the first metal wire and the second metal wire are adjacent to each other, and the extension direction of the first metal wire is parallel to the extension direction of the axis of symmetry.

10. The semiconductor layout pattern of claim 1, further comprising a plurality of dummy fin structures located on the substrate, and some of the dummy fin structures located between the fin structures, wherein the width and height of the dummy fin structures are smaller than the width and height of the fin structures.

11. A method for fabricating a semiconductor layout pattern, comprising: Provide a base; Multiple ternary content addressable memory (TCAM) cells are formed on the substrate, wherein the layout of at least two TCAM cells is mirror-symmetrical to each other along the axis of symmetry; Each TCAM unit includes multiple transistors, and the substrate includes multiple fin structures arranged in the Y direction and multiple gate structures arranged in the X direction, wherein some of the gate structures span the fin structures and constitute the multiple transistors of the TCAM unit; and The plurality of gate structures include a first gate structure connected to the search line SLB and a second gate structure not connected to the search line SLB. The first gate structure and the second gate structure are arranged in parallel, and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

12. The method for fabricating a semiconductor layout pattern as claimed in claim 11, wherein the extension direction of the axis of symmetry is parallel to the extension direction of each of the fin structures, and the extension direction of the axis of symmetry is perpendicular to the extension direction of each of the gate structures.

13. The method for fabricating a semiconductor layout pattern as claimed in claim 11, wherein each TCAM unit includes a plurality of transistors, comprising a comparator logic circuit and two six-transistor layout patterns, wherein each six-transistor layout pattern comprises: The first pull-up transistor (PU1) and the first pull-down transistor (PD1) form the first inverter (INV1), the second pull-up transistor (PU2) and the second pull-down transistor (PD2) form the second inverter (INV2), and the first access transistor (PG1) and the second access transistor (PG2) are connected to the first inverter and the second inverter. The comparison logic circuit includes a first transistor T1 and a second transistor T2 connected in series, and a third transistor T3 and a fourth transistor T4 connected in series, wherein the gate structure of the second transistor T2 is connected to the gate structure of the second pull-down transistor (PD2).

14. The method for fabricating a semiconductor layout pattern as described in claim 13, wherein the first gate structure spans a portion of the fin structure and constitutes the first transistor T1, and the second gate structure does not span the fin structure.

15. The method for fabricating a semiconductor layout pattern as claimed in claim 11, wherein the plurality of gate structures further includes a third gate structure, the third gate structure spanning the fin structure and constituting the second transistor T2, wherein the third gate structure and the second gate structure are aligned with each other in the X direction.

16. The method for fabricating a semiconductor layout pattern as claimed in claim 11, further comprising forming a first metal layer (M1) including a plurality of metal wires, wherein the first metal wires included in the first metal layer (M1) overlap with the axis of symmetry, and the second metal wires included in the first metal layer (M1) are electrically connected to the first gate structure through a zero-layer contact plug (V0), wherein, in cross-sectional view, the zero-layer contact plug (V0) is located below the second metal wires.

17. The method for fabricating a semiconductor layout pattern as claimed in claim 16, wherein the first metal wire is electrically connected to the second metal layer (M2) via a first contact plug (V1) and is connected to a voltage source (Vss).

18. The method for fabricating a semiconductor layout pattern as claimed in claim 17, wherein, in cross-sectional view, the first layer contact plug (V1) is located above the first metal wire, and there is no contact plug directly below the first metal wire.

19. The method for fabricating a semiconductor layout pattern as described in claim 16, wherein the first metal wire and the second metal wire are parallel to each other, the first metal wire and the second metal wire are adjacent to each other, and the extension direction of the first metal wire is parallel to the extension direction of the axis of symmetry.

20. The method for fabricating a semiconductor layout pattern as claimed in claim 11, further comprising forming a plurality of dummy fin structures on the substrate, and some of the dummy fin structures being located between the fin structures, wherein the width and height of the dummy fin structures are smaller than the width and height of the fin structures.

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