A double-sided selective topcon cell and a preparation method and application thereof

Abstract

The application provides a double-sided selective TOPCon cell and a preparation method and application thereof, and relates to the technical field of photovoltaic cells.The double-sided selective TOPCon cell comprises an N-type silicon substrate and metal electrodes arranged on the front and back surfaces of the N-type silicon substrate, the front surface of the N-type silicon substrate is provided with an N+ crystalline silicon layer, the back surface is provided with a P+ crystalline silicon layer, and the doping concentration of the N+ crystalline silicon layer and the P+ crystalline silicon layer is increased from the side close to the N-type silicon substrate to the side far away from the silicon substrate.The double-sided selective TOPCon cell improves the electron convergence ability and carrier transport efficiency of the non-metalized area, and the N+ and P+ crystalline silicon layers on the surface are provided with a concentration gradient, the concentration close to the substrate side is lower than that far away from the substrate, so that the carriers transmitted through the metal electrode can be smoothly transmitted into the substrate, thereby improving the transport efficiency of the carriers.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and in particular to a bifacial selective TOPCon cell, its preparation method, and its application. Background Technology

[0002] TOPCon (Tunnel Oxide Passivated Contact) is a next-generation high-efficiency crystalline silicon solar cell technology following PERC (Passivated Emitter and Back Contact). Its core technology utilizes a passivated contact structure of "tunnel oxide layer + doped polycrystalline silicon layer" to significantly reduce carrier recombination losses and achieve higher conversion efficiency. Currently, TOPCon cells are mainly divided into front junction and back junction TOPCon cells, and Poly-finger technology has been widely applied. This technology significantly reduces parasitic absorption caused by doped polycrystalline silicon by removing the Poly layer in the non-contact area, thus reducing energy loss. Among them, the back junction + Poly-finger cell, as shown in publication number CN120344021A, uses front-side Poly-finger technology to reduce the light-blocking area of ​​the cell surface through a rational design of the Poly layer distribution, allowing more photons to be absorbed by the cell, thereby improving light absorption efficiency and contributing to increased short-circuit current density. Furthermore, based on this TOPCon cell, the fabrication of bifacial selective TOPCon cells can further reduce parasitic absorption caused by polycrystalline silicon, thus improving the photoelectric conversion efficiency of the cell, as shown in patent publication CN120091648A.

[0003] However, due to manufacturing process limitations, the metal electrode may partially penetrate the tunnel oxide layer and directly contact the substrate, leading to severe recombination at the metal electrode-substrate interface, thereby reducing the cell's open-circuit voltage and efficiency. Furthermore, while the bifacial selective TOPCon cell structure reduces parasitic absorption in polycrystalline silicon on the front side, it also reduces the electron aggregation capacity of the non-metallized regions, thus lowering the cell's electron current. Although the back side improves passivation of the non-electrode contact areas, it requires laser etching and alkaline cleaning, demanding high precision in process control.

[0004] In view of this, there is an urgent need for a TOPCon battery structure and its fabrication method to solve the above problems. Summary of the Invention

[0005] This invention addresses the problems of low electron focusing capacity in the non-metallized region and the potential for metal electrodes to partially penetrate the tunnel oxide layer and directly contact the substrate, leading to severe recombination at the metal electrode-substrate interface in current bifacial selective TOPCon solar cells. It provides a bifacial selective TOPCon solar cell by setting a doping concentration gradient between the N+ crystalline silicon layer on the front side and the P+ crystalline silicon layer on the back side of an N-type silicon substrate. Simultaneously, a tunnel oxide layer is deposited on the non-gateway region of the N-type silicon substrate away from the substrate, effectively improving the electron focusing capacity in the non-metallized region and thus increasing the cell's electron current. This also provides good interface passivation for the metal electrodes disposed within the substrate, reducing interfacial recombination between the metal electrode and the substrate. A P+ / N+ crystalline silicon layer with a higher doping concentration on the side away from the substrate than on the side closer to the substrate is fabricated across the entire surface of the N-type silicon substrate. This doping concentration gradient within the P+ / N+ crystalline silicon layer allows charge carriers transported through the metal electrodes to be smoothly transported to the substrate, thereby improving carrier transport efficiency and reducing interfacial recombination between the metal electrode and the substrate.

[0006] Another objective of this invention is to provide a method for preparing a bifacial selective TOPCon battery.

[0007] Another object of the present invention is to provide an application of bifacial selective TOPCon cells in the fabrication of photovoltaic modules.

[0008] Another object of the present invention is to provide a photovoltaic module.

[0009] In a first aspect, the present invention provides a bifacial selective TOPCon cell, comprising an N-type silicon substrate and metal electrodes disposed on the front and back sides of the N-type silicon substrate; The N-type silicon substrate has an N+ crystalline silicon layer on its front surface and a P+ crystalline silicon layer on its back surface. The doping concentration of the N+ and P+ crystalline silicon layers increases gradually from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate.

[0010] According to the bifacial selective TOPCon cell protected by the present invention, preferably, both the front and back surfaces of the N-type silicon substrate have gate line regions and non-gate line regions. On the front surface, from the N-type silicon substrate outwards, the gate line regions are sequentially configured as an N+ crystalline silicon layer, a front tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, an aluminum oxide passivation layer, and a silicon nitride antireflection layer; the non-gate line regions are sequentially configured as an N+ crystalline silicon layer, a front tunneling oxide layer, an aluminum oxide passivation layer, and a silicon nitride antireflection layer. The back surface of the back surface extends outward from the N-type silicon substrate, with the gate area sequentially configured as a P+ crystalline silicon layer, a back tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, an aluminum oxide passivation layer, and a silicon nitride antireflection layer; the non-gate area sequentially configured as a P+ crystalline silicon layer, a back tunneling oxide layer, an aluminum oxide passivation layer, and a silicon nitride antireflection layer.

[0011] According to the bifacial selective TOPCon cell protected by the present invention, preferably, the doping concentration of the N+ crystalline silicon layer is E+17 to E+19 atoms / cm². 3 .

[0012] According to the bifacial selective TOPCon cell protected by the present invention, preferably, the doping concentration ratio of the N+ crystalline silicon layer on the side closer to the N-type silicon substrate to the side farther from the silicon substrate is 1:100 to 1:10.

[0013] According to the bifacial selective TOPCon solar cell protected by the present invention, preferably, the doping concentration of the P+ crystalline silicon layer is E+20 to E+21 atoms / cm². 3 .

[0014] According to the bifacial selective TOPCon cell protected by the present invention, preferably, the doping concentration ratio of the P+ crystalline silicon layer on the side closer to the N-type silicon substrate to the side farther from the silicon substrate is 1:100 to 1:10.

[0015] According to the bifacial selective TOPCon cell protected by the present invention, preferably, the thickness of the N+ crystalline silicon layer is 20~100nm, more preferably 20~50nm; According to the bifacial selective TOPCon cell protected by the present invention, preferably, the thickness of the P+ crystalline silicon layer is 20~100nm, more preferably 20~50nm.

[0016] Secondly, the present invention also specifically protects a method for preparing a bifacial selective TOPCon battery, comprising the following steps: S1. Polish the N-type silicon substrate on both sides, and prepare a P+ crystalline silicon layer on the back side of the N-type silicon substrate by boron diffusion, with the doping concentration increasing in a gradient from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate; S2. A tunneling oxide layer and a P+ polycrystalline silicon layer are sequentially prepared on the surface of the P+ crystalline silicon layer; S3. Texturing the front side of the N-type silicon substrate, and preparing an N+ crystalline silicon layer with a doping concentration that gradually increases from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate by phosphorus diffusion on the front side of the N-type silicon substrate; S4. A tunneling oxide layer and an N+ polycrystalline silicon layer are sequentially prepared on the surface of the N+ crystalline silicon layer; S5. Remove the polysilicon layers in the non-metallized areas on the front and back sides, retain the polysilicon layers in the metallized areas, and prepare aluminum oxide layers and anti-reflection passivation layers on the front and back sides.

[0017] Thirdly, the present invention also specifically protects the application of a bifacial selective TOPCon cell in the preparation of photovoltaic modules.

[0018] Fourthly, the present invention also specifically protects a photovoltaic module, including the bifacial selective TOPCon cell, wherein an N+ crystalline silicon layer is prepared on the full area of ​​the front side of an N-type silicon substrate. The N+ crystalline silicon layer has a concentration difference, and the doping concentration on the side away from the substrate is higher than that on the side closer to the substrate, thereby enhancing the electron gathering ability of the non-metallization region and thus increasing the electron current of the cell.

[0019] Beneficial effects: This invention provides a bifacial selective TOPCon cell. A tunneling silicon oxide layer is deposited on the non-gateway region of an N-type silicon substrate, away from the substrate, to enhance the electron gathering ability of the non-metallized region, thereby increasing the cell's electron current. A P+ / N+ crystalline silicon layer with a higher doping concentration on the side away from the substrate than on the side closer to the substrate is fabricated on the entire surface of the N-type silicon substrate. This doping concentration difference in the N+ / P+ crystalline silicon layer allows charge carriers transported through the metal electrode to be smoothly transported to the substrate, thereby improving the carrier transport efficiency and reducing interfacial recombination between the metal electrode and the substrate. Even if the metal electrode penetrates the tunneling oxide layer and directly contacts the substrate, the P+ / N+ crystalline silicon layer disposed within the substrate can still cover the metal electrode, thus providing good interfacial passivation for the metal electrode disposed within the substrate and reducing interfacial recombination between the metal electrode and the substrate. Attached Figure Description

[0020] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0021] Figure 1 This is a schematic diagram of the bifacial selective TOPCon cell of the present invention. Wherein, 100: N-type silicon substrate; 110: N+ crystalline silicon; 120: front tunneling oxide layer; 130: N+ polycrystalline silicon layer; 140: P+ crystalline silicon; 150: back tunneling oxide layer; 160: P+ polycrystalline silicon; 170: front Al2O3 layer; 180: front silicon nitride; 190: back passivation / antireflection layer; 200: front metal electrode; 210: back metal electrode. Detailed Implementation

[0022] The following examples are for illustrative purposes only and are not intended to limit the scope of the invention. Where specific techniques or conditions are not specified in the examples, they should be performed according to the techniques or conditions described in the literature in this field, or according to the product instructions. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased from legitimate channels.

[0023] Explanation of terminology used in this invention: Poly-finger technology: The polycrystalline silicon layer of the battery is patterned so that a thicker polycrystalline silicon layer is maintained under the electrodes to ensure good ohmic contact and conductivity, while the polycrystalline silicon layer in the non-electrode areas is thinned to reduce parasitic light absorption, thereby achieving a balance between optimizing passivation, reducing contact resistance and improving photoelectric conversion efficiency.

[0024] In a specific embodiment, the present invention provides a bifacial selective TOPCon cell, including an N-type silicon substrate and metal electrodes disposed on the front and back sides of the N-type silicon substrate. An N+ crystalline silicon layer is disposed on the front surface of the N-type silicon substrate, and a P+ crystalline silicon layer is disposed on the back surface. The doping concentration of the N+ crystalline silicon layer and the P+ crystalline silicon layer increases in a gradient from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate.

[0025] In some specific embodiments, the N-type silicon substrate of the bifacial selective TOPCon cell mentioned in this invention has gate line regions and non-gate line regions on both the front and back surfaces. The front surface, from the N-type silicon substrate outwards, consists of: an N+ crystalline silicon layer, a front tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, an aluminum oxide passivation layer, and a silicon nitride antireflection layer in sequence; and a non-gate line region consisting of an N+ crystalline silicon layer, a front tunneling oxide layer, an aluminum oxide passivation layer, and a silicon nitride antireflection layer in sequence. The back surface, from the N-type silicon substrate outwards, consists of: a P+ crystalline silicon layer, a back tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, an aluminum oxide passivation layer, and a silicon nitride antireflection layer in the gate area; and a P+ crystalline silicon layer, a back tunneling oxide layer, an aluminum oxide passivation layer, and a silicon nitride antireflection layer in the non-gate area.

[0026] It should be noted that: In the bifacial selective TOPCon cell provided by this invention, an n+ crystalline silicon layer is fabricated over the entire front surface of an N-type silicon substrate. This N+ crystalline silicon layer has a concentration gradient, with the doping concentration on the side farther from the substrate being higher than that on the side closer to the substrate. Similarly, a P+ crystalline silicon layer is fabricated over the entire back surface of the N-type silicon substrate. This P+ crystalline silicon layer also has a concentration gradient, with the doping concentration on the side farther from the substrate being higher than that on the side closer to the substrate. This concentration gradient in the P+ / N+ crystalline silicon layer creates a built-in electric field that assists carrier migration, allowing carriers transported through the metal electrodes to be smoothly transported to the substrate, reducing carrier recombination losses, and thus improving the efficiency of carrier transport and collection to the substrate. Even if the metal electrode penetrates the tunnel oxide layer and directly contacts the substrate, the P+ / N+ crystalline silicon layer within the substrate still covers the metal electrode, thus providing good interface passivation and reducing interfacial recombination between the metal electrode and the substrate.

[0027] Furthermore, the deposition of a tunneling silicon oxide layer in the non-gate region of the N-type silicon substrate away from the silicon substrate enhances the electron gathering ability of the non-metallized region, thereby increasing the electron current of the battery.

[0028] The bifacial selective TOPCon cell provided by this invention optimizes the structure of the back junction TOPCon cell, enhances the electron focusing capability of the non-gate area on the front side of the back junction TOPCon cell, and even if the metal electrode penetrates the tunnel oxide layer, the penetrated tunnel oxide layer can still meet the passivation requirements of the substrate.

[0029] In some specific embodiments, the doping concentration of the gate line region on the positive surface of the N-type silicon substrate mentioned in this invention satisfies the following: N-type silicon substrate < N+ crystalline silicon layer < phosphorus-doped polycrystalline silicon layer.

[0030] In some specific embodiments, the doping concentration of the N+ crystalline silicon layer mentioned in this invention is E+17 to E+19 atoms / cm². 3 For example, it can be E+17 atoms / cm 3 E+18 atoms / cm 3 E+19 atoms / cm 3 Equal point values ​​or any range of values.

[0031] The doping concentration of N+ crystalline silicon layers is higher than that of N-type silicon substrates (E+16~E+17 atoms / cm²). 2 This forms a high-low junction with the substrate, improving the lateral transport rate of charge carriers and reducing the series resistance of the photovoltaic cell, while maintaining a lower doping concentration than phosphorus-doped polycrystalline silicon layers (E+19~E+21 atom / cm). 2 This facilitates the transport of charge carriers from the phosphorus-doped polycrystalline silicon layer with a higher doping concentration to the N+ crystalline silicon layer with a lower doping concentration, thereby accelerating the transport speed of charge carriers and increasing the open-circuit voltage of the photovoltaic cell.

[0032] In some specific embodiments, the doping concentration of the gate line region on the back surface of the N-type silicon substrate mentioned in this invention satisfies the following: N-type silicon substrate < P+ crystalline silicon layer < phosphorus-doped polycrystalline silicon layer.

[0033] In some specific embodiments, the doping concentration of the p+ crystalline silicon layer mentioned in this invention is E+20 to E+21 atoms / cm². 3 .

[0034] The doping concentration of P+ crystalline silicon layers is higher than that of N-type silicon substrates (E+16~E+17 atoms / cm). 2This forms a high-low junction with the substrate, improving the lateral transport rate of charge carriers and reducing the series resistance of the photovoltaic cell, while maintaining a lower doping concentration than phosphorus-doped polycrystalline silicon layers (E+21~E+22 atom / cm). 2 This facilitates the transport of charge carriers from the phosphorus-doped polycrystalline silicon layer with a higher doping concentration to the N+ crystalline silicon layer with a lower doping concentration, thereby accelerating the transport speed of charge carriers and increasing the open-circuit voltage of the photovoltaic cell.

[0035] In some specific embodiments, the thickness of the N+ crystalline silicon layer mentioned in this invention is 20~100nm, for example, it can be a point value such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm or any range of values, preferably 20~50nm.

[0036] In some specific embodiments, the thickness of the P+ crystalline silicon layer mentioned in this invention is 20~100nm, for example, it can be a point value such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm or any range of values, preferably 20~50nm.

[0037] Within the thickness range of the N+ crystalline silicon layer and P+ crystalline silicon layer protected by this invention, after the metal electrode penetrates the tunnel oxide layer, the N+ / P+ crystalline silicon layer can also cover the metal electrode, thereby playing a good interface passivation role and further improving the reliability of photovoltaic cells.

[0038] Furthermore, the thickness settings of the N+ and P+ crystalline silicon layers can, on the one hand, form good surface field passivation and selective contact, reducing interfacial recombination between the metal electrode and the silicon substrate, and on the other hand, avoid the extension of the transport path and the increase of recombination loss caused by excessive layer thickness. Appropriate thickness control can ensure that photogenerated carriers are transported to the substrate quickly and with low loss, significantly improving carrier collection efficiency.

[0039] In some specific embodiments, the positive surface of the N-type silicon substrate mentioned in this invention is textured.

[0040] The textured surface design of the front surface of the N-type silicon substrate can effectively reduce the reflection loss of sunlight and improve the light utilization efficiency.

[0041] In a specific embodiment, the present invention also provides a method for preparing a bifacial selective TOPCon battery, comprising the following steps: S1. Polish the N-type silicon substrate on both sides, and prepare a P+ crystalline silicon layer on the back side of the N-type silicon substrate by boron diffusion, with the doping concentration increasing in a gradient from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate; S2. A tunneling oxide layer and a P+ polycrystalline silicon layer are sequentially prepared on the surface of the P+ crystalline silicon layer; S3. Texturing the front side of the N-type silicon substrate, and preparing an N+ crystalline silicon layer with a doping concentration that gradually increases from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate by phosphorus diffusion on the front side of the N-type silicon substrate; S4. A tunneling oxide layer and an N+ polycrystalline silicon layer are sequentially prepared on the surface of the N+ crystalline silicon layer; S5. Remove the polysilicon layers in the non-metallized areas on the front and back sides, retain the polysilicon layers in the metallized areas, and prepare aluminum oxide layers and anti-reflection passivation layers on the front and back sides.

[0042] In some specific exemplary embodiments, the present invention more specifically provides a method for preparing a bifacial selective TOPCon cell, comprising the following steps: S1. An N-type silicon substrate is polished on both sides. A concentration gradient P+ crystalline silicon layer is prepared on the back side of the substrate by boron diffusion. The doping concentration of the p+ crystalline silicon layer on the side away from the substrate is higher than that on the side closer to the substrate. Acid etching is used to remove the borosilicate glass that has diffused to the front, edge, and back sides of the silicon wafer. S2. A tunneling oxide layer and a P+ polycrystalline silicon layer are prepared on the surface of the P+ crystalline silicon layer using a PECVD (Plasma-Enhanced Chemical Vapor Deposition) device. The borosilicate glass diffused around the front and edge of the silicon wafer is removed by acid etching. The polycrystalline silicon layer diffused around the front is removed by alkaline washing. The borosilicate glass layer on the back is removed by acid washing. S3. Texturing the front side of the silicon substrate and preparing N+ crystalline silicon with a concentration gradient by phosphorus diffusion on the front side of the substrate, wherein the doping concentration of the P+ crystalline silicon layer on the side away from the substrate is higher than the doping concentration on the side closer to the substrate, and acid etching is used to remove the phosphorosilicate glass that has diffused to the back, edge and front of the silicon wafer. S4. A tunneling oxide layer and an N+ polycrystalline silicon layer are prepared on the surface of the N+ crystalline silicon layer using a PECVD device. The phosphosilicate glass diffused around the back and edge of the silicon wafer is removed by acid etching. The polycrystalline silicon layer diffused around the back is removed by alkaline washing. The phosphosilicate glass layer on the front is removed by acid washing. S5. Remove the polycrystalline silicon layer in the non-metallized areas on the front and back sides by laser or chemical etching, while retaining the polycrystalline silicon layer in the metallized areas; deposit an aluminum oxide layer and an anti-reflection passivation layer on the front and back sides respectively; and fabricate grid electrodes on the front and back sides of the battery using screen printing equipment.

[0043] The specific steps of S1 are detailed below: 1) Substrate pretreatment: The N-type silicon substrate is polished on both sides to remove impurities and damaged layers from the substrate surface, providing a smooth and clean surface for subsequent boron diffusion.

[0044] 2) Preparation of gradient concentration boron diffusion layer: A P+ crystalline silicon layer with a doping concentration that gradually increases from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate is prepared by boron diffusion process on the back side of the N-type silicon substrate.

[0045] In this process, the concentration gradient (difference between surface and bulk doping concentration) and the doping thickness (junction depth) are achieved in synergy through four major categories of process conditions: temperature parameters, gas atmosphere, time period, and boron source supply. The specific control logic is as follows: temperature determines the slope of the concentration gradient, the boron source flow rate determines the peak value of surface doping, and the cyclic push junction technology avoids the boron-rich layer from destroying the concentration gradient; the doping thickness is mainly temperature-driven and is precisely controlled through cyclic push junction.

[0046] The specific process for gradient concentration boron diffusion (each parameter can be selected as a fixed value within the corresponding range) is as follows: Pre-deposition: The temperature is controlled at 800~860℃, the gas source ratio is BCl3:O2:N2≈1:(3~5):(20~40), the deposition time is 10~30min, and the chamber pressure is atmospheric pressure or 100~150mbar. Through this step, a highly doped surface layer is formed on the back side of the substrate. Oxygen-driven propulsion: The temperature is raised to 900~950℃, and a mixture of O2 and N2 gas is introduced (the boron source is disconnected) for 20~40 minutes. This step shapes the doping concentration gradient, achieving a distribution that gradually decreases from high surface doping to the interior of the substrate. Post-processing: First, anneal at 900℃ in N2 atmosphere for 5~10 min, then cool down at a rate of ≤5℃ / min, and finally soak in 1%~5% HF solution for 1~3 min to remove borosilicate glass (BSG) generated during diffusion, thus completing the preparation of P+ crystalline silicon layer.

[0047] Cyclic push-knot process: It adopts a cyclic mode of "short-time anaerobic diffusion + short-time aerobic inhibition" to achieve precise control of the knot depth under the condition of a similar total time (e.g., 10 cycles × 8 min = 80 min) and at the same time make the concentration gradient slope more stable.

[0048] In some specific embodiments, the present invention also provides an application of bifacial selective TOPCon cells in the fabrication of photovoltaic modules.

[0049] In some specific embodiments, the present invention also provides a photovoltaic module including the bifacial selective TOPCon cell.

[0050] Example 1 A bifacial selective TOPCon battery, such as Figure 1 As shown, it includes the following structure: The N-type silicon substrate 100 has a front and back structure. The front surface of the N-type silicon substrate is textured. The front and back sides are respectively provided with gate line regions and non-gate line regions. The N+ crystalline silicon layer is provided on the front side and the P+ crystalline silicon layer is provided on the back side of the N-type silicon substrate. An N+ crystalline silicon layer 110, a front tunneling oxide layer 120, an aluminum oxide passivation layer 170, and a silicon nitride antireflection layer 180 are disposed on the non-gateline area on the front side. An N+ crystalline silicon layer 110, a front tunneling oxide layer 120, a phosphorus-doped polycrystalline silicon layer 130, an aluminum oxide passivation layer 170, and a silicon nitride antireflection layer 180 are disposed on the front gate line region. A P+ crystalline silicon layer 140, a back tunneling oxide layer 150, and an aluminum oxide passivation layer + silicon nitride anti-reflection layer are disposed on the non-gateline area on the back side. A P+ crystalline silicon layer 140, a back-side tunneling oxide layer 150, a phosphorus-doped polycrystalline silicon layer 160, and an aluminum oxide passivation layer + silicon nitride anti-reflection layer are disposed on the back gate line region. Metal grid line electrode 200 is provided on the front side and metal grid line electrode 210 is provided on the back side.

[0051] Concentration of N+ crystalline silicon on the front side of the battery: E+17~E+19 atoms / cm 3 The N+ crystalline silicon layer has a concentration gradient, with the doping concentration on the side closer to the silicon substrate being lower than that on the side farther from the silicon substrate, but higher than that on the silicon substrate. The ratio of the concentration on the side closer to the N-type silicon substrate to that on the side farther from the silicon substrate is 1:50. The thickness of the N+ crystalline silicon layer is 40 nm. Concentration of p+ crystalline silicon on the back side: E+20~E+21 atoms / cm 3 The P+ crystalline silicon layer has a concentration gradient, with the doping concentration on the side closer to the silicon substrate being lower than that on the side farther from the silicon substrate; the ratio of the concentration on the side closer to the N-type silicon substrate to that on the side farther from the silicon substrate is 1:50; the thickness of the P+ crystalline silicon layer is 40 nm.

[0052] Example 2 A method for preparing a bifacial selective TOPCon cell according to Example 1 includes the following steps: S1. Double-sided polishing of the N-type silicon substrate removes impurities and damaged layers from the substrate surface, providing a smooth and clean surface for subsequent boron diffusion; A P+ crystalline silicon layer with a doping concentration that gradually increases from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate is prepared by boron diffusion process on the back side of an N-type silicon substrate. The specific process for gradient concentration boron diffusion (each parameter can be selected as a fixed value within the corresponding range) is as follows: Pre-deposition: The temperature is controlled at 830℃, the gas source ratio is BCl3:O2:N2≈1:4:30, the deposition time is 20min, the chamber pressure is atmospheric pressure, and a highly doped layer is formed on the back side of the substrate (oxygen-free diffusion for a short time). Oxygen-driven propulsion: The temperature is raised to 930℃, and a mixture of O2 and N2 gas is introduced (the boron source is disconnected) for 30 minutes to form a doping concentration gradient, achieving a distribution that gradually decreases from high surface doping to the interior of the substrate (short-term oxygen suppression). Post-processing: First, anneal at 900℃ in N2 atmosphere for 8 min, then cool down at a rate of ≤5℃ / min, and finally soak in 3% HF solution for 2 min to remove borosilicate glass (BSG) generated during diffusion, thus completing the preparation of the P+ crystalline silicon layer.

[0053] S2. A tunneling oxide layer and a P+ polycrystalline silicon layer are prepared on the surface of the P+ crystalline silicon layer using a PECVD device. The borosilicate glass diffused around the front and edge of the silicon wafer is removed by acid etching. The polycrystalline silicon layer diffused around the front is removed by alkaline washing. The borosilicate glass layer on the back is removed by acid washing.

[0054] S3. Texturing the front side of the silicon substrate and preparing N+ crystalline silicon with a concentration gradient by phosphorus diffusion on the front side of the substrate, wherein the doping concentration of the P+ crystalline silicon layer on the side away from the substrate is higher than the doping concentration on the side closer to the substrate, and acid etching is used to remove the phosphorosilicate glass that has diffused to the back, edge and front of the silicon wafer.

[0055] S4. A tunneling oxide layer and an N+ polycrystalline silicon layer are prepared on the surface of the N+ crystalline silicon layer using a PECVD device. The phosphosilicate glass diffused around the back and edge of the silicon wafer is removed by acid etching. The polycrystalline silicon layer diffused around the back is removed by alkaline washing. The phosphosilicate glass layer on the front is removed by acid washing.

[0056] S5. Remove the polycrystalline silicon layer in the non-metallized areas on the front and back sides by laser or chemical etching, while retaining the polycrystalline silicon layer in the metallized areas; deposit an aluminum oxide layer and an anti-reflection passivation layer on the front and back sides respectively; and fabricate grid electrodes on the front and back sides of the battery using screen printing equipment.

[0057] Example 3 A bifacial selective TOPCon cell differs from Example 1 in that the thicknesses of the N+ crystalline silicon layers are 20nm, 30nm, and 50nm, respectively; and the thicknesses of the P+ crystalline silicon layers are 20nm, 30nm, and 50nm.

[0058] When the thickness is greater than or equal to 20 nm, even if the metal electrode penetrates the tunnel oxide layer and comes into direct contact with the substrate, the P+ / N+ crystalline silicon layer set in the substrate can still cover the metal electrode, thereby providing a good interface passivation effect for the metal electrode set in the substrate and reducing the interface recombination between the metal electrode and the substrate.

[0059] Example 4 A bifacial selective TOPCon cell differs from Example 1 in that: the N+ / P+ thickness is consistent, and the doping concentration on the side closer to the substrate is changed; the doping concentration ratio on the side farther from the substrate is 1:1, 1:10, and 1:100.

[0060] For cells of the same thickness, a concentration gradient is provided, which allows charge carriers transported through the metal electrodes to be successfully transported into the substrate, thereby improving the charge carrier transport efficiency.

[0061] Comparative Example 1 A TOPCon cell with a selectively passivated contact structure, as disclosed in CN120091648A, comprises: a silicon wafer 1; a first tunneling oxide layer 2; a first boron-doped polycrystalline silicon 3; a second boron-doped polycrystalline silicon 4; a second tunneling oxide layer 5; a phosphorus-doped polycrystalline silicon 6; a back alumina film 7; a front alumina film 8; a back silicon nitride film 9; a front silicon nitride film 10; a back electrode 11; and a front electrode 12.

[0062] Result detection Electrical performance tests were conducted on the batteries of the above embodiments and Comparative Example 1 to obtain parameters such as short-circuit current (Isc), open-circuit voltage (Voc), fill factor (FF), and energy conversion efficiency (Eta), as shown in Table 1 below.

[0063] The battery's short-circuit current (Isc), open-circuit voltage (Voc), fill factor (FF), and photoelectric conversion efficiency (Eta) were measured using an AAA-grade solar simulator under standard test conditions (STC): irradiance 1000 W / m². 2 AM1.5G spectrum, battery temperature 25℃. The test followed GB / T6495.1-1996, and the measured data were corrected for temperature and irradiance to the standard test conditions before calculating each parameter.

[0064] Table 1 shows the electrical performance test results of the embodiments and comparative examples.

[0065] As shown in Table 1, compared with the bifacial selective TOPCon cell of the comparative example, the efficiency of the bifacial selective cell with concentration gradient prepared in the above embodiments of the present invention is further improved. Specifically, the deposition of a tunneling silicon oxide layer on the non-gate region away from the silicon substrate enhances the electron gathering ability of the non-metallized region, reduces recombination in the non-metallized region, strengthens electron gathering ability, and increases minority carrier lifetime, resulting in improved Voc and Isc. Simultaneously, the doping concentration difference allows charge carriers transported through the metal electrode to be smoothly transported to the substrate, thereby improving carrier transport efficiency, reducing series resistance and lateral transport loss, and significantly improving FF.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A bifacial selective TOPCon cell, comprising an N-type silicon substrate and metal electrodes disposed on the front and back surfaces of the N-type silicon substrate, characterized in that, The N-type silicon substrate has an N+ crystalline silicon layer on its front surface and a P+ crystalline silicon layer on its back surface. The doping concentration of the N+ and P+ crystalline silicon layers increases gradually from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate.

2. The bifacial selective TOPCon cell according to claim 1, characterized in that The N+ crystalline silicon layer has a doping concentration of E+17 to E+19 atoms / cm3 3 .

3. The bifacial selective TOPCon cell according to claim 2, characterized in that The doping concentration ratio of the N+ crystalline silicon layer on the side closer to the N-type silicon substrate to the side farther from the silicon substrate is 1:100 to 1:

10.

4. The bifacial selective TOPCon cell according to claim 1, characterized in that The P+crystalline silicon layer has a doping concentration of E+20 to E+21 atoms / cm3 3 .

5. The bifacial selective TOPCon cell according to claim 4, characterized in that The doping concentration ratio of the P+ crystalline silicon layer on the side closer to the N-type silicon substrate to the side farther from the silicon substrate is 1:100 to 1:

10.

6. The bifacial selective TOPCon cell according to any one of claims 1 to 5, wherein The thickness of the N+ crystalline silicon layer is 20~100 nm, preferably 20-50 nm.

7. The bifacial selective TOPCon cell according to claim 6, wherein The thickness of the P+ crystalline silicon layer is 20~100 nm, preferably 20-50 nm.

8. A method for preparing the bifacially selective TOPCon cell according to any one of claims 1 to 7, characterized in that Includes the following steps: S1. Polish the N-type silicon substrate on both sides, and prepare a P+ crystalline silicon layer on the back side of the N-type silicon substrate by boron diffusion, with the doping concentration increasing in a gradient from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate; S2. A tunneling oxide layer and a P+ polycrystalline silicon layer are sequentially prepared on the surface of the P+ crystalline silicon layer; S3. Texturing the front side of the N-type silicon substrate, and preparing an N+ crystalline silicon layer with a doping concentration that gradually increases from the side closer to the N-type silicon substrate to the side farther away from the silicon substrate by phosphorus diffusion on the front side of the N-type silicon substrate; S4. A tunneling oxide layer and an N+ polycrystalline silicon layer are sequentially prepared on the surface of the N+ crystalline silicon layer; S5. Remove the polysilicon layers in the non-metallized areas on the front and back sides, retain the polysilicon layers in the metallized areas, and prepare aluminum oxide layers and anti-reflection passivation layers on the front and back sides.

9. The application of the bifacial selective TOPCon cell according to any one of claims 1 to 7 in the preparation of photovoltaic modules.

10. A photovoltaic module, characterized in that, Includes the bifacial selective TOPCon battery as described in any one of claims 1 to 7.

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