Light emitting device based on nano-patterned substrate and optical interconnection system

Abstract

The application discloses a light-emitting device based on a nano-pattern substrate and an optical interconnection system, and relates to the technical field of semiconductor optoelectronic device manufacturing. The light-emitting device comprises a nano-pattern substrate and an active layer located on the nano-pattern substrate. The surface of the nano-pattern substrate has a nano-scale pattern structure for converting an epitaxial growth interface from a continuous interface into a discrete interface with lateral elastic relaxation capability, so as to regulate in-plane stress boundary conditions in the epitaxial growth process. The emission wavelength of the active layer is located in a preset long-wavelength waveband range. The nano-scale pattern structure releases the in-plane stress of the active layer through the lateral elastic relaxation capability, so as to expand the stable growth temperature range of the active layer. The application can solve the problems of active layer crystal quality degradation and high injection efficiency sudden drop of a long-wavelength InGaN-based light-emitting device in related technologies, can expand the quantum well growth temperature window and improve the crystal quality, and can make the device maintain stable modulation bandwidth and light-emitting efficiency under high temperature and high current density.

Description

Technical Field

[0001] This application relates to the field of semiconductor optoelectronic device manufacturing technology, and in particular to a light-emitting device and optical interconnect system based on a nanopatterned substrate. Background Technology

[0002] In the fabrication of InGaN-based light-emitting devices in the long wavelength range of visible light (emission wavelength 560 nm to 650 nm), a high proportion of In composition needs to be incorporated into the InGaN active layer to obtain the target emission wavelength. However, the introduction of high In composition leads to increased lattice mismatch and accumulation of residual compressive stress during epitaxial growth, which in turn induces crystallographic defects such as increased dislocation density, non-uniform spatial distribution of In composition, and phase separation, resulting in reduced quantum efficiency and insufficient stability of emission wavelength within the device.

[0003] Related technologies employ patterned sapphire substrates as epitaxial growth substrates to improve the crystal quality of epitaxial layers and enhance light extraction efficiency. However, this method is prone to localized stress concentrations at the top or sidewalls of the pattern, leading to epitaxial layer warping and uneven distribution of step flow, which adversely affects the crystal quality of long-wavelength InGaN quantum wells. Furthermore, to suppress the desorption and thermal decomposition of In components under high In composition conditions, long-wavelength InGaN quantum wells typically need to be formed at relatively low process temperatures. Low-temperature growth conditions limit the surface migration ability of adsorbed atoms, resulting in increased quantum well interface roughness and higher density of non-radiative recombination centers, further restricting the device's luminous efficiency and high-temperature operational stability.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This application provides a light-emitting device and optical interconnect system based on a nano-patterned substrate. By controlling the epitaxial stress boundary conditions of the nano-patterned substrate, the stable growth temperature window of the long-wavelength InGaN quantum well can be extended and the crystal quality of the active region can be improved, thereby enabling the device to maintain stable electro-optic modulation bandwidth and luminous efficiency under high temperature and high current density conditions.

[0006] To solve the above-mentioned technical problems, this application provides the following technical solution: This application provides a light-emitting device based on a nanopatterned substrate, including a nanopatterned substrate and an active layer located on the nanopatterned substrate; The surface of the nanopatterned substrate has a nanoscale patterned structure that transforms the epitaxial growth interface from a continuous interface to a discrete interface with lateral elastic relaxation capability, which is used to control the in-plane stress boundary conditions during the epitaxial growth process. The emission wavelength of the active layer is within a preset long wavelength band. The nanoscale patterned structure releases the in-plane stress of the active layer through the lateral elastic relaxation capability, thereby expanding the stable growth temperature range of the active layer. The geometric parameters of the nanoscale patterned structure are configured such that, during epitaxial growth, the epitaxial layer forms a lateral elastic relaxation region between adjacent patterned units to achieve the control of the stress boundary conditions.

[0007] Another aspect of this application provides an optical interconnect system, including a three-dimensional integrated packaging structure and an optical interconnect emitting unit disposed inside the three-dimensional integrated packaging structure; The optical interconnect emitting unit adopts a red Micro-LED fabricated based on a nano-patterned substrate as described above; The red Micro-LED maintains its electro-optic modulation capability under the stress boundary conditions of the nanoscale patterned structure, with a working environment where the temperature inside the three-dimensional encapsulation structure reaches or exceeds 400K and the current density is 20 A / cm², so as to realize optical interconnect communication without relying on active thermoelectric cooling or liquid cooling devices.

[0008] The advantages of the technical solution provided in this application are that, due to the nanoscale patterned substrate surface having a nanoscale patterned structure that transforms the epitaxial growth interface from a continuous interface to a discrete interface with lateral elastic relaxation capability, during the epitaxial growth stage of light-emitting device fabrication, the nanoscale patterned structure discretizes the originally continuous growth interface into multiple independent growth units. Before lateral merging, the sidewalls of each growth unit are exposed to the gas phase environment and are not rigidly constrained by adjacent units, thus gaining the ability to undergo free elastic deformation along the lateral direction. When the epitaxial layer generates in-plane compressive stress due to lattice mismatch, this lateral elastic relaxation region provides each discrete growth unit with geometrical degrees of freedom for stress release, allowing the stress to be partially released through lateral elastic deformation before the growth units merge, rather than accumulating and being transferred to the subsequently grown active layer. Compared to the way stress is transferred and continuously accumulated along a large in-plane range under continuous interface conditions, this discrete interface... The combination of lateral elastic relaxation regions alters the stress state of the epitaxial layer at the mechanical boundary condition level, significantly reducing the in-plane residual compressive stress level experienced by the active layer during growth. Effective stress release improves the thermodynamic stability of the InGaN active layer during growth. While maintaining the same In composition to sustain the target emission wavelength, the stable growth temperature range of the active layer is extended compared to using planar substrates or micrometer-scale patterned substrates. This allows for the formation of an active layer with superior crystal quality at higher process temperatures than conventional processes. The improved crystal quality directly manifests as a reduction in the density of non-radiative recombination centers and an increase in the spatial uniformity of the In composition in the active layer. This leads to an improvement in the internal quantum efficiency of the device under electrical injection conditions, a corresponding increase in electro-optical conversion efficiency, a reduction in the standard deviation of emission wavelength between different device units on the same wafer, and enhanced luminous brightness of the device under the same injection conditions. Furthermore, this application also provides a corresponding optical interconnect system for light-emitting devices based on nanopatterned substrates, further enhancing the practicality of these devices. This optical interconnect system offers corresponding advantages.

[0009] The technical features mentioned above, those to be mentioned below, and those shown individually in the accompanying drawings can be arbitrarily combined, as long as the combined technical features are not contradictory. All feasible combinations of features are the technical content explicitly described in this application. Any one of the multiple sub-features contained in the same statement can be applied independently, without necessarily being applied together with other sub-features.

[0010] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of the hardware composition applicable to the light-emitting device based on a nano-patterned substrate provided in this application; Figure 2 A schematic diagram comparing the epitaxial growth boundary conditions of the nanopatterned substrate (NPSS) and the traditional patterned sapphire substrate (PSS) provided in this application; Figure 3 A schematic diagram of the Micro-LED array device based on a nano-patterned substrate provided in this application; Figure 4 A schematic diagram of the optical interconnect system provided in this application; Figure 5 A schematic diagram of the high-temperature three-dimensional integrated packaging environment provided in this application; Figure 6 A schematic diagram of the structure of a red Micro-LED based on a nano-patterned substrate provided in this application; Figure 7 A schematic diagram illustrating the luminescent performance of the red Micro-LED based on a nano-patterned substrate provided in this application; Figure 8 A schematic diagram illustrating the selection of optical interconnect technology routes in the high-temperature three-dimensional integrated system provided in this application; Figure 9 A flowchart illustrating the optical interconnect technology route selection method provided in this application. Detailed Implementation

[0013] To enable those skilled in the art to better understand the technical solutions of this application, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The terms "first," "second," "third," "fourth," etc., used in the specification and the aforementioned drawings are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. The term "exemplary" means "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments.

[0014] To obtain InGaN-based light-emitting devices with emission wavelengths in the 560nm to 650nm range, a material system with a significantly higher In content than that used in blue or green light-emitting devices must be incorporated into the InGaN quantum well. The lattice constant mismatch between InN and GaN causes the high-In-content InGaN epitaxial layer to experience significant biaxial compressive stress during heteroepitaxial growth and subsequent cooling. This residual stress not only directly leads to dislocation multiplication and stacking fault formation in the epitaxial layer but also induces a non-uniform spatial distribution of In content, i.e., phase separation, causing the actual emission wavelength to deviate from the design value and broadening the emission spectrum. The stress-induced crystallographic defects act as non-radiative recombination centers, significantly reducing the carrier radiative recombination probability, manifested as a sharp decrease in internal quantum efficiency with increasing In content.

[0015] To alleviate stress accumulation during epitaxial growth, patterned sapphire substrate technology is employed. This type of substrate utilizes periodic micron-scale protrusions on the sapphire surface, leveraging the mirror force provided by the pattern sidewalls and the lateral overgrowth mechanism of the epitaxial layer to release some residual stress. However, traditional micron-scale patterned sapphire substrates typically have large pattern heights. The pattern period and duty cycle design mean that the epitaxial layer remains primarily under continuous or quasi-continuous mechanical boundary conditions during merging, limiting the stress release effect to the constraints of the pattern geometry. In the top region and sidewall transition area of ​​the pattern, the step flow distribution at the epitaxial growth front is prone to local disturbances, forming stress concentration areas. This leads to increased warpage of the epitaxial layer and the upward extension of penetrating dislocations into the active region, adversely affecting the crystal quality and luminescence uniformity of long-wavelength InGaN quantum wells.

[0016] On the other hand, the epitaxial growth process window for long-wavelength InGaN quantum wells is strictly limited by the thermodynamic stability of the In composition. Due to the low In-N bond binding energy, high-In-content InGaN materials are prone to In composition precipitation and thermal decomposition at higher growth temperatures. To maintain the target In composition content in the quantum well, traditional epitaxial processes are forced to control the quantum well growth temperature within a relatively low range. Under low-temperature growth conditions, the migration rate of the reaction precursor on the growth surface is limited, and atoms cannot fully reach the lowest energy positions of the lattice, resulting in a decrease in atomic-level flatness and an increase in interface state density at the quantum well interface, and the formation of high-density point defects and impurity complexes inside the well layer. The crystal quality degradation and the increase in non-radiative recombination centers introduced by the aforementioned low-temperature growth are particularly prominent under high injection current density conditions, further exacerbating the problem of a sharp drop in efficiency of long-wavelength InGaN-based light-emitting devices.

[0017] As can be seen from the above, the related technologies have significant shortcomings in terms of stress control capability and crystal quality optimization, making it difficult to simultaneously meet the stress release and high-quality, high-temperature growth requirements of high-In composition quantum wells. To address this issue, this application provides a light-emitting device that can effectively engineer stress boundary conditions during epitaxial growth, extend the stable growth temperature window of long-wavelength InGaN quantum wells, and improve the luminous efficiency and performance stability of the device under high injection conditions. The electro-optical conversion efficiency (WPE) of this light-emitting device is at least 15% higher than that of conventional PSS substrate devices of the same wavelength, and its internal quantum efficiency is improved by 15% to 40% compared to devices of the same wavelength grown using conventional PSS substrates. Due to the control of epitaxial stress boundary conditions by the nanopatterned substrate, the well layer growth temperature is increased by 10 to 50°C compared to conventional PSS substrates, thereby improving the crystal quality and In composition uniformity of the well layer; the emission wavelength standard deviation of the light-emitting device is reduced by 10% to 30%, and the brightness is increased by more than 20% under the same injection conditions. The various non-limiting embodiments of this application are described in detail below with reference to the accompanying drawings and specific embodiments. Please refer to [link to relevant documentation] first. Figure 1 The light-emitting device based on a nanopatterned substrate provided in this application may include the following: Light-emitting devices based on nanopatterned substrates include a nanopatterned substrate and an active layer located on the nanopatterned substrate. The surface of the nanopatterned substrate possesses a nanoscale patterned structure that transforms the epitaxial growth interface from a continuous interface to a discrete interface with lateral elastic relaxation capability, used to control the in-plane stress boundary conditions during epitaxial growth. The geometric parameters of the nanoscale patterned structure are configured such that, during epitaxial growth, the epitaxial layer forms lateral elastic relaxation regions between adjacent patterned units to achieve control of stress boundary conditions. The emission wavelength of the active layer is located within a preset long wavelength band. The nanoscale patterned structure releases the in-plane stress of the active layer through lateral elastic relaxation capability, thereby extending the stable growth temperature range of the active layer. Nanopatterned substrates refer to substrates with nanoscale geometric patterns formed on their surfaces through micro- and nanoscale fabrication processes such as photolithography and etching. These substrates serve as the basis for epitaxial growth, and their surface morphology directly affects the nucleation and growth behavior of the epitaxial layer. The active layer refers to the functional layer in a light-emitting device that performs electro-optic conversion; it is typically composed of a multi-quantum-well structure, where charge carriers undergo radiative recombination and emit photons. A continuous interface refers to a continuous and uninterrupted epitaxial growth interface on a traditional planar substrate or a micrometer-scale patterned substrate, through which stress is continuously transmitted. A discrete interface refers to an epitaxial growth interface divided into multiple separate growth units by a nanoscale patterned structure, with physical intervals between the units, allowing the epitaxial layer to undergo lateral elastic deformation. Lateral elastic relaxation capability refers to the ability of the epitaxial layer to release stress through elastic deformation in a direction parallel to the substrate surface, distinct from longitudinal (perpendicular to the substrate surface) stress relaxation. In-plane stress boundary conditions refer to the stress state and distribution characteristics of the epitaxial layer in a plane parallel to the substrate surface, including the magnitude, direction, and uniformity of the stress. Geometric parameters refer to the quantitative geometric characteristics of nanoscale patterned structures, such as height, spacing, period, and duty cycle. Lateral elastic relaxation regions refer to stress-relieving areas in the epitaxial layer formed by the lateral elastic relaxation capability of the nanoscale patterned structure, typically located above the gaps between adjacent patterned units.

[0018] In this embodiment, the substrate of the light-emitting device can be any substrate with nanoscale patterns, such as sapphire, SiC, or Si substrates. That is, a nanoscale pattern structure is formed on the surface of any substrate. The shape of the nanoscale pattern can be one or more combinations of conical, frustum-shaped, cylindrical, or hexagonal pyramidal shapes to constitute the nanoscale patterned substrate. The geometric parameters of the nanoscale pattern structure must satisfy the condition that transforms the epitaxial growth interface from a traditional continuous stress transmission path into discrete growth units with lateral elastic relaxation capability, thereby changing the in-plane stress boundary conditions of the epitaxial layer. Figure 2As shown in the diagram, a comparison of epitaxial growth boundary conditions between a nanopatterned substrate (NPSS) and a conventional patterned sapphire substrate (PSS) illustrates how the nanopatterned structure transforms the epitaxial growth interface from a continuous interface into discrete growth units with lateral elastic relaxation capabilities, thereby controlling the in-plane stress boundary conditions during epitaxial growth. An active layer is also deployed on this nanopatterned substrate. The emission wavelength of the active layer is within a preset long-wavelength band, which is a pre-defined range of long-wavelength visible light, for example, 560–650 nm. Correspondingly, the emission wavelength of the active layer is within the 560–650 nm range, which falls within the long-wavelength visible light band. Based on the control of epitaxial stress boundary conditions by the nanopatterned substrate, the active layer achieves a larger stable operating range. The well layer growth temperature can be increased by 10–50 °C compared to the conventional PSS substrate. This expanded stable growth temperature range allows the active layer to grow at higher temperatures than conventional processes, thereby improving crystal quality and compositional uniformity.

[0019] In the technical solution provided in this application embodiment, since the surface of the nano-patterned substrate has a nanoscale patterned structure that transforms the epitaxial growth interface from a continuous interface to a discrete interface with lateral elastic relaxation capability, during the epitaxial growth stage of light-emitting device fabrication, the nanoscale patterned structure discretizes the originally continuous growth interface into multiple independent growth units. Before lateral merging, the sidewalls of each growth unit are exposed to the gas phase environment and are not rigidly constrained by adjacent units, thus gaining the ability to undergo free elastic deformation along the lateral direction. When the epitaxial layer generates in-plane compressive stress due to lattice mismatch, this lateral elastic relaxation region provides each discrete growth unit with geometrical degrees of freedom for stress release, allowing the stress to be partially released through lateral elastic deformation before the growth units merge, rather than accumulating and being transferred to the subsequently grown active layer. Compared to the way stress is transferred and continuously accumulated along the in-plane under continuous interface conditions, this discrete interface and... The combination of lateral elastic relaxation regions alters the stress state of the epitaxial layer at the mechanical boundary condition level, significantly reducing the in-plane residual compressive stress level experienced by the active layer during growth. Effective stress release improves the thermodynamic stability of the InGaN active layer during growth. While maintaining the same In composition to preserve the target emission wavelength, the stable growth temperature range of the active layer is extended compared to using planar substrates or micrometer-scale patterned substrates. This allows for the formation of an active layer with superior crystal quality at higher process temperatures than conventional processes. The improved crystal quality directly manifests as a reduction in the density of non-radiative recombination centers and an increase in the spatial uniformity of the In composition in the active layer. This leads to an improvement in the internal quantum efficiency of the device under electrical injection conditions, a corresponding increase in electro-optical conversion efficiency, a reduction in the standard deviation of emission wavelength between different device units on the same wafer, and enhanced luminous intensity of the device under the same injection conditions.

[0020] Based on the above embodiments, considering that improper geometric configuration of the nanoscale patterned structure may lead to the following problems: If the height is too large, longitudinal growth of the epitaxial layer is difficult, and lateral relaxation capability is insufficient; if the spacing is too small, the lateral relaxation space is limited, and stress release is insufficient; if the spacing is too large, crystal quality is prone to decrease when the epitaxial layer grows above the gap; if the duty cycle is too high, the stress release effect is weakened, and if the duty cycle is too low, epitaxial support is insufficient. Based on the above, this embodiment further defines the geometric parameters of the nanoscale patterned structure, which may include the following: The height, spacing, period, and duty cycle of the nanoscale pattern structure are configured as follows: the height of the nanoscale pattern structure does not exceed 2 micrometers, the spacing is 0.01 to 1 micrometer, the period is 0.01 to 1 micrometer, and the duty cycle is 30% to 70%.

[0021] In this context, height refers to the dimension of the nanoscale patterned structure in the direction perpendicular to the substrate surface, i.e., the distance from the bottom to the top of the pattern. Pattern spacing refers to the minimum horizontal distance between two adjacent nanoscale patterned structures. Pattern period refers to the horizontal distance between the center points of two adjacent nanoscale patterned structures, which is equal to the sum of the pattern width and the pattern spacing. Duty cycle refers to the ratio of the area occupied by the pattern to the total area of ​​the nanoscale patterned structure, reflecting the density of the pattern.

[0022] In this embodiment, the height of the nanoscale patterned structure of the light-emitting device is set to no more than 2 micrometers. This limitation ensures that the patterned structure does not protrude excessively, which would make longitudinal growth of the epitaxial layer difficult. The configuration of pattern spacing of 0.01 to 1 micrometer and pattern period of 0.01 to 1 micrometer ensures that the gap between adjacent patterned units is within a suitable range, allowing for lateral elastic relaxation while avoiding crystal quality degradation caused by excessive gaps. The pattern duty cycle is 30% to 70%, ensuring the rationality of the pattern distribution and balancing stress release and epitaxial support area. This ensures that the nanoscale patterned structure is within the nanoscale range. While ensuring the growthability of the epitaxial layer, it also allows the epitaxial layer to form an effective lateral elastic relaxation region between adjacent patterned units, achieving full release of in-plane stress. This expands the stable growth temperature range of the active layer and improves crystal quality and light-emitting performance.

[0023] Based on the above embodiments, when the height of the nanoscale patterned structure is in the range of 1 to 2 micrometers, although it is still at the nanoscale, the lateral elastic relaxation capability is relatively limited, and the stress release effect is not as good as that of patterned structures with smaller heights. For long-wavelength InGaN active layers with high indium content, stronger lateral stress relaxation capability is required to fully release the compressive stress caused by lattice mismatch. Based on this, this embodiment further limits the height of the nanoscale patterned structure to no more than 1 micrometer to enhance the lateral stress relaxation capability during epitaxial growth. Lateral stress relaxation capability refers to the ability of the nanoscale patterned structure to allow the epitaxial layer to undergo lateral elastic deformation to release stress, which is directly related to the pattern height. The smaller the pattern height, the more significant the lateral elastic relaxation effect, thereby more effectively expanding the stable growth temperature range of the active layer and further improving crystal quality and luminescence efficiency.

[0024] Based on the above embodiments, if the height and duty cycle are not properly combined, the stress relief channels may not be continuous or unevenly distributed, resulting in uneven stress distribution within the wafer scale and affecting device consistency. Therefore, this embodiment further limits the height of the nanoscale pattern structure to 800 nanometers ± fluctuation value, and the pattern duty cycle to between 45% and 65%, so as to form a laterally continuous stress relief channel in the epitaxial layer.

[0025] The 800 nm ± fluctuation value refers to the target height of the nanoscale patterned structure being 800 nm, allowing for a certain range of process fluctuations, typically ±10% or ±20%. Laterally connected stress relief channels refer to continuously distributed channel regions within the epitaxial layer that allow stress to be transmitted and released laterally, formed by the periodic arrangement of nanoscale patterned structures.

[0026] The 800 nm height in this embodiment is within the preferred range for the nanoscale, providing sufficient lateral elastic relaxation capability while ensuring the growth quality of the epitaxial layer. The 45%–65% duty cycle ensures uniform pattern distribution, resulting in uniform distribution of stress relief channels across the wafer scale. Through the synergistic effect of the 800 nm height and the 45%–65% duty cycle, laterally continuous stress relief channels are formed in the epitaxial layer. These channels allow for uniform release of in-plane stress across the wafer scale, avoiding localized stress concentration and thus improving the uniformity of the epitaxial layer and the consistency of the device.

[0027] Furthermore, considering that sharp edges or excessively small radii of curvature exist at the top or bottom of the nanoscale patterned structure, stress concentration is likely to occur at these locations during epitaxial growth, leading to dislocation multiplication and defect formation, which affects the crystal quality and luminescence performance of the active layer. Based on this, this application further defines the curvature transition characteristics of the nanoscale patterned structure: the connection regions between the top and bottom of the nanoscale patterned structure are both continuous curvature transition structures, with the top curvature radius greater than or equal to 50 nm and the bottom transition curvature radius greater than or equal to ≥20 nm.

[0028] In this context, "top" refers to the highest point of the nanoscale pattern structure in the vertical direction, typically the vertex or top surface of the pattern. "Valley connection region" refers to the lowest point between two adjacent nanoscale pattern structures, i.e., the bottom region of the gap between the patterns. A continuous curvature transition structure refers to a pattern contour that exhibits a smooth curve transition at turning points, without sharp edges or abrupt changes. The radius of curvature refers to the radius of the curvature circle of the contour curve at a given point, reflecting the degree of curvature of the curve. The larger the radius of curvature, the smoother the curve.

[0029] In this embodiment, the top and valley connection regions of the nanoscale patterned structure are designed with continuous curvature transition structures. This continuous curvature transition structure avoids the sharp edges common in traditional patterned structures, reducing local stress concentrations and step-like defects during epitaxial growth. Furthermore, the top curvature radius is quantified to ≥50nm and the valley transition curvature radius to ≥20nm, ensuring smooth growth of the epitaxial layer at the top and sidewalls of the pattern and eliminating local stress concentration points. This structure reduces the defect density during epitaxial growth and improves the crystal quality and luminescence efficiency of the active layer.

[0030] Based on the above embodiments, if the cross-sectional shape of the nanoscale patterned structure is not properly designed, such as having sharp edges or an excessive aspect ratio, it may lead to difficulties in epitaxial growth and a decrease in crystal quality. This embodiment further defines the nanoscale patterned structure as a periodic nanopattern formed on the surface of the substrate or the template layer, with its cross-section having an arched, ridged, or wavy profile, and adjacent patterns are connected by a valley bottom transition area.

[0031] In this context, "substrate surface" refers to the upper surface of the original substrate used for epitaxial growth, typically made of materials such as sapphire, silicon carbide, or silicon. "Template layer surface" refers to the surface on the original substrate after a buffer or template material has been grown; this template layer improves the growth quality of subsequent epitaxial layers. "Periodic nanopattern" refers to a nanoscale pattern structure arranged in a repetitive pattern according to a certain period. "Arch" refers to a shape with a rounded, convex cross-section. "Arch-top ridge" refers to a cross-section with a rounded top and sloping sides, resembling a ridge. "Wave" refers to a cross-section with a periodically undulating, wave-like shape. "Valley connection region" refers to the bottom region where adjacent nanopatterns are connected by a smooth curve.

[0032] In this embodiment, the cross-sectional shape of the nanoscale pattern structure ensures the smoothness of the pattern outline. By cooperating with the continuous curvature transition structure, the epitaxial growth interface is further optimized, providing an optimized growth surface morphology for the epitaxial layer. This morphology is conducive to the lateral growth and merging of the epitaxial layer, reduces defect formation, and improves crystal quality and luminescence performance.

[0033] Based on the above embodiments, this embodiment further specifies that the light-emitting device is a Micro-LED. The Micro-LED includes, from bottom to top, a nano-patterned substrate, an n-type GaN template layer, an active layer, a p-type AlGaN electron blocking layer, and a p-type GaN layer. The active layer is an InGaN / GaN multi-quantum-well structure. During the growth process of the InGaN well layer of the active layer, the molar ratio of group V source to group III source and the carrier gas ratio are adjusted to emit light signals with wavelengths in the range of 560 to 650 nm. The Micro-LED is suitable for a current density of 20 A / cm² and maintains an electro-optic modulation bandwidth of not less than 100 MHz within the operating temperature range of 300 to 480 K.

[0034] Micro-LED refers to miniature light-emitting diodes, typically those with a chip size of less than 100 micrometers, suitable for applications such as high-resolution displays and high-speed optical communications. An n-type GaN template layer refers to an n-type gallium nitride layer doped with donor impurities (usually silicon), serving as a support layer for both the electron injection layer and the active layer. A p-type AlGaN electron blocking layer refers to a p-type aluminum gallium nitride layer doped with acceptor impurities (usually magnesium), utilizing its wide bandgap to block electron leakage from the active layer to the p-type region. A p-type GaN layer refers to a p-type gallium nitride layer doped with acceptor impurities, serving as a hole injection layer and an ohmic contact layer. An InGaN / GaN multi-quantum-well structure refers to an active region structure composed of alternating stacks of InGaN well layers and GaN barrier layers, utilizing quantum confinement effects to improve radiative recombination efficiency. A Group V source refers to a Group V element source used in MOCVD growth, typically ammonia (NH3), providing the nitrogen source. Group III source refers to the source of Group III elements in MOCVD growth, typically trimethylgallium (TMGa) or trimethylindium (TMIn), providing gallium or indium sources. Molar ratio refers to the ratio of the molar flow rates of Group V sources to those of Group III sources, affecting crystal quality and compositional incorporation. Carrier gas ratio refers to the proportion of carrier gas (usually hydrogen or nitrogen) in the total gas flow rate, affecting boundary layer thickness and reactant transport. Electro-optic modulation bandwidth refers to the speed at which a light-emitting device responds to an electrical signal, defined as the frequency at which the modulation depth decreases to 50% of the DC value or -3 dB, reflecting the device's high-speed response capability.

[0035] In this embodiment, by adjusting the molar ratio of group V to group III sources and the carrier gas ratio, the active layer of the Micro-LED can maintain an emission wavelength of 560–650 nm at a higher growth temperature within the extended temperature window provided by the nanopatterned substrate, while simultaneously improving crystal quality. The nanopatterned substrate, through stress boundary condition modulation, improves the strain distribution and carrier injection uniformity of the active layer, reducing non-radiative recombination losses. This improvement enables the Micro-LED to maintain an electro-optic modulation bandwidth of no less than 100 MHz even under high current densities of 20 A / cm² and high temperatures of 300–480 K, meeting the requirements of high-temperature, high-speed optical interconnect applications.

[0036] Based on the above embodiments, this application also provides a method for fabricating a light-emitting device based on a nanopatterned substrate, which may include the following: A substrate with a nanopattern structure is provided, which is used to modulate stress boundary conditions. An n-type GaN template layer is grown on the substrate, followed by a long-wavelength active layer. Stress boundary condition modulation improves the strain distribution and carrier injection uniformity of the active layer. Finally, a p-type layer is grown to form a complete device structure. The device reduces nonradiative recombination loss and current congestion under high current density through stress boundary condition modulation.

[0037] In this embodiment, a sapphire substrate is first provided, although a SiC or Si substrate can also be used. A periodically arranged nanoscale patterned structure is formed on the surface of the sapphire substrate using nanoimprint lithography combined with inductively coupled plasma dry etching to constitute a nanopatterned substrate (NPSS). This patterned structure transforms the originally planar epitaxial growth interface into a discrete interface with lateral elastic relaxation capability. Each patterned protrusion unit and the recessed regions between them constitute multiple independent discrete growth initiation sites. During subsequent GaN epitaxial growth using metal-organic chemical vapor deposition, the initial nucleation stage preferentially occurs in the patterned recessed regions and the lower part of the patterned sidewalls, rather than directly forming a continuous two-dimensional film. As growth progresses, the discrete growth units gradually grow and eventually merge laterally. However, before and during merging, the sidewalls of each growth unit are exposed to the vapor environment and are not rigidly constrained by adjacent units, thus possessing the ability to undergo lateral free elastic deformation. This lateral elastic relaxation mechanism fundamentally changes the in-plane stress boundary conditions of the epitaxial layer, allowing the biaxial compressive stress that originally accumulated inside the epitaxial layer under continuous interface conditions to be partially released before merging. Subsequently, an n-type GaN template layer was grown on a nanopatterned substrate using metal-organic chemical vapor deposition (MOCVD). Because the nanopatterned substrate modulates the stress state of the epitaxial layer from the early stages of growth, the GaN template layer achieves more uniform stress release during growth, reducing residual compressive stress in the epitaxial layer and minimizing wafer warpage. This provides a more stable epitaxial foundation for the subsequent growth of the active layer. After forming the n-type GaN template layer, an InGaN / GaN multi-quantum-well active layer was grown on top. Due to the continuous modulation of the epitaxial stress boundary conditions by the nanopatterned substrate, the in-plane stress of the InGaN multi-quantum-well was effectively alleviated during growth, allowing the quantum wells to maintain thermodynamic stability even at higher growth temperatures. While maintaining the same In composition, compared to epitaxial processes using traditional patterned sapphire substrates, the quantum well growth temperature can be increased by 10°C to 50°C, thus expanding the stable growth temperature range. This effectively improves the crystal quality, interface flatness, and compositional uniformity of the quantum wells while maintaining the target emission wavelength. After completing the growth of the multi-quantum-well active layer, a p-type AlGaN electron blocking layer and a p-type GaN layer are grown to form a complete long-wavelength InGaN-based light-emitting diode structure. Thanks to the aforementioned stress boundary condition modulation and the expansion of the quantum well growth window, the fabricated light-emitting device has a lower dislocation density and non-radiative recombination center density, thereby improving the device's luminous efficiency, emission wavelength uniformity, and performance stability.

[0038] Based on the above embodiments, the present invention also provides an implementation method for Micro-LED arrays and defines the complete layer structure thickness and array-level stress distribution characteristics, which may include the following: The light-emitting device is a Micro-LED array, which includes multiple Micro-LEDs of the same or different sizes. Each Micro-LED, from bottom to top, includes a nano-patterned substrate, an n-type GaN template layer, an active layer, a p-type AlGaN electron blocking layer, and a p-type GaN layer. The thickness of the n-type GaN template layer is 1–3 micrometers, the active layer is an InGaN / GaN multi-quantum-well structure, and the thickness of the InGaN well layer is 2–3 nanometers, while the thickness of the GaN barrier layer is 10–12 nanometers. Under the control of the surface stress boundary conditions of the nano-patterned substrate, the Micro-LED array has a uniform stress distribution on the wafer scale to reduce the emission wavelength dispersion and brightness dispersion of the Micro-LED device units. It is suitable for a current density of 20 A / cm² and maintains an electro-optic modulation bandwidth of not less than 100 MHz within the operating temperature range of 300–480 K.

[0039] Micro-LED array refers to an array structure composed of multiple Micro-LED device units arranged in a certain pattern, used to achieve high brightness, high resolution, or parallel optical communication. The pixel size, array density, and driving method of the Micro-LED array can be adjusted according to specific application requirements, and this application does not impose any limitations on them. Well layer refers to a thin layer with a narrow bandgap in a multi-quantum-well structure, used for carrier confinement and radiative recombination. Barrier layer refers to a barrier layer with a wide bandgap in a multi-quantum-well structure, used to isolate adjacent well layers. Wafer scale refers to the scale range of the entire epitaxial wafer or chip, typically 2 inches, 4 inches, 6 inches, or larger. Uniform stress distribution means that within the wafer scale, the magnitude and direction of the in-plane stress of the epitaxial layer remain consistent, without significant local stress concentration or gradient changes.

[0040] In this embodiment, a long-wavelength InGaN epitaxial structure is prepared using the nano-patterned substrate and epitaxial growth method described in the above embodiments, and multiple Micro-LED device units of the same or different sizes are formed on the epitaxial structure to constitute a Micro-LED array. Due to the control effect of the nano-patterned substrate on the intra-surface stress boundary conditions during epitaxial growth, the stress distribution of the epitaxial layer is more uniform at the wafer scale, resulting in similar growth environments and stress states for InGaN multiple quantum wells at different locations within the array region. Under the aforementioned stress homogenization conditions, the emission wavelength and luminous intensity distribution of each Micro-LED device unit in the array are more concentrated, and its emission wavelength dispersion and brightness dispersion are significantly reduced compared to Micro-LED arrays prepared using traditional patterned sapphire substrates. This is beneficial for achieving the device consistency requirements in high-resolution displays or array light source applications, such as... Figure 3As shown, by homogenizing the stress distribution, the emission wavelength and brightness dispersion among the Micro-LED device units in the array can be reduced, thereby improving the consistency and stability of the array devices. Furthermore, since stress concentration and local defect generation are suppressed, the Micro-LED array in this embodiment exhibits good luminescence stability under different driving conditions, reducing the performance drift caused by local stress differences in individual devices within the array, resulting in a uniform stress distribution in the epitaxial layer at the wafer scale. This uniform stress distribution ensures that the active layers of each Micro-LED device unit in the array have similar growth environments and crystal quality, thereby reducing emission wavelength and brightness dispersion and improving the consistency and reliability of the array. Simultaneously, the uniform stress distribution reduces local defects and carrier crowding, enabling the array to maintain an electro-optic modulation bandwidth of no less than 100MHz under conditions of 20 A / cm² and 300–480K, thereby improving the overall reliability of the array devices.

[0041] With the development of data centers, high-performance computing, and artificial intelligence systems, the demand for data transmission bandwidth between chips continues to increase. In 3D integrated and high-power-density packaging architectures, the close vertical stacking of logic computing units and high-bandwidth memory units leads to a high concentration of heat flux. Local areas within the package are subjected to thermal environments exceeding traditional room-temperature design benchmarks for extended periods, with local steady-state operating temperatures often reaching or exceeding 400K. This high-temperature packaging environment imposes constraints on the material properties and device behavior of the internal optical interconnect physical layer that differ from those under ambient temperature conditions. Existing optical interconnect engineering solutions are mostly based on narrow-bandgap III-V compound semiconductor light sources. The intrinsic carrier transport behavior of such material systems is highly sensitive to temperature changes. In the ambient temperature range above 300K, the nonradiative recombination rate increases significantly, and the carrier leakage effect intensifies, manifesting as an exponential increase in threshold current with temperature, a decrease in differential quantum efficiency, and a sharp decay in electro-optic modulation bandwidth with increasing temperature. To suppress the aforementioned high-temperature performance degradation, the system typically requires active thermoelectric cooling units or liquid-cooled channel structures, which significantly increases the overall system power consumption and package volume, limiting the integration density and scalability of 3D integrated systems. In view of this, this application also constructs an optical interconnect system suitable for high-temperature environments based on the light-emitting device described in the above embodiments, which may include the following: The optical interconnect system of this embodiment includes a three-dimensional integrated packaging structure and an optical interconnect emitting unit disposed inside the three-dimensional integrated packaging structure. The optical interconnect emitting unit adopts a red Micro-LED fabricated using a light-emitting device based on a nano-patterned substrate as described in any of the embodiments. Any embodiment here refers to the substrate of the red Micro-LED being the nano-patterned substrate described in the above embodiments. The light signal emitted by the active layer must be red light. The red Micro-LED maintains its electro-optic modulation capability under the stress boundary conditions of the nanoscale patterned structure, in an operating environment where the temperature inside the three-dimensional packaging structure reaches or exceeds 400K and the current density is 20 A / cm², achieving optical interconnect communication without relying on active thermoelectric cooling or liquid cooling devices. Figure 4 As shown, the red Micro-LED is disposed inside the package and enables optical interconnect communication between chips or between the chip and the interposer.

[0042] For example, the emission wavelength of the active layer of the red Micro-LED is not less than 630 nanometers, and the electro-optic modulation bandwidth attenuation of the red Micro-LED is less than 10% under the conditions of working environment where the temperature inside the three-dimensional packaging structure reaches or exceeds 400K and the current density is 20 A / cm².

[0043] Among them, three-dimensional integrated packaging structure refers to a structure that integrates multiple chips or functional layers into the same package through vertical stacking and interconnection technology, featuring high integration, high bandwidth, and low latency. Optical interconnect emitting unit refers to the light source device in an optical interconnect system used to convert electrical signals into optical signals and emit them. Active thermoelectric cooling refers to the technology of active cooling using the Peltier effect, such as thermoelectric coolers (TECs). Liquid cooling device refers to a cooling system that dissipates heat through liquid circulation. Electro-optic modulation bandwidth attenuation refers to the decrease in electro-optic modulation bandwidth relative to room temperature or standard operating conditions under high temperature or high current density conditions. Less than 10% means the attenuation is controlled within 10%, reflecting the performance stability of the device under high temperature and high injection conditions.

[0044] In this embodiment, the InGaN / GaN multi-quantum-well active structure can be fabricated using the nanopatterned substrate (NPSS) and epitaxial growth method described in the above embodiments. By comprehensively controlling the geometric parameters of the nanopattern and the epitaxial growth conditions, the emission peak wavelength of the light-emitting device is located in the real red band at a wavelength not lower than 630 nm. Due to the control effect of the nanopatterned substrate on the surface stress boundary conditions during epitaxial growth, the long-wavelength InGaN quantum well maintains thermodynamic stability under higher growth temperatures, thereby avoiding the crystal quality degradation problem that easily occurs under low-temperature growth conditions. For example, as shown... Figure 5 and Figure 6As shown, the red Micro-LED comprises, from bottom to top, a patterned substrate, an n-type GaN template layer, an active layer, a p-type AlGaN electron blocking layer, and a p-type GaN layer. The active layer is an InGaN / GaN multiple quantum well (MQW) structure with an emission wavelength of at least 630 nm. The red Micro-LED is suitable for a current density of 20 A / cm² and maintains an electro-optic modulation bandwidth of at least 100 MHz within an operating temperature range of 300–480 K. Compared to InGaN-based light-emitting devices of the same wavelength fabricated using traditional patterned sapphire substrates, the real red light-emitting device fabricated in this embodiment exhibits higher luminous intensity and better luminous uniformity while maintaining an emission peak wavelength of at least 630 nm. This performance improvement is mainly due to the improved quality and compositional uniformity of the quantum well crystals, as well as the effective suppression of non-radiative recombination channels. Furthermore, the light-emitting device in this embodiment exhibits more stable wavelength output characteristics at the device level, with a significantly reduced emission wavelength dispersion, which is beneficial for achieving more consistent colorimetric performance in display or lighting applications. Meanwhile, due to the optimized stress distribution, the stability of the device's luminescence performance under varying operating current conditions is also improved. It should be noted that the emission peak wavelength and performance parameters of the real red band luminescent device in this embodiment can be appropriately adjusted according to specific application requirements; this invention is not limited to a specific wavelength value or performance index.

[0045] For example, such as Figure 7As shown, three-dimensional integrated packaging structures include HBM-on-logic, HBM-on-GPU, logic-on-logic, or multi-chip stacked structures. The internal environment of these packaging structures experiences high-temperature operation due to increased power density. HBM-on-logic refers to a three-dimensional integrated architecture where high-bandwidth memory is stacked on top of a logic chip. HBM-on-GPU refers to a three-dimensional integrated architecture where high-bandwidth memory is stacked on top of a graphics processor. Logic-on-logic refers to a three-dimensional integrated architecture where logic chips are vertically stacked. Multi-chip stacking refers to a packaging form where multiple functional chips are vertically interconnected through technologies such as through-silicon vias (TSVs) or microbumps. Power density-enhanced three-dimensional heterogeneous integrated packaging refers to a three-dimensional packaging structure where chip stacking and high integration lead to a significant increase in power consumption per unit area, resulting in a high-temperature operating environment. Taking the HBM-on-logic architecture as an example, it includes a logic computing chip and one or more high-bandwidth memory chips. The memory chips are vertically stacked on top of the logic chips, and the two are electrically interconnected through a microbump array and a silicon interposer. Logic chips generate a lot of heat during operation. Due to the stacked structure hindering the vertical conduction of heat, a local high-temperature zone is formed in the interface area between the logic chip and the memory chip inside the package, with temperatures reaching over 400K.

[0046] The optical interconnect emitting unit is located inside the three-dimensional integrated package structure. Its location can be selected according to system design requirements: it can be located on the upper edge of the logic chip, using the driving circuit provided by the logic chip to directly modulate the Micro-LED; it can also be located on the silicon interposer, receiving electrical signals from the chip through metal wiring in the interposer; or it can be located on the back of the memory chip, with electrical signals extracted through through-silicon vias. The optical interconnect emitting unit uses a red Micro-LED prepared in the above embodiment, with a mesa size of 30μm × 30μm, outputting red light with a center wavelength of not less than 630nm at an injection current density of 20 A / cm². The optical signal transmission path is used to transmit the modulated optical signal output by the optical interconnect emitting unit to the receiving end. The specific form of the transmission path can be selected according to the package space and transmission distance: in short-distance chip-to-chip communication scenarios, free-space optical transmission can be used, with collimation and focusing of the beam through a microlens array; in longer-distance scenarios or scenarios requiring multi-channel parallel transmission, polymer waveguides or fiber arrays can be used for constrained transmission. The receiving end uses a silicon-based photodetector or a III-V group photodetector to convert the optical signal back into an electrical signal, thus completing the optical interconnect communication.

[0047] During the operation of the optical interconnect system in this embodiment, the local temperature inside the three-dimensional package structure reaches or exceeds 400K, while the red Micro-LED is driven with a current density of 20 A / cm² to generate sufficient optical output power. Under this high-temperature, high-injection recombination condition, the red Micro-LED, through the stress modulation mechanism provided by the nano-patterned substrate, has a low crystal quality defect density in its active layer and a limited number of non-radiative recombination centers, thus maintaining effective electro-optical conversion capability and stable modulation response. With this electro-optical modulation capability, the optical interconnect emitting unit converts the electrical data signal from the chip into a modulated optical signal. The optical signal propagates through the optical signal transmission path to the receiving end and is restored to an electrical signal, thereby achieving high-speed optical interconnect communication between chips or within the package without relying on active thermoelectric cooling or liquid cooling devices.

[0048] As shown above, the red Micro-LED based on a nano-patterned substrate in this embodiment maintains its electro-optic modulation capability even at temperatures reaching or exceeding 400K and 20 A / cm² through stress boundary condition modulation. This high-temperature stability allows the optical interconnect system to achieve stable optical interconnect communication without relying on active thermoelectric cooling or liquid cooling devices, reducing system energy consumption and structural complexity. Furthermore, the nano-patterned substrate improves the strain distribution and carrier injection uniformity of the active layer, suppressing non-radiative recombination and carrier leakage under high-temperature and high-injection conditions. This improvement ensures that the electro-optic modulation bandwidth attenuation of the red Micro-LED is controlled to be less than 10% at temperatures reaching or exceeding 400K and 20 A / cm², guaranteeing the high-speed performance stability and reliability of the high-temperature three-dimensional integrated optical interconnect system.

[0049] Finally, this application also provides a method for selecting optical interconnect technology routes, such as... Figure 8 and Figure 9 As shown, the process may include the following: determining the high-temperature packaging environment formed during the operation of the three-dimensional integrated system, wherein the local operating temperature inside the package is not lower than 400K; evaluating the optical interconnect emission technology route based on the high-temperature packaging environment, with evaluation criteria including high-temperature modulation stability, temperature sensitivity, and dependence on active cooling devices; selecting, based on the evaluation results, a long-wavelength InGaN-based light-emitting device on a nano-patterned substrate controlled by stress boundary conditions as the technology route for the optical interconnect emission unit; configuring the optical interconnect emission unit based on the selected technology route so that the formed optical interconnect system can achieve stable optical interconnect communication within the high-temperature packaging environment without relying on active thermoelectric cooling or liquid cooling devices. For example, in the evaluation criteria for the optical interconnect emission technology route, modulation stability under high-temperature conditions has higher priority than peak optical performance under room temperature conditions.

[0050] High-temperature packaging environment refers to the thermal environment formed inside the package due to chip stacking and high power density operation, with a local operating temperature of not less than 400K. Optical interconnect emission technology refers to the types of light source devices and corresponding technical solutions used to convert electrical signals to optical signals in an optical interconnect system. High-temperature modulation stability refers to the ability of an optical emitting unit to maintain its electro-optic modulation bandwidth without significant attenuation at ambient temperatures above room temperature. Temperature sensitivity refers to the magnitude of change in the performance parameters of the optical emitting unit (such as output optical power and modulation bandwidth) with temperature. Active cooling device refers to a device that achieves forced heat dissipation through external energy input, including thermoelectric coolers and liquid cooling circulation systems.

[0051] In the selection of optical interconnect technology routes, the first step is to determine the high-temperature packaging environment generated during the operation of the 3D integrated system. Typical architectures of 3D integrated systems include HBM-on-logic, HBM-on-GPU, logic-on-logic, and multi-chip stacked structures. In these architectures, computing chips and memory chips are interconnected at high density in the vertical direction through microbumps or through-silicon vias, with the spacing between chips being only tens of micrometers. The Joule heat generated by the logic chips during operation and the power consumption of the memory chips are superimposed in a small space, and the heat dissipation path is limited, causing the temperature in local areas inside the package to reach or exceed 400K. The existence and spatial distribution of this high-temperature environment can be confirmed through thermal simulation or actual temperature measurement. Secondly, based on the determined high-temperature packaging environment, candidate optical interconnect emission technologies are evaluated. The evaluation criteria include at least the following three aspects: first, high-temperature modulation stability, i.e., the ability of the optical emitting unit to maintain its electro-optic modulation bandwidth at an ambient temperature of 400K; second, temperature sensitivity, i.e., the gradient of key performance parameters of the optical emitting unit within the temperature range of 300K to 480K; and third, the degree of dependence on active cooling devices, i.e., whether the optical emitting unit must be used with thermoelectric or liquid cooling devices to maintain stable operation. In the above evaluation criteria, modulation stability under high-temperature conditions has higher priority than peak optical performance at room temperature. This is because in the actual operating conditions of 3D integrated packaging, the device is constantly under high temperature, and peak performance at room temperature has no practical engineering significance. Based on the evaluation results, a long-wavelength InGaN-based light-emitting device based on a nanopatterned substrate was selected as the technical route for the optical interconnect emitting unit. This light-emitting device is the nanopatterned substrate-based light-emitting device described in the above embodiment. The InGaN material system was selected based on the following criteria: its wide bandgap characteristic results in significantly lower thermal escape of charge carriers at high temperatures compared to narrow bandgap III-V semiconductors; the nanopatterned substrate improves the crystal quality of the active layer and reduces the density of nonradiative recombination centers through stress boundary condition modulation, thus maintaining high internal quantum efficiency even at high injection current densities; and the device exhibits less than 10% attenuation of electro-optic modulation bandwidth at a working current density of 20 A / cm² within a temperature range of 300K to 480K, meeting the requirements for high-speed optical interconnects in high-temperature environments. Finally, optical interconnect emitter units are configured based on the selected technology to enable the resulting optical interconnect system to achieve stable optical interconnect communication within a high-temperature packaging environment without relying on active thermoelectric cooling or liquid cooling devices. For example, the selected InGaN-based red Micro-LED is placed at a predetermined location within a three-dimensional integrated package, such as on the surface of a logic chip layer, a memory chip layer, or an interposer, and forms an optical signal transmission path with the receiver via an optical waveguide or free-space optical path. Since the light emitting unit can operate stably at a high temperature of 400K without active cooling, the system can eliminate the need for thermoelectric coolers or liquid cooling components, thereby reducing overall power consumption, reducing package size and increasing integration density.

[0052] For example, during the evaluation process, a comparative analysis was conducted between narrow bandgap III-V semiconductor light sources (such as laser diodes or light-emitting diodes based on GaAs or InP material systems) and the InGaN-based red micro-LED based on a nanopatterned substrate described in this application. Narrow bandgap III-V semiconductor light sources can achieve high output optical power and modulation bandwidth at room temperature of 300K. However, when the ambient temperature rises to 400K, carrier leakage in the active region significantly intensifies, the non-radiative Auger recombination rate increases, leading to a substantial increase in threshold current, a sharp drop in output optical power, and a typical attenuation of more than 50% in the -3dB electro-optic modulation bandwidth. To maintain its basic operating capability at high temperatures, an active thermoelectric cooler must be equipped to control the junction temperature within the rated range, which results in increased system power consumption and increased packaging complexity. In contrast, the InGaN-based red Micro-LED with a nanopatterned substrate described in this application exhibits significant advantages in the temperature range of 300K to 480K. This is due to the wide bandgap of InGaN material effectively suppressing carrier thermal escape, while the stress modulation effect of the nanopatterned substrate improves the crystal quality of the active layer and reduces non-radiative recombination losses under high injection conditions. Furthermore, its electro-optic modulation bandwidth attenuation is less than 10%, and it can operate stably without an active cooling device. Based on the above comparative analysis, the technical solution provided in this application has significant advantages in high-temperature three-dimensional integrated systems.

[0053] The foregoing provides a detailed description of a light-emitting device and optical interconnect system based on a nano-patterned substrate provided in this application. The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Whether the units and algorithm steps of the various examples described in the disclosed embodiments are implemented in electronic hardware or computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, and such implementations should not be considered beyond the scope of this application. Several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A light-emitting device based on a nanopatterned substrate, characterized in that, It includes a nanopatterned substrate and an active layer located on the nanopatterned substrate; The surface of the nanopatterned substrate has a nanoscale patterned structure that transforms the epitaxial growth interface from a continuous interface to a discrete interface with lateral elastic relaxation capability, which is used to control the in-plane stress boundary conditions during the epitaxial growth process. The emission wavelength of the active layer is within a preset long wavelength band. The nanoscale patterned structure releases the in-plane stress of the active layer through the lateral elastic relaxation capability, thereby expanding the stable growth temperature range of the active layer. The geometric parameters of the nanoscale patterned structure are configured such that, during epitaxial growth, the epitaxial layer forms a lateral elastic relaxation region between adjacent patterned units to achieve the control of the stress boundary conditions.

2. The light-emitting device based on a nanopatterned substrate according to claim 1, characterized in that, The height, spacing, period, and duty cycle of the nanoscale graphic structure are configured as follows: The height of the nanoscale patterned structure does not exceed 2 micrometers, the pattern spacing is 0.01 to 1 micrometer, the pattern period is 0.01 to 1 micrometer, and the pattern duty cycle is 30% to 70%.

3. The light-emitting device based on a nanopatterned substrate according to claim 2, characterized in that, The height of the nanoscale patterned structure does not exceed 1 micrometer, in order to enhance the ability to relax lateral stress during epitaxial growth.

4. The light-emitting device based on a nanopatterned substrate according to claim 2, characterized in that, The height of the nanoscale patterned structure is 800 nanometers ± fluctuation value, and the duty cycle of the pattern is between 45% and 65% to form a laterally connected stress relief channel in the epitaxial layer.

5. The light-emitting device based on a nanopatterned substrate according to claim 1, characterized in that, The top and valley connecting regions of the nanoscale patterned structure are both continuous curvature transition structures, with a top curvature radius greater than or equal to 50 nm and a valley transition curvature radius greater than or equal to 20 nm.

6. The light-emitting device based on a nanopatterned substrate according to claim 5, characterized in that, The nanoscale patterned structure is a periodic nanopattern formed on the surface of a substrate or template layer. Its cross-section has an arched, ridged, or wavy profile, and adjacent patterns are connected by valleys.

7. The light-emitting device based on a nanopatterned substrate according to any one of claims 1 to 6, characterized in that, The light-emitting device is a Micro-LED; During the growth of the InGaN well layer of the active layer, by adjusting the molar ratio of group V source to group III source and the carrier gas ratio, optical signals with wavelengths in the range of 560 to 650 nm are emitted. The Micro-LED is suitable for a current density of 20 A / cm² and maintains an electro-optic modulation bandwidth of not less than 100MHz within an operating temperature range of 300–480K.

8. The light-emitting device based on a nanopatterned substrate according to claim 7, characterized in that, The light-emitting device is a Micro-LED array, which includes multiple Micro-LEDs of the same or different sizes; Each Micro-LED, from bottom to top, comprises the aforementioned nano-patterned substrate, an n-type GaN template layer, the aforementioned active layer, a p-type AlGaN electron blocking layer, and a p-type GaN layer; wherein, the thickness of the n-type GaN template layer is 1–3 micrometers, the active layer is an InGaN / GaN multiple quantum well structure, and the thickness of the InGaN well layer is 2–3 nanometers, and the thickness of the GaN barrier layer is 10–12 nanometers; The Micro-LED array, under the control of the in-plane stress boundary conditions by the nano-patterned substrate, has a uniform stress distribution on the wafer scale, thereby reducing the emission wavelength dispersion and brightness dispersion of the Micro-LED device unit. It is also suitable for a current density of 20 A / cm² and maintains an electro-optic modulation bandwidth of not less than 100MHz within the operating temperature range of 300 to 480K.

9. An optical interconnect system, characterized in that, Includes a three-dimensional integrated packaging structure and an optical interconnect emitting unit disposed inside the three-dimensional integrated packaging structure; The optical interconnect emitting unit is a red Micro-LED fabricated based on a nano-patterned substrate as described in any one of claims 1 to 8; The red Micro-LED maintains its electro-optic modulation capability under the stress boundary conditions of the nanoscale patterned structure, with a working environment where the temperature inside the three-dimensional encapsulation structure reaches or exceeds 400K and the current density is 20 A / cm², so as to realize optical interconnect communication without relying on active thermoelectric cooling or liquid cooling devices.

10. The optical interconnect system according to claim 9, characterized in that, The active layer of the red Micro-LED emits wavelengths of not less than 630 nanometers, and the electro-optic modulation bandwidth attenuation of the red Micro-LED is less than 10% under the conditions of working environment where the temperature inside the three-dimensional packaging structure reaches or exceeds 400K and current density is 20 A / cm².

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