LED chip structure, preparation method thereof and LED light emitting device

Abstract

This invention provides an LED chip structure, its fabrication method, and an LED light-emitting device. The LED chip structure includes: a substrate, an N-type doped gallium nitride layer, a quantum well layer, a P-type doped gallium nitride layer, and a transparent conductive layer; at least a portion of a first insulating layer is disposed on the side of the transparent conductive layer away from the substrate; a DBR reflective layer is disposed on the surface of the first insulating layer, and the first insulating layer and the DBR reflective layer have multiple vias exposing the transparent conductive layer; the DBR reflective layer includes alternating first and second reflective layers; a second insulating layer is disposed on the side of the DBR reflective layer away from the substrate, at least covering the second reflective layer exposed by the sidewalls of the vias; a silver reflective layer is disposed on the side of the second insulating layer away from the substrate, filling the vias. The second insulating layer completely isolates the second reflective layer from the silver, preventing silver migration from the second reflective layer during long-term high-temperature and high-humidity aging, thus improving reliability and lifespan.

Description

Technical Field

[0001] This invention relates to the field of LED chip technology, specifically to LED chip structures, their fabrication methods, and LED light-emitting devices. Background Technology

[0002] With the rapid development of LED technology, its applications in displays, lighting, and backlighting are becoming increasingly widespread. However, traditional upright LEDs suffer from limited light extraction efficiency due to electrode obstruction, especially in high-power applications where insufficient heat dissipation and current expansion become key factors restricting brightness improvement. Flip-chip LEDs, by changing the chip structure and packaging method, can effectively reduce electrode obstruction of light, enhance light extraction efficiency, and optimize current distribution and heat dissipation performance, thereby significantly improving device brightness and reliability, providing important technical support for high-performance LED applications.

[0003] As demands for brightness and luminous efficacy increase, the structure of LED chip flip-chip products has upgraded from Ag reflection to DBR (Distributed Bragg Reflector) + Ag reflection. Typically, thin-layer DBRs (3-5 pairs) are used in conjunction with Ag to improve the luminous brightness of the LED chip. However, certain problems still exist in the current LED chip structure. For example, in long-term high-temperature and high-humidity environments, LED chips age, and Ag migrates through the DBR reflective layer, causing LED light-emitting devices to fail. Summary of the Invention

[0004] This invention aims to at least partially address one of the technical problems in related technologies. Therefore, one object of this invention is to provide an LED chip structure that effectively prevents silver migration through the DBR reflective layer, thereby improving chip reliability.

[0005] In one aspect, the present invention provides an LED chip structure. According to an embodiment of the present invention, the LED chip structure includes: a substrate, and an N-type doped gallium nitride layer, a quantum well layer, a P-type doped gallium nitride layer, and a transparent conductive layer sequentially disposed on one side of the substrate; The LED chip structure further includes: a first insulating layer, at least a portion of which is disposed on the transparent conductive layer away from the substrate; a DBR reflective layer, which is disposed on the surface of the first insulating layer away from the substrate, wherein the first insulating layer and the DBR reflective layer have multiple vias, and the vias expose the transparent conductive layer; the DBR reflective layer includes alternating first and second reflective layers, wherein the reflectivity of the second reflective layer is greater than that of the first reflective layer; a second insulating layer, which is disposed on the side of the DBR reflective layer away from the substrate and at least covers the second reflective layer exposed by the sidewall of the via; and a silver reflective layer, which is disposed on the side of the second insulating layer away from the substrate and fills the vias, and is electrically connected to the P-type doped gallium nitride layer.

[0006] In the LED chip structure described above, the second insulating layer can completely isolate the high-reflectivity second reflective layer in the DBR reflective layer at the inner wall of the through hole from the silver reflective layer, thus forming a physical barrier between the two. In this way, during long-term high-temperature and high-humidity aging, it can effectively prevent the metallic silver in the silver reflective layer from migrating from the second reflective layer of the DBR reflective layer, thereby improving the reliability and service life of the chip.

[0007] According to an embodiment of the present invention, in the vertical direction, the through-hole includes a first sub-through-hole and a second sub-through-hole that are connected. The through-hole satisfies one of the following conditions: the first sub-through-hole at least penetrates the DBR reflective layer; the second sub-through-hole penetrates the second insulating layer and a portion of the first insulating layer that is not penetrated by the first sub-through-hole; the second insulating layer covers the sidewall of the first sub-through-hole; the film layer disposed adjacent to the first insulating layer in the DBR reflective layer is a first reflective layer; the depth of the first sub-through-hole is less than that in the DBR reflective layer; and the first reflective layer disposed adjacent to the first insulating layer is not penetrated by the first sub-through-hole.

[0008] According to an embodiment of the present invention, in the same through-hole, the diameter of the first sub-through-hole is larger than that of the second sub-through-hole, and the orthographic projection of the first sub-through-hole on the substrate covers the orthographic projection of the second sub-through-hole on the substrate.

[0009] According to an embodiment of the present invention, the LED chip structure further satisfies at least one of the following conditions: the thickness of the second insulating layer is 10-100 nm; the material of the second insulating layer includes at least one of aluminum oxide, silicon oxide, silicon nitride, and aluminum nitride; the thickness of the first insulating layer is 50-800 nm; the material of the first insulating layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride; the thickness of the DBR reflective layer is 400-1500 nm; the material of the first reflective layer includes at least one of silicon oxide, aluminum oxide, aluminum arsenide, and magnesium fluoride; the material of the second reflective layer includes at least one of titanium dioxide, tantalum pentoxide, aluminum oxide, and silicon nitride; the thickness of the silver reflective layer is 80-300 nm; and the depth of the second sub-via is 100-300 nm.

[0010] According to an embodiment of the present invention, the P-type doped gallium nitride layer and the quantum well layer have a first via penetrating the P-type doped gallium nitride layer and the quantum well layer, the first via exposing a portion of the surface of the N-type doped gallium nitride layer; the first insulating layer, the DBR reflective layer, and a portion of the second insulating layer located in the first via have a second via, the second via exposing a portion of the surface of the N-type doped gallium nitride layer; the LED chip structure further includes: a first passivation layer, the first passivation layer covering the silver reflective layer, the first passivation layer having a third via, the third via exposing a portion of the surface of the silver reflective layer, and the first passivation layer located within the first via having A fourth via; a first electrode and a second electrode spaced apart, both the first electrode and the second electrode being disposed on the side of the first passivation layer away from the substrate, the first electrode being electrically connected to the silver reflective layer through the third via, and the second electrode being electrically connected to the N-type doped gallium nitride layer through the fourth via; a second passivation layer, the second passivation layer covering a portion of the first electrode and the second electrode, having a fifth via exposing a portion of the surface of the first electrode and a sixth via exposing a portion of the surface of the second electrode; a third electrode and a fourth electrode spaced apart, the third electrode being electrically connected to the first electrode through the fifth via, and the fourth electrode being electrically connected to the second electrode through the sixth via.

[0011] According to an embodiment of the present invention, the LED chip structure further includes: a metal attachment layer located between the silver reflective layer and the second insulating layer; and / or a metal protective layer disposed on the surface of the silver reflective layer away from the substrate.

[0012] In another aspect of the present invention, a method for fabricating the aforementioned LED chip structure is provided. According to an embodiment of the present invention, the method for fabricating the LED chip structure includes: sequentially forming an N-type doped gallium nitride layer, a quantum well layer, a P-type doped gallium nitride layer, and a transparent conductive layer on one side of a substrate; forming a first insulating layer on the side of the transparent conductive layer away from the substrate; forming a DBR reflective layer on the surface of the first insulating layer away from the substrate, the DBR reflective layer including alternately arranged first and second reflective layers, the reflectivity of the second reflective layer being greater than that of the first reflective layer; etching the DBR reflective layer and the first insulating layer to form a plurality of vias, the vias exposing the transparent conductive layer; forming a second insulating layer on the side of the DBR reflective layer away from the substrate, the second insulating layer at least covering the second reflective layer exposed on the sidewall of the vias; forming a silver reflective layer on the side of the second insulating layer away from the substrate, the silver reflective layer filling the vias and electrically connected to the P-type doped gallium nitride layer.

[0013] In the above method for preparing LED chip structure, the formation of the second insulating layer can completely isolate the titanium oxide in the DBR reflective layer exposed at the inner wall of the through hole from the silver reflective layer, so that a good physical barrier is formed between the two. In this way, during long-term high temperature and high humidity aging, the metallic silver in the silver reflective layer can be effectively prevented from migrating from the second reflective layer of the DBR reflective layer, thereby improving the reliability and service life of the chip.

[0014] According to an embodiment of the present invention, a method for forming the via and the second insulating layer includes: performing a first etching on the DBR reflective layer to form a first sub-via; depositing to form a second insulating layer, wherein the second insulating layer covers the sidewall of the first sub-via within the first sub-via; and performing a second etching on the second insulating layer within the first sub-via and the corresponding first insulating layer that was not first etched to form a second sub-via.

[0015] According to an embodiment of the present invention, the method for fabricating an LED chip structure further includes: after forming the P-type doped gallium nitride layer, etching the P-type doped gallium nitride layer and the quantum well layer to form a first via, the first via exposing a portion of the surface of the N-type doped gallium nitride layer; after forming the DBR reflective layer, etching the DBR reflective layer located in the first via simultaneously during the first etching; after depositing and forming the second insulating layer, etching the first insulating layer and the second insulating layer located in the first via simultaneously during the second etching to form a second via, the second via exposing a portion of the surface of the N-type doped gallium nitride layer.

[0016] According to an embodiment of the present invention, the method for fabricating an LED chip structure further includes: forming a first passivation layer covering the silver reflective layer, and etching the first passivation layer to form a third via and a fourth via, wherein the third via exposes a portion of the surface of the silver reflective layer, and the fourth via is located within the first via; forming a first electrode and a second electrode spaced apart, wherein the first electrode is electrically connected to the silver reflective layer through the third via, and the second electrode is electrically connected to an N-type doped gallium nitride layer through the fourth via; forming a second passivation layer covering a portion of the first electrode and the second electrode, and etching the second passivation layer to form a fifth via exposing a portion of the surface of the first electrode and a sixth via exposing a portion of the surface of the second electrode; forming a third electrode and a fourth electrode spaced apart, wherein the third electrode is electrically connected to the first electrode through the fifth via, and the fourth electrode is electrically connected to the second electrode through the sixth via.

[0017] In another aspect, the present invention provides an LED light-emitting device. According to an embodiment of the present invention, the LED light-emitting device includes the LED chip structure described above. Therefore, the LED light-emitting device has good reliability and a long service life. Those skilled in the art will understand that the LED light-emitting device possesses all the features and advantages of the LED chip structure described above, and will not be elaborated further here.

[0018] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of an LED chip structure in one embodiment of the present invention; Figure 2 This is a schematic diagram of the LED chip structure in another embodiment of the present invention; Figure 3 This is a schematic diagram of the LED chip portion structure in another embodiment of the present invention; Figure 4 This is a schematic diagram of the LED chip structure in another embodiment of the present invention; Figure 5 , Figure 6 and Figure 7 This is a schematic diagram of the LED chip structure fabrication in another embodiment of the present invention. Detailed Implementation

[0020] The present invention will be explained below with reference to embodiments. Those skilled in the art will understand that the following embodiments are for illustrative purposes only and should not be considered as limiting the scope of the invention. Where specific techniques or conditions are not specified in the embodiments, they are performed according to the techniques or conditions described in the literature in the field or according to the product instructions. Reagents or instruments whose manufacturers are not specified are all conventional products that can be obtained commercially.

[0021] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a particular range. Ranges defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, it is expected that ranges of 60-110 and 80-120 are also included. Furthermore, if minimum range values ​​of 1 and 2 are listed, and if maximum range values ​​of 3, 4, and 5 are listed, then the following ranges are all expected: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In this application, unless otherwise stated, the numerical range "ab" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0-5" indicates that all real numbers between "0-5" have been listed in this article; "0-5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is stated as an integer ≥2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0022] The present invention will now be described with reference to specific embodiments. It should be noted that these embodiments are merely descriptive and do not limit the present invention in any way.

[0023] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature marked "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] In one aspect, the present invention provides an LED chip structure. According to an embodiment of the present invention, referring to... Figure 1 and Figure 2 The LED chip structure includes: a substrate 10, and an N-type doped gallium nitride layer 11, a quantum well layer 12, a P-type doped gallium nitride layer 13, and a transparent conductive layer 14 sequentially disposed on one side of the substrate 10.

[0025] Furthermore, the LED chip structure also includes: a first insulating layer 15, at least a portion of which is disposed on the side of the transparent conductive layer 14 away from the substrate 10; a DBR reflective layer 16, which is disposed on the surface of the first insulating layer 15 away from the substrate 10, the first insulating layer 15 and the DBR reflective layer 16 having a plurality of vias 1, and the vias 1 exposing the transparent conductive layer 14, the DBR reflective layer 16 including alternating first and second reflective layers, the reflectivity of the second reflective layer being greater than that of the first reflective layer; a second insulating layer 17, which is disposed on the side of the DBR reflective layer 16 away from the substrate 10, and at least covers the second reflective layer exposed on the sidewall of the via 1; and a silver reflective layer 18, which is disposed on the side of the second insulating layer 17 away from the substrate 10, and fills the via 1, the silver reflective layer 18 being electrically connected to the P-type doped gallium nitride layer 13.

[0026] In the LED chip structure described above, the second insulating layer 17 can completely isolate the high-reflectivity second reflective layer in the DBR reflective layer 16 at the inner wall of the through hole 01 from the silver reflective layer, thus forming a physical barrier between the two. In this way, during long-term high-temperature and high-humidity aging, the metallic silver in the silver reflective layer can be effectively prevented from migrating from the second reflective layer of the DBR reflective layer, thereby improving the reliability and service life of the chip.

[0027] According to some embodiments of the present invention, the DBR reflective layer is composed of alternating stacks of a high-refractive-index first reflective layer and a low-refractive-index second reflective layer. By alternating high- and low-refractive-index materials and matching thicknesses, the specular reflectivity and light extraction efficiency can be improved, while reducing film stress, suppressing leakage current and interface defects, and improving the chip's optoelectronic performance and long-term reliability. In the direction away from the substrate, the DBR reflective layer includes a first reflective layer, a second reflective layer, a first reflective layer, a second reflective layer, and so on, or the DBR reflective layer includes a second reflective layer, a first reflective layer, a second reflective layer, a first reflective layer, and so on, with a total number of DBR reflective layers greater than or equal to 3 layers.

[0028] In some embodiments, the material of the first reflective layer includes, but is not limited to, at least one of silicon oxide, aluminum oxide, aluminum arsenide, and magnesium fluoride, and the material of the second reflective layer includes at least one of titanium dioxide, tantalum pentoxide, aluminum oxide, and silicon nitride. The materials of different first reflective layers can be the same or different, wherein each first reflective layer can be a single material or a composite layer structure of multiple different materials. Similarly, the materials of different second reflective layers can be the same or different, wherein each second reflective layer can be a single material or a composite layer structure of multiple different materials.

[0029] According to some embodiments of the present invention, with reference to Figure 3In the vertical direction (i.e., the stacking direction of each layer of the LED chip structure), the via 01 includes a first sub-via 1 and a second sub-via 2 that are connected. The depth of the via is the sum of the depths of the first sub-via 1 and the second sub-via 2, which is equal to the sum of the thickness of the DBR reflective layer 16 and the thickness of the first insulating layer. The via 01 can be one of the following: In some embodiments, the first sub-via 1 penetrates at least through the DBR reflective layer 16, the second sub-via 2 penetrates a portion of the first insulating layer 15 that is not penetrated by the first sub-via 1, and the second insulating layer 17 covers the sidewall of the first sub-via 1. Thus, the first sub-via 1 penetrates at least through the DBR reflective layer 16, meaning the depth of the first sub-via 1 is greater than or equal to the thickness of the DBR reflective layer 16. The second insulating layer 17 covers the sidewall of the first sub-via 1, completely covering the exposed cross-section of the DBR reflective layer. This completely isolates the silver reflective layer from the second reflective layer in the DBR reflective layer 16, effectively preventing the migration of metallic silver from the second reflective layer of the DBR reflective layer, thereby improving the chip's reliability and lifespan.

[0030] Furthermore, refer to Figure 3 The depth of the first sub-via 1 is greater than the thickness of the DBR reflective layer 16, that is, the first sub-via 1 extends from the DBR reflective layer 16 to part of the first insulating layer 15. Thus, the depth of the second sub-via 2 is less than the first insulating layer 15. In this way, the second insulating layer can better cover and isolate the exposed surface of the DBR reflective layer in the via, preventing the metallic silver of the silver reflective layer from migrating from the second reflective layer of the DBR reflective layer, thereby further improving the reliability and lifespan of the chip structure.

[0031] In other embodiments, the film layer adjacent to the DBR reflective layer 16 and the first insulating layer 15 is a first reflective layer (i.e., a composite structure of sequentially arranged first reflective layer, second reflective layer, first reflective layer, second reflective layer, etc., in the direction away from the substrate). The depth of the first sub-via is less than that of the DBR reflective layer, and the first reflective layer adjacent to the first insulating layer is not penetrated by the first sub-via. Thus, the depth of the first sub-via is less than the thickness of the DBR reflective layer, and the depth of the second sub-via is the sum of the thickness of the first insulating layer and the thickness of the first reflective layer not penetrated by the first sub-via. During fabrication, when etching to form the first sub-via, the DBR reflective layer is etched to the position closest to the first insulating layer. In this way, the second insulating layer can still effectively isolate and protect the exposed second reflective layer of the DBR reflective layer in the via, preventing the metallic silver of the silver reflective layer from migrating from the second reflective layer of the DBR reflective layer, thereby further improving the reliability and lifespan of the chip structure.

[0032] According to some embodiments of the present invention, with reference to Figures 1 to 3In the same via 01, the diameter of the first sub-via 1 is larger than the diameter of the second sub-via 2, and the orthographic projection of the first sub-via 1 on the substrate 10 covers the orthographic projection of the second sub-via 2 on the substrate 10. In this way, the coverage area of ​​the second insulating layer 17 in the via can be extended, thereby extending the migration path of metallic silver, thus better preventing the migration of metallic silver and improving the reliability and lifespan of the chip structure.

[0033] According to some embodiments of the present invention, the thickness of the second insulating layer 17 is 10~100nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 100nm, etc. In some embodiments, the material of the second insulating layer includes at least one of aluminum oxide, silicon oxide, silicon nitride, and aluminum nitride. The second insulating layer with the above-mentioned materials and thicknesses has a good insulating effect, which can effectively block the migration of metallic silver to the DBR reflective layer, thus improving the reliability and lifespan of the chip structure.

[0034] According to some embodiments of the present invention, the thickness of the first insulating layer is 50~800nm, such as 50nm, 80nm, 100nm, 120nm, 150nm, 180nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, etc. In some embodiments, the material of the first insulating layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. Thus, the first insulating layer has good insulating isolation and protection effects on the reflective layers (including the DBR reflective layer and the silver reflective layer), while also providing optical matching and current blocking functions, thereby preventing leakage and metal migration, and improving reflection efficiency and chip reliability.

[0035] In some embodiments, as described above, the depth of the second sub-via is 100-300 nm. In terms of process, when etching to form the first sub-via, a 100-300 nm thick first insulating layer is left unetched, or a 100-300 nm thick first insulating layer and first reflective layer material are retained. Thus, in terms of process, this thickness of material can be used as a buffer to prevent damage to the epitaxial layer during etching of the DBR reflective layer.

[0036] According to some embodiments of the present invention, the thickness of the DBR reflective layer is 400~1500nm, such as 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, 1100nm, 1200nm, 1300nm, 1400nm, 1500nm, etc.

[0037] According to some embodiments of the present invention, the thickness of the silver reflective layer is 80~300nm, such as 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 200nm, 250nm, 300nm, etc. This thickness of silver reflective layer ensures high blue light reflectivity while also achieving low contact resistance, low film stress, and high adhesion, suppressing silver migration and film cracking, and improving chip light extraction efficiency, electrical stability, and long-term reliability.

[0038] According to some embodiments of the present invention, with reference to Figure 1 and Figure 2 As shown, the substrate 10, N-type doped gallium nitride layer 11, quantum well layer 12, and P-type doped gallium nitride layer 13 form an island structure. The specific type of substrate includes, but is not limited to, sapphire substrate, silicon carbide substrate, silicon substrate, gallium nitride substrate, or aluminum nitride substrate; the thickness of the N-type doped gallium nitride layer can be 2–4 micrometers; the thickness of the P-type doped gallium nitride layer can be 50–200 nm; the total thickness of the quantum well layer can be 80–150 nm, and the quantum well layer can be a multi-quantum well structure formed by alternating stacks of indium gallium nitride (ITO) and gallium nitride (GaN) barrier layers; the material of the transparent conductive layer includes, but is not limited to, transparent conductive materials such as ITO, IZO, and ZnO, and its thickness can be 10–60 nm.

[0039] According to some embodiments of the present invention, with reference to Figure 1 and Figure 2 As shown, the P-type doped gallium nitride layer 13 and the quantum well layer 12 have a first via 001 that penetrates the P-type doped gallium nitride layer 13 and the quantum well layer 12, and the first via 001 exposes a portion of the surface of the N-type doped gallium nitride layer 11; the first insulating layer 15, the DBR reflective layer 16 and the second insulating layer 17 located in the first via 001 have a second via 002, and the second via 002 exposes a portion of the surface of the N-type doped gallium nitride layer 11.

[0040] According to some embodiments of the present invention, the LED chip structure further includes a metal adhesion layer located between the silver reflective layer and the second insulating layer. That is, during the fabrication process, a metal adhesion layer is pre-formed before the formation of the silver reflective layer, thereby improving the adhesion of the silver reflective layer. In some embodiments, the material of the metal adhesion layer includes at least one of chromium, titanium, and nickel.

[0041] According to some embodiments of the present invention, the LED chip structure further includes a metal protective layer disposed on the surface of the silver reflective layer away from the substrate. That is, during the fabrication process, after the formation of the silver reflective layer, a metal protective layer is formed on the surface of the silver reflective layer to protect it. In some embodiments, the material of the metal protective layer includes, but is not limited to, at least one of nickel, titanium, tungsten, and platinum, or an alloy of the above metals.

[0042] In some embodiments of the present invention, reference is made to... Figure 4 The LED chip structure further includes: a first passivation layer 19 covering a silver reflective layer 18; the first passivation layer 19 having a third via 003 exposing a portion of the surface of the silver reflective layer 18; and the first passivation layer 19 having a fourth via 004 within the first via 001; a first electrode 20 and a second electrode 21 spaced apart, both disposed on the side of the first passivation layer 19 away from the substrate 10; the first electrode 20 being electrically connected to the silver reflective layer 18 through the third via 003. The second electrode 21 is electrically connected to the N-type doped gallium nitride layer 11 through a fourth via 004. A second passivation layer 22 covers a portion of the first electrode 20 and the second electrode 21. The second passivation layer 22 has a fifth via 005 exposing a portion of the surface of the first electrode 20 and a sixth via 006 exposing a portion of the surface of the second electrode 21. A third electrode 23 and a fourth electrode 24 are spaced apart. The third electrode 23 is electrically connected to the first electrode 20 through the fifth via 005, and the fourth electrode 23 is electrically connected to the second electrode 21 through the sixth via 006. Therefore, the LED chip structure has good performance characteristics.

[0043] In some embodiments, the material of the first passivation layer includes, but is not limited to, insulating materials such as aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, and silicon oxynitride, and the thickness can be 200~2000nm; in other embodiments, the first passivation layer can be the same material and structure as the DBR reflective layer, that is, it is composed of alternating stacks of high refractive index dielectric layers and low refractive index dielectric layers, the low refractive index material can be silicon oxide or silicon nitride, the high refractive index material can be titanium oxide, etc., the number of layers is greater than or equal to 3, and the total thickness is 100~6000nm.

[0044] In some embodiments, the material of the second passivation layer includes, but is not limited to, insulating materials such as aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, and silicon oxynitride, and the thickness can be 200~2000nm; in other embodiments, the second passivation layer can be the same material and structure as the DBR reflective layer, that is, it is composed of alternating stacks of high refractive index dielectric layers and low refractive index dielectric layers, the low refractive index material can be silicon oxide or silicon nitride, the high refractive index material can be titanium oxide, etc., the number of layers is greater than or equal to 3, and the total thickness is 100~6000nm.

[0045] In some embodiments, the materials of the first electrode and the second electrode can be at least one of the metal materials such as Cr, Al, Ti, Pt, Ni, and Au, and the thicknesses can be 50 nanometers to 5000 micrometers, respectively. The first electrode is electrically connected to a P-type doped gallium nitride layer, and the second electrode is connected to an N-type doped gallium nitride layer.

[0046] In some embodiments, the materials of the third and fourth electrodes can be metals such as Cr, Al, Ti, Pt, Ni, Au, Sn, and Au / Sn alloys, with a thickness of 1000-5000 nm. The third electrode is electrically connected to the P-type doped gallium nitride layer, and the fourth electrode is connected to the N-type doped gallium nitride layer.

[0047] In another aspect, the present invention provides a method for fabricating the aforementioned LED chip structure. According to an embodiment of the present invention, referring to… Figures 5 to 7 Methods for preparing LED chip structures include: S1: An N-type doped gallium nitride layer 11, a quantum well layer 12, a P-type doped gallium nitride layer 13, and a transparent conductive layer 14 are sequentially formed on one side of the substrate 10, such as... Figure 5 As shown.

[0048] According to some embodiments of the present invention, after forming the P-type doped gallium nitride layer 13, the P-type doped gallium nitride layer 13 and the quantum well layer 12 are etched to form a first via 001, the first via 001 exposing a portion of the surface of the N-type doped gallium nitride layer 11.

[0049] S2: A first insulating layer 15 is formed on the side of the transparent conductive layer 14 away from the substrate, such as... Figure 5 As shown.

[0050] In some embodiments, the method for forming the first insulating layer includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD).

[0051] S3: A DBR reflective layer 16 is formed on the surface of the first insulating layer 15 away from the substrate, such as... Figure 5 As shown.

[0052] In some embodiments, the DBR reflective layer includes alternating first and second reflective layers. For example, in the direction away from the substrate, the DBR reflective layer includes a first reflective layer, a second reflective layer, a first reflective layer, a second reflective layer, and so on, or the DBR reflective layer includes a second reflective layer, a first reflective layer, a second reflective layer, a first reflective layer, and so on, and the total number of DBR reflective layers is greater than or equal to 3 layers.

[0053] In some embodiments, the material of the first reflective layer includes, but is not limited to, at least one of silicon oxide, aluminum oxide, aluminum arsenide, and magnesium fluoride, and the material of the second reflective layer includes at least one of titanium dioxide, tantalum pentoxide, aluminum oxide, and silicon nitride. The materials of different first reflective layers can be the same or different, wherein each first reflective layer can be a single material or a composite layer structure of multiple different materials. Similarly, the materials of different second reflective layers can be the same or different, wherein each second reflective layer can be a single material or a composite layer structure of multiple different materials.

[0054] In some embodiments, the method for forming the DBR reflective layer includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD).

[0055] S4: A plurality of vias 1 are formed by etching the DBR reflective layer 16 and the first insulating layer 15, and the vias 1 expose a transparent conductive layer 14. A second insulating layer 17 is formed on the side of the DBR reflective layer 16 away from the substrate 10, and the second insulating layer 17 at least covers the second reflective layer exposed on the sidewall of the via 1. Figure 6 and Figure 7 As shown.

[0056] In some embodiments, refer to Figure 6 , Figure 7 The method for forming the through-hole 1 and the second insulating layer 17 includes: S41: The DBR reflective layer 16 is etched first to form a first sub-via 1. In some embodiments, after the DBR reflective layer 16 is formed, during the first etching, the DBR reflective layer 16 located in the first via 001 is also etched simultaneously, such as... Figure 6 As shown.

[0057] S42: A second insulating layer 17 is deposited to form the first sub-via 1, covering the sidewall of the first sub-via 1, such as... Figure 7 As shown.

[0058] S43: The second insulating layer 17 inside the first sub-via 1 and its corresponding un-etched first insulating layer 15 are subjected to a second etching to form the second sub-via 2, such as... Figure 2 and Figure 3 As shown.

[0059] The etching process for forming through-holes can be achieved through one of the following methods: In some embodiments, when etching to form the first sub-via 1, the corresponding DBR reflective layer 16 is completely etched, and may even be further etched to a portion of the first insulating layer 15. Thus, the resulting first sub-via 1 penetrates at least through the DBR reflective layer 16, and the second sub-via 2 penetrates the portion of the first insulating layer 15 not penetrated by the first sub-via 1. The second insulating layer 17 covers the sidewalls of the first sub-via 1. In this way, the depth of the first sub-via 1 is greater than or equal to the thickness of the DBR reflective layer 16, and the second insulating layer 17 covers the sidewalls of the first sub-via 1. This completely covers the exposed cross-section of the DBR reflective layer on the sidewalls, effectively isolating the silver reflective layer from the second reflective layer in the DBR reflective layer 16, thus preventing the metallic silver from migrating from the second reflective layer of the DBR reflective layer, thereby improving the chip's reliability and lifespan.

[0060] In other embodiments, the film layer adjacent to the DBR reflective layer and the first insulating layer is a first reflective layer (i.e., a composite structure of sequentially arranged first reflective layer, second reflective layer, first reflective layer, second reflective layer, etc., in the direction away from the substrate). When etching to form the first sub-via, while ensuring that the second reflective layer is completely etched away, the first etching may not completely penetrate the DBR reflective layer. A portion of the thickness of the first reflective layer closest to the first insulating layer can be retained, meaning the first reflective layer closest to the first insulating layer is not completely etched through. In the second etching, the remaining first reflective layer and the first insulating layer are simultaneously etched away to form the second sub-via. Thus, the depth of the formed first sub-via is less than that of the DBR reflective layer, and the depth of the second sub-via is the sum of the thickness of the first insulating layer and the thickness of the first reflective layer not penetrated by the first sub-via. In this way, the second insulating layer can still effectively isolate and protect the exposed second reflective layer of the DBR reflective layer in the via, preventing the metallic silver of the silver reflective layer from migrating from the second reflective layer of the DBR reflective layer, thereby further improving the reliability and lifespan of the chip structure.

[0061] In some embodiments, after the second insulating layer 17 is deposited and formed, during the second etching, the first insulating layer 15 and the second insulating layer 17 located in the first via 001 are simultaneously etched to form a second via 002, which exposes a portion of the surface of the N-type doped gallium nitride layer 11.

[0062] The above method forms a patterned DBR reflective layer, a first insulating layer, and a second insulating layer, which effectively protects the DBR reflective layer during the fabrication process.

[0063] The first etching can be ICP etching (inductively coupled ion etching), and the second etching can be ICP etching or BOE etching (buffered oxide etching).

[0064] S5: A silver reflective layer 18 is formed on the side of the second insulating layer 17 away from the substrate 10, and the silver reflective layer 18 fills the via 01. The silver reflective layer 18 is electrically connected to the p-type doped gallium nitride layer 13. Figure 1 As shown.

[0065] In some embodiments, the silver reflective layer can be formed by electron beam evaporation or magnetron sputtering.

[0066] According to some embodiments of the present invention, the method for fabricating an LED chip structure may further include: depositing a metal adhesion layer, wherein a metal adhesion layer is pre-formed before forming a silver reflective layer, i.e., the metal adhesion layer is located between the silver reflective layer and the second insulating layer, thereby improving the adhesion of the silver reflective layer. In some embodiments, the material of the metal adhesion layer includes at least one of chromium, titanium, and nickel.

[0067] According to some embodiments of the present invention, the method for fabricating an LED chip structure may further include: depositing a metal protective layer to form a metal protective layer on the surface of a silver reflective layer to protect the silver reflective layer, i.e., the metal protective layer is formed on the surface of the silver reflective layer away from the substrate. In some embodiments, the material of the metal protective layer includes, but is not limited to, at least one of nickel, titanium, tungsten, and platinum, or an alloy of the above metals.

[0068] According to an embodiment of the present invention, the method for fabricating an LED chip structure further includes: forming a first passivation layer 19, the first passivation layer 19 covering a silver reflective layer 18, and etching the first passivation layer 19 to form a third via 003 and a fourth via 004, the third via 003 exposing a portion of the surface of the silver reflective layer 18, and the fourth via 004 located within the first via 001; forming a first electrode 20 and a second electrode 21 spaced apart, the first electrode 20 being electrically connected to the silver reflective layer 18 through the third via 003, and the second electrode 21 being connected through the fourth via 001. 004 is electrically connected to the N-type doped gallium nitride layer 11; a second passivation layer 22 is formed, which covers a portion of the first electrode 20 and the second electrode 21. The second passivation layer 22 is etched to form a fifth via 005 exposing a portion of the surface of the first electrode 20 and a sixth via 006 exposing a portion of the surface of the second electrode 21; a third electrode 23 and a fourth electrode 24 are formed at intervals, with the third electrode 23 electrically connected to the first electrode 20 through the fifth via 005, and the fourth electrode 24 electrically connected to the second electrode 21 through the sixth via 006. Figure 4 As shown.

[0069] In the above method for preparing LED chip structure, the formation of the second insulating layer can completely isolate the second reflective layer in the DBR reflective layer exposed at the inner wall of the through hole from the silver reflective layer, so that a good physical barrier is formed between the two. In this way, during long-term high temperature and high humidity aging, the metallic silver in the silver reflective layer can be effectively prevented from migrating from the second reflective layer of the DBR reflective layer, thereby improving the reliability and service life of the chip.

[0070] In another aspect, the present invention provides an LED light-emitting device. According to an embodiment of the present invention, the LED light-emitting device includes the LED chip structure described above. Therefore, the LED light-emitting device has good reliability and a long service life. Those skilled in the art will understand that the LED light-emitting device possesses all the features and advantages of the LED chip structure described above, and will not be elaborated further here.

[0071] In some embodiments of the present invention, the LED light-emitting device can be a silver mirror flip-chip high-voltage product, which can be applied to lighting, backlighting and other fields.

[0072] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0073] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An LED chip structure, characterized in that, include: A substrate, and an N-type doped gallium nitride layer, a quantum well layer, a P-type doped gallium nitride layer, and a transparent conductive layer sequentially disposed on one side of the substrate; Also includes: A first insulating layer, at least a portion of which is disposed on the side of the transparent conductive layer away from the substrate; A DBR reflective layer is disposed on the surface of the first insulating layer away from the substrate. The first insulating layer and the DBR reflective layer have multiple vias, and the vias expose the transparent conductive layer. The DBR reflective layer includes alternating first and second reflective layers, and the reflectivity of the second reflective layer is greater than that of the first reflective layer. A second insulating layer is disposed on the side of the DBR reflective layer away from the substrate, and the second insulating layer at least covers the second reflective layer exposed by the via sidewall; A silver reflective layer is disposed on the side of the second insulating layer away from the substrate and fills the via, and is electrically connected to the P-type doped gallium nitride layer.

2. The LED chip structure according to claim 1, characterized in that, In the vertical direction, the through hole includes a first sub-through hole and a second sub-through hole that are connected, and the through hole satisfies one of the following conditions: The first sub-via penetrates at least the DBR reflective layer, the second sub-via penetrates the portion of the first insulating layer that is not penetrated by the first sub-via, and the second insulating layer covers the sidewall of the first sub-via; The film layer adjacent to the first insulating layer of the DBR reflective layer is the first reflective layer. The depth of the first sub-via is less than that of the DBR reflective layer, and the first reflective layer adjacent to the first insulating layer is not penetrated by the first sub-via.

3. The LED chip structure according to claim 2, characterized in that, In the same via, the diameter of the first sub-via is larger than the diameter of the second sub-via, and the orthographic projection of the first sub-via on the substrate covers the orthographic projection of the second sub-via on the substrate.

4. The LED chip structure according to claim 2 or 3, characterized in that, It also meets at least one of the following conditions: The thickness of the second insulating layer is 10~100nm; The material of the second insulating layer includes at least one of aluminum oxide, silicon oxide, silicon nitride, and aluminum nitride; The thickness of the first insulating layer is 50~800nm; The material of the first insulating layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride; The total thickness of the DBR reflective layer is 400~1500nm; The material of the first reflective layer includes at least one of silicon oxide, aluminum oxide, aluminum arsenide, and magnesium fluoride, and the material of the second reflective layer includes at least one of titanium dioxide, tantalum pentoxide, aluminum oxide, and silicon nitride. The thickness of the silver reflective layer is 80~300nm; The depth of the second sub-via is 100~300nm.

5. The LED chip structure according to claim 2 or 3, characterized in that, The P-type doped gallium nitride layer and the quantum well layer have a first via through the P-type doped gallium nitride layer and the quantum well layer, the first via exposing a portion of the surface of the N-type doped gallium nitride layer; The first insulating layer, the DBR reflective layer, and the second insulating layer portion located in the first via have a second via, the second via exposing a portion of the surface of the N-type doped gallium nitride layer; Also includes: A first passivation layer covers the silver reflective layer, the first passivation layer has a third via, the third via exposes a portion of the surface of the silver reflective layer, and the first passivation layer located within the first via has a fourth via. A first electrode and a second electrode are spaced apart, both of which are disposed on the side of the first passivation layer away from the substrate. The first electrode is electrically connected to the silver reflective layer through the third via, and the second electrode is electrically connected to the N-type doped gallium nitride layer through the fourth via. A second passivation layer covers a portion of the first electrode and the second electrode, and has a fifth via that exposes a portion of the surface of the first electrode and a sixth via that exposes a portion of the surface of the second electrode. A third electrode and a fourth electrode are spaced apart. The third electrode is electrically connected to the first electrode through the fifth via, and the fourth electrode is electrically connected to the second electrode through the sixth via.

6. The LED chip structure according to claim 2 or 3, characterized in that, Also includes: A metal adhesion layer is located between the silver reflective layer and the second insulating layer; And / or, a metal protective layer disposed on the surface of the silver reflective layer away from the substrate.

7. A method for preparing an LED chip structure according to any one of claims 1 to 6, characterized in that, include: An N-type doped gallium nitride layer, a quantum well layer, a P-type doped gallium nitride layer, and a transparent conductive layer are sequentially formed on one side of the substrate. A first insulating layer is formed on the side of the transparent conductive layer away from the substrate; A DBR reflective layer is formed on the surface of the first insulating layer away from the substrate. The DBR reflective layer includes an alternately arranged first reflective layer and a second reflective layer, wherein the reflectivity of the second reflective layer is greater than that of the first reflective layer. The DBR reflective layer and the first insulating layer are etched to form a plurality of vias, and the vias expose the transparent conductive layer; A second insulating layer is formed on the side of the DBR reflective layer away from the substrate, and the second insulating layer at least covers the second reflective layer exposed by the sidewall of the via. A silver reflective layer is formed on the side of the second insulating layer away from the substrate, and the silver reflective layer fills the via and is electrically connected to the P-type doped gallium nitride layer.

8. The method according to claim 7, characterized in that, The method of forming the through-hole and the second insulating layer includes: The DBR reflective layer is etched in the first step to form a first sub-via; The second insulating layer is deposited to form a second insulating layer that covers the sidewall of the first sub-via within the first sub-via. The second sub-via is formed by second etching of the second insulating layer within the first sub-via and the corresponding first insulating layer that was not etched by the first etching.

9. The method according to claim 8, characterized in that, Also includes: After forming the P-type doped gallium nitride layer, the P-type doped gallium nitride layer and the quantum well layer are etched to form a first via, the first via exposing a portion of the surface of the N-type doped gallium nitride layer; After the DBR reflective layer is formed, the DBR reflective layer located in the first via is simultaneously etched during the first etching process. After the second insulating layer is deposited and formed, during the second etching, the first insulating layer and the second insulating layer located in the first via are simultaneously etched to form a second via, which exposes a portion of the surface of the N-type doped gallium nitride layer.

10. The method according to claim 9, characterized in that, Also includes: A first passivation layer is formed, which covers the silver reflective layer. The first passivation layer is etched to form a third via and a fourth via. The third via exposes a portion of the surface of the silver reflective layer, and the fourth via is located within the first via. A first electrode and a second electrode are formed at intervals. The first electrode is electrically connected to the silver reflective layer through the third via, and the second electrode is electrically connected to the N-type doped gallium nitride layer through the fourth via. A second passivation layer is formed, which covers a portion of the first electrode and the second electrode. The second passivation layer is etched to form a fifth via that exposes a portion of the surface of the first electrode and a sixth via that exposes a portion of the surface of the second electrode. A third electrode and a fourth electrode are formed at intervals. The third electrode is electrically connected to the first electrode through the fifth via, and the fourth electrode is electrically connected to the second electrode through the sixth via.

11. An LED light-emitting device, characterized in that, The LED chip structure includes any one of claims 1 to 6.

Images