A method for manufacturing a vertical stacked LED integrated chip

Abstract

The application relates to the technical field of LED, in particular to a preparation method of a vertical stacked LED integrated chip, the method is characterized in that: a plurality of groups of luminous bodies with different vertical projection areas are sequentially stacked from bottom to top and from large to small in vertical projection area, and each group of luminous bodies is one-to-one bonded and connected through a bonding layer; a first step and a second step are formed by etching a local area of the bonding layer; and P electrodes and N electrodes are respectively prepared on the first step and the second step, so that a vertical stacked LED integrated chip is prepared; in the LED integrated chip, the P electrodes and the N electrodes are respectively arranged on the first step and the second step at the side of the luminous bodies; the flip structure is realized; the light-emitting surface (the side of the N-type semiconductor layer) is not blocked by the electrodes; the light-emitting efficiency is improved; in addition, when the vertical stacked LED integrated chip is applied, the electrodes are directly connected with the bonding pads in a driving substrate, external leads are not needed, the space occupied by the leads is avoided, and the application of the vertical stacked LED integrated chip in a high-density and high-integration scene is facilitated.

Description

Technical Field

[0001] This invention relates to the field of LED chip technology, and more specifically to a method for fabricating a flip-chip vertically stacked LED integrated chip. Background Technology

[0002] As core components for photoelectric conversion, light emitters are widely used in displays, lighting, backlighting, and other fields. Integrating multiple light emitters yields an LED integrated chip. In traditional LED integrated chips, light emitters are mostly arranged in a planar configuration, which suffers from problems such as large lateral space occupation and low integration density.

[0003] Vertically stacked LED integrated chips are advanced semiconductor optoelectronic devices that integrate multiple light-emitting elements by stacking them vertically into a single unit, effectively improving many problems associated with planar arrangements. However, currently common vertically stacked LED integrated chips have a front-mounted structure, with the electrodes and light-emitting surfaces located on the same side, which is not conducive to light emission. Furthermore, they require external leads to connect to the driving substrate, resulting in a complex structure that limits their application in high-density, high-integration scenarios. Summary of the Invention

[0004] In view of the above-mentioned shortcomings in the prior art, one object of this application is to provide a method for fabricating a vertically stacked LED integrated chip with a flip-chip structure. The LED integrated chip fabricated by this method can effectively reduce the influence of electrodes on light emission and improve light emission efficiency.

[0005] A method for fabricating a vertically stacked LED integrated chip, characterized in that the method includes: A plurality of light emitters are provided, wherein the vertical projection area of ​​the light emitters in the same group is equal, and the vertical projection area of ​​the light emitters in each group is different. Each light emitter includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked together. The side where the N-type semiconductor layer is located is the light-emitting surface, and at least one side of the N-type semiconductor layer protrudes to form a second step. Each group of light-emitting bodies is stacked sequentially from bottom to top and from largest to smallest vertical projection area. Before placing the next group of light-emitting bodies, a bonding layer is pre-set on the surface of the previous group of light-emitting bodies that has been placed. Etching a local area of ​​the bonding layer exposes a local area at the top of the P-type semiconductor layer of each light emitter, forming a first step, and simultaneously exposing the second step; A P-electrode is fabricated on the first step, and an N-electrode is fabricated on the second step. The P-electrode is electrically connected to the P-type semiconductor layer, and the N-electrode is electrically connected to the N-type semiconductor layer.

[0006] Its further feature is that, The light emitter includes a first group of light emitters to an nth group of light emitters. The first group of light emitters includes a plurality of first light emitters, and the nth group of light emitters includes a plurality of nth light emitters. The vertical projected areas of the first group of light emitters to the nth group of light emitters are set to M1 to Mn, respectively, then M1 > M2 > ... > Mn. The bonding layer includes at least a second bonding layer to an nth bonding layer. The second bonding layer is located between the first light emitter and the second light emitter, ... and the nth bonding layer is located between the (n-1)th light emitter and the nth light emitter.

[0007] Furthermore, the light-emitting bodies in each group are stacked sequentially from bottom to top and from largest to smallest vertical projected area. Before placing the next group of light-emitting bodies, a bonding layer is pre-formed on the surface of the previous group of light-emitting bodies, including: A plurality of the first light-emitting elements are transferred to a substrate, with the light-emitting surface of the first light-emitting elements facing the substrate; A second bonding layer is disposed on the electrode side of the first light emitter; Transfer several second light emitters to the second bonding layer, with the second light emitters stacked correspondingly to the first light emitters; A third bonding layer is disposed on the electrode side of the second light emitter; Several third light emitters are transferred to the third bonding layer, and the third light emitters are stacked correspondingly with the second light emitters; And so on; Transfer several nth luminescent elements to the nth bonding layer; The first bonding layer to the nth bonding layer are etched to expose a local area at the top of the P-type semiconductor layer of each of the first light emitters to the nth light emitter, forming a first step, and at the same time exposing the second step.

[0008] Furthermore, when transferring the second light-emitting body to the nth light-emitting body, the axes of the first light-emitting body to the nth light-emitting body are located on the same straight line, or one of the corner lines of the first light-emitting body to the nth light-emitting body is located on the same straight line.

[0009] Furthermore, when n=3, the light emitter includes a first light emitter, a second light emitter, and a third light emitter, and the bonding layer includes a first bonding layer, a second bonding layer, and a third bonding layer. When transferring the second light emitter to the third light emitter, the second light emitter and the first light emitter are staggered laterally, exposing a local area at the top of the P-type semiconductor layer of the first light emitter to form a first-level step. The second light emitter and the third light emitter are staggered longitudinally, exposing a local area at the top of the P-type semiconductor layer of the second light emitter to form a second-level step. The local area at the top of the P-type semiconductor layer of the third light emitter is a third-level step. The first-level step, the second-level step, and the third-level step are used to set the P electrode, and the second step is used to set the N electrode.

[0010] Furthermore, the vertical projected areas of the first bonding layer to the nth bonding layer decrease sequentially, or the vertical projected areas of the first bonding layer to the nth bonding layer are equal.

[0011] Furthermore, the upper surface area of ​​the bonding layer is the same as the lower surface area of ​​the adjacent upper light-emitting body, or the lower surface area of ​​the bonding layer is the same as the upper surface area of ​​the adjacent lower light-emitting body, or the upper surface area of ​​the bonding layer is greater than the lower surface area of ​​the adjacent upper light-emitting body, and the lower surface area of ​​the bonding layer is greater than the upper surface area of ​​the adjacent lower light-emitting body.

[0012] Furthermore, before fabricating the P electrode and N electrode, an insulating layer or an insulating reflective layer is provided on the surface of the first step and the second step, or a conductive material is filled in the bonding layer etching area corresponding to the first step and the second step, and an insulating layer or an insulating reflective layer is provided on the surface of the bonding layer. A local area of ​​the insulating layer or insulating reflective layer is etched to form a first etched hole and a second etched hole; Conductive material is deposited in the first and second etched holes and the corresponding areas to form the P electrode and N electrode. The bottom end of the P electrode penetrates the insulating layer or the insulating reflective layer and is electrically connected to the P-type semiconductor layer. The bottom end of the N electrode penetrates the insulating layer or the insulating reflective layer and is electrically connected to the N-type semiconductor layer.

[0013] Furthermore, the insulating layer includes, but is not limited to, an SO2 layer, a SiNx layer, or an AlN layer.

[0014] Furthermore, the insulating reflective layer includes an insulating DBR reflective layer, which includes alternating stacked SiO2 layers and TiO2 layers; or, the DBR reflective layer includes a static reflective unit, a silicon resonant spacer layer, and a tunable reflective unit stacked sequentially, wherein the tunable reflective unit is disposed away from the non-light-emitting surface of the light emitter, and the tunable reflective unit includes alternating stacked first SiO2 layers and VO2 layers; the static reflective unit includes alternating stacked second SiO2 layers and TiO2 layers; and the silicon resonant spacer layer includes a hydrogenated amorphous silicon layer.

[0015] Furthermore, the insulating reflective layer includes two insulating layers and a reflective layer distributed between the two insulating layers. The reflective layer includes a Ni / Ag / Au metal reflective layer, an ITO / Ag / Tiw hybrid reflective layer, or a DBR reflective layer, and the reflective layer is used for light reflection.

[0016] Furthermore, each of the light emitters also includes a current spreading layer and / or an ohmic contact layer, wherein the current spreading layer is located on the surface of the P-type semiconductor layer, and the P electrode is electrically connected to the P-type semiconductor layer through the current spreading layer; the ohmic contact layer is located on the first step, and the N electrode is electrically connected to the N-type semiconductor layer through the ohmic contact layer.

[0017] Furthermore, the current spreading layer includes, but is not limited to, an ITO layer, an AZO layer, or a GZO layer.

[0018] Furthermore, the P electrodes of each light-emitting body in the same integrated region are connected in series through the anode connection layer to form a common anode structure, or the N electrodes of each light-emitting body in the same integrated region are connected in series through the cathode connection layer to form a common cathode structure.

[0019] Furthermore, in the same LED integrated chip, when the N electrodes of each of the light-emitting elements are connected in series to form a common cathode structure, the electrodes include at least a first P electrode, a second P electrode, a third P electrode, and a common N electrode, where the common N electrode refers to a cathode connection layer that connects the N electrodes in series. When the P electrodes of each of the light-emitting elements are connected in series to form a common anode structure, the electrodes include at least a first N electrode, a second N electrode, a third N electrode, and a common P electrode, where the common P electrode refers to a cathode connection layer that connects the P electrodes in series.

[0020] Furthermore, the first P electrode, the second P electrode, the third P electrode, and the common N electrode are arranged in a rectangular shape; or, the first P electrode, the second P electrode, and the third P electrode are located on one side of the light-emitting body, and the common N electrode is located on the other side of the light-emitting body; or, the first P electrode, the second P electrode, the third P electrode, and the common N electrode are located on adjacent sides of the light-emitting body, respectively.

[0021] Furthermore, the light-emitting bodies in the same group have the same light color, and the light-emitting bodies include at least red LED chips, blue LED chips, and blue LED chips, or the light-emitting bodies in each group have the same light color. The bonding layer includes bonding materials and light-color conversion materials, and the light-color conversion materials include at least quantum dots or phosphors, used to convert the light color of the light-emitting bodies into other colors.

[0022] Furthermore, in the same LED integrated chip, all the monochromatic light emitters emit blue light, the quantum dots include red quantum dots and green quantum dots, the first bonding layer includes the red quantum dots, which is used to convert the light color of the first light emitter into red, the second bonding layer includes transparent quantum dots or does not contain quantum dots, which is used to bond the first light emitter and the second light emitter together and directly transmit the light of the second light emitter, and the third bonding layer includes green quantum dots, which is used to bond the second light emitter and the third light emitter together and convert the light color of the third light emitter into green.

[0023] The technical solution of this application has the following technical advantages: A vertically stacked LED integrated chip is prepared using the method described in this application. In this LED integrated chip, the P electrode and N electrode are respectively disposed on the first and second steps on the side of the light emitter, realizing a flip-chip structure. This ensures that the light-emitting surface (the side where the N-type semiconductor layer is located) is unobstructed by electrodes, effectively improving the light extraction efficiency. Furthermore, when this vertically stacked LED integrated chip is applied, the electrodes directly connect to the pads in the driving substrate, eliminating the need for external leads and avoiding the space occupied by leads. This is beneficial for its application in high-density, high-integration scenarios. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the front view structure of Embodiment 1 of the vertically stacked LED integrated chip of this application; Figure 2 This is a top view of the structure of a first embodiment of the vertically stacked LED integrated chip of this application; Figure 3 This is a schematic diagram of the front view structure of Embodiment 2 of the vertically stacked LED integrated chip of this application; Figure 4 This is a top view of the structure of Embodiment 2 of the vertically stacked LED integrated chip of this application; Figure 5 This is a schematic diagram of the front view structure of Embodiment 3 of the vertically stacked LED integrated chip of this application; Figure 6 This is a top view of the structure of Embodiment 3 of the vertically stacked LED integrated chip of this application; Figure 7 This is a schematic diagram of the front view structure of Embodiment 4 of the vertically stacked LED integrated chip of this application; Figure 8 This is a top view of Embodiment 4 of the vertically stacked LED integrated chip of this application; Figure 9 This is a schematic diagram of the front view structure of Embodiment 5 of the vertically stacked LED integrated chip of this application; Figure 10 This is a top view of Embodiment 5 of the vertically stacked LED integrated chip of this application; Figure 11 This is a schematic diagram of the front view structure of Embodiment Six of the Vertically Stacked LED Integrated Chip of this application; Figure 12 This is a top view of Embodiment Six of the Vertically Stacked LED Integrated Chip of this Application; Figure 13 This is a schematic diagram of the front view structure of Embodiment 7 of the vertically stacked LED integrated chip of this application; Figure 14 This is a top view of Embodiment 7 of the vertically stacked LED integrated chip of this application; Figure 15 This is a schematic diagram of the front view structure of Embodiment 8 of the vertically stacked LED integrated chip of this application; Figure 16 This is a top view of Embodiment 8 of the vertically stacked LED integrated chip of this application; Figure 17 This is a schematic diagram of the front view structure of Embodiment 9 of the vertically stacked LED integrated chip of this application; Figure 18 This is a schematic diagram of the front view structure of Embodiment 10 of the vertically stacked LED integrated chip of this application; Figure 19 This is a schematic diagram of the front view structure of Embodiment Eleven of the Vertically Stacked LED Integrated Chip of this Application; Figure 20 This is a schematic diagram of the front view structure of Embodiment Twelve of the Vertically Stacked LED Integrated Chip of this Application; Figure 21 This is a schematic diagram of the front view structure of Embodiment Thirteen of the Vertically Stacked LED Integrated Chip of this Application; Figure 22 This is a schematic diagram of the front view structure of Embodiment Fourteen of the vertically stacked LED integrated chip of this application; Figure 23 This is a schematic diagram of the front view structure of Embodiment 15 of the vertically stacked LED integrated chip of this application; Figure 24 This is a schematic diagram of the front view structure of Embodiment Sixteen of the vertically stacked LED integrated chip of this application; Figure 25 This is a schematic diagram of the front view structure of Embodiment Seventeen of the Vertically Stacked LED Integrated Chip of this application; Figure 26 This is a schematic diagram of the front view structure of Embodiment 18 of the vertically stacked LED integrated chip of this application; Figure 27 This is a schematic diagram of the front view structure of Embodiment Nineteen of the Vertically Stacked LED Integrated Chip of this application; Figure 28 This is a schematic diagram of the front view structure of Embodiment 20 of the vertically stacked LED integrated chip of this application; Figure 29 This is a schematic diagram of the front view structure of Embodiment 21 of the vertically stacked LED integrated chip of this application; Figure 30 This is a top view of embodiment twenty-one of the vertically stacked LED integrated chips of this application; Figure 31 This is a structural schematic diagram of the fabrication process of the first intermediate component of the vertically stacked LED integrated chip in this application; Figure 32 This is a schematic diagram of the structure during the fabrication process of the second intermediate component of the vertically stacked LED integrated chip in this application; Figure 33 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment 1 of this application; Figure 34 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment 2 of this application; Figure 35 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment 3 of this application; Figure 36 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment 4 of this application; Figure 37 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment 5 of this application; Figure 38 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment Six of this application; Figure 39 This is a schematic diagram of the fabrication process of Embodiment 7 of the vertically stacked LED integrated chip of this application; Figure 40This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment 8 of this application; Figure 41 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment Nine of this application; Figure 42 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment 10 of this application; Figure 43 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment Eleven of this application; Figure 44 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment Twelve of this application; Figure 45 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment Thirteen of this application; Figure 46 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip in Embodiment Fourteen of this application; Figure 47 This is a schematic diagram of the fabrication process of the vertically stacked LED integrated chip embodiment twenty-one of this application.

[0026] Reference numerals: First light-emitting body 101, Second light-emitting body 102, Third light-emitting body 103; N electrode 201, P electrode 202; First bonding layer 301, second bonding layer 302, third bonding layer 303; N-type semiconductor layer 1001, P-type semiconductor layer 1002; 1. Substrate; 4. First step; 5. Second step; 6. Common N electrode; 7. Insulating layer or insulating reflective layer. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product or device.

[0029] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0030] The following discloses specific embodiments of several methods for fabricating vertically stacked LED integrated chips. First, a first intermediate component of the vertically stacked LED integrated chip is fabricated, referring to... Figure 31 The specific preparation steps of the first intermediate component include: X1. Provide several groups of light-emitting bodies, including a first group of light-emitting bodies to a nth group of light-emitting bodies. The first group of light-emitting bodies includes several first light-emitting bodies 101, the second group of light-emitting bodies includes several second light-emitting bodies 102, and the nth group of light-emitting bodies includes several nth light-emitting bodies. The vertical projection area of ​​the light-emitting bodies in the same group is equal, and the vertical projection area of ​​each group of light-emitting bodies is not equal. Set the vertical projection areas of the first light-emitting bodies 101 to the nth light-emitting bodies to be M1 to Mn respectively, then M1 > M2 > ... > Mn.

[0031] Each light emitter includes an N-type semiconductor layer 1001, a light-emitting layer, and a P-type semiconductor layer 1002 stacked together. The side where the N-type semiconductor layer is located is the light-emitting surface, and at least one side of the N-type semiconductor layer 1001 protrudes to form a second step 5.

[0032] X2. Stack the light-emitting bodies sequentially from bottom to top, with the vertical projected area decreasing in size. The first light-emitting body 101, the second light-emitting body 102 to the nth light-emitting body are distributed in a stepped manner from bottom to top, and the axes of the first light-emitting body 101, the second light-emitting body 102 to the nth light-emitting body are located on the same straight line, thus obtaining an integrated body with several arrays. It should be noted that before placing the next group of light-emitting bodies, a bonding layer is pre-set on the surface of the previous group of light-emitting bodies. The bonding layer includes the first bonding layer 301 to the nth bonding layer, specifically: X21. Using a mass transfer process, a number of first light emitters 101 are transferred to the substrate, and the first light emitters 101 are arrayed. The light-emitting surface of the first light emitter 101 faces the substrate. Before transferring the first light emitter 101, a bonding layer material is pre-formed on the substrate 1 by means of coating or film application to form a first bonding layer 301. The first light emitter 101 is bonded to the substrate 1 through the first bonding layer 301. The substrate 1 is a light-transmitting substrate, which includes a glass substrate or a sapphire substrate, preferably a glass substrate.

[0033] It should be noted that, in another embodiment, the first bonding layer 301 may not be provided, and the first light-emitting body 101 may be directly transferred to the substrate before subsequent coating or film application. In this process, in order to prevent the first light-emitting body 101 from shifting, a positioning groove may be pre-formed in the substrate 1 and the first light-emitting body 101 may be placed in the positioning groove. X22. Using an adhesive coating process or a film lamination process, a bonding layer material is disposed on the side where the electrode of the first light emitter 101 is located to form a second bonding layer 302. X23. Using a mass transfer process, several second light emitters 102 are transferred to the second bonding layer 302. The second light emitters 102 and the first light emitters 101 are stacked vertically and correspondingly. One side edge of the second light emitters 102 and the first light emitters 101 are staggered to form a first step. The axes of the second light emitters 102 and the first light emitters 101 are on the same straight line. The first step and the second step 5 are distributed on opposite sides of the second light emitters. X24. Using an adhesive coating process or a film lamination process, a bonding layer material is disposed on the side where the electrode of the second light emitter 102 is located to form a third bonding layer 303. X25. Using a mass transfer process, the third light-emitting body 103 is transferred to the third bonding layer 303. The third light-emitting body 103 and the second light-emitting body 102 are stacked vertically and their edges intersect to form a first step. The axes of the third light-emitting body 103, the second light-emitting body 102, and the first light-emitting body 101 are on the same straight line. Similarly, several nth light-emitting bodies are transferred to the nth bonding layer to obtain the first intermediate component.

[0034] Fabrication of a second intermediate component for vertically stacked LED integrated chips, reference Figure 32 The specific preparation steps for the second intermediate component include: Y1. Provide several groups of light-emitting bodies, including a first group of light-emitting bodies to a nth group of light-emitting bodies. The first group of light-emitting bodies includes several first light-emitting bodies 101, and the nth group of light-emitting bodies includes several nth light-emitting bodies. The vertical projection area of ​​the light-emitting bodies in the same group is equal, and the vertical projection area of ​​each group of light-emitting bodies is not equal. Set the vertical projection areas of the first light-emitting bodies 101 to the nth light-emitting bodies to be M1 to Mn respectively, then M1 > M2 > ... > Mn.

[0035] Each light emitter includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked together. The side containing the N-type semiconductor layer is the light-emitting surface, and at least one side of the N-type semiconductor layer protrudes to form a second step 5.

[0036] Y2. The light-emitting bodies are stacked vertically from bottom to top, with their vertical projected areas decreasing in size. The first light-emitting body 101, the second light-emitting body 102, and the third light-emitting body 103 are arranged in a stepped pattern from bottom to top. One corner of each light-emitting body 101, the second light-emitting body 102, and the third light-emitting body 103 lies on the same straight line, resulting in an integrated body with several arrays. Before placing the next group of light-emitting bodies, a bonding layer is pre-formed on the surface of the previous group of light-emitting bodies. The bonding layer includes the first bonding layer 301 to the nth bonding layer, specifically: Y21. Using a mass transfer process, a number of first light emitters 101 are transferred to the substrate, and the first light emitters 101 are distributed in an array. The light-emitting surface of the first light emitter 101 faces the substrate. Before transferring the first light emitter 101, a bonding layer material is pre-deposited on the substrate 1 by means of coating or film application to form a first bonding layer 301. The first light emitter 101 is bonded to the substrate 1 through the first bonding layer 301. It should be noted that, in another embodiment, the first bonding layer 301 may not be provided, and the first light-emitting body 101 may be directly transferred to the substrate before subsequent coating or film application. In this process, in order to prevent the first light-emitting body 101 from shifting, a positioning groove may be pre-formed in the substrate and the first light-emitting body 101 may be placed in the positioning groove. Y22. Using a coating process or a film-applying process, a bonding layer material is provided on the side where the electrode of the first light-emitting body 101 is located to form a second bonding layer 302. Y23. Using a mass transfer process, several second light emitters 102 are transferred to the second bonding layer 302. The second light emitters 102 and the first light emitters 101 are stacked vertically and their edges intersect to form a first step. The corner lines of the second light emitters 102 and the first light emitters 101 are on the same straight line. The first step and the second step 5 are distributed on the adjacent sides of the second light emitters. Y24. Using a coating process or a film-applying process, a bonding layer material is provided on the side where the electrode of the second light-emitting body 102 is located, and a third bonding layer 303 is provided on the surface of the second light-emitting body 102. Y25. Using a mass transfer process, the third light-emitting body 103 is transferred to the third bonding layer 303. The third light-emitting body 103 and the second light-emitting body 102 are stacked vertically and their edges intersect to form a first step. The corner lines of the third light-emitting body 103, the second light-emitting body 102, and the first light-emitting body 101 are on the same straight line. Similarly, several nth light-emitting bodies are transferred to the nth bonding layer to obtain the second intermediate component.

[0037] Based on the aforementioned first or second intermediate component, a vertically stacked LED integrated chip is fabricated. Taking n=3 as an example, the light emitter includes a first light emitter 101, a second light emitter 102, and a third light emitter 103, and the bonding layer includes a first bonding layer 301, a second bonding layer 302, and a third bonding layer 303.

[0038] Example 1: Method for fabricating vertically stacked LED integrated chips, refer to Figure 33 The method includes steps X1 and X2 as described above, and also includes the following steps: X3. Using photolithography etching, the first bonding layer 301 to the third bonding layer 303 are etched, exposing a partial area at the top of the first step of the first light emitter 101 to the third light emitter 103, and simultaneously exposing the second step 5. After etching, the vertical projected area of ​​the first bonding layer 301 to the third bonding layer 303 decreases sequentially from bottom to top, and is equal to the lower surface area of ​​the adjacent upper light emitter.

[0039] X4. Using electron beam evaporation or magnetron sputtering deposition, conductive materials are deposited on the first step 4 and the second step 5 to form P electrode 202 and N electrode 201. The first step 4 and P electrode 202, and the second step 5 and N electrode 201 are distributed on opposite sides of the light emitter.

[0040] X5. Cut based on the gap between two adjacent integrated units to obtain an independent vertically stacked LED integrated chip of Embodiment 1.

[0041] Example 1: A vertically stacked LED integrated chip was prepared using the above method. Figure 1 , Figure 2 As shown, it includes light emitters and electrodes. The light emitters include a first light emitter 101 to an nth light emitter arranged in a stacked manner from bottom to top (i.e., vertically stacked, with the vertical direction being the Z direction). Each light emitter includes an N-type semiconductor layer 1001, a light-emitting layer, and a P-type semiconductor layer 1002 stacked together. The electrodes include a P electrode 202 and an N electrode 201.

[0042] In this embodiment, n is 3, so the light emitters include: a first light emitter 101, a second light emitter 102, and a third light emitter 103. The first light emitter 101, the second light emitter 102, and the third light emitter 103 are respectively a red LED chip, a green LED chip, and a blue LED chip, emitting red light, blue light, and green light respectively. The red, blue, and green light are mixed to achieve color display. In this embodiment, the size of the light emitters is less than 100μm, preferably a Micro LED less than 50μm.

[0043] Adjacent light emitters are bonded together by bonding layers, which include a first bonding layer 301 to an (n-1)th bonding layer. When n is 3, the bonding layers include a first bonding layer 301, a second bonding layer 302, and a third bonding layer 303. The first bonding layer 301 covers the light-emitting surface of the first light emitter 101. The first light emitter 101 and the second light emitter 102 are bonded together by the second bonding layer 302, and the second light emitter 102 and the third light emitter 103 are bonded together by the third bonding layer 303. The bonding layer materials include, but are not limited to, epoxy resin, polyimide (PI), benzocyclobutene (BCB), and poly(p-phenylenebenzodioxazole) (PBO). In this embodiment, polyimide is preferred. In this embodiment, the vertical projected areas of the first bonding layer 301 to the third bonding layer 303 decrease sequentially from bottom to top, and the upper surface areas of the first bonding layer to the third bonding layer are equal to the lower surface areas of the adjacent upper light emitter. Under this structure, the P electrode 202 is directly electrically connected to the P-type semiconductor layer 1002.

[0044] It should be noted that, in another embodiment, the first light emitter 101, the second light emitter 102, and the third light emitter 103 are all blue LED chips. The bonding layer between two adjacent light emitters includes epoxy resin and a light color conversion material. The light color conversion material is preferably quantum dots. Quantum dots are used to convert the blue light emitted by the blue LED chip into other colors. For example, the first bonding layer 301 contains red quantum dots to convert the light color of the first light emitter 102 into red light. The second bonding layer 302 contains transparent quantum dots or does not contain quantum dots to directly transmit the blue light emitted by the second light emitter 102. The third bonding layer 303 contains blue quantum dots to convert the light color of the third light emitter 103 into green light. The red, green, and blue light colors are mixed to achieve color display.

[0045] To facilitate the placement of the P-electrode 202 and N-electrode 201, the light-emitting elements in this application are arranged in a stepped pattern from bottom to top, with one top side of the light-emitting element (i.e., the top side where the P-type semiconductor layer is located) exposed, forming a first step 4. At least one side of the N-type semiconductor layer protrudes to form a second step 5. The P-electrode 202 is located on the first step 4 and electrically connected to the P-type semiconductor layer, while the N-electrode 201 is located on the second step 5 and electrically connected to the N-type semiconductor layer. Furthermore, the central axes of the first light-emitting element 101, the second light-emitting element 102, and the third light-emitting element 103 are aligned on the same straight line, with the first step 4 and the P-electrode 202, and the second step 5 and the N-electrode 201 distributed on opposite sides of the light-emitting elements.

[0046] Example 2: Method for fabricating vertically stacked LED integrated chips, refer to Figure 34 The method includes steps Y1 and Y2 as described above, and also includes the following steps: Y3 employs photolithography etching to etch the first bonding layer 301 to the third bonding layer 303, exposing a partial area at the top of the first step of the first light emitter 101 to the third light emitter 103, while simultaneously exposing the second step 5. After etching, the vertical projected area of ​​the first bonding layer 301 to the third bonding layer 303 decreases sequentially from bottom to top, becoming equal to the lower surface area of ​​the adjacent upper light emitter.

[0047] Y4. Using electron beam evaporation or magnetron sputtering deposition, conductive materials are deposited on the first step 4 and the second step 5 to form P electrode 202 and N electrode 201. The first step 4 and P electrode 202, and the second step 5 and N electrode 201 are distributed on adjacent sides of the light emitter.

[0048] Y5. Cut based on the gap between two adjacent integrated bodies to obtain an independent vertically stacked LED integrated chip as described in Example 2.

[0049] Example 2: A vertically stacked LED integrated chip was prepared using the above method. (Refer to...) Figure 3 , Figure 4 In this second embodiment, the structure of the light source and bonding layer is the same as in the first embodiment. The difference from the first embodiment is that one of the corner lines of the first light source 101, the second light source 102, and the third light source 103 are located on the same straight line, and the first step 4 and the P electrode 202, and the second step 5 and the N electrode 201 are located on adjacent sides of the light source.

[0050] It should be noted that this application does not specifically limit the distribution positions of P electrode 202, N electrode 201, first step 4, and second step 5; each distribution position can be flexibly designed according to the corresponding method of the light-emitting body.

[0051] Example 3: Method for fabricating vertically stacked LED integrated chips, refer to Figure 35The method includes steps X1 and X2 as described above, and also includes the following steps: X3. Using photolithography etching, the first bonding layer 301 to the third bonding layer 303 are etched, exposing a partial area at the top of the first step of the first light emitter 101 to the third light emitter 103, and simultaneously exposing the second step 5. After etching, the vertical projected area of ​​the first bonding layer 301 to the third bonding layer 303 decreases sequentially from bottom to top, and is equal to the upper surface area of ​​the adjacent lower light emitter.

[0052] X4. Using electron beam evaporation or magnetron sputtering deposition, conductive materials are deposited on the first step 4 and the second step 5 to form P electrode 202 and N electrode 201. The first step 4 and P electrode 202, and the second step 5 and N electrode 201 are distributed on opposite sides of the light emitter.

[0053] X5. Cut based on the gap between two adjacent integrated units to obtain an independent vertically stacked LED integrated chip as described in Example 3.

[0054] Example 3, which describes the preparation of a vertically stacked LED integrated chip using the above method, is referenced. Figure 5 , Figure 6 In this third embodiment, the structure and arrangement of the light emitters are the same as in the first embodiment. The difference from the first embodiment is that the area of ​​the lower surface of the bonding layer is equal to the area of ​​the upper surface of the adjacent lower light emitter, which is beneficial to improving the electrical isolation effect. In this structure, the bottom ends of the first P electrode and the second P electrode need to penetrate through the corresponding first bonding layer 301 and second bonding layer 302 and then be electrically connected to the P-type semiconductor layer of the first light emitter 101 and the second light emitter 102, respectively. The third electrode is directly electrically connected to the P-type semiconductor layer of the third light emitter 103.

[0055] Example 4: Method for fabricating vertically stacked LED integrated chips, refer to Figure 36 The method includes steps Y1 and Y2 as described above, and also includes the following steps: Y3 employs photolithography etching to etch the first bonding layer 301 to the third bonding layer 303, exposing a partial area at the top of the first step of the first light emitter 101 to the third light emitter 103, while simultaneously exposing the second step 5. After etching, the vertical projected area of ​​the first bonding layer 301 to the third bonding layer 303 decreases sequentially from bottom to top, becoming equal to the upper surface area of ​​the adjacent lower light emitter.

[0056] Y4. Using electron beam evaporation or magnetron sputtering deposition, conductive materials are deposited on the first step 4 and the second step 5 to form P electrode 202 and N electrode 201. The first step 4 and P electrode 202, and the second step 5 and N electrode 201 are distributed on adjacent sides of the light emitter.

[0057] Y5. Cut based on the gap between two adjacent integrated units to obtain an independent vertically stacked LED integrated chip as described in Example 4.

[0058] Example 4: A vertically stacked LED integrated chip was prepared using the above method. (Refer to...) Figure 7 , Figure 8 In this fourth embodiment, the structure and arrangement of the light emitters are the same as in the second embodiment. The difference between this fourth embodiment and the second embodiment is that the area of ​​the lower surface of the bonding layer is equal to the area of ​​the upper surface of the adjacent lower light emitter, which is beneficial to improving the electrical isolation effect. In this structure, the bottom ends of the first P electrode and the second P electrode need to penetrate through the corresponding first bonding layer 301 and second bonding layer 302 and then be electrically connected to the P-type semiconductor layer of the first light emitter 101 and the second light emitter 102, respectively. The third electrode is directly electrically connected to the P-type semiconductor layer of the third light emitter 103.

[0059] Example 5: Method for fabricating vertically stacked LED integrated chips, refer to Figure 37 The method includes steps X1 and X2 as described above, and also includes the following steps: X3. Using photolithography etching, the first bonding layer 301 to the third bonding layer 303 are etched, exposing a partial area at the top of the first step of the first light emitter 101 to the third light emitter 103, and simultaneously exposing the second step 5. After etching, the vertical projected areas of the first bonding layer 301 to the third bonding layer 303 are equal, and each is larger than the upper surface area of ​​the adjacent lower light emitter and the lower surface area of ​​the adjacent upper light emitter.

[0060] X4. Using electron beam evaporation or magnetron sputtering deposition, conductive materials are deposited on the first step 4 and the second step 5 to form P electrode 202 and N electrode 201. The first step 4 and P electrode 202, and the second step 5 and N electrode 201 are distributed on opposite sides of the light emitter.

[0061] X5. Cut based on the gap between two adjacent integrated units to obtain an independent vertically stacked LED integrated chip as described in Example 5.

[0062] Example 5, which describes the preparation of a vertically stacked LED integrated chip using the above method, is referenced. Figure 9 , Figure 10 In this fifth embodiment, the structure and arrangement of the light-emitting body are the same as in the first embodiment. The difference between this fifth embodiment and the first embodiment is that the vertical projection areas of the first bonding layer 301 to the (n-1)th bonding layer are equal and all larger than the vertical projection area of ​​the first light-emitting body. This structure is beneficial to further improve the electrical isolation effect, and at the same time, it is beneficial to obtain a more stable LED integrated chip. It is also beneficial to keep the surfaces of the P electrode 202 and the N electrode 201 flush, so as to facilitate subsequent flip-chip alignment and connection with the driving substrate.

[0063] Example 6: Method for fabricating vertically stacked LED integrated chips, refer to Figure 38 The method includes steps Y1 and Y2 as described above, and also includes the following steps: Y3 employs photolithography etching to etch the first bonding layer 301 to the third bonding layer 303, exposing a partial area at the top of the first step of the first light emitter 101 to the third light emitter 103, and simultaneously exposing the second step 5. After etching, the vertical projected areas of the first bonding layer 301 to the third bonding layer 303 are equal, and each is larger than the upper surface area of ​​the adjacent lower light emitter and the lower surface area of ​​the adjacent upper light emitter.

[0064] Y4. Conductive materials are deposited on the first step 4 and the second step 5 using electron beam evaporation or magnetron sputtering to form P electrode 202 and N electrode 201. The first step 4 and P electrode 202, and the second step 5 and common N electrode 6 are distributed on adjacent sides of the light emitter.

[0065] Y5. Cut based on the gap between two adjacent integrators to obtain an independent vertically stacked LED integrated chip as described in Example 6.

[0066] Example 6, which describes the preparation of a vertically stacked LED integrated chip using the above method, is referenced. Figure 11 , Figure 12 In this sixth embodiment, the structure and arrangement of the light-emitting body are the same as in the second embodiment. The difference between this sixth embodiment and the second embodiment is that the vertical projection areas of the first bonding layer 301 to the (n-1)th bonding layer are equal and all larger than the vertical projection area of ​​the first light-emitting body. This structure is beneficial to further improve the electrical isolation effect, and at the same time, it is beneficial to obtain a more stable LED integrated chip. It is also beneficial to keep the surfaces of the P electrode 202 and the N electrode 201 flush, so as to facilitate subsequent flip-chip alignment and connection with the driving substrate.

[0067] Example 7: Method for fabricating vertically stacked LED integrated chips, refer to Figure 39 The method includes steps X1 and X2 as described above, and also includes the following steps: X3. Using photolithography etching, the first bonding layer 301 to the third bonding layer 303 are etched, exposing a partial area at the top of the first step of the first light emitter 101 to the third light emitter 103, and simultaneously exposing the second step 5. After etching, the first bonding layer 301 to the third bonding layer 303 cover the lower surface of the adjacent upper light emitter and the upper surface of the adjacent lower light emitter. The vertical projected areas of the first bonding layer 301 to the third bonding layer 303 are equal, and each is larger than the upper surface area of ​​the adjacent lower light emitter and the lower surface area of ​​the adjacent upper light emitter.

[0068] X4. Using electron beam evaporation or magnetron sputtering deposition, conductive materials are deposited on the first step 4 and the second step 5 to form P electrode 202 and N electrode 201. The N electrode 201 is connected through a cathode connection layer to form a common cathode structure, i.e., a common N electrode 6. The first step 4 and the P electrode 202, and the second step 5 and the common N electrode 6 are distributed on opposite sides of the light emitter.

[0069] X5. Cut based on the gap between two adjacent integrated units to obtain an independent vertically stacked LED integrated chip as described in Example 7.

[0070] Example 8: Method for fabricating vertically stacked LED integrated chips, refer to Figure 40 The method includes steps Y1 and Y2 as described above, and also includes the following steps: Y3 employs photolithography etching to etch the first bonding layer 301 to the third bonding layer 303, exposing a partial area at the top of the first step of the first light emitter 101 to the third light emitter 103, and simultaneously exposing the second step 5. The first step 4 and the second step 5 are distributed on adjacent sides of the light emitter. After etching, the vertical projected areas of the first bonding layer 301 to the third bonding layer 303 are equal, and each is larger than the upper surface area of ​​the adjacent lower light emitter and the lower surface area of ​​the adjacent upper light emitter.

[0071] Y4. Using electron beam evaporation or magnetron sputtering deposition, conductive materials are deposited on the first step 4 and the second step 5 to form P electrode 202 and N electrode 201. N electrode 201 is connected through a cathode connection layer to form a common cathode structure, i.e., a common N electrode 6. The first step 4 and P electrode 202, and the second step 5 and common N electrode 6 are distributed on adjacent sides of the light emitter.

[0072] Y5. Cut based on the gap between two adjacent integrated units to obtain an independent vertically stacked LED integrated chip as described in Example 8.

[0073] Vertically stacked LED integrated chips were prepared using the above methods in Examples 7 and 8. The difference between Examples 7 and 8 and Examples 5 and 6 is that the P-electrode 202 or N-electrode 201 are connected in series through a cathode connection layer or an anode connection layer to form a common cathode structure or a common anode structure. This simplifies the external driving circuit. Taking the common cathode structure as an example, refer to... Figures 13-16 In addition, the vertical projected areas of the first bonding layer 301 to the third bonding layer 303 are equal and are all larger than the vertical projected area of ​​the first light emitter 101. This is beneficial for keeping the surfaces of the first P electrode, the second P electrode, the third P electrode and the common N electrode 6 flush.

[0074] Example 9: Method for fabricating vertically stacked LED integrated chips, refer to Figure 41The method includes the fabrication steps X1, X2, and X3 of the vertically stacked LED integrated chip in Example 1; Example 10: Method for fabricating vertically stacked LED integrated chips, refer to Figure 42 The method includes the fabrication steps Y1, Y2, and Y3 of the vertically stacked LED integrated chip in Example 2; Example 11: Method for fabricating vertically stacked LED integrated chips, refer to Figure 43 The method includes the fabrication steps X1, X2, and X3 of the vertically stacked LED integrated chip in Example 3; Example 12: Method for fabricating vertically stacked LED integrated chips, refer to Figure 44 The method includes the fabrication steps Y1, Y2, and Y3 of the vertically stacked LED integrated chip in Example 4; Example 13: Method for fabricating vertically stacked LED integrated chips, refer to Figure 45 The method includes the fabrication steps X1, X2, and X3 of the vertically stacked LED integrated chip in Example 5; Example 14: Method for fabricating vertically stacked LED integrated chips, refer to Figure 46 The method includes the fabrication steps Y1, Y2, and Y3 of the vertically stacked LED integrated chip in Example 6; The fabrication methods of vertically stacked LED integrated chips in Examples 9 to 12 above each include step X4 / Y4, which includes: Before X41 / Y41, P electrode 202 and N electrode 201 are prepared, an insulating layer or insulating reflective layer 7 is deposited on the surface of the first step 4 and the second step 5 by a deposition process. The deposition process includes magnetron sputtering or plasma-enhanced chemical vapor deposition. X42 / Y42: Using photolithography etching process, local areas of the insulating layer or insulating reflective layer 7 corresponding to the first step 4 and the second step 5 are etched to form the first etched hole and the second etched hole. X43 / Y43 uses magnetron sputtering or electron beam evaporation to deposit conductive materials in the first and second etched holes and corresponding areas to form P electrode 202 and N electrode 201. The first step 4 and P electrode 202, and the second step 5 and N electrode 201 are distributed on opposite sides or adjacent sides of the light emitter.

[0075] X5 / Y5, based on the gap between two adjacent integrators, is cut to obtain an independent vertically stacked LED integrated chip of Embodiment 1.

[0076] The fabrication methods of vertically stacked LED integrated chips in Examples 13 and 14 further include step X4 / Y4, which includes: X41 / Y41 uses magnetron sputtering or electron beam evaporation to fill the etched areas of the first bonding layer 301 and the second bonding layer 302 corresponding to the first step 4 and the second step 5 with conductive material. X42 / Y42, an insulating layer or insulating reflective layer 7 is deposited on the surface of the second bonding layer 302 using a deposition process, including magnetron sputtering or plasma-enhanced chemical vapor deposition. X43 / Y43 uses photolithography etching process to etch a local area of ​​the insulating layer or insulating reflective layer 7 to form a first etch hole and a second etch hole. The first etch hole and the second etch hole correspond to the conductive material areas filled in the first bonding layer 301 and the second bonding layer 302. X43 / Y43: Using magnetron sputtering or electron beam evaporation, conductive materials are deposited in the first and second etched holes and corresponding areas to form P electrode 202 and N electrode 201. The first step 4 and P electrode 202, and the second step 5 and N electrode 201 are distributed on opposite or adjacent sides of the light-emitting body. X5 / Y5, based on the gap between two adjacent integrators, is cut to obtain independent vertically stacked LED integrated chips as described in Embodiment Thirteen or Embodiment Fourteen.

[0077] Vertically stacked LED integrated chips were prepared using the methods described above in Examples 9 to 14, as referenced. Figures 17-22 In embodiments nine to fourteen, an insulating layer or an insulating reflective layer 7 is provided on the basis of the structure of embodiments one to eight above. The insulating layer is used to achieve insulation between the N electrode 201 and the P electrode 202, and the insulating reflective layer is used for light reflection and insulation between the N electrode 201 and the P electrode 202.

[0078] In Examples 9 to 12, an insulating layer or insulating reflective layer 7 covers the surfaces of the first step 4 and the second step 5. The bottom end of the P electrode 202 penetrates the insulating layer or insulating reflective layer 7 and is electrically connected to the P-type semiconductor layer. The bottom end of the N electrode 201 penetrates the insulating layer or insulating reflective layer 7 and is electrically connected to the N-type semiconductor layer.

[0079] In Examples 13 and 14, an insulating layer or insulating reflective layer 7 covers the surface of the third bonding layer. The bottom end of the P electrode 202 penetrates the insulating layer or insulating reflective layer 7 and the bonding layer and is electrically connected to the P-type semiconductor layer. The bottom end of the N electrode 201 penetrates the insulating layer or insulating reflective layer 7 and the bonding layer and is electrically connected to the N-type semiconductor layer.

[0080] In one specific embodiment, when an insulating layer is provided, the insulating layer includes an SO2 layer, a SiNx layer, or an AlN layer, with SiO2 being preferred in this embodiment.

[0081] In another specific embodiment, when an insulating reflective layer is provided, the insulating reflective layer includes an insulating DBR insulating layer, and the insulating DBR reflective layer includes alternating stacked SiO2 layers and TiO2 layers, or the DBR reflective layer includes a static reflective unit, a silicon resonant spacer layer, and a tunable reflective unit stacked sequentially. The tunable reflective unit is disposed away from the light emitter and is composed of alternating stacked first SiO2 layers and VO2 layers. The static reflective unit includes alternating stacked second SiO2 layers and TiO2 layers, and the silicon resonant spacer layer includes a hydrogenated amorphous silicon layer.

[0082] It should be noted that, in other embodiments, when an insulating reflective layer is provided, the insulating reflective layer includes two insulating layers and a reflective layer distributed between the two insulating layers. The reflective layer includes a Ni / Ag / Au metal reflective layer, an ITO / Ag / Tiw hybrid reflective layer, or a DBR reflective layer, and the reflective layer is used for light reflection.

[0083] It should also be noted that in embodiments one through fourteen, the structure of the light emitter is the same. In another embodiment, each light emitter further includes a current spreading layer and an ohmic contact layer. The current spreading layer is located on the surface of the P-type semiconductor layer and is used for current spreading. The P electrode 202 is electrically connected to the P-type semiconductor layer through the current spreading layer. The ohmic contact layer is located on the first step 4, and the N electrode 201 is electrically connected to the N-type semiconductor layer through the ohmic contact layer. The current spreading layer includes an ITO layer, an AZO layer, or a GZO layer, preferably an ITO layer. The bottom end of the N electrode 201 penetrates the reflective layer and is electrically connected to the N-type semiconductor layer. The bottom end of the P electrode 202 penetrates the reflective layer and is sequentially electrically connected to the current spreading layer and the P-type semiconductor layer. In other embodiments, the upper surfaces of the N electrode 201 and the P electrode 202 can be kept flush to facilitate flip-chip alignment of the vertically stacked LED integrated chip with the driving substrate.

[0084] The fabrication methods of vertically stacked LED integrated chips in Examples 15 to 20 include the fabrication steps X1 / Y1 to X5 / Y5 of the vertically stacked LED integrated chips in Examples 9 to 14 above. The difference between these methods and those in Examples 9 to 14 is that, when fabricating the P electrode and N electrode, taking the fabrication of the common N electrode 6 as an example, conductive materials are deposited in the first etched hole and the second etched hole, and the conductive materials in the second etched hole are electrically connected through the conductive materials to obtain the P electrode 202 and the common N electrode 6.

[0085] Vertically stacked LED integrated chips were prepared using the methods described above, as shown in Examples 15-20. (Refer to...) Figures 23-28In Examples 15 to 20, the P electrode 202 or N electrode 201 in Examples 9 to 14 are connected in series through the anode connection layer or the cathode connection layer to form a common cathode structure or a common anode structure, respectively. This is beneficial to simplify the external driving circuit. In addition, the setting of the insulating layer or insulating reflective layer 7 is beneficial to the preparation and formation of a common cathode structure or a common anode structure. Taking the common cathode structure as an example.

[0086] In this application, no specific limitation is made on the stacking method of the light-emitting elements from bottom to top. It should be noted that in the above embodiments, the distribution method in which the axes of the light-emitting elements are located on the same straight line is suitable for rectangular or circular light-emitting elements, but it is not conducive to saving horizontal space. The distribution method in which one corner of the light-emitting elements is located on the same straight line saves horizontal space to a certain extent, but occupies more vertical space and is not conducive to the expansion of the pad size. In another embodiment, the stacking method of the light-emitting elements and the distribution position of the pads can be designed according to the requirements, as shown in Embodiment 21.

[0087] Example 21: Method for fabricating vertically stacked LED integrated chips, refer to Figure 47 This includes steps X1, X2, and X3, or Y1, Y2, and Y3, with the difference being that in step X2 or step Y2, the stacking method of the first light-emitting body 101, the second light-emitting body 102, and the third light-emitting body 103 is different. The first light-emitting body 101, the second light-emitting body 102, and the third light-emitting body 103 are arranged alternately from bottom to top to form a first step. Specifically, the second light-emitting body 102 and the first light-emitting body 101 are alternately distributed in the transverse direction (i.e., the X direction), so that a local area at the top of the P-type semiconductor layer of the first light-emitting body 101 is exposed, forming a first-level first step. The second light-emitting body 102 and the third light-emitting body 103 are alternately distributed in the longitudinal direction (i.e., the Y direction), so that a local area at the top of the P-type semiconductor layer of the second light-emitting body 102 is exposed, forming a second-level first step. The local area at the top of the P-type semiconductor layer of the third light-emitting body 103 is a third-level first step. The first-level first step, the second-level first step, and the third-level first step are used to set the P electrode, and the second step is used to set the N electrode.

[0088] This embodiment twenty-one also includes the LED integrated chip preparation methods X4 / Y4~X5 / Y5 of the above embodiments nine to twelve. The difference between these methods and those of embodiments nine to twelve is that in step X43 / Y43, when preparing the P electrode and N electrode, taking the preparation of the common N electrode 6 as an example, conductive materials are deposited in the first etched hole and the second etched hole, and the conductive materials in the second etched hole are electrically connected through the conductive materials to obtain the P electrode 202 and the common N electrode 6.

[0089] Example 21: Vertically stacked LED integrated chips were prepared using the methods described above. (Refer to...) Figure 29 , Figure 30 In this embodiment twenty-one, the vertically stacked LED integrated chip includes several light emitters, electrodes, and reflective layers. The light emitters include a first light emitter 101 to an nth light emitter arranged in a stacked manner from bottom to top. Each light emitter includes an N-type semiconductor layer 1001, a light-emitting layer, and a P-type semiconductor layer 1002 stacked in a stacked manner. One side of the N-type semiconductor layer 1001 protrudes to form a second step. The electrodes include a P electrode 202 and an N electrode 201.

[0090] In this embodiment, n is 3, and the light-emitting body includes: a first light-emitting body 101, a second light-emitting body 102, and a third light-emitting body 103. The first light-emitting body 101, the second light-emitting body 102, and the third light-emitting body 103 are arranged alternately from bottom to top to form a first step. The alternation method is different from the above embodiments one to twenty, and the specific details are described in the above structure.

[0091] To save horizontal and vertical space, P and N electrodes with extended dimensions are fabricated. At the same time, by simplifying the external driving circuit, in this embodiment, the N electrodes are connected in series to form a common cathode structure. The first-stage, second-stage, third-stage, and second-stage steps are arranged in a quadrilateral shape, so that the three P electrodes and one common N electrode are distributed on the four sides of the LED integrated chip, thereby making full use of the LED integrated chip space and facilitating the acquisition of a smaller LED integrated chip.

[0092] The first light emitter 101, the second light emitter 102, and the third light emitter 103 are respectively a red LED chip, a green LED chip, and a blue LED chip, which emit red light, green light, and blue light respectively. The red, green, and blue light colors are mixed to display the desired light color, such as white light.

[0093] Adjacent light emitters are bonded together by bonding layers, which include a first bonding layer 301 to an (n-1)th bonding layer. When n is 3, the bonding layers include a first bonding layer 301, a second bonding layer 302, and a third bonding layer 303. The first bonding layer 301 covers the light-emitting surface of the first light emitter 101. The first light emitter 101 and the second light emitter 102 are bonded together by the second bonding layer 302, and the second light emitter 102 and the third light emitter 103 are bonded together by the third bonding layer 303. The bonding layer material includes epoxy resin, polyimide (PI), benzocyclobutene (BCB), or poly(p-phenylenebenzodioxazole) (PBO). In this embodiment, epoxy resin is preferred.

[0094] It should be noted that, in another embodiment, the first light emitter 101, the second light emitter 102, and the third light emitter 103 are all blue LED chips. The bonding layer between two adjacent light emitters includes epoxy resin and a light color conversion material. The light color conversion material includes quantum dots or phosphors. In this embodiment, quantum dots are preferred, which are used to convert the blue light emitted by the blue LED chip into other colors. For example, the first bonding layer 301 contains red quantum dots, which are used to convert the light color of the first light emitter 102 into red light. The second bonding layer 302 contains transparent quantum dots or does not contain quantum dots, which are used to directly transmit the blue light emitted by the second light emitter 102. The third bonding layer 303 contains blue quantum dots, which are used to convert the light color of the third light emitter 103 into green light. The red, green, and blue light colors are mixed to display the desired light color, such as white light.

[0095] An insulating layer or insulating reflective layer 7 covers the surfaces of the first step 4 and the second step 5. In another embodiment, the insulating layer or insulating reflective layer 7 covers the surface of the nth bonding layer. The bottom end of the P electrode 202 penetrates the insulating layer or insulating reflective layer 7 and is electrically connected to the P-type semiconductor layer. The bottom end of the N electrode 201 penetrates the insulating layer or insulating reflective layer 7 and is electrically connected to the N-type semiconductor layer. In this embodiment, the specific structure of the insulating layer or insulating reflective layer 7 is the same as in embodiments nine to fourteen above, and will not be described in detail again.

[0096] The vertically stacked LED integrated chips from any one or more of the embodiments 1 to 21 described above are applied to a display module. The display module includes a substrate and vertically stacked LED integrated chips arrayed on the substrate. In this display module, the vertically stacked LED integrated chips serve as pixels. In the above fabrication method, steps X5 / Y5 may be omitted, i.e., no cutting is required. Alternatively, cutting can be performed based on the display module size with different gaps to directly obtain a display module of the required size. In other embodiments, the substrate may be removed according to display requirements, allowing the vertically stacked LED integrated chip array to be distributed on a driving substrate (e.g., a PCB board).

[0097] It should be noted that this application does not specifically limit the application scenarios of vertically stacked LED integrated chips. The aforementioned vertically stacked LED integrated chips can also be applied to other application scenarios such as smart lighting.

[0098] It is understood that the above detailed description of the present invention is for illustrative purposes only and is not intended to limit the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention to achieve the same technical effects; as long as the usage requirements are met, they are all within the protection scope of the present invention.

Claims

1. A method for fabricating a vertically stacked LED integrated chip, characterized in that, The method includes: A plurality of light emitters are provided, wherein the vertical projection area of ​​the light emitters in the same group is equal, and the vertical projection area of ​​each group of light emitters is different. Each light emitter includes an N-type semiconductor layer (1001), a light-emitting layer, and a P-type semiconductor layer (1002) stacked together. The side where the N-type semiconductor layer is located is the light-emitting surface. At least one side of the N-type semiconductor layer (1001) protrudes to form a second step (5). Each group of light-emitting bodies is stacked sequentially from bottom to top and from largest to smallest vertical projection area. Before placing the next group of light-emitting bodies, a bonding layer is pre-set on the surface of the previous group of light-emitting bodies that has been placed. Etch a local area of ​​the bonding layer to expose a local area at the top of the P-type semiconductor layer of each light emitter, forming a first step (4), and simultaneously expose the second step (5); A P electrode (202) is prepared in the first step (4), and an N electrode (201) is prepared in the second step (5). The P electrode (202) is electrically connected to the P-type semiconductor layer (1002), and the N electrode (201) is electrically connected to the N-type semiconductor layer (1001).

2. The method for fabricating a vertically stacked LED integrated chip according to claim 1, characterized in that, The light emitter includes a first group of light emitters to an nth group of light emitters. The first group of light emitters includes a plurality of first light emitters (101), and the nth group of light emitters includes a plurality of nth light emitters. The vertical projection areas of the first light emitters (101) to the nth light emitters are set to M1 to Mn, respectively, then M1 > M2 > ... > Mn. The bonding layer includes at least a second bonding layer (302) to an nth bonding layer. The second bonding layer (302) is located between the first light emitter (101) and the second light emitter (102). ... The nth bonding layer is located between the (n-1)th light emitter and the nth light emitter.

3. The method for fabricating a vertically stacked LED integrated chip according to claim 2, characterized in that, The light-emitting elements in each group are stacked sequentially from bottom to top and from largest to smallest vertical projected area. Before placing the next group of light-emitting elements, a bonding layer is pre-formed on the surface of the previous group of light-emitting elements, including: Transfer a plurality of the first light emitters (101) to the substrate (1), with the light-emitting surface of the first light emitters (101) facing the substrate (1). A second bonding layer (302) is provided on the electrode side of the first light emitter (101). Several second light emitters (102) are transferred to the second bonding layer (302), and the second light emitters (102) are stacked correspondingly with the first light emitters (101); A third bonding layer (303) is provided on the electrode side of the second light emitter (102). Several third light emitters (103) are transferred to the third bonding layer (303), and the third light emitters (103) are stacked correspondingly with the second light emitters (102); And so on; Transfer several nth luminescent elements to the nth bonding layer; The first bonding layer (301) to the nth bonding layer are etched to expose the top part of the P-type semiconductor layer of each of the first light emitters (101) to the nth light emitter, forming the first step (4), and at the same time exposing the second step (5).

4. The method for fabricating a vertically stacked LED integrated chip according to claim 3, characterized in that, When the second light-emitting body (102) to the nth light-emitting body are transferred, the axes of the first light-emitting body (101) to the nth light-emitting body are located on the same straight line, or one of the corner lines of the first light-emitting body (101) to the nth light-emitting body are located on the same straight line.

5. The method for fabricating a vertically stacked LED integrated chip according to claim 3, characterized in that, When n=3, the light emitter includes a first light emitter (101), a second light emitter (102), and a third light emitter (103). The bonding layer includes a first bonding layer (301), a second bonding layer (302), and a third bonding layer (303). When the second light emitter (102) and the third light emitter (103) are transferred, the second light emitter (102) and the first light emitter (101) are distributed alternately in the transverse direction, so that a local area at the top of the P-type semiconductor layer of the first light emitter (101) is exposed, forming a first-level first step. The second light emitter (102) and the third light emitter (103) are distributed alternately in the longitudinal direction, so that a local area at the top of the P-type semiconductor layer of the second light emitter (102) is exposed, forming a second-level first step. The local area at the top of the P-type semiconductor layer of the third light emitter (103) is a third-level first step. The first-level first step, the second-level first step, and the third-level first step are used to set the P electrode (202), and the second step (5) is used to set the N electrode (201).

6. The method for fabricating a vertically stacked LED integrated chip according to claim 1, characterized in that, The light-emitting elements in the same group have the same light color, and the light-emitting elements include at least red LED chips, blue LED chips, and green LED chips.

7. The method for fabricating a vertically stacked LED integrated chip according to claim 1, characterized in that, The light-emitting bodies in each group have the same light color. The bonding layer includes a bonding material and a light-color conversion material. The light-color conversion material includes at least quantum dots or phosphors and is used to convert the light color of the light-emitting body into other colors.

8. The method for fabricating a vertically stacked LED integrated chip according to claim 2 or 5, characterized in that, The vertical projected areas of the first bonding layer (301) to the nth bonding layer decrease sequentially, or the vertical projected areas of the first bonding layer (301) to the nth bonding layer are equal.

9. The method for fabricating a vertically stacked LED integrated chip according to claim 8, characterized in that, The upper surface area of ​​the bonding layer is the same as the lower surface area of ​​the adjacent upper light-emitting body, or the lower surface area of ​​the bonding layer is the same as the upper surface area of ​​the adjacent lower light-emitting body, or the upper surface area of ​​the bonding layer is greater than the lower surface area of ​​the adjacent upper light-emitting body, and the lower surface area of ​​the bonding layer is greater than the upper surface area of ​​the adjacent lower light-emitting body.

10. The method for fabricating a vertically stacked LED integrated chip according to claim 1, characterized in that, Before preparing the P electrode (202) and N electrode (201), an insulating layer or an insulating reflective layer (7) is provided on the surface of the first step (4) and the second step (5), or a conductive material is filled in the bonding layer etching area corresponding to the first step (4) and the second step (5), and an insulating layer or an insulating reflective layer (7) is provided on the surface of the bonding layer. A local area of ​​the insulating layer or insulating reflective layer (7) is etched to form a first etched hole and a second etched hole; Conductive materials are deposited in the first etched hole, the second etched hole and the corresponding area to form the P electrode (202) and the N electrode (201). The bottom end of the P electrode (202) penetrates the insulating layer or the insulating reflective layer (7) and is electrically connected to the P-type semiconductor layer (1002). The bottom end of the N electrode (201) penetrates the insulating layer or the insulating reflective layer (7) and is electrically connected to the N-type semiconductor layer (1001).

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