LED chip and preparation method thereof

Abstract

The application discloses an LED chip and a preparation method thereof. The preparation method of the LED chip comprises the following steps: S1, depositing an N-type GaN layer, an active light-emitting layer and a P-type GaN layer to form a first epitaxial layer; S2, etching to form an N-type GaN conductive step and a plurality of isolation channels, and dividing into independent epitaxial units; S3, preparing a first insulating layer, a metal reflecting layer, a second insulating layer and a through hole, and the shortest center distance of adjacent through holes is L1; S4, preparing a metal connecting layer to electrically connect a plurality of metal reflecting layers to form a partition; S5, preparing a third insulating layer and a through hole, so that the shortest center distance L2 from the through hole to each second insulating layer through hole is the same; S6, preparing a P-type conductive metal layer and electrically connecting, and then preparing a semiconductor layer; and S7, removing a sapphire substrate, exposing the N-type GaN layer, etching to form a P-type conductive through hole, and preparing a P-type pad layer. The application aims to solve the technical problem that, in the prior art, different chip line resistances exist in the same partition of an ADB intelligent vehicle lamp due to packaging process fluctuation, and then uneven dark and bright phenomenon is generated.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and particularly relates to an LED chip and its preparation method. Background Technology

[0002] Light-emitting diode (LED) chips, with their energy-saving and high-efficiency characteristics, are widely used in both lighting and display fields. In recent years, automotive lighting has also increasingly switched to LED chips, giving rise to traditional LED headlights and intelligent headlights with Adaptive High Beam (ADB) and Adaptive On-Beam (AOB) capabilities. ADB intelligent headlights achieve this by packaging several LED chips onto a substrate, then partitioning these chips into sections, each driven independently, thus enabling adaptive high beam functionality. However, due to variations in the packaging process, chips within the same section may exhibit different line resistances, leading to uneven brightness at the moment of activation.

[0003] Therefore, how to solve the problem of uneven brightness caused by differences in line resistance of chips in the same zone of ADB smart headlights has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide an LED chip and its manufacturing method, thereby solving the technical problem in existing ADB smart vehicle lights where variations in packaging processes lead to different line resistances in chips within the same partition, resulting in uneven brightness.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution: A method for fabricating an LED chip includes the following steps: S1, a sapphire substrate is provided, and an N-type GaN layer, an active light-emitting layer and a P-type GaN layer are sequentially deposited on the sapphire substrate to form a first epitaxial layer on the sapphire substrate; S2, etching a portion of the P-type GaN layer on the first epitaxial layer until the N-type GaN layer is exposed, so as to form an N-type GaN layer conductive step and several isolation channels on the first epitaxial layer. The several isolation channels intersect each other to form a grid structure. The several isolation channels divide the first epitaxial layer into several independent epitaxial units, and a second epitaxial layer is formed on the sapphire substrate. S3, a first insulating layer is prepared on the second epitaxial layer, and a first insulating layer via corresponding to the P-type GaN layer of each epitaxial unit is formed in the first insulating layer to form a third epitaxial layer on the sapphire substrate; a plurality of metal reflective layers corresponding to the epitaxial units are prepared on the third epitaxial layer, and each metal reflective layer is electrically connected to the corresponding epitaxial unit through the first insulating layer via to form a fourth epitaxial layer on the sapphire substrate; a second insulating layer is prepared on the fourth epitaxial layer, and a second insulating layer via corresponding to each metal reflective layer is formed in the second insulating layer, and the shortest center distance between the second insulating layer vias on two adjacent epitaxial units is L1 to form a fifth epitaxial layer on the sapphire substrate; S4, a plurality of metal interconnect layers are prepared on the fifth epitaxial layer. Each metal interconnect layer electrically connects a plurality of corresponding metal reflective layers through a plurality of second insulating layer vias. A plurality of epitaxial units electrically connected by the same metal interconnect layer form a partition to form a sixth epitaxial layer on the sapphire substrate. S5, a third insulating layer is prepared on the sixth epitaxial layer, and a third insulating layer via corresponding to the metal connection layer of each partition is formed in the third insulating layer. Within the same partition, the shortest center distance L2 from the third insulating layer via to each second insulating layer via in the partition is the same, so as to form a seventh epitaxial layer on the sapphire substrate. S6, a P-type conductive metal layer is prepared on the seventh epitaxial layer, and the P-type conductive metal layer is electrically connected to the metal connection layer through the via of the third insulating layer to form an eighth epitaxial layer on the sapphire substrate; a semiconductor layer is prepared on the eighth epitaxial layer; S7, Remove the sapphire substrate to expose the N-type GaN layer, etch the N-type GaN layer until the P-type conductive metal layer is exposed to form a P-type conductive via; Prepare a P-type pad layer on the side of the N-type GaN layer opposite to the P-type conductive metal layer, the P-type pad layer corresponding to the position of the P-type conductive via.

[0006] Furthermore, the semiconductor layer includes a fourth insulating layer, a first bonding metal layer, a second bonding metal layer, and a conductive silicon substrate sequentially disposed on the eighth epitaxial layer; the step of fabricating the semiconductor layer on the eighth epitaxial layer includes: A fourth insulating layer is prepared on the P-type conductive metal layer, and an N-type insulating layer via is etched in the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer to form an N-type insulating layer via that penetrates to the conductive step of the N-type GaN layer. A first bonding metal layer is prepared on the fourth insulating layer, a conductive silicon substrate is provided, and a second bonding metal layer is prepared on the conductive silicon substrate, and the first bonding metal layer is bonded to the second bonding metal layer.

[0007] Furthermore, the range of L1 is 50μm to 80μm, the width of the isolation channel is 2μm to 5μm, and the number of epitaxial units contained in each partition is 2 to 6.

[0008] Furthermore, the step of fabricating a plurality of metal reflective layers corresponding to the epitaxial units on the third epitaxial layer includes: On the side of the third epitaxial layer facing away from the sapphire substrate, a negative photoresist is coated corresponding to each epitaxial unit. The photoresist in the area where the metal reflective layer is to be formed is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. Then, an ITO thin film, Ag metal, Ti metal, Ni metal, Pt metal, Ti metal, Ni metal, Pt metal and Ti metal are deposited sequentially using an electron beam evaporation process. Finally, the photoresist and the metal on it are removed by a lift-off process to form the metal reflective layer.

[0009] Furthermore, the specific steps for fabricating a metal interconnect layer on the fifth epitaxial layer include: On the side of the fifth epitaxial layer facing away from the sapphire substrate, a negative photoresist is coated corresponding to each of the partitions. The photoresist in the area where the metal interconnect layer is to be formed is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. Then, Al metal, Ti metal, Al metal, Ti metal, Al metal, Ti metal, Pt metal, and Ti metal are sequentially deposited using an electron beam evaporation process. Finally, the photoresist and the metal on it are removed by a lift-off process to form the metal interconnect layer.

[0010] Furthermore, the specific steps for fabricating a P-type conductive metal layer on the seventh epitaxial layer include: On the side of the seventh epitaxial layer facing away from the sapphire substrate, a negative photoresist is coated corresponding to each of the partitions. The photoresist in the area where the P-type conductive metal layer is to be formed is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. Then, Ti metal, Au metal, Ti metal, Ni metal, Ti metal, Ni metal and Ti metal are deposited sequentially using an electron beam evaporation process. Finally, the photoresist and the metal on it are removed by a lift-off process to form the P-type conductive metal layer.

[0011] Furthermore, the specific steps for preparing the P-type pad layer include: A negative photoresist is coated on the side of the N-type GaN layer facing away from the P-type conductive metal layer. The photoresist in the area where the P-type pad layer is to be formed is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. Then, Ti metal, Ni metal and Au metal are deposited sequentially using an electron beam evaporation process. Finally, the photoresist and the metal on it are removed by a lift-off process to form the P-type pad layer.

[0012] Furthermore, the thicknesses of the metal reflective layers are as follows: ITO film thickness is 30 Å–50 Å, Ag metal thickness is 1200 Å–2000 Å, Ti metal thickness is 1000 Å–2000 Å, Ni metal thickness is 1000 Å–2000 Å, Pt metal thickness is 1000 Å–2000 Å, Ti metal thickness is 1000 Å–2000 Å, Ni metal thickness is 1000 Å–2000 Å, Pt metal thickness is 2000 Å–3000 Å, and Ti metal thickness is 30 Å–50 Å; the thicknesses of the metal bonding layers are as follows: Al metal thickness is 3000 Å–5000 Å, Ti metal thickness is 1000 Å–2000 Å, Al metal thickness is 3000 Å–5000 Å, Ti metal thickness is 1000 Å–2000 Å, and Al metal thickness is 30 Å–50 Å. The thickness of the P-type conductive metal layer is 3000 Å to 5000 Å, the thickness of the Ti metal is 1000 Å to 2000 Å, the thickness of the Pt metal is 2000 Å to 3000 Å, and the thickness of the Ti metal is 30 Å to 50 Å. The thicknesses of the P-type conductive metal layers are as follows: Ti metal 30 Å to 50 Å, Au metal 8000 Å to 10000 Å, Ti metal 1000 Å to 2000 Å, Ni metal 30 Å to 50 Å. The thickness of the metal is 1000Å~2000Å, the thickness of Ti metal is 1000Å~2000Å, the thickness of Ni metal is 1000Å~2000Å, and the thickness of Ti metal is 30Å~50Å. The thicknesses of the P-type pad layers are as follows: the thickness of Ti metal is 500Å~1000Å, the thickness of Ni metal is 500Å~1000Å, and the thickness of Au metal is 4000Å~6000Å.

[0013] Furthermore, the first, second, third, and fourth insulating layers are all SiO2 thin films, and the first, second, third, and fourth insulating layers are all deposited using PECVD technology. The vias in the first insulating layer are formed using BOE etching solution, and the vias in the second and third insulating layers are formed using inductively coupled plasma etching technology.

[0014] An LED chip, manufactured using any one of the above-described LED chip fabrication methods.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: by preparing isolation channels to divide the epitaxial layer into several independent epitaxial units, and then completing the electrical connection of the epitaxial units in the same partition through the metal interconnection layer, the partitioning is completed during the chip fabrication stage, avoiding the problem of different chip line resistance in the same partition due to packaging process fluctuations in the traditional solution; at the same time, by setting the shortest center distance L2 of the third insulating layer via in each partition to be the same as that of each second insulating layer via in the same partition, the physical path length of the current flowing from the P-type conductive metal layer through the metal interconnection layer to each epitaxial unit in the partition is consistent, thereby eliminating the line resistance difference between each epitaxial unit, realizing the effect of simultaneously driving and turning off all epitaxial units in the partition, solving the problem of uneven brightness caused by line resistance difference in ADB smart car lights, and improving light output uniformity and product yield. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram (top view and cross-sectional view) of the structure of the N-type GaN layer conductive steps and isolation channels formed in step S2 of the LED chip fabrication method according to an embodiment of the present invention. Figure 2 This is a schematic diagram (top view and cross-sectional view) of the structure forming the first insulating layer through hole in step S3 of the LED chip fabrication method according to an embodiment of the present invention. Figure 3 This is a schematic diagram (top view and cross-sectional view) of the metal reflective layer fabricated in step S3 of the LED chip fabrication method according to an embodiment of the present invention. Figure 4 This is a schematic diagram (top view and cross-sectional view) of the structure of the second insulating layer and the through hole in the second insulating layer in step S3 of the LED chip fabrication method according to an embodiment of the present invention. Figure 5 This is a schematic diagram (top view and cross-sectional view) of the metal interconnect layer fabricated in step S4 of the LED chip fabrication method according to an embodiment of the present invention. Figure 6 This is a schematic diagram (top view and cross-sectional view) of the structure of the third insulating layer in step S5 of the LED chip fabrication method according to an embodiment of the present invention. Figure 7 This is a schematic diagram (top view and cross-sectional view) of the structure of the P-type conductive metal layer prepared in step S6 of the LED chip preparation method according to an embodiment of the present invention. Figure 8 This is a schematic diagram (top view and cross-sectional view) of the structure of the fourth insulating layer and the N-type insulating layer through hole in step S6 of the LED chip fabrication method of this embodiment of the invention. Figure 9 This is a schematic diagram (top view and cross-sectional view) of step S6 in the LED chip fabrication method of this embodiment of the invention, showing the fabrication of the first bonding metal layer, the second bonding metal layer, and the structure after bonding. Figure 10 This is a schematic diagram (top view and cross-sectional view) of the structure in step S7 of the LED chip fabrication method of this embodiment of the invention, showing the removal of the sapphire substrate and the formation of a P-type conductive via. Figure 11 This is a schematic diagram (top view and cross-sectional view along line A) of the structure of the P-type pad layer in step S7 of the LED chip fabrication method according to an embodiment of the present invention.

[0017] 10. Sapphire substrate; 111. N-type GaN layer; 112. Active light-emitting layer; 113. P-type GaN layer; 114. Conductive step of N-type GaN layer; 115. Isolation channel; 12. First insulating layer; 13. Metal reflective layer; 14. Second insulating layer; 141. Second insulating layer via; 15. Metal interconnect layer; 16. Third insulating layer; 161. Third insulating layer via; 17. P-type conductive metal layer; 18. Fourth insulating layer; 181. N-type insulating layer via; 191. First bonding metal layer; 192. Second bonding metal layer; 20. Conductive silicon substrate; 211. P-type conductive via; 22. P-type pad layer; A. Cutting line.

[0018] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0019] To make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0020] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," "up," "down," and similar expressions used herein are for illustrative purposes only and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0021] In this invention, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0022] Example 1: Please see Figures 1 to 11 A method for preparing an LED chip includes the following steps.

[0023] S1, a sapphire substrate 10 is provided, and an N-type GaN layer 111, an active light-emitting layer 112 and a P-type GaN layer 113 are deposited sequentially from bottom to top on the sapphire substrate 10 to form a first epitaxial layer on the sapphire substrate 10.

[0024] S2, photoresist is coated on the side of the first epitaxial layer facing away from the sapphire substrate 10. An etching mask is formed by exposure and development. Then, a portion of the P-type GaN layer 113 is etched using inductively coupled plasma etching until the N-type GaN layer 111 is exposed. This forms the conductive steps 114 of the N-type GaN layer at the outermost edge of the chip, and several isolation channels 115 inside the chip. In this embodiment, the several isolation channels 115 intersect to form a mesh structure, dividing the first epitaxial layer into four independent epitaxial units, which are arranged in a 2x2 matrix. The width of the isolation channels 115 is 3.5 μm. After etching, the photoresist is removed, and a second epitaxial layer is formed on the sapphire substrate 10.

[0025] S3, a silicon dioxide thin film is deposited as a first insulating layer 12 on the side of the second epitaxial layer facing away from the sapphire substrate 10 using a PECVD process. Photoresist is coated on the surface of the first insulating layer 12, and after exposure and development, the first insulating layer 12 is etched using BOE etching solution to form first insulating layer vias corresponding to the P-type GaN layer 113 of each epitaxial unit. After removing the photoresist, a third epitaxial layer is formed.

[0026] Then, a negative photoresist is coated on the side of the third epitaxial layer facing away from the sapphire substrate 10. The photoresist in the area where the metal reflective layer is to be formed is exposed using a photomask. After development, the photoresist in the unexposed areas is removed. ITO thin film, Ag metal, Ti metal, Ni metal, Pt metal, Ti metal, Ni metal, Pt metal, and Ti metal are sequentially deposited using an electron beam evaporation process. The thicknesses of the deposited layers are as follows: ITO film thickness is 30 Å–50 Å, Ag metal thickness is 1200 Å–2000 Å, Ti metal thickness is 1000 Å–2000 Å, Ni metal thickness is 1000 Å–2000 Å, Pt metal thickness is 1000 Å–2000 Å, Ti metal thickness is 1000 Å–2000 Å, Ni metal thickness is 1000 Å–2000 Å, Pt metal thickness is 2000 Å–3000 Å, and Ti metal thickness is 30 Å–50 Å. Then, the photoresist and its metal are removed using a lift-off process, forming an independent metal reflective layer 13 on each epitaxial unit. Each metal reflective layer 13 is electrically connected to the corresponding P-type GaN layer 113 of the epitaxial unit through a corresponding first insulating layer via, forming a fourth epitaxial layer.

[0027] Next, a silicon dioxide thin film is deposited again on the side of the fourth epitaxial layer facing away from the sapphire substrate 10 using a PECVD process to form a second insulating layer 14. Photoresist is applied, and after exposure and development, inductively coupled plasma etching is used to form second insulating layer vias 141 corresponding to each metal reflective layer 13. In this embodiment, the shortest center distance L1 between the second insulating layer vias 141 on adjacent epitaxial units is set to 65 μm. After removing the photoresist, a fifth epitaxial layer is formed.

[0028] S4, a negative photoresist is coated on the side of the fifth epitaxial layer facing away from the sapphire substrate 10. After exposure and development, Al metal, Ti metal, Al metal, Ti metal, Al metal, Ti metal, Pt metal, and Ti metal are sequentially deposited using an electron beam evaporation process. The thicknesses of each deposited layer are as follows: Al metal thickness is 3000 Å–5000 Å, Ti metal thickness is 1000 Å–2000 Å, Al metal thickness is 3000 Å–5000 Å, Ti metal thickness is 1000 Å–2000 Å, Pt metal thickness is 2000 Å–3000 Å, and Ti metal thickness is 30 Å–50 Å. Then, the photoresist and the metal on it are removed using a lift-off process to form a metal interconnect layer 15. In this embodiment, each metal interconnect layer 15 electrically connects the corresponding four metal reflective layers 13 through four second insulating layer vias 141, thereby forming a partition of these four epitaxial units. In this embodiment, the entire chip contains one partition, forming a sixth epitaxial layer.

[0029] S5, a silicon dioxide thin film is deposited as the third insulating layer 16 on the side of the sixth epitaxial layer facing away from the sapphire substrate 10 using a PECVD process. Photoresist is applied, and after exposure and development, inductively coupled plasma etching is used to form third insulating layer vias 161 corresponding to the metal interconnect layers 15 of each partition. In this embodiment, each partition corresponds to one third insulating layer via 161, and within that partition, the shortest center distance L2 from the third insulating layer via 161 to each second insulating layer via 141 within that partition is the same. In this embodiment, the four second insulating layer vias 141 are symmetrically distributed, and L2 is 40 μm for each. After removing the photoresist, a seventh epitaxial layer is formed.

[0030] S6, a negative photoresist is coated on the side of the seventh epitaxial layer facing away from the sapphire substrate 10. After exposure and development, Ti metal, Au metal, Ti metal, Ni metal, Ti metal, Ni metal, and Ti metal are sequentially deposited using an electron beam evaporation process. The thicknesses of each deposited layer are as follows: Ti metal thickness is 30 Å to 50 Å, Au metal thickness is 8000 Å to 10000 Å, Ti metal thickness is 1000 Å to 2000 Å, Ni metal thickness is 1000 Å to 2000 Å, Ti metal thickness is 1000 Å to 2000 Å, Ni metal thickness is 1000 Å to 2000 Å, and Ti metal thickness is 30 Å to 50 Å. Then, the photoresist and the metal on it are removed using a lift-off process to form a P-type conductive metal layer 17. The P-type conductive metal layer 17 is electrically connected to the metal interconnect layer 15 through a third insulating layer via 161 to form the eighth epitaxial layer.

[0031] A semiconductor layer is fabricated on the eighth epitaxial layer. The semiconductor layer includes a fourth insulating layer, a first bonding metal layer, a second bonding metal layer, and a conductive silicon substrate 20 sequentially disposed on the eighth epitaxial layer. Specifically, a silicon dioxide thin film is deposited as the fourth insulating layer 18 on the side of the eighth epitaxial layer facing away from the sapphire substrate 10 using a PECVD process. After coating with photoresist and exposure and development, the fourth insulating layer 18, the third insulating layer 16, the second insulating layer 14, and the first insulating layer 12 are sequentially etched using an inductively coupled plasma etching process to form an N-type insulating layer via 181 that penetrates to the conductive step 114 of the N-type GaN layer.

[0032] Next, Cr, Al, Ti, Ni, Sn, Ni, and Sn metals are sequentially deposited on the fourth insulating layer 18 and the N-type insulating layer via 181 using an electron beam evaporation process to form a first bonding metal layer 191. A conductive silicon substrate 20 is also provided, and Ti, Ni, Sn, Ni, and Sn metals are sequentially deposited on this substrate 20 using an electron beam evaporation process to form a second bonding metal layer 192. Then, the first bonding metal layer 191 and the second bonding metal layer 192 are bonded together using a thermo-pressing bonding process.

[0033] S7. The sapphire substrate 10 is removed using a laser lift-off process to expose the N-type GaN layer 111. The N-type GaN layer 111 is etched until the P-type conductive metal layer 17 is exposed to form a P-type conductive via 211. Specifically, photoresist is coated on the exposed N-type GaN layer 111. After exposure and development, inductively coupled plasma etching is used to etch the N-type GaN layer 111 above the P-type conductive metal layer 17 and the first insulating layer 12, the second insulating layer 14, and the third insulating layer 16 below this area to form the P-type conductive via 211. After removing the photoresist, a P-type pad layer 22 is prepared on the side of the N-type GaN layer 111 facing away from the P-type conductive metal layer 17. The P-type pad layer 22 corresponds to the position of the P-type conductive via 211. The specific fabrication steps of the P-type pad layer 22 are as follows: a negative photoresist is coated on the side of the N-type GaN layer 111 facing away from the P-type conductive metal layer 17. The photoresist in the area where the P-type pad layer 22 is to be formed is exposed by a photomask. After development, the photoresist in the unexposed area is removed. Then, Ti metal, Ni metal and Au metal are deposited sequentially using an electron beam evaporation process. The thicknesses of each deposited layer are as follows: the thickness of Ti metal is 500 Å to 1000 Å, the thickness of Ni metal is 500 Å to 1000 Å, and the thickness of Au metal is 4000 Å to 6000 Å. Finally, the photoresist and the metal on it are removed by a lift-off process to form the P-type pad layer 22.

[0034] Example 2 This embodiment is basically the same as Embodiment 1, except that the shortest center distance L1 between adjacent second insulating layer through holes 141 is set to 50μm in this embodiment.

[0035] Example 3 This embodiment is basically the same as Embodiment 1, except that the shortest center distance L1 between adjacent second insulating layer through holes 141 is set to 80μm in this embodiment.

[0036] Example 4 This embodiment is basically the same as Embodiment 1, except that the width of the isolation channel 115 is set to 2μm in this embodiment.

[0037] Example 5 This embodiment is basically the same as Embodiment 1, except that the width of the isolation channel 115 is set to 5μm in this embodiment.

[0038] Example 6 This embodiment is basically the same as Embodiment 1, except that each partition in this embodiment contains two extensional units. At this time, the isolation channel 115 still has a grid structure, but only two adjacent units are used to form a partition.

[0039] Example 7 This embodiment is basically the same as Embodiment 1, except that each partition in this embodiment contains 6 epitaxial units. The six epitaxial units are arranged in a 2x3 matrix, and the isolation channel 115 has a grid structure.

[0040] Comparative Example 1 This comparative example is basically the same as Example 1, except that the shortest center distance L2 from the third insulating layer via 161 to each second insulating layer via 141 within the same partition is different in this comparative example. Specifically, the L2 of the four second insulating layer vias 141 is set to 40μm, 42μm, 44μm and 46μm respectively, with a maximum difference of 15%.

[0041] Comparative Example 2 This comparative example is basically the same as Example 1, except that the shortest center distance L1 between adjacent second insulating layer vias 141 is set to 40 μm.

[0042] Comparative Example 3 This comparative example is basically the same as Example 1, except that the shortest center distance L1 between adjacent second insulating layer vias 141 is set to 90 μm.

[0043] Comparative Example 4 This comparative example is basically the same as Example 1, except that the width of the isolation channel 115 in this comparative example is set to 1μm.

[0044] Comparative Example 5 This comparative example is basically the same as Example 1, except that the width of the isolation channel 115 in this comparative example is set to 6μm.

[0045] Comparative Example 6 This comparative example is basically the same as Example 1, except that each partition in this comparative example contains only one epitaxial unit. In this case, no true partition is formed, and the metal interconnect layer 15 connects only one unit.

[0046] Comparative Example 7 This comparative example is basically the same as Example 1, except that each partition in this comparative example contains 8 epitaxial units. The eight epitaxial units are arranged in a 2x4 matrix, and the isolation channel 115 has a grid structure.

[0047] Comparative Example 8 This comparative example is basically the same as Example 1, except that the etching of the isolation channel 115 in step S2 is not performed in this comparative example, that is, the isolation channel 115 is not formed and the epitaxial unit is not divided, and the complete first epitaxial layer structure is retained.

[0048] Comparative Example 9 This comparative example is basically the same as Example 1, except that the shortest center distance L1 between adjacent second insulating layer vias 141 is set to 50 μm, the width of the isolation channel 115 is set to 2 μm, the number of epitaxial units contained in each partition is 2, and the shortest center distance L2 from the third insulating layer via 161 to each second insulating layer via 141 in the same partition is different, with a difference of 10%.

[0049] The present invention also provides an LED chip, which is manufactured using any of the above-described methods for preparing an LED chip.

[0050] Furthermore, performance tests were conducted on the LED chips prepared in all embodiments and comparative examples, as detailed below: The test environment temperature is controlled at 25℃±2℃. Before the test, the chip under test is aged at the rated current for 30 minutes to reach a steady-state working state.

[0051] Brightness uniformity test within a zone: The LED chip under test is fixed on a precision probe stage equipped with tungsten carbide probes with a tip diameter not exceeding 10 μm and a position adjustment accuracy of 1 μm. A 3.0V forward DC driving voltage is applied between the P-type pad layer 22 and the N-type GaN layer conductive step 114 of the chip. The driving voltage is provided by a high-precision programmable DC power supply with a voltage accuracy of ±0.01V. Each independent epitaxial cell within the same zone is lit sequentially, with only one cell lit at a time, and no voltage applied to the remaining cells. A 300mm diameter integrating sphere is used to collect the light output. The inner wall of the integrating sphere is coated with barium sulfate high-reflectivity diffuse reflective material, and the integrating sphere is connected to a spectroradiometer. After the light output stabilizes, the light output power of each epitaxial cell in the visible light range of 380nm to 780nm is recorded in milliwatts. For the light output power of all epitaxial cells within the same zone, the difference between the maximum and minimum values ​​is calculated, divided by the average value of all cells in that zone, and then multiplied by 100% to obtain the percentage of brightness uniformity deviation for that zone. Each sample was measured in three different zones and the average value was taken.

[0052] Turn-on delay time difference test: A high-speed photodetector with a bandwidth of not less than 500MHz and a response time of less than 1ns is used, along with a digital storage oscilloscope with a sampling rate of 2.5GS / s. The photosensitive surface of the photodetector is placed directly above the chip under test, at a distance of no more than 1mm. A 3.0V step voltage signal is simultaneously applied to all epitaxial cells in the same partition by a switching circuit controlled by a signal generator, with a voltage rise time of less than 0.5ns. The oscilloscope records the output signal of the photodetector corresponding to each epitaxial cell simultaneously using an external trigger. The time elapsed from the moment the voltage is applied to each cell until the light output intensity reaches 90% of the steady-state light output intensity of that cell is recorded as the turn-on delay time of that cell. The difference between the maximum and minimum turn-on delay times of all cells in the same partition is recorded as Δt, in nanoseconds. Each sample is measured 5 times and the average value is taken.

[0053] Thermal reliability testing: The chip under test is mounted on an aging test fixture with temperature control, set at 25℃±1℃. A constant current source is used to apply a DC drive current of 1.5 times the rated current to the chip, with a current stability of ±1%. The chip operates continuously for 500 hours, with a test interruption every 100 hours. After a 30-minute recovery period at 25℃, the chip's optical output power is measured. The optical output power measurement uses the same integrating sphere and spectroradiometer as the brightness uniformity test, with the drive current restored to the rated current. If the chip burns out due to open or short circuit within 500 hours, or if the optical output power attenuation exceeds 15% of the initial measurement value in any single measurement, the chip is deemed to have failed thermal reliability testing. At least 30 chips are tested in each group, and the number of failed chips and the time of the first failure are recorded.

[0054] Leakage Current Test: Using a semiconductor parameter analyzer, fix the chip under test (DUT) on the probe station. Select two adjacent epitaxial cells within the same partition and apply a -5V reverse bias between the P-type pad layers 22 of the two adjacent epitaxial cells. The reverse bias is provided by the voltage source of the parameter analyzer, with a voltage accuracy of ±0.1V. Measure the reverse current flowing between the two cells and record it in microamps. If the leakage current exceeds 1μA, the electrical isolation effect of isolation channel 115 is considered insufficient, and there is a risk of crosstalk between adjacent cells. Three pairs of adjacent cells at different locations are selected for measurement for each chip, and the maximum value is taken as the leakage current value of that chip.

[0055] The specific parameters used in Examples 1 to 7 and Comparative Examples 1 to 9 of the present invention and the corresponding test results are shown in Table 1.

[0056] Table 1:

[0057] A comparison of Examples 1 to 7 with Comparative Examples 1 to 9 shows that: Regarding L2 consistency, L2 was completely identical in Examples 1 to 7, with brightness uniformity deviations ranging from 0.9% to 2.3% and turn-on delay time differences Δt ranging from 1.8 ns to 2.6 ns. In Comparative Example 1, L2 showed a 15% difference, with a brightness uniformity deviation of 18.5% and a Δt of 22.3 ns, both significantly higher than in all examples. In Comparative Example 9, with L1, the width of the isolation channel 115, and the number of units all taken as endpoint values, L2 showed only a 10% difference, but the brightness uniformity deviation still reached 12.3%, with a Δt of 15.6 ns, also significantly worse than the examples. This demonstrates that complete L2 consistency is crucial for eliminating uneven brightness.

[0058] Regarding the spacing L1 between adjacent vias in the second insulating layer, the L1 in Examples 2, 1, and 3 were 50 μm, 65 μm, and 80 μm, respectively, with brightness uniformity deviations of 1.5%, 1.2%, and 1.8%, and Δt values ​​of 2.3 ns, 2.1 ns, and 2.2 ns, respectively. All three examples maintained normal reliability after 500 hours. In Comparative Example 2, L1 was 40 μm, with a brightness uniformity deviation of 2.0%, similar to the examples, but it burned out after 150 hours, indicating significantly lower reliability than the examples. In Comparative Example 3, L1 was 90 μm, with a brightness uniformity deviation of 6.8%, higher than all examples, and a Δt value of 3.5 ns. This demonstrates that controlling L1 within the range of 50 μm to 80 μm is crucial for balancing reliability and uniformity.

[0059] Regarding the width of the isolation channel 115, in Examples 4, 1, and 5, the widths of the isolation channel 115 are 2 μm, 3.5 μm, and 5 μm, respectively, with leakage currents of 0.35 μA, 0.08 μA, and 0.08 μA, and brightness uniformity deviations of 1.3%, 1.2%, and 1.4%, respectively. In Comparative Example 4, the width is 1 μm, and the leakage current is as high as 4.80 μA, significantly higher than all examples, indicating a risk of crosstalk. In Comparative Example 5, the width is 6 μm, with a leakage current of 0.08 μA, comparable to the examples, and a brightness uniformity deviation of 1.6%, similar to the examples. This demonstrates that a width range of 2 μm to 5 μm for the isolation channel 115 can ensure both isolation effectiveness and maintain good brightness uniformity.

[0060] Regarding the number of units within a partition, Examples 6, 1, and 7 have 2, 4, and 6 units respectively, with brightness uniformity deviations of 0.9%, 1.2%, and 2.3%, and Δt values ​​of 1.8 ns, 2.1 ns, and 2.6 ns respectively. All examples maintain normal reliability after 500 hours. Comparative Example 6 has only 1 unit, making partitioned driving impossible. Comparative Example 7 has 8 units, resulting in a brightness uniformity deviation of 7.2%, a Δt value of 3.8 ns, and a 22% light decay after 300 hours, indicating inferior reliability and uniformity compared to the examples. This demonstrates that a unit count range of 2 to 6 is a reasonable range for ensuring effective partitioned driving and long-term reliability.

[0061] Regarding the necessity of isolation channel 115, in Comparative Example 8, isolation channel 115 is not formed, making it impossible to achieve partitioning at the chip level. Instead, it can only rely on package partitioning, which is the root cause of uneven brightness caused by differences in package line resistance in the prior art. Its performance is significantly inferior to all embodiments.

[0062] In summary, this invention, by ensuring that the shortest center distance L2 from the third insulating layer via to each second insulating layer via within the same partition is exactly the same, and by controlling the spacing L1 between adjacent second insulating layer vias to 50μm to 80μm, the isolation channel width to 2μm to 5μm, and the number of epitaxial units in each partition to 2 to 6, can stabilize the brightness uniformity deviation below 2.3% and the turn-on delay time difference below 2.6ns, while avoiding thermal burnout and leakage crosstalk, successfully solves the technical problem of uneven chip brightness within the same partition caused by packaging process fluctuations in ADB smart vehicle lights.

[0063] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0064] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating an LED chip, characterized in that, Includes the following steps: S1, a sapphire substrate is provided, and an N-type GaN layer, an active light-emitting layer and a P-type GaN layer are sequentially deposited on the sapphire substrate to form a first epitaxial layer on the sapphire substrate; S2, etching a portion of the P-type GaN layer on the first epitaxial layer until the N-type GaN layer is exposed, so as to form an N-type GaN layer conductive step and several isolation channels on the first epitaxial layer. The several isolation channels intersect each other to form a grid structure. The several isolation channels divide the first epitaxial layer into several independent epitaxial units, and a second epitaxial layer is formed on the sapphire substrate. S3, a first insulating layer is prepared on the second epitaxial layer, and a first insulating layer via corresponding to the P-type GaN layer of each epitaxial unit is formed in the first insulating layer to form a third epitaxial layer on the sapphire substrate; a plurality of metal reflective layers corresponding to the epitaxial units are prepared on the third epitaxial layer, and each metal reflective layer is electrically connected to the corresponding epitaxial unit through the first insulating layer via to form a fourth epitaxial layer on the sapphire substrate; a second insulating layer is prepared on the fourth epitaxial layer, and a second insulating layer via corresponding to each metal reflective layer is formed in the second insulating layer, and the shortest center distance between the second insulating layer vias on two adjacent epitaxial units is L1 to form a fifth epitaxial layer on the sapphire substrate; S4, a plurality of metal interconnect layers are prepared on the fifth epitaxial layer. Each metal interconnect layer electrically connects a plurality of corresponding metal reflective layers through a plurality of second insulating layer vias. A plurality of epitaxial units electrically connected by the same metal interconnect layer form a partition to form a sixth epitaxial layer on the sapphire substrate. S5, a third insulating layer is prepared on the sixth epitaxial layer, and a third insulating layer via corresponding to the metal connection layer of each partition is formed in the third insulating layer. Within the same partition, the shortest center distance L2 from the third insulating layer via to each second insulating layer via in the partition is the same, so as to form a seventh epitaxial layer on the sapphire substrate. S6, a P-type conductive metal layer is prepared on the seventh epitaxial layer, and the P-type conductive metal layer is electrically connected to the metal connection layer through the via of the third insulating layer to form an eighth epitaxial layer on the sapphire substrate; A semiconductor layer is fabricated on the eighth epitaxial layer; S7, Remove the sapphire substrate to expose the N-type GaN layer, etch the N-type GaN layer until the P-type conductive metal layer is exposed to form a P-type conductive via; Prepare a P-type pad layer on the side of the N-type GaN layer opposite to the P-type conductive metal layer, the P-type pad layer corresponding to the position of the P-type conductive via.

2. The method for preparing an LED chip according to claim 1, characterized in that, The semiconductor layer includes a fourth insulating layer, a first bonding metal layer, a second bonding metal layer, and a conductive silicon substrate sequentially disposed on the eighth epitaxial layer; The steps for fabricating a semiconductor layer on the eighth epitaxial layer include: A fourth insulating layer is prepared on the P-type conductive metal layer, and an N-type insulating layer via is etched in the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer to form an N-type insulating layer via that penetrates to the conductive step of the N-type GaN layer. A first bonding metal layer is prepared on the fourth insulating layer, a conductive silicon substrate is provided, and a second bonding metal layer is prepared on the conductive silicon substrate, and the first bonding metal layer is bonded to the second bonding metal layer.

3. The method for preparing an LED chip according to claim 1, characterized in that, The range of L1 is 50μm to 80μm, the width of the isolation channel is 2μm to 5μm, and the number of epitaxial units contained in each partition is 2 to 6.

4. The method for preparing an LED chip according to claim 1, characterized in that, The step of fabricating a plurality of metal reflective layers corresponding to the epitaxial units on the third epitaxial layer includes: On the side of the third epitaxial layer facing away from the sapphire substrate, a negative photoresist is coated corresponding to each epitaxial unit. The photoresist in the area where the metal reflective layer is to be formed is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. Then, an ITO thin film, Ag metal, Ti metal, Ni metal, Pt metal, Ti metal, Ni metal, Pt metal and Ti metal are deposited sequentially using an electron beam evaporation process. Finally, the photoresist and the metal on it are removed by a lift-off process to form the metal reflective layer.

5. The method for preparing an LED chip according to claim 1, characterized in that, The specific steps for fabricating the metal interconnect layer on the fifth epitaxial layer include: On the side of the fifth epitaxial layer facing away from the sapphire substrate, a negative photoresist is coated corresponding to each of the partitions. The photoresist in the area where the metal interconnect layer is to be formed is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. Then, Al metal, Ti metal, Al metal, Ti metal, Al metal, Ti metal, Pt metal, and Ti metal are sequentially deposited using an electron beam evaporation process. Finally, the photoresist and the metal on it are removed by a lift-off process to form the metal interconnect layer.

6. The method for preparing an LED chip according to claim 1, characterized in that, The specific steps for fabricating a P-type conductive metal layer on the seventh epitaxial layer include: On the side of the seventh epitaxial layer facing away from the sapphire substrate, a negative photoresist is coated corresponding to each of the partitions. The photoresist in the area where the P-type conductive metal layer is to be formed is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. Then, Ti metal, Au metal, Ti metal, Ni metal, Ti metal, Ni metal and Ti metal are deposited sequentially using an electron beam evaporation process. Finally, the photoresist and the metal on it are removed by a lift-off process to form the P-type conductive metal layer.

7. The method for preparing an LED chip according to claim 1, characterized in that, The specific steps for preparing the P-type pad layer include: A negative photoresist is coated on the side of the N-type GaN layer facing away from the P-type conductive metal layer. The photoresist in the area where the P-type pad layer is to be formed is exposed by a photomask. After development, the photoresist in the unexposed areas is removed. Then, Ti metal, Ni metal and Au metal are deposited sequentially using an electron beam evaporation process. Finally, the photoresist and the metal on it are removed by a lift-off process to form the P-type pad layer.

8. The method for preparing an LED chip according to claim 1, characterized in that, The thicknesses of the metal reflective layers are as follows: ITO film thickness is 30 Å–50 Å, Ag metal thickness is 1200 Å–2000 Å, Ti metal thickness is 1000 Å–2000 Å, Ni metal thickness is 1000 Å–2000 Å, Pt metal thickness is 1000 Å–2000 Å, Ti metal thickness is 1000 Å–2000 Å, Ni metal thickness is 1000 Å–2000 Å, Pt metal thickness is 2000 Å–3000 Å, and Ti metal thickness is 30 Å–50 Å. The thicknesses of the metal bonding layers are as follows: Al metal thickness is 3000 Å–5000 Å, Ti metal thickness is 1000 Å–2000 Å, Al metal thickness is 3000 Å–5000 Å, Ti metal thickness is 1000 Å–2000 Å, and Al metal thickness is... The thicknesses of the P-type conductive metal layers are as follows: Ti metal thickness is 3000 Å to 5000 Å, Ti metal thickness is 1000 Å to 2000 Å, Pt metal thickness is 2000 Å to 3000 Å, and Ti metal thickness is 30 Å to 50 Å. The thickness of the metal is 1000Å–2000Å, the thickness of the Ti metal is 1000Å–2000Å, the thickness of the Ni metal is 1000Å–2000Å, and the thickness of the Ti metal is 30Å–50Å. The thicknesses of the P-type pad layers are as follows: the thickness of the Ti metal is 500Å–1000Å, the thickness of the Ni metal is 500Å–1000Å, and the thickness of the Au metal is 4000Å–6000Å.

9. The method for preparing an LED chip according to claim 1, characterized in that, The first, second, third, and fourth insulating layers are all SiO2 thin films. The first, second, third, and fourth insulating layers are all deposited using PECVD technology. The vias in the first insulating layer are formed using BOE etching solution, and the vias in the second and third insulating layers are formed using inductively coupled plasma etching technology.

10. An LED chip, characterized in that, It is manufactured using the method for preparing an LED chip according to any one of claims 1 to 9.

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