Flexible organic synapse transistor array mimicking visual perception and memory and preparation method and application thereof

Abstract

The application relates to a flexible organic synapse transistor array simulating visual perception and memory and a preparation method and application thereof, and belongs to the field of flexible electronic devices. The organic synapse transistor array is composed of multiple photosensitive organic synapse transistor units and adopts a topological structure of orthogonal cross addressing to realize visual perception and memory. The device array realizes imaging through gray scale mapping by reading the current change amount caused by a light stimulation signal; the visual learning process is simulated by adjusting the number and length of light pulses; the forgetting characteristics of visual information are simulated by using the relaxation time after the light pulse stimulation is over; and the light synapse function with long-term memory capacity can be presented. The flexible organic synapse transistor array provided by the application can simplify the manufacturing process and reduce the cost, has advantages such as simple structure and outstanding performance, can simulate a visual sensing memory system, and widens the application of heterojunction organic photosensitive semiconductors and devices in visual perception, image processing and neuromorphic computing.

Description

Technical Field

[0001] This invention belongs to the field of flexible electronic devices, and relates to a flexible organic synaptic transistor array that simulates visual perception and memory, its fabrication method, and its application. Background Technology

[0002] With the rapid development of the Internet of Things, artificial intelligence, and flexible electronics, single transistors or single-function devices often fall short of the demands of image perception and neuromorphic computing, limiting their applications in visual sensing, image recognition, and neuromorphic computing. Traditional image sensors and integrated chips primarily rely on silicon-based transistor arrays, such as charge-coupled devices (CCDs) and complementary metal-oxide-semiconductor (CMOS) devices. However, traditional silicon-based transistor arrays are typically fabricated on rigid substrates, making them ill-suited for emerging applications such as flexible wearable electronics, bendable smart sensing interfaces, and biomimetic vision systems. Furthermore, as the scale of device arrays continues to increase, system power consumption, heat dissipation pressure, and space occupation also increase. For neuromorphic applications, CCD and CMOS image sensors primarily handle image acquisition and signal readout, still relying on the traditional architecture where sensing, storage, and computation are separated. This makes it difficult to directly achieve bio-synaptic memory retention, weighting, and parallel processing functions at the device level, resulting in significant limitations in flexible, low-power, and integrated sensing-storage-computing neuromorphic vision systems.

[0003] Organic field-effect transistors (OFETs) possess advantages such as tunable structure, abundant material selection, low-temperature fabrication, compatibility with flexible substrates, and large-area processing potential. They also enable excellent optical signal sensing and amplification, making them a crucial technological pathway for constructing flexible artificial synapses and neuromorphic electronic devices. Compared to traditional rigid silicon-based transistor arrays, OFET-based photosensitive device arrays are more suitable for flexible wearable electronics and biomimetic visual sensing systems. By controlling the composition, interface state, and device structure of the photosensitive organic semiconductor thin film, functions such as low-power synaptic response, photoelectric modulation, memory retention, and multi-level conductivity control can be achieved, thus providing a solid foundation for constructing flexible optoelectronic synapse arrays.

[0004] While OFET (Organic Electron-Factory) artificial synaptic devices have made some progress in simulating synaptic plasticity, modulating photoresponse, and low-power information processing, several shortcomings remain. On the one hand, most devices still use rigid substrates, making it difficult to meet the requirements of flexible wearable systems for flexibility, adhesion, and mechanical stability. On the other hand, mainstream research still focuses on achieving basic synaptic functions with a single OFET synaptic device. How to achieve the array design, fabrication, and integration of flexible devices to enhance their potential in practical applications such as image sensing, visual memory, and neuromorphic computing remains a significant challenge. Therefore, designing and fabricating a flexible organic synaptic transistor array that simulates visual perception and memory is of great significance and application value for promoting intelligent sensing and brain-like computing systems. Summary of the Invention

[0005] In view of this, one objective of the present invention is to provide a flexible organic synaptic transistor array that simulates visual perception and memory; a second objective of the present invention is to provide a method for fabricating a flexible organic synaptic transistor array that simulates visual perception and memory; and a third objective of the present invention is to provide an application of a flexible organic synaptic transistor array that simulates visual perception and memory in the fields of visual sensing, image processing, and neuromorphic computing.

[0006] 1. According to one aspect of the present invention, a flexible organic synaptic transistor array is provided to simulate visual perception and memory, the organic synaptic transistor array comprising n×m photosensitive high-performance organic synaptic transistor units arranged in a matrix to realize visual imaging and memory.

[0007] This organic synaptic transistor array employs an orthogonal cross-addressing topology: The gates of the organic synaptic transistor cells located in the same horizontal row are electrically connected to each other, forming a horizontal word line; The drains of the organic synaptic transistor cells located in the same vertical column are electrically connected to each other, forming a vertical bit line.

[0008] In this configuration, word lines and bit lines are arranged orthogonally in spatial projection, and an organic synaptic transistor unit is arranged at each intersection node of word lines and bit lines. Furthermore, physical and electrical isolation is achieved between the intersection nodes and adjacent device units through a dielectric layer to avoid charge crosstalk and short circuits.

[0009] Furthermore, the physical device structure of each organic synaptic transistor unit is a top-gate bottom contact structure, including a substrate, a source / drain electrode pair located on the surface of the substrate, an organic heterojunction photosensitive semiconductor layer located on the surfaces of the substrate and the source / drain electrode pair, a double dielectric layer formed by dielectric layer I and dielectric layer II located on the surface of the organic heterojunction photosensitive semiconductor layer, and a gate located on the surface of the double dielectric layer.

[0010] Furthermore, the source / drain electrodes are interdigitated electrode pairs located between the surface of the substrate and the organic heterojunction photosensitive semiconductor layer, and a conductive channel with micro-nano scale spacing is formed between the source and drain electrodes. The gate region covers the channel region of the corresponding source / drain electrode pair, and the number of source / drain electrode pairs and gates are both n×m (n and m are both greater than or equal to 2).

[0011] Furthermore, the number of source / drain electrode pairs and gate electrodes is preferably 10 × 10.

[0012] Furthermore, the organic synaptic transistor array divides the target image into n×m grayscale pixels and uses each organic synaptic transistor unit to simulate a visual neuron. Organic synaptic transistor units all possess excellent photosensitive memory characteristics, which are used to perform synaptic weight memory of the gray values ​​of corresponding pixels, thereby realizing the learning and forgetting simulation of external visual information.

[0013] Furthermore, in simulating visual perception and memory, the organic synaptic transistor array uses an external circuit to read the postsynaptic current changes on the bit lines and converts these changes into grayscale values ​​for corresponding pixels using a grayscale mapping mechanism. The number and duration of the input light pulses characterize the learning and iterative features of the brain's visual system, while the relaxation time after the light pulse stimulation ends characterizes the forgetting characteristics of visual information.

[0014] Furthermore, the substrate material of the organic synaptic transistor array is any one or more of polyethylene naphthalate, polyethylene terephthalate, polyimide, polydimethylsiloxane, polycarbonate, polyvinyl alcohol, glass, silicon dioxide / silicon, and sapphire.

[0015] The source, drain, or gate material of the organic synaptic transistor unit is any one of gold, silver, aluminum, copper, chromium, platinum, titanium, nickel, indium tin oxide, fluorine-doped tin oxide, zinc aluminum oxide, and conductive polymer.

[0016] Among them, the conductive polymer is a polymer material with a conjugated main electron system on its main chain and achieves a conductive state through doping, including any one of polyaniline, polypyrrole, polythiophene, poly(3,4-ethylenedioxythiophene) and polyacetylene.

[0017] The organic heterojunction photosensitive semiconductor material is a combination of at least two of the following: indahedron dithiophene-benzothiadiazole copolymer or its derivatives, poly-3-hexylthiophene, poly{4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b']dithiophenyl-2,6-diyl}{3-fluoro-2-[(2-ethylhexyl)carbonyl]thiophene[3,4-b]thiophenediyl} or its derivatives, benzodithiophene, and diketopyrrolopyrrole.

[0018] The dielectric material of the organic synaptic transistor array is any one or more of the following: polyacrylic acid electrolytes, polyethylene glycol and its derivatives, polyvinyl alcohol and its derivatives, polyacrylamide and its derivatives, polymethyl methacrylate and its derivatives, polystyrene and its derivatives, amorphous fluoropolymers and their derivatives, transparent metal oxide dielectrics, and silicon dioxide.

[0019] 2. According to another aspect of the present invention, a method for fabricating the above-described flexible organic synaptic transistor array simulating visual perception and memory is provided, comprising the following steps: (1) On the substrate surface, using mask I, a source / drain electrode pair consisting of n×m source electrodes and n×m drain electrodes is prepared by magnetron sputtering, vacuum thermal evaporation or atomic layer deposition (n and m are both greater than or equal to 2). (2) An organic heterojunction photosensitive semiconductor layer is prepared on the source / drain electrode pair and the substrate surface by spin coating, blade coating or inkjet printing, and then annealed. (3) On the surface of the organic heterojunction photosensitive semiconductor layer, dielectric layer I and dielectric layer II are formed sequentially by spin coating, blade coating, inkjet printing, atomic layer deposition, vacuum thermal evaporation or magnetron sputtering. (4) On the surface of dielectric layer II, a mask template II is combined and an array of n×m gates is formed by magnetron sputtering, vacuum thermal evaporation or atomic layer deposition to obtain a flexible organic synaptic transistor array.

[0020] Furthermore, in step (1), the characteristic physical pattern of the mask template I is manifested as multiple parallel elongated interdigital patterns, with square or circular patterns symmetrically arranged at both ends of each elongated interdigital pattern, which are used to prepare elongated interdigital source / drain electrode pairs.

[0021] Furthermore, in step (2), when preparing the organic heterojunction photosensitive semiconductor layer by spin coating, the organic semiconductor material is optimized by blending two or more organic polymer semiconductors with high mobility and high photoresponse capability to form an organic hetero semiconductor layer material solution. The organic polymer semiconductors include, but are not limited to, indahedron dithiophene-benzothiadiazole copolymer and poly(3-hexylthiophene). Furthermore, in the organic heterosemiconductor layer material solution, the total concentration of the semiconductor material is 5 ~ 20 mg / mL, and the mass ratio of the daunodithiophene-benzothiadiazole copolymer to poly(3-hexylthiophene) is 1:10 ~ 10:1; Furthermore, the spin coating speed is 500 ~ 3000 rpm, the spin coating time is 30 ~ 120 s; the annealing temperature after spin coating is 80 ~ 120 ℃, and the annealing time is not less than 20 min.

[0022] Furthermore, in step (4), the characteristic physical pattern of the mask template II is manifested as multiple parallel strip patterns, which are used to prepare a parallel strip gate array, and the extension direction of the parallel strip patterns is orthogonal to the extension direction of the elongated interdigitated pattern.

[0023] Furthermore, the fabricated gate array serves as a top gate structure, covering a double dielectric layer; in the overlapping region of each strip gate and the elongated interdigitated source / drain electrode pair, an independently addressable organic synaptic transistor unit is formed in the organic synaptic transistor array.

[0024] 3. According to another aspect of the present invention, the above-described flexible organic synaptic transistor array simulating visual perception and memory is provided for application in the fields of visual perception, image processing, artificial vision systems, or neuromorphic computing.

[0025] The beneficial effects of this invention are as follows: (1) This invention provides a flexible organic synaptic transistor array that simulates visual perception and memory. It mainly uses photosensitive organic synaptic transistors as basic device units. Through the synergistic effect of the organic heterojunction photosensitive semiconductor layer and the double dielectric layer, it realizes multi-band optical signal response, synaptic weight regulation, and low-voltage operation. This device array can convert external optical stimulus signals into readable postsynaptic current signals, providing a new device architecture and technical path for flexible visual perception and artificial visual memory devices.

[0026] (2) The flexible organic synaptic transistor array proposed in this invention utilizes the three-terminal structure advantage of a single organic synaptic transistor unit and simulates the learning, memory and forgetting process of visual information by controlling the synaptic response characteristics of the photoelectric pulse device. At the same time, by constructing n×m photosensitive organic synaptic transistor units into a matrix array and adopting an addressing method with orthogonal cross-addressing of word lines and bit lines, parallel acquisition, reading and grayscale mapping imaging of multi-pixel visual information can be realized, thereby meeting the application requirements of high-performance image perception, image memory and artificial vision systems.

[0027] (3) The flexible organic synaptic transistor array proposed in this invention has advantages such as clear structure, good process compatibility, low fabrication cost, and ease of large-area integration. Its fabrication process can employ methods such as magnetron sputtering, vacuum thermal evaporation, atomic layer deposition, spin coating, blade coating, or inkjet printing, and can be combined with flexible substrates, intrinsically flexible organic semiconductor materials, and dielectric materials to construct flexible, lightweight, and highly integrated device arrays. Therefore, this invention not only promotes the development of flexible visual sensors and artificial vision systems, but also provides important support for neuromorphic electronic devices and intelligent terminals that integrate sensing, storage, and computing.

[0028] (4) The flexible organic synaptic transistor array proposed in this invention can also serve as an important functional carrier for brain-like neuromorphic electronic systems, realizing a high-resolution wide-angle bionic vision system with excellent surface adaptability. It can be fused and integrated with various flexible sensing materials, photoelectric detection devices, memory devices and traditional image sensors, achieving synergistic enhancement of visual perception, synaptic memory and parallel computing functions at the device array level, thus providing an important foundation for the development and application of new sensing-storage-computing integrated electronic devices, intelligent vision systems and flexible intelligent terminals.

[0029] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0030] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the mask template for the flexible organic synaptic transistor array provided in Example 1, where (a) is mask template I for fabricating source / drain electrode pairs and (b) is mask template II for fabricating the gate array; Figure 2 This is a schematic diagram of the flexible organic synaptic transistor array provided in Example 1; Figure 3 A physical diagram of the flexible organic synaptic transistor array provided in Example 1; Figure 4 The diagram shows the characteristic curves of a single organic synaptic transistor unit in the array provided in Example 1, where (a) is the transfer characteristic curve and (b) is the output characteristic curve. Figure 5 A graph showing the change in excitatory postsynaptic current of a single organic synaptic transistor unit in the array provided in Example 1 as a function of the duration of light stimulation. Figure 6 A graph showing the change in excitatory postsynaptic current of a single organic synaptic transistor unit in the array provided in Example 1 as the number of light stimuli varies. Figure 7 A schematic diagram of the equivalent circuit of the flexible organic synaptic transistor array provided in Example 1; Figure 8 The diagram shows (a) a visual nerve simulation of the organic synaptic transistor array prepared in Example 1, and (b) a mapping image of the current change of each pixel under different pulse numbers and different pulse end times.

[0031] Figure reference numerals: 1-substrate; 2-source; 3-drain; 4-organic heterojunction photosensitive semiconductor layer; 5-dielectric layer I; 6-dielectric layer II; 7-gate. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0033] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0034] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0035] The organic heterojunction photosensitive semiconductor layer materials used in the following examples are high-mobility polymer semiconductor materials, namely, dazometrene-benzothiadiazole copolymer and low-cost poly-3-hexylthiophene. The former has the following structural formula: The latter's structural formula is , where n is a positive integer.

[0036] Unless otherwise specified, the following embodiments are performed according to existing technology. Unless otherwise stated, the raw materials and solvents in the embodiments of the present invention can be purchased commercially. The benzothiophene-benzothiadiazole copolymer is available from Shenzhen Ruixun Optoelectronic Materials Technology Co., Ltd. Poly(3-hexylthiophene) is available from Beijing Bailingwei Technology Co., Ltd. Chlorobenzene solvent and butyl acetate solvent are available from Sigma-Aldrich (Shanghai) Trading Co., Ltd. Polyacrylic acid and polyethylene glycol are available from Sigma-Aldrich (Shanghai) Trading Co., Ltd. Polystyrene is available from Sigma-Aldrich (Shanghai) Trading Co., Ltd. Methanol solvent is available from Shanghai Aladdin Biochemical Technology Co., Ltd. The polyethylene naphthalate (PEG) substrate is available from Shenzhen Huanan Xiangcheng Technology Co., Ltd.

[0037] Example 1 This embodiment provides a flexible organic synaptic transistor array that simulates visual perception and memory, the structure of which is as follows: Figure 1 As shown, from top to bottom, it includes a substrate 1, an organic heterojunction photosensitive semiconductor layer 4, a dielectric layer I 5, a dielectric layer II 6, and a gate 7. Meanwhile, a source 2 and a drain 3 with a channel pattern are located on the surfaces at both ends of the substrate 1.

[0038] The fabrication method of this flexible organic synaptic transistor array is as follows: (1) Polyethylene naphthalate with a thickness of 125 μm was used as substrate 1; (2) On the surface of substrate 1, a vacuum thermal evaporation process is used through mask I (vacuum degree is approximately 2 × 10⁻⁶). -4 A 50 nm thick gold layer was prepared using a evaporation rate of approximately 0.5–1.5 Å / s (Pa, evaporation rate of approximately 0.5–1.5 Å / s) to serve as the source 2 and drain 3 of a 10 × 10 array, with the channel width and length between the source 2 and drain 3 being 3.75 mm and 0.15 mm, respectively. (3) In a glove box under a nitrogen atmosphere, prepare a solution of indahedron dithiophene-benzothiadiazole copolymer:poly3-hexylthiophene chlorobenzene with a total concentration of 10 mg / mL and a mass ratio of 1:3 and spin-coat it onto the substrate 1 with source 2 and drain 3 prepared in step (2) (wherein the spin coating speed is 1000 rpm and the spin coating time is 30 s). After spin coating, anneal it on a heating stage at 120 ℃ for 20 min to prepare the organic heterojunction photosensitive semiconductor layer 4. (4) In a glove box under a nitrogen atmosphere, a polystyrene butyl acetate solution with a concentration of 5 mg / mL was spin-coated onto the organic heterojunction photosensitive semiconductor layer 4 obtained in step (3) (the spin-coating speed was 2000 rpm and the spin-coating time was 30 s), and then left to stand for 10 min to prepare dielectric layer I5. (5) In a glove box under nitrogen atmosphere, a methanol solution of polyacrylic acid: polyethylene glycol with a mass ratio of 7:3 (wherein the concentration of polyacrylic acid is 30 mg / mL) is spin-coated onto the dielectric layer I5 obtained in step (4) (wherein the spin-coating speed is 500 rpm, the spin-coating time is 60 s, and the spin-coating is done twice). Then, the dielectric layer II6 is prepared by annealing on a heating stage at 80 ℃ for 120 min. (6) On dielectric layer II6, a vacuum thermal evaporation process (vacuum degree approximately 2 × 10⁶) is used through mask II. - 4 A 50 nm thick gold gate 7 was prepared by evaporation rate of approximately 0.5 ~ 1.5 Å / s (Pa). Ten gates covered the channel portions formed between the ten source and drain electrodes, thus preparing a flexible organic synaptic transistor array.

[0039] Examples 2 to 15 The differences in the fabrication process of the flexible organic synaptic transistor arrays provided in Examples 2 to 15 compared to those in Example 1 are shown in Table 1. The parts not described are the same as those in Example 1.

[0040] Table 1. Conditions for fabricating flexible organic synaptic transistor arrays simulating visual perception and memory in different embodiments.

[0041] Using an Agilent 4155C semiconductor parameter analyzer, the electrical performance of each organic synaptic transistor unit in the organic synaptic transistor array prepared in Example 1 was tested. The tests showed that the performance fluctuations between transistor device units were small, and the uniformity of large-area film deposition was good. Figure 4 Figures (a) and (b) show typical transfer and output characteristic curves of a single organic synaptic transistor unit in the organic synaptic transistor array of Example 1. Figure 4 It can be seen that individual basic components in the organic synaptic transistor array can operate stably at a low voltage of -1.5 V, exhibiting good low-power transistor characteristics.

[0042] Furthermore, using an Agilent 4155C semiconductor parameter analyzer, the synaptic performance of each organic synaptic transistor unit in the organic synaptic transistor array prepared in Example 1 was tested. The synaptic plasticity of the device was examined by adjusting the duration and amount of light stimulation. The synaptic response of the organic synaptic transistor unit is as follows: Figure 5 and Figure 6 As shown, Figure 5 The figure shows the change curve of excitatory postsynaptic current in a single transistor unit as a function of the duration of optical stimulation. Figure 6The figure shows the excitatory postsynaptic current variation curve of a single transistor unit as a function of the amount of light stimulation. From... Figure 5 and Figure 6 It can be seen that with the increase of photostimulation duration or the accumulation of stimulation pulses, the response amplitude and retention time of the postsynaptic current are significantly enhanced. These results indicate that the organic synaptic transistor array provided by this invention possesses excellent photoelectric pulse response synaptic weight modulation capability, and has great application potential in neuromorphic computing and high-density information storage.

[0043] To verify the feasibility of the flexible organic synaptic transistor array in system-level applications, visual perception and memory simulation tests were conducted on the organic synaptic transistor array prepared in Example 1 using an Agilent 4155C semiconductor parameter analyzer and an optocoupler isolation relay. Figure 7 The diagram shown is an equivalent circuit diagram of the organic synaptic transistor array provided in Embodiment 1. Figure 7 As shown, the array is divided into 10 columns, with 10 synaptic transistors in each column connected in parallel. Their drains are all connected to the bias terminal of that column, and their sources are all connected to a common ground terminal. The gates of all transistors in the same row are shared, used to regulate the gate bias voltage of the device. Through this parallel column connection and independent gate addressing circuit architecture, the synaptic weights of any specific pixel (i.e., organic synaptic transistor unit) in the array can be precisely modulated and read independently.

[0044] In the visual perception and memory simulation test, a mask with an "arrow" pattern was first introduced in front of the organic synaptic transistor array prepared in Example 1 to block it. Then, the patterned synaptic transistor array was stimulated with 1, 20, and 50 light pulses (wavelengths of 520 nm and 685 nm, respectively) (pulse width 400 ms, pulse interval 100 ms), and the current change of each organic synaptic transistor unit (pixel) in the transistor array before and after the pulse was recorded. The number of pulses represents the number of learning iterations in the brain, while the time after the pulse corresponds to the forgetting time.

[0045] Visual perception and memory simulation of the learning and forgetting process, such as Figure 8 As shown, (a) is a schematic diagram of a visual neural simulation, and (b) is an image mapping of current changes in each pixel in the array under different pulse numbers and different pulse end times. Figure 8 As can be seen, after multiple pulse stimuli (e.g., 50 times), the array can present a clear "arrow" image with high contrast and maintain it for a relatively long time; while the image traces from a small number of stimuli decay rapidly. That is, the organic synaptic transistor array provided in this embodiment exhibits the characteristics of rapid learning and slow forgetting, effectively simulating the dynamic learning and forgetting process in humans, and has good potential in visual perception and memory.

[0046] In summary, this invention provides an organic synaptic transistor array for simulating visual perception and memory, its fabrication method, and its applications. This organic synaptic transistor array primarily uses organic synaptic transistors as its basic device units. Its semiconductor layer utilizes two solution-processed polymer organic semiconductor materials, forming an organic heterojunction photosensitive semiconductor layer to achieve photoelectric characteristic modulation of the device. This invention develops an organic synaptic transistor array that simulates visual perception and memory through photoelectric stimulation under low-voltage operation. The organic synaptic transistor array provided by this invention exhibits excellent synaptic function and can effectively simulate the learning and forgetting process through a series of photoelectric pulse stimulations, demonstrating a certain long-range memory capability. Compared to traditional technologies, the organic synaptic transistor array provided by this invention introduces an independent row-column addressing circuit architecture, which simplifies the manufacturing process and reduces costs from an array perspective. It not only has advantages such as simple structure, superior performance, and low power consumption, but also successfully simulates a visual sensing and memory system, thereby broadening the application of heterojunction organic semiconductors in visual sensing, image processing, and neuromorphic computing.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A flexible organic synaptic transistor array that simulates visual perception and memory, characterized in that, It includes a matrix arrangement of n×m photosensitive high-performance organic synaptic transistor units to achieve visual imaging and memory, where n and m are both greater than or equal to 2; When simulating visual perception and memory, this organic synaptic transistor array divides the target image into n×m grayscale pixels and uses the photosensitive memory characteristics of each organic synaptic transistor unit to simulate visual neurons, performing synaptic weight memory on the grayscale values ​​of the corresponding pixels, thereby simulating the learning and forgetting of external visual information.

2. The organic synaptic transistor array according to claim 1, characterized in that, This organic synaptic transistor array employs an orthogonal cross-addressing topology: The gates of the organic synaptic transistor units located in the same horizontal row are electrically connected to each other, forming a horizontal word line; The drains of the organic synaptic transistor units located in the same vertical column are electrically connected to each other, forming a vertical bit line; The word lines and bit lines are arranged orthogonally in spatial projection, and an organic synaptic transistor unit is arranged at each intersection node of the word line and bit line; and physical and electrical isolation is achieved between the intersection node and adjacent organic synaptic transistor units through a dielectric layer to avoid charge crosstalk and short circuit.

3. The organic synaptic transistor array according to claim 1, characterized in that, When the organic synaptic transistor array simulates visual perception and memory, the external circuit reads the postsynaptic current change on the bit line and uses a grayscale mapping mechanism to convert the current change into the grayscale value of the corresponding pixel for imaging. Among them, the number and duration of input light pulses characterize the learning iteration characteristics of the brain's visual system, while the relaxation time after the light pulse stimulation ends characterizes the forgetting characteristics of visual information.

4. The organic synaptic transistor array according to claim 1, characterized in that, The organic synaptic transistor unit includes a substrate (1), a source / drain electrode pair located on the surface of the substrate (1), an organic heterojunction photosensitive semiconductor layer (4) located on the surface of the substrate (1) and the source / drain electrode pair, a double dielectric layer formed by dielectric layer I (5) and dielectric layer II (6) located on the surface of the organic heterojunction photosensitive semiconductor layer (4), and a gate (7) located on the surface of the double dielectric layer. The source / drain electrode pair is an interdigitated electrode pair located between the substrate (1) and the organic heterojunction photosensitive semiconductor layer (4), and a conductive channel with micro-nano scale spacing is formed between the source (2) and the drain (3). The gate (7) covers the channel region of the corresponding source / drain electrode pair.

5. The organic synaptic transistor array according to claim 4, characterized in that, The substrate material is any one or more of polyethylene naphthalate, polyethylene terephthalate, polyimide, polydimethylsiloxane, polycarbonate, polyvinyl alcohol, glass, silicon dioxide / silicon and sapphire; The source, drain, or gate material is any one of gold, silver, aluminum, copper, chromium, platinum, titanium, nickel, indium tin oxide, fluorine-doped tin oxide, zinc aluminum oxide, and conductive polymer; the conductive polymer is a polymer material with a conjugated main electron system on its main chain and achieves a conductive state through doping, including any one of polyaniline, polypyrrole, polythiophene, poly(3,4-ethylenedioxythiophene), and polyacetylene; The organic heterojunction photosensitive semiconductor layer material is a combination of at least two of the following: indahedron dithiophene-benzothiadiazole copolymer or its derivatives, poly3-hexylthiophene, poly{4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b']dithiophenyl-2,6-diyl}{3-fluoro-2-[(2-ethylhexyl)carbonyl]thiophene[3,4-b]thiophenediyl} or its derivatives, benzodithiophene, and diketopyrrolopyrrole; The dielectric layer material is any one or more of the following: polyacrylic acid electrolytes, polyethylene glycol and its derivatives, polyvinyl alcohol and its derivatives, polyacrylamide and its derivatives, polymethyl methacrylate and its derivatives, polystyrene and its derivatives, amorphous fluoropolymers and their derivatives, transparent metal oxide dielectrics, and silicon dioxide.

6. A method for fabricating a flexible organic synaptic transistor array that simulates visual perception and memory, characterized in that, The method includes: Using mask template I, source / drain electrode pairs consisting of n×m source electrodes and n×m drain electrodes are prepared on the substrate surface by magnetron sputtering, vacuum thermal evaporation or atomic layer deposition, where n and m are both greater than or equal to 2; Organic heterojunction photosensitive semiconductor layers are prepared on the source / drain electrode pair and the substrate surface by spin coating, blade coating or inkjet printing, and then annealed. On the surface of an organic heterojunction photosensitive semiconductor layer, dielectric layer I and dielectric layer II are sequentially prepared by spin coating, blade coating, inkjet printing, atomic layer deposition, vacuum thermal evaporation or magnetron sputtering. On the surface of dielectric layer II, an array of n×m gates is formed by combining mask II and preparing it through magnetron sputtering, vacuum thermal evaporation or atomic layer deposition, thereby obtaining a flexible organic synaptic transistor array.

7. The method according to claim 6, characterized in that, The characteristic physical pattern of the mask template I is multiple parallel, elongated interdigitated patterns. Each elongated interdigitated pattern has square or circular patterns symmetrically arranged at both ends, which are used to prepare elongated interdigitated source / drain electrode pairs.

8. The method according to claim 7, characterized in that, The characteristic physical pattern of the mask template II is a plurality of parallel strip patterns, which are used to prepare a parallel strip gate array, and the extension direction of the strip patterns is orthogonal to the extension direction of the elongated interdigitated pattern. The fabricated gate array serves as the top gate structure, covering a double dielectric layer. In the overlapping region of each strip gate and the elongated interdigitated source / drain electrode pair, an independently addressable organic synaptic transistor unit is formed in the organic synaptic transistor array.

9. The method according to claim 6, characterized in that, When preparing an organic heterojunction photosensitive semiconductor layer using spin coating, the organic semiconductor material is optimized by blending two or more organic polymer semiconductors with high mobility and high photoresponse capability to form an organic heterojunction semiconductor layer material solution. The organic polymer semiconductors include, but are not limited to, indahedron dithiophene-benzothiadiazole copolymer and poly-3-hexylthiophene. In the organic heterosemiconductor layer material solution, the total concentration of the semiconductor material is 5 ~ 20 mg / mL, and the mass ratio of the daunodithiophene-benzothiadiazole copolymer to poly(3-hexylthiophene) is 1:10 ~ 10:1; The spin coating speed is 500 ~ 3000 rpm, and the spin coating time is 30 ~ 120 s; the annealing temperature after spin coating is 80 ~ 120 ℃, and the annealing time is not less than 20 min.

10. The application of the flexible organic synaptic transistor array according to any one of claims 1 to 9 in the fields of visual perception, image processing, artificial vision systems, or neuromorphic computing.

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