Display device

Abstract

A display device includes a display panel including a light emitting element, a driver including a first gate emission signal generator generating a first driving signal and a second gate emission signal generator generating a second driving signal different from the first driving signal, a first conductive layer including a clock line electrically connected to each of the first gate emission signal generator and the second gate emission signal generator, and a second conductive layer disposed on the first conductive layer, and the second conductive layer defines a first opening overlapping at least a portion of the clock line and a second opening spaced apart from the first opening in a plan view.

Description

Technical Field

[0001] The embodiments relate to display devices and electronic devices including display devices. Background Technology

[0002] The display device may include a display panel and a driver for driving the display panel. The driver may include a gate driver for providing gate signals, a data driver for providing data voltages, and a transmit driver for providing transmit signals.

[0003] The display panel may include a power supply electrode connected to the cathode electrode of the pixel to stably supply voltage to the cathode electrode, and a clock line connected to the gate driver and the emitter driver. When the power supply electrode and the clock line overlap in a plan view, parasitic capacitance may be generated between the power supply electrode and the clock line. Summary of the Invention

[0004] The embodiment provides a display device with reduced power consumption.

[0005] An embodiment provides an electronic device including a display device.

[0006] A display device according to an embodiment of the present disclosure includes: a display panel including a light-emitting element; a driver including a first gate emission signal generator that generates a first driving signal and a second gate emission signal generator that generates a second driving signal different from the first driving signal; a first conductive layer including a clock line electrically connected to each of the first gate emission signal generator and the second gate emission signal generator; and a second conductive layer disposed on the first conductive layer, wherein the second conductive layer defines a first opening that overlaps with at least a portion of the clock line in a plan view and a second opening spaced apart from the first opening.

[0007] In an embodiment, the second gate emitter signal generator may be adjacent to the first gate emitter signal generator in a first direction, and the first gate emitter signal generator and the second gate emitter signal generator may be symmetrical with respect to a first virtual line extending in a second direction intersecting the first direction.

[0008] In an embodiment, the driver may include multiple stages arranged in rows (row-based); each of the multiple stages may include a first gate emit signal generator and a second gate emit signal generator, and the clock line may include: a first clock line connected to a stage in an odd-numbered row of the multiple stages; and a second clock line connected to a stage in an even-numbered row of the multiple stages.

[0009] In an embodiment, the first opening may include: a first sub-opening that overlaps with at least a portion of a first clock line in a plan view; and a second sub-opening that overlaps with at least a portion of a second clock line in a plan view.

[0010] In an embodiment, the first sub-opening and the second sub-opening may be symmetrical with respect to a second virtual line extending in a second direction.

[0011] In an embodiment, the area where the first sub-aperture and the first clock line overlap in the plan view can be equal to the area where the second sub-aperture and the second clock line overlap in the plan view.

[0012] In an embodiment, the first clock line may include: a first extension portion extending in a second direction; and a first protrusion portion protruding from the first extension portion, and a first sub-opening may overlap with the first extension portion in a plan view.

[0013] In an embodiment, the second clock line may include: a second extension portion extending in a second direction; and a second protrusion portion protruding from the second extension portion, and the second sub-opening may overlap with the second extension portion in a plan view.

[0014] In an embodiment, the second opening may include: a third sub-opening; and a fourth sub-opening spaced apart from the third sub-opening in a first direction, and the fourth sub-opening being staggered relative to the third sub-opening in a second direction.

[0015] In an embodiment, the planar shape of each of the first and second sub-openings may be different from the planar shape of each of the third and fourth sub-openings.

[0016] In an embodiment, the first opening may overlap with the first clock line and the second clock line in a plan view.

[0017] In an embodiment, the first conductive layer may further include a low-voltage line disposed between the first clock line and the second clock line.

[0018] In an embodiment, the second conductive layer may overlap with the first gate emitter and the second gate emitter in a planar view.

[0019] In an embodiment, the second conductive layer may include a first region overlapping the clock line in a plan view and a second region not overlapping the clock line in a plan view, the first opening may be defined in the first region, and the second opening may be defined in the second region.

[0020] In an embodiment, the light-emitting element may include a pixel electrode, a common electrode, and a light-emitting layer between the pixel electrode and the common electrode, and the second conductive layer may be electrically connected to the common electrode.

[0021] An electronic device according to an embodiment of the present disclosure includes a display device and a processor that provides input image data and input signals to the display device. The display device includes: a display panel including light-emitting elements; a driver including a first gate emission signal generator that generates a first driving signal and a second gate emission signal generator that generates a second driving signal different from the first driving signal; a first conductive layer including a clock line electrically connected to each of the first and second gate emission signal generators; and a second conductive layer disposed on the first conductive layer, the second conductive layer defining a first opening overlapping at least a portion of the clock line in a plan view and a second opening spaced apart from the first opening.

[0022] In an embodiment, the second gate emitter signal generator may be adjacent to the first gate emitter signal generator in the first direction, and the first gate emitter signal generator and the second gate emitter signal generator may be symmetrical with respect to a virtual line extending in a second direction intersecting the first direction.

[0023] In an embodiment, the clock line may include a first clock line and a second clock line spaced apart from the first clock line in a first direction, and the first opening may include a first sub-opening that overlaps with at least a portion of the first clock line in a plan view and a second sub-opening that overlaps with at least a portion of the second clock line in a plan view.

[0024] In an embodiment, the first sub-opening and the second sub-opening may be symmetrical with respect to a virtual line extending in a second direction.

[0025] In an embodiment, the area where the first sub-aperture and the first clock line overlap in the plan view can be equal to the area where the second sub-aperture and the second clock line overlap in the plan view.

[0026] In a display device according to an embodiment of the present disclosure, the display device may include a conductive layer defining an opening that overlaps with a first clock line and a second clock line in a plan view. The area of ​​the first clock line overlapping the opening in the plan view and the area of ​​the second clock line overlapping the opening in the plan view may be substantially the same. Therefore, the parasitic capacitance formed between the first clock line and the second clock line and the conductive layer can be reduced, and thus the power consumption of the display device can be reduced, and the deviation between the parasitic capacitance formed between the first clock line and the conductive layer and the parasitic capacitance formed between the second clock line and the conductive layer can be minimized. Attached Figure Description

[0027] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is shown Figure 1 A block diagram of the display device.

[0029] Figure 3 It is along Figure 1 The cross-sectional view taken from line II′.

[0030] Figure 4 It is shown Figure 2 A block diagram of an example gate emitter driver.

[0031] Figure 5 It is shown that it includes Figure 4 A block diagram of an example stage in a gate emitter driver.

[0032] Figure 6 It is shown that it includes Figure 4 A circuit diagram of an example stage in a gate emitter driver.

[0033] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 This is a layout diagram illustrating the stages included in a gate emitter driver according to an embodiment of the present disclosure.

[0034] Figure 23 , Figure 24 and Figure 25 This is a layout diagram illustrating the stages included in a gate emitter driver according to an embodiment of the present disclosure.

[0035] Figure 26 , Figure 27 and Figure 28 This is a layout diagram illustrating the stages included in a gate emitter driver according to an embodiment of the present disclosure.

[0036] Figure 29 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0037] Figure 30 This is a schematic diagram illustrating an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0038] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0039] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0040] Reference Figure 1 The display device DD may include a display panel 100.

[0041] Display panel 100 may include a display area DA and a non-display area NDA. The display area DA may be defined as an area that generates light to display an image. Display panel 100 may include pixels PX disposed in the display area DA. For example, the pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 may be perpendicular to the first direction DR1. Each of the plurality of pixels PX may generate light according to a driving signal. Therefore, an image can be displayed in the display area DA. For example, the image may be displayed on a third direction DR3 that intersects each of the first direction DR1 and the second direction DR2. For example, the third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2.

[0042] The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can at least partially surround the display area DA in a plan view. The non-display area NDA can be defined as an area where no image is displayed. The non-display area NDA can include the peripheral area PA, the bend area BA, and the pad area PDA.

[0043] The peripheral region PA can be located around the display region DA. The peripheral region PA can at least partially surround the display region DA in the plan view.

[0044] The bending region BA can be located on one side of the peripheral region PA. For example, the bending region BA can extend from one side of the peripheral region PA and can be bent in the downward direction. In other words, the display panel 100 can be bent relative to a reference axis extending in the first direction DR1 within the bending region BA. In this case, the pad region PDA can be located on the bottom surface of the display device DD. When the display panel 100 is in the unfolded state, the bending region BA can be located between the peripheral region PA and the pad region PDA.

[0045] The pad area PDA can be spaced apart from the peripheral area PA. For example, when the display panel 100 is in the unfolded state, the pad area PDA and the peripheral area PA can be spaced apart from each other in the second direction DR2. The bending area BA can be located between the pad area PDA and the peripheral area PA. The display panel 100 may also include pads PD disposed in the pad area PDA.

[0046] The display panel 100 may include a first driver DRV1, a second driver DRV2, and a driver chip D-IC disposed in the non-display area NDA.

[0047] The first driver DRV1 and the second driver DRV2 can be disposed in the peripheral region PA of the display panel 100. The first driver DRV1 and the second driver DRV2 can be spaced apart from each other. For example, the first driver DRV1 can be disposed in the peripheral region PA adjacent to a first side (e.g., the left side) of the display area DA, and the second driver DRV2 can be disposed in the peripheral region PA adjacent to a second side (e.g., the right side) of the display area DA. In embodiments, each of the first driver DRV1 and the second driver DRV2 can correspond to the description below. Figure 2 The gate emitter driver 300. In an embodiment, one of the first driver DRV1 and the second driver DRV2 may be omitted.

[0048] A driver chip D-IC can be disposed in the pad area PDA of the display panel 100. The driver chip D-IC can be connected to the pad PD via an anisotropic conductive film. The driver chip D-IC can provide drive signals to the pixel PX. The drive signals can include various signals for driving the pixel PX, such as drive voltage or data voltage. The drive signals can be transmitted to the pixel PX via the driver chip D-IC and the pad PD. In an embodiment, the driver chip D-IC can correspond to Figure 2 Data drive 500.

[0049] although Figure 1 Although not shown, the printed circuit board can be disposed in the pad area PDA of the display panel 100. The printed circuit board can be connected to the pad PD via an anisotropic conductive film. For example, the printed circuit board can be a flexible printed circuit board (FPCB).

[0050] Figure 2 It is shown Figure 1 A block diagram of the display device.

[0051] Reference Figure 1 and Figure 2 The display device DD may include a display panel 100 and a panel driver for driving the display panel 100. The panel driver may include a controller 200, a gate emitter driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0052] The display panel 100 may include gate lines GL, data lines DL, emitter lines EL, and pixels PX. Pixels PX may be electrically connected to the gate lines GL, data lines DL, and emitter lines EL. For example, each of the multiple gate lines GL may extend in a first direction DR1, each of the multiple emitter lines EL may extend in the first direction DR1, and each of the multiple data lines DL may extend in a second direction DR2.

[0053] The controller 200 can receive input image data IMG and input signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input signals CONT may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and / or a master clock signal, etc.

[0054] The controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input signal CONT. The controller 200 can output the first control signal CONT1 to the gate emitter driver 300. The first control signal CONT1 may include a vertical start signal and a clock signal. The controller 200 can output the second control signal CONT2 and the data signal DATA to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal. The controller 200 can output the third control signal CONT3 to the gamma reference voltage generator 400.

[0055] The gate-emitter driver 300 can generate a gate signal GS and an emit signal EM in response to a first control signal CONT1. The gate-emitter driver 300 can output the gate signal GS to the gate line GL. The gate-emitter driver 300 can also output the emit signal EM to the emit line EL. For example, the gate signal GS may include a write gate signal, a compensated gate signal, an initialized gate signal, or a bias gate signal, etc. However, this disclosure is not limited thereto.

[0056] In this embodiment, the gate emitter driver 300 may be disposed in the peripheral region PA of the display panel 100. For example, the gate emitter driver 300 may be mounted in the peripheral region PA of the display panel 100. The gate emitter driver 300 may correspond to the first driver DRV1 and the second driver DRV2.

[0057] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. For example, the gamma reference voltage generator 400 can be located in the controller 200 or the data driver 500.

[0058] Data driver 500 can receive a second control signal CONT2 and a data signal DATA from controller 200. Data driver 500 can receive a gamma reference voltage VGREF from gamma reference voltage generator 400. Data driver 500 can use the gamma reference voltage VGREF to convert the data signal DATA into an analog data voltage VDATA. Data driver 500 can output the data voltage VDATA to data line DL.

[0059] In this embodiment, the data driver 500 may be disposed in the pad area PDA of the display panel 100. For example, the data driver 500 may be installed in the pad area PDA of the display panel 100. The data driver 500 may correspond to a driver chip D-IC.

[0060] For example, the controller 200 and the data driver 500 can be integrated into one unit. The driver module in which the controller 200 and the data driver 500 are integrated can be referred to as a timing controller embedded data driver (TED).

[0061] Figure 3 It is along Figure 1 The cross-sectional view taken from line II′.

[0062] Reference Figure 3 The display panel 100 may include a substrate SUB, a buffer layer BUF, a first thin film transistor TR1, a first gate insulating layer GI1, a second gate insulating layer GI2, a capacitor electrode CAPE, a second thin film transistor TR2, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, a first via insulating layer VIA1, a connection electrode LCE, a second via insulating layer VIA2, a light-emitting element LD, a pixel defining layer PDL, and a packaging layer TFE.

[0063] The first thin-film transistor TR1 may include a first lower electrode BME1, a first pixel active pattern PACT1, a first pixel gate electrode GE1, a first pixel output electrode SE1, and a second pixel output electrode DE1. The first thin-film transistor TR1 may be a transistor connected to the light-emitting element LD via a connection electrode LCE. The second thin-film transistor TR2 may include a second lower electrode BME2, a second pixel active pattern PACT2, a second pixel gate electrode GE2, a third pixel output electrode SE2, and a fourth pixel output electrode DE2. The light-emitting element LD may include a pixel electrode PE, a light-emitting layer EML, and a common electrode CME.

[0064] The substrate SUB can be made of transparent or opaque materials. Examples of materials that can be used as a substrate SUB include glass, quartz, plastic, or silicon. These can be used alone or in combination with each other.

[0065] The first lower electrode BME1 can be disposed on the substrate SUB. The first lower electrode BME1 can overlap with the first pixel active pattern PACT1 in a planar view. For example, the first lower electrode BME1 can be used as the lower gate electrode of the first thin-film transistor TR1. The first lower electrode BME1 can include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. Examples of conductive materials that can be used as the first lower electrode BME1 include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used individually or in combination with each other.

[0066] A buffer layer BUF can be disposed on the substrate SUB and can cover the first lower electrode BME1. The buffer layer BUF can prevent metal atoms or impurities from diffusing from the substrate SUB into the upper assembly. Furthermore, when the surface of the substrate SUB is inconsistent (e.g., uneven), the buffer layer BUF can improve the flatness of the substrate SUB surface. The buffer layer BUF can include an inorganic insulating material. Examples of inorganic insulating materials that can be used as the buffer layer BUF include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. In this embodiment, the buffer layer (BUF) can be omitted.

[0067] The first pixel active pattern PACT1 can be disposed on the substrate SUB. For example, the first pixel active pattern PACT1 can be disposed on the buffer layer BUF. The first pixel active pattern PACT1 can include a semiconductor material such as silicon semiconductor material or oxide semiconductor material. For example, silicon semiconductor can include amorphous silicon or polycrystalline silicon. For example, oxide semiconductor can include oxides selected from at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). In an embodiment, the first pixel active pattern PACT1 can include a silicon semiconductor material.

[0068] The first gate insulating layer GI1 can be disposed on the buffer layer BUF and can cover the first pixel active pattern PACT1. The first gate insulating layer GI1 may include an inorganic insulating material.

[0069] The first pixel gate electrode GE1 can be disposed on the first gate insulating layer GI1. The first pixel gate electrode GE1 can overlap with the first pixel active pattern PACT1 in a planar view. For example, the first pixel gate electrode GE1 can be used as the upper gate electrode of the first thin-film transistor TR1. The first pixel gate electrode GE1 can include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. These can be used individually or in combination with each other.

[0070] The second gate insulating layer GI2 can be disposed on the first gate insulating layer GI1 and can cover the first pixel gate electrode GE1. The second gate insulating layer GI2 may include an inorganic insulating material.

[0071] A capacitor electrode CAPE can be disposed on the second gate insulating layer GI2. The capacitor electrode CAPE can overlap with the first pixel gate electrode GE1 in a planar view. For example, the capacitor electrode CAPE can form (or define) a capacitor together with the first pixel gate electrode GE1. The capacitor electrode CAPE can include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. These can be used individually or in combination with each other.

[0072] The second lower electrode BME2 can be disposed on the second gate insulating layer GI2. For example, the second lower electrode BME2 can be used as the lower gate electrode of the second thin-film transistor TR2. The second lower electrode BME2 can include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. These can be used individually or in combination with each other.

[0073] The first interlayer insulating layer ILD1 can be disposed on the second gate insulating layer GI2 and can cover the capacitor electrode CAPE and the second lower electrode BME2. The first interlayer insulating layer ILD1 may include an inorganic insulating material.

[0074] The second pixel active pattern PACT2 can be disposed on the first interlayer insulating layer ILD1. The second pixel active pattern PACT2 can include a semiconductor material such as silicon semiconductor material or oxide semiconductor material. In an embodiment, the second pixel active pattern PACT2 can include an oxide semiconductor material.

[0075] The third gate insulating layer GI3 can be disposed on the first interlayer insulating layer ILD1 and can cover the second pixel active pattern PACT2. The third gate insulating layer GI3 may include an inorganic insulating material.

[0076] The second pixel gate electrode GE2 can be disposed on the third gate insulating layer GI3. The second pixel gate electrode GE2 can overlap with the second pixel active pattern PACT2 in a planar view. For example, the second pixel gate electrode GE2 can be used as the upper gate electrode of the second thin-film transistor TR2. The second pixel gate electrode GE2 can include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. These can be used individually or in combination with each other.

[0077] The second interlayer insulating layer ILD2 can be disposed on the third gate insulating layer GI3 and can cover the second pixel gate electrode GE2. The second interlayer insulating layer ILD2 may include an inorganic insulating material.

[0078] The first pixel output electrode SE1 and the second pixel output electrode DE1 can be disposed on the second interlayer insulating layer ILD2. Each of the first pixel output electrode SE1 and the second pixel output electrode DE1 can be connected to the first pixel active pattern PACT1 through a contact hole penetrating the lower insulating layer (e.g., the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2).

[0079] Therefore, a first thin-film transistor TR1, including a first lower electrode BME1, a first pixel active pattern PACT1, a first pixel gate electrode GE1, a first pixel output electrode SE1, and a second pixel output electrode DE1, can be formed on a substrate SUB.

[0080] The third pixel output electrode SE2 and the fourth pixel output electrode DE2 can be disposed on the second interlayer insulating layer ILD2. Each of the third pixel output electrode SE2 and the fourth pixel output electrode DE2 can be connected to the second pixel active pattern PACT2 through a contact hole penetrating the lower insulating layer (e.g., the third gate insulating layer GI3 and the second interlayer insulating layer ILD2).

[0081] Therefore, the second thin-film transistor TR2, including the second lower electrode BME2, the second pixel active pattern PACT2, the second pixel gate electrode GE2, the third pixel output electrode SE2, and the fourth pixel output electrode DE2, can be formed on the substrate SUB (e.g., on the second gate insulating layer GI2).

[0082] A first via insulating layer VIA1 can be disposed on the second interlayer insulating layer ILD2 and can cover the first pixel output electrode SE1, the second pixel output electrode DE1, the third pixel output electrode SE2, and the fourth pixel output electrode DE2. The first via insulating layer VIA1 can include an organic insulating material. Examples of organic insulating materials that can be used as the first via insulating layer VIA1 include polyimide resins, polyamide resins, silicone resins, acrylic resins (e.g., polyacrylic acid resins), or epoxy resins. These can be used alone or in combination with each other.

[0083] The connection electrode LCE can be disposed on the first via insulating layer VIA1. The connection electrode LCE can be electrically connected to the first thin-film transistor TR1. For example, the connection electrode LCE can be connected to the second pixel output electrode DE1 (or the first pixel output electrode SE1) through a contact hole penetrating the lower insulating layer (e.g., the first via insulating layer VIA1). The first thin-film transistor TR1 can be electrically connected to the light-emitting element LD through the connection electrode LCE. The connection electrode LCE can include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. These can be used individually or in combination with each other.

[0084] The second via insulating layer VIA2 can be disposed on the first via insulating layer VIA1 and can cover the connection electrode LCE. The second via insulating layer VIA2 may include an organic insulating material.

[0085] The pixel electrode PE can be disposed on the second via insulating layer VIA2. The pixel electrode PE can be connected to the connection electrode LCE through a contact hole penetrating the lower insulating layer (e.g., the second via insulating layer VIA2). The pixel electrode PE can include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. These can be used individually or in combination with each other. For example, the pixel electrode PE can operate as an anode.

[0086] The pixel defining layer (PDL) may be disposed on the second via insulating layer (VIA2). The PDL may cover the edge of the pixel electrode (PE) and may expose at least a portion of the upper surface of the pixel electrode (PE). The PDL may comprise organic insulating materials and / or inorganic insulating materials.

[0087] An emissive layer (EML) can be disposed on the pixel electrode (PE). The EML can emit light of a selected color (e.g., red, green, or blue). In embodiments, the EML may include at least one of organic light-emitting materials and quantum dots. For example, the EML may have a monolayer structure including one emissive layer or a multilayer structure including multiple emissive layers.

[0088] A common electrode (CME) can be disposed on and cover the pixel defining layer (PDL) and the emissive layer (EML). The CME can comprise conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. These can be used individually or in combination. For example, the CME can be used as a cathode.

[0089] Therefore, the light-emitting element LD, including the pixel electrode PE, the light-emitting layer EML, and the common electrode CME, can be formed on the substrate SUB (e.g., on the second via insulating layer VIA2).

[0090] The TFE encapsulation layer can be disposed on the common electrode CME. The TFE encapsulation layer prevents impurities or moisture from penetrating into the light-emitting element (LD) from the outside. The TFE encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0091] Figure 4 It is shown Figure 2 A block diagram of an example gate emitter driver. Figure 5 It is shown that it includes Figure 4 A block diagram of an example stage in a gate emitter driver.

[0092] Reference Figure 1 , Figure 4 and Figure 5 The gate emitter driver 300 may include multiple stages STG1, STG2, STG3, STG4, ..., a first clock line CKL1 and a second clock line CKL2.

[0093] Levels STG1, STG2, STG3, STG4, ... can be arranged in the column direction (e.g., the second direction DR2), with each level in its own row. For example, the first level STG1 can be located in the first row and can generate a drive signal output to the pixel PX arranged in the first row. The second level STG2 can be located in the second row and can generate a drive signal output to the pixel PX arranged in the second row. The third level STG3 can be located in the third row and can generate a drive signal output to the pixel PX arranged in the third row. The fourth level STG4 can be located in the fourth row and can generate a drive signal output to the pixel PX arranged in the fourth row.

[0094] Each of the first clock line CKL1 and the second clock line CKL2 can extend in a column direction (e.g., the second direction DR2). The first clock line CKL1 can output a first clock signal, and the second clock line CKL2 can output a second clock signal CLK2. The first clock line CKL1 and the second clock line CKL2 can be alternately connected to stages STG1, STG2, STG3, STG4, ... For example, stages located in odd-numbered rows can be connected to the first clock line CKL1, and stages located in even-numbered rows can be connected to the second clock line CKL2. For example, as... Figure 4 As shown, the first stage STG1 and the third stage STG3 can be connected to the first clock line CKL1, and the second stage STG2 and the fourth stage STG4 can be connected to the second clock line CKL2.

[0095] The first stage STG1 can receive the vertical start signal FLM as an input signal, and subsequent stages STG2, STG3, STG4, ... can receive the corresponding carry signals CR1, CR2, CR3, CR4, ... from the previous stage as input signals. For example, the second stage STG2 can receive the first carry signal CR1, the third stage STG3 can receive the second carry signal CR2, and the fourth stage STG4 can receive the third carry signal CR3.

[0096] In the embodiment, each of STG1, STG2, STG3, STG4, ... can generate the above reference. Figure 2 The description refers to two different types of drive signals, namely the transmit signal EM and the gate signal GS (e.g., write gate signal, compensate gate signal, initialize gate signal, or bias gate signal).

[0097] In an embodiment, such as Figure 5As shown, each of stages STG1, STG2, STG3, STG4, ... can generate two different types of drive signals. For example, each of stages STG1, STG2, STG3, STG4, ... can generate a transmit signal EM and a gate signal GS.

[0098] For example, the first-level STG1 can generate a first carry signal CR1, a first transmit signal EM[1], and a first gate signal GS[1] based on the vertical start signal FLM. Each of the first transmit signal EM[1] and the first gate signal GS[1] can be applied to the pixel PX arranged in the first row. For example, the second-level STG2 can generate a second carry signal CR2, a second transmit signal EM[2], and a second gate signal GS[2] based on the first carry signal CR1. Each of the second transmit signal EM[2] and the second gate signal GS[2] can be applied to the pixel PX arranged in the second row. The third-level STG3 can generate a third carry signal CR3, a third transmit signal EM[3], and a third gate signal GS[3] based on the second carry signal CR2. Each of the third transmit signal EM[3] and the third gate signal GS[3] can be applied to the pixel PX arranged in the third row. The fourth-level STG4 can generate a fourth carry signal CR4, a fourth transmit signal EM[4], and a fourth gate signal GS[4] based on the third carry signal CR3. Each of the fourth transmit signal EM[4] and the fourth gate signal GS[4] can be applied to the pixel PX arranged in the fourth row.

[0099] In the embodiment, the transmitted signals EM[1], EM[2], EM[3], EM[4], ... can correspond to the references above. Figure 2 The described transmit signal EM, and the gate signals GS[1], GS[2], GS[3], GS[4], ... can correspond to the above reference. Figure 2 The gate signal GS is described.

[0100] Each of the stages STG1, STG2, STG3, STG4, ... can have substantially the same or similar structures. For example, each of the stages STG1, STG2, STG3, STG4, ... can include a first gate emit signal generator 310 and a second gate emit signal generator 320.

[0101] Therefore, in the following description, the second stage STG2 will be referred to, and the descriptions of the remaining stages STG1, STG3, STG4, ... will be omitted. In the following description, for ease of explanation, the second transmit signal EM[2] will be referred to as the transmit signal EM, and the second gate signal GS[2] will be referred to as the gate signal GS.

[0102] like Figure 5 As shown, the second-stage STG2 may include a first gate emit signal generator 310 and a second gate emit signal generator 320.

[0103] The first gate emitter signal generator 310 can be connected to the second clock line CKL2. The first gate emitter signal generator 310 can receive the second clock signal CLK2 through the second clock line CKL2.

[0104] The second gate emitter signal generator 320 can be connected to the second clock line CKL2. In an embodiment, the second gate emitter signal generator 320 can be connected to the second clock line CKL2 to which the first gate emitter signal generator 310 is connected. The second gate emitter signal generator 320 can receive the second clock signal CLK2 through the second clock line CKL2.

[0105] In an embodiment, the first gate emitter signal generator 310 can generate the above reference. Figure 2 The first drive signal is described in the transmit signal EM and the gate signal GS. The second gate transmit signal generator 320 can generate the above-described reference. Figure 2 The second drive signal, which is different from the first drive signal, is described in the transmit signal EM and the gate signal GS.

[0106] In an embodiment, the first gate emitter signal generator 310 can generate an emitter signal EM based on the second clock signal CLK2, and the second gate emitter signal generator 320 can generate a gate signal GS based on the second clock signal CLK2.

[0107] In this embodiment, the first gate emitter signal generator 310 and the second gate emitter signal generator 320 can be connected to the same second clock line CKL2. That is, the first gate emitter signal generator 310 and the second gate emitter signal generator 320 can share the same clock line. Therefore, the integration density of the gate emitter driver 300 can be improved. Furthermore, since the first gate emitter signal generator 310 and the second gate emitter signal generator 320 share the same clock line, no additional clock signal needs to be output, and thus the power consumption of the gate emitter driver 300 can be reduced.

[0108] The gate emitter driver 300 may correspond to the first driver DRV1 and the second driver DRV2. That is, each of the first driver DRV1 and the second driver DRV2 may include a first gate emitter signal generator 310 and a second gate emitter signal generator 320.

[0109] In this embodiment, the first drive signal generated by the first gate emit signal generator 310 of the first driver DRV1 can be an emit signal EM, and the second drive signal generated by the second gate emit signal generator 320 of the first driver DRV1 can be a gate signal GS. Furthermore, the first drive signal generated by the first gate emit signal generator 310 of the second driver DRV2 can be a gate signal GS different from the second drive signal of the first driver DRV1, and the second drive signal generated by the second gate emit signal generator 320 of the second driver DRV2 can be a gate signal GS different from the second drive signal of the first driver DRV1 and the first drive signal of the second driver DRV2.

[0110] For example, the first drive signal of the first driver DRV1 can be the transmit signal EM, the second drive signal of the first driver DRV1 can be the bias gate signal in the gate signal GS, the first drive signal of the second driver DRV2 can be the compensation gate signal in the gate signal GS, and the second drive signal of the second driver DRV2 can be the initialization gate signal in the gate signal GS. However, this disclosure is not limited thereto.

[0111] Figure 6 It is shown that it includes Figure 4 A circuit diagram of an example stage in a gate emitter driver.

[0112] Reference Figure 4 , Figure 5 and Figure 6 Each stage (e.g., the second stage STG2) may include a first gate emit signal generator 310 and a second gate emit signal generator 320.

[0113] The first gate emitter signal generator 310 may include an input block 311, a voltage limiting block 312, an inverting block 313, a carry signal output block 314, and a drive signal output block 315. The second gate emitter signal generator 320 may include an input block 321, a voltage limiting block 322, an inverting block 323, a carry signal output block 324, and a drive signal output block 325. The first gate emitter signal generator 310 and the second gate emitter signal generator 320 may have substantially the same or similar and symmetrical circuit structures.

[0114] Input blocks 311 and 321 can receive input signals (e.g., a first carry signal CR1). For example, input block 311 of the first gate emitter signal generator 310 can receive the first carry signal CR1 from the carry line 310_CL1 of the first gate emitter signal generator 310. For example, input block 321 of the second gate emitter signal generator 320 can receive the first carry signal CR1 from the carry line 320_CL1 of the second gate emitter signal generator 320.

[0115] Input blocks 311 and 321 can output the first carry signal CR1 to control nodes NQ1 and NQ2 in response to a clock signal (e.g., a second clock signal CLK2). Control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2.

[0116] Input blocks 311 and 321 may include a first transistor T1. The first transistor T1 may include a gate electrode for receiving a second clock signal CLK2, a first electrode for receiving a first carry signal CR1, and a second electrode connected to a first control node NQ1. In an embodiment, the first transistor T1 may be a p-type transistor.

[0117] Voltage limiting blocks 312 and 322 can limit the voltages of control nodes NQ1 and NQ2 based on a second low gate voltage VGL2. Voltage limiting blocks 312 and 322 may include a second transistor T2. The second transistor T2 may include a gate electrode receiving the second low gate voltage VGL2, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2. In an embodiment, the second transistor T2 may be a p-type transistor.

[0118] Inverting blocks 313 and 323 invert the voltages of control nodes NQ1 and NQ2 and output them to the inverting control node NQB. Inverting blocks 313 and 323 may include a third transistor T3 and a fourth transistor T4. The third transistor T3 may include a gate electrode connected to the second control node NQ2, a first electrode receiving a second low gate voltage VGL2, and a second electrode connected to the inverting control node NQB. The fourth transistor T4 may include a gate electrode connected to the first control node NQ1, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the inverting control node NQB. In an embodiment, the third transistor T3 may be an n-type transistor, and the fourth transistor T4 may be a p-type transistor.

[0119] Carry signal output blocks 314 and 324 can output a carry signal (e.g., a second carry signal CR2). Carry signal output blocks 314 and 324 can output a first low gate voltage VGL1 to the carry output node NCR in response to the voltage of the second control node NQ2, and can output a high gate voltage VGH to the carry output node NCR in response to the voltage of the inverting control node NQB. In an embodiment, each of the first low gate voltage VGL1 and the second low gate voltage VGL2 can be lower than the high gate voltage VGH. In an embodiment, the second low gate voltage VGL2 can be lower than the first low gate voltage VGL1.

[0120] Carry signal output blocks 314 and 324 may include a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 may include a gate electrode connected to the second control node NQ2, a first electrode receiving a first low gate voltage VGL1, and a second electrode connected to the carry output node NCR. The eighth transistor T8 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the carry output node NCR. In this embodiment, each of the seventh transistor T7 and the eighth transistor T8 may be a p-type transistor.

[0121] Drive signal output blocks 315 and 325 can output drive signals. In an embodiment, drive signal output block 315 of the first gate emitter signal generator 310 can output an emitter signal EM, and drive signal output block 325 of the second gate emitter signal generator 320 can output a gate signal GS.

[0122] Drive signal output blocks 315 and 325 can output a second low gate voltage VGL2 to drive output node NDS in response to the voltage of the second control node NQ2, and can output a high gate voltage VGH to drive output node NDS in response to the voltage of the inverting control node NQB.

[0123] Drive signal output blocks 315 and 325 may include a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 may include a gate electrode connected to the second control node NQ2, a first electrode receiving a second low gate voltage VGL2, and a second electrode connected to the drive output node NDS. The sixth transistor T6 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the drive output node NDS. In this embodiment, each of the fifth transistor T5 and the sixth transistor T6 may be a p-type transistor.

[0124] In an embodiment, drive signal output blocks 315 and 325 may further include a first capacitor C1 and a second capacitor C2. The first capacitor C1 may include a first electrode connected to the second control node NQ2 and a second electrode connected to the drive output node NDS. The second capacitor C2 may include a first electrode receiving a high gate voltage VGH and a second electrode connected to the inverting control node NQB.

[0125] In this embodiment, the seventh transistor T7 of carry signal output blocks 314 and 324 and the fifth transistor T5 of drive signal output blocks 315 and 325 can each be a p-type transistor. Therefore, it is possible to prevent the threshold voltage of the fifth transistor T5 and the threshold voltage of the seventh transistor T7 from shifting in the negative direction. Furthermore, since it is not necessary to increase the size of the fifth transistor T5 and the seventh transistor T7 for mobility compensation, the unused space of the gate emitter driver 300 can be reduced.

[0126] although Figure 6 The illustration shows that each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 includes only an upper gate electrode, but this disclosure is not limited thereto. In embodiments, each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 may also include a lower gate electrode.

[0127] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 This is a layout diagram illustrating the stages included in a gate emitter driver according to an embodiment of the present disclosure. For example, Figures 7 to 22 It can be shown as including Figure 4 A layout diagram of an example stage in the gate emitter driver 300.

[0128] Figures 7 to 21 This can be shown as included in the gate emitter driver (e.g., Figure 4 The second stage (e.g., in the gate emitter driver 300) is an example of a stage. Figure 4 The layout diagram of the second level STG2. Figure 22 This can be illustrated by including the gate emitter driver (e.g., Figure 4 A layout diagram of a portion of multiple stages in a gate emitter driver 300.

[0129] Reference Figures 7 to 21 Including gate emitter drivers (e.g., Figure 4 Each stage in the gate emitter driver 300 may include a first gate emitter signal generator 310 and a second gate emitter signal generator 320.

[0130] In one embodiment, the second gate emitter signal generator 320 may be adjacent to the first gate emitter signal generator 310 in the first direction DR1. In another embodiment, the first gate emitter signal generator 310 and the second gate emitter signal generator 320 may be symmetrical with respect to a dummy line (i.e., the first dummy line) extending in the second direction DR2. The first gate emitter signal generator 310 and the second gate emitter signal generator 320 may have substantially similar structures that are symmetrical with respect to the dummy line. However, this disclosure is not limited thereto.

[0131] Figure 7 This is a layout diagram showing the first conductive layer CL1.

[0132] Reference Figure 3 and Figure 7 A first conductive layer CL1 can be disposed on a substrate SUB. The first conductive layer CL1 may include a conductive material such as a metal, alloy, conductive metal nitride, conductive metal oxide, or transparent conductive oxide. The first conductive layer CL1 may include a first lower conductive pattern BMP1, a second lower conductive pattern BMP2, a third lower conductive pattern BMP3, a fourth lower conductive pattern BMP4, and a fifth lower conductive pattern BMP5. The first lower conductive patterns BMP1, BMP2, BMP3, BMP4, and BMP5 may be spaced apart from each other. The first lower conductive patterns BMP1, BMP2, BMP3, BMP4, and BMP5 may be... Figure 3 The first lower electrode BME1 is disposed in the same layer.

[0133] The buffer layer BUF can be disposed on the first conductive layer CL1 and can cover the first lower conductive pattern BMP1, the second lower conductive pattern BMP2, the third lower conductive pattern BMP3, the fourth lower conductive pattern BMP4, and the fifth lower conductive pattern BMP5. For example, the buffer layer BUF may include an inorganic insulating material.

[0134] Figure 8 This is a layout diagram showing the first active layer ACL1. Figure 9 The first active layer ACL1 is further configured in Figure 7 The layout diagram on the first conductive layer CL1.

[0135] Further reference Figure 8 and Figure 9 The first active layer ACL1 can be set on the first conductive layer CL1. For example, the first active layer ACL1 can be set on the buffer layer BUF.

[0136] In this embodiment, the first active layer ACL1 may include a silicon semiconductor material. The silicon semiconductor material may include amorphous silicon or polycrystalline silicon, etc.

[0137] The first active layer ACL1 may include a first active pattern AP1, a second active pattern AP2, a third active pattern AP3, a fourth active pattern AP4, and a fifth active pattern AP5. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, the fourth active pattern AP4, and the fifth active pattern AP5 may be spaced apart from each other. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, the fourth active pattern AP4, and the fifth active pattern AP5 may be... Figure 3 The first pixel active pattern PACT1 is set in the same layer.

[0138] The first lower conductive pattern BMP1 may at least partially overlap with the first active pattern AP1 in the planar view. The portion of the first lower conductive pattern BMP1 that overlaps with the first active pattern AP1 in the planar view may be the lower gate electrode of the first transistor T1.

[0139] The second lower conductive pattern BMP2 may at least partially overlap with the first active pattern AP1 in the planar view. The portion of the second lower conductive pattern BMP2 that overlaps with the first active pattern AP1 in the planar view may be the lower gate electrode of the second transistor T2.

[0140] The third lower conductive pattern BMP3 may at least partially overlap with the second active pattern AP2 in the planar view. The portion of the third lower conductive pattern BMP3 that overlaps with the second active pattern AP2 in the planar view may be the lower gate electrode of the fourth transistor T4.

[0141] The fourth lower conductive pattern BMP4 may at least partially overlap with each of the third active pattern AP3 and the fourth active pattern AP4 in the planar view. The first portion of the fourth lower conductive pattern BMP4 overlapping with the third active pattern AP3 in the planar view may be the lower gate electrode of the fifth transistor T5. The second portion of the fourth lower conductive pattern BMP4 overlapping with the fourth active pattern AP4 in the planar view may be the lower gate electrode of the seventh transistor T7.

[0142] The fifth lower conductive pattern BMP5 may at least partially overlap with each of the third active pattern AP3 and the fifth active pattern AP5 in a planar view. The first portion of the fifth lower conductive pattern BMP5 overlapping with the third active pattern AP3 in a planar view may be the lower gate electrode of the sixth transistor T6. The second portion of the fifth lower conductive pattern BMP5 overlapping with the fifth active pattern AP5 in a planar view may be the lower gate electrode of the eighth transistor T8.

[0143] The first gate insulating layer GI1 may be disposed on the first active layer ACL1 and may cover the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, the fourth active pattern AP4, and the fifth active pattern AP5. For example, the first gate insulating layer GI1 may include an inorganic insulating material.

[0144] Figure 10 This is a layout diagram showing the second conductive layer CL2. Figure 11 The second conductive layer CL2 is further disposed therein. Figure 9 The layout diagram on the first active layer ACL1.

[0145] Further reference Figure 10 and Figure 11 The second conductive layer CL2 can be disposed on the first active layer ACL1. For example, the second conductive layer CL2 can be disposed on the first gate insulating layer GI1.

[0146] The second conductive layer CL2 may include a conductive material such as a metal, alloy, conductive metal nitride, conductive metal oxide, or transparent conductive oxide. The second conductive layer CL2 may include a first gate pattern GP1, a second gate pattern GP2, a third gate pattern GP3, a fourth gate pattern GP4, and a fifth gate pattern GP5. The first gate pattern GP1, the second gate pattern GP2, the third gate pattern GP3, the fourth gate pattern GP4, and the fifth gate pattern GP5 may be spaced apart from each other. The first gate pattern GP1, the second gate pattern GP2, the third gate pattern GP3, the fourth gate pattern GP4, and the fifth gate pattern GP5 may be... Figure 3 The first pixel gate electrode GE1 is set in the same layer.

[0147] The first gate pattern GP1 may at least partially overlap with the first active pattern AP1 in a planar view. The first gate pattern GP1 may also at least partially overlap with the first lower conductive pattern BMP1 in a planar view. The portion of the first gate pattern GP1 that overlaps with the first active pattern AP1 in a planar view may be the upper gate electrode of the first transistor T1.

[0148] The second gate pattern GP2 may at least partially overlap with the first active pattern AP1 in a planar view. The second gate pattern GP2 may also at least partially overlap with the second lower conductive pattern BMP2 in a planar view. The portion of the second gate pattern GP2 that overlaps with the first active pattern AP1 in a planar view may be the upper gate electrode of the second transistor T2.

[0149] The third gate pattern GP3 may at least partially overlap with the second active pattern AP2 in the planar view. The third gate pattern GP3 may also at least partially overlap with the third lower conductive pattern BMP3 in the planar view. The portion of the third gate pattern GP3 that overlaps with the second active pattern AP2 in the planar view may be the upper gate electrode of the fourth transistor T4.

[0150] The fourth gate pattern GP4 may at least partially overlap with each of the third active pattern AP3 and the fourth active pattern AP4 in the planar view. The fourth gate pattern GP4 may also at least partially overlap with the fourth lower conductive pattern BMP4 in the planar view. The first portion of the fourth gate pattern GP4 overlapping with the third active pattern AP3 in the planar view may be the upper gate electrode of the fifth transistor T5. The second portion of the fourth gate pattern GP4 overlapping with the fourth active pattern AP4 in the planar view may be the upper gate electrode of the seventh transistor T7.

[0151] The fifth gate pattern GP5 may at least partially overlap with each of the third active pattern AP3 and the fifth active pattern AP5 in a planar view. The fifth gate pattern GP5 may also at least partially overlap with the fifth lower conductive pattern BMP5 in a planar view. The first portion of the fifth gate pattern GP5 overlapping with the third active pattern AP3 in a planar view may be the upper gate electrode of the sixth transistor T6. The second portion of the fifth gate pattern GP5 overlapping with the fifth active pattern AP5 in a planar view may be the upper gate electrode of the eighth transistor T8.

[0152] The second gate insulating layer GI2 can be disposed on the second conductive layer CL2 and can cover the first gate pattern GP1, the second gate pattern GP2, the third gate pattern GP3, the fourth gate pattern GP4, and the fifth gate pattern GP5. For example, the second gate insulating layer GI2 may include an inorganic insulating material.

[0153] Figure 12This is a layout diagram showing the third conductive layer CL3. Figure 13 The third conductive layer CL3 is further set in Figure 11 The layout diagram on the second conductive layer CL2.

[0154] Further reference Figure 12 and Figure 13 The third conductive layer CL3 can be disposed on the second conductive layer CL2. For example, the third conductive layer CL3 can be disposed on the second gate insulating layer GI2.

[0155] The third conductive layer CL3 may include a conductive material such as a metal, alloy, conductive metal nitride, conductive metal oxide, or transparent conductive oxide. The third conductive layer CL3 may include a sixth gate pattern GP6, a seventh gate pattern GP7, and an eighth gate pattern GP8. The sixth gate pattern GP6, the seventh gate pattern GP7, and the eighth gate pattern GP8 may be spaced apart from each other. The sixth gate pattern GP6, the seventh gate pattern GP7, and the eighth gate pattern GP8 may be... Figure 3 The capacitor electrodes CAPE are arranged in the same layer.

[0156] The seventh gate pattern GP7 may at least partially overlap with the fourth gate pattern GP4 in a planar view. A second gate insulating layer GI2 may be disposed between the seventh gate pattern GP7 and the fourth gate pattern GP4. The seventh gate pattern GP7 and the fourth gate pattern GP4 may form (or define) a first capacitor C1.

[0157] The eighth gate pattern GP8 may at least partially overlap with the fifth gate pattern GP5 in a planar view. A second gate insulating layer GI2 may be disposed between the eighth gate pattern GP8 and the fifth gate pattern GP5. The eighth gate pattern GP8 and the fifth gate pattern GP5 may form (or define) a second capacitor C2.

[0158] The first interlayer insulating layer ILD1 can be disposed on the third conductive layer CL3 and can cover the sixth gate pattern GP6, the seventh gate pattern GP7, and the eighth gate pattern GP8. For example, the first interlayer insulating layer ILD1 can include an inorganic insulating material.

[0159] Figure 14 This is a layout diagram showing the second active layer ACL2 and the fourth conductive layer CL4. Figure 15 The second active layer ACL2 and the fourth conductive layer CL4 are further set in Figure 13 The layout diagram on the third conductive layer CL3.

[0160] Further reference Figure 14 and Figure 15The second active layer ACL2 can be disposed on the third conductive layer CL3. For example, the second active layer ACL2 can be disposed on the first interlayer insulating layer ILD1.

[0161] In an embodiment, the second active layer ACL2 may include an oxide semiconductor material. For example, the oxide semiconductor material may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The second active layer ACL2 may include a sixth active pattern AP6. The sixth active pattern AP6 may be associated with... Figure 3 The second pixel active pattern PACT2 is set in the same layer.

[0162] The sixth gate pattern GP6 may at least partially overlap with the sixth active pattern AP6 in the planar view. The portion of the sixth gate pattern GP6 that overlaps with the sixth active pattern AP6 in the planar view may be the lower gate electrode of the third transistor T3.

[0163] The third gate insulating layer GI3 can be disposed on the second active layer ACL2 and can cover the sixth active pattern AP6. For example, the third gate insulating layer GI3 may include an inorganic insulating material.

[0164] The fourth conductive layer CL4 can be disposed on the second active layer ACL2. For example, the fourth conductive layer CL4 can be disposed on the third gate insulating layer GI3.

[0165] The fourth conductive layer CL4 may include a conductive material such as a metal, alloy, conductive metal nitride, conductive metal oxide, or transparent conductive oxide. The fourth conductive layer CL4 may include a ninth gate pattern GP9. The ninth gate pattern GP9 may be combined with... Figure 3 The second pixel gate electrode GE2 is disposed in the same layer.

[0166] The ninth gate pattern GP9 may at least partially overlap with the sixth active pattern AP6 in the planar view. The portion of the ninth gate pattern GP9 that overlaps with the sixth active pattern AP6 in the planar view may be the upper gate electrode of the third transistor T3.

[0167] The second interlayer insulating layer ILD2 can be disposed on the fourth conductive layer CL4 and can cover the ninth gate pattern GP9. For example, the second interlayer insulating layer ILD2 can include an inorganic insulating material.

[0168] Figure 16 This is a layout diagram showing the fifth conductive layer CL5. Figure 17The fifth conductive layer CL5 is further set in Figure 15 The layout diagram on the fourth conductive layer CL4.

[0169] Further reference Figure 6 , Figure 16 and Figure 17 The fifth conductive layer CL5 can be disposed on the fourth conductive layer CL4. For example, the fifth conductive layer CL5 can be disposed on the second interlayer insulating layer ILD2.

[0170] The fifth conductive layer CL5 may include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. The fifth conductive layer CL5 may include a first connection pattern CP1, a second connection pattern CP2, a third connection pattern CP3, a fourth connection pattern CP4, a fifth connection pattern CP5, a sixth connection pattern CP6, a seventh connection pattern CP7, an eighth connection pattern CP8, a ninth connection pattern CP9, a tenth connection pattern CP10, an eleventh connection pattern CP11, a twelfth connection pattern CP12, and a thirteenth connection pattern CP13. The first connection pattern CP1, the second connection pattern CP2, the third connection pattern CP3, the fourth connection pattern CP4, the fifth connection pattern CP5, the sixth connection pattern CP6, the seventh connection pattern CP7, the eighth connection pattern CP8, the ninth connection pattern CP9, the tenth connection pattern CP10, the eleventh connection pattern CP11, the twelfth connection pattern CP12, and the thirteenth connection pattern CP13 may be spaced apart from each other. The first connecting pattern CP1, the second connecting pattern CP2, the third connecting pattern CP3, the fourth connecting pattern CP4, the fifth connecting pattern CP5, the sixth connecting pattern CP6, the seventh connecting pattern CP7, the eighth connecting pattern CP8, the ninth connecting pattern CP9, the tenth connecting pattern CP10, the eleventh connecting pattern CP11, the twelfth connecting pattern CP12, and the thirteenth connecting pattern CP13 can be combined with... Figure 3 The first pixel output electrode SE1, the second pixel output electrode DE1, the third pixel output electrode SE2, and the fourth pixel output electrode DE2 are set in the same layer.

[0171] The first connection pattern CP1 can receive the second low gate voltage VGL2. The first connection pattern CP1 can be connected to the second gate pattern GP2 through a contact hole. Therefore, the first connection pattern CP1 can provide the second low gate voltage VGL2 to the upper gate electrode of the second transistor T2.

[0172] The second connection pattern CP2 can receive the second clock signal CLK2. The second connection pattern CP2 can be connected to the first gate pattern GP1 through a contact hole. Therefore, the second connection pattern CP2 can provide the second clock signal CLK2 to the upper gate electrode of the first transistor T1.

[0173] The third connection pattern CP3 can be connected to the third gate pattern GP3 and the first active pattern AP1 through a contact hole. Therefore, the third connection pattern CP3 can electrically connect the upper gate electrode of the fourth transistor T4 and the second transistor T2.

[0174] The fourth connection pattern CP4 can be connected to the fourth gate pattern GP4 and the first active pattern AP1 through a contact hole. Therefore, the fourth connection pattern CP4 can electrically connect the upper gate electrode of the fifth transistor T5 and the second transistor T2.

[0175] The fifth connection pattern CP5 can be connected to the third active pattern AP3 through a contact hole. The fifth connection pattern CP5 can electrically connect the fifth transistor T5 and the sixth transistor T6.

[0176] The sixth connection pattern CP6 and the seventh connection pattern CP7 can receive the second low gate voltage VGL2. Each of the sixth connection pattern CP6 and the seventh connection pattern CP7 can be connected to the third active pattern AP3 via a contact hole. Therefore, the sixth connection pattern CP6 and the seventh connection pattern CP7 can provide the second low gate voltage VGL2 to the fifth transistor T5.

[0177] The eighth connection pattern CP8 can be connected to the second active pattern AP2, the sixth active pattern AP6, and the fifth gate pattern GP5 through contact holes. Therefore, the eighth connection pattern CP8 can electrically connect the upper gate electrode of the eighth transistor T8, the third transistor T3, and the fourth transistor T4.

[0178] The ninth connection pattern CP9 can receive a high gate voltage VGH. The ninth connection pattern CP9 can be connected via contact holes to the second active pattern AP2, the third active pattern AP3, the eighth gate pattern GP8, and the fifth active pattern AP5. Therefore, the ninth connection pattern CP9 can provide the high gate voltage VGH to the fourth transistor T4, the sixth transistor T6, the second capacitor C2, and the eighth transistor T8.

[0179] The tenth connection pattern CP10 can be connected to the fourth gate pattern GP4 and the ninth gate pattern GP9 through a contact hole. Therefore, the tenth connection pattern CP10 can electrically connect the upper gate electrode of the seventh transistor T7 and the upper gate electrode of the third transistor T3.

[0180] Eleventh connection pattern CP11 can receive the second low gate voltage VGL2. Eleventh connection pattern CP11 can be connected to the sixth active pattern AP6 via a contact hole. Therefore, eleventh connection pattern CP11 can provide the second low gate voltage VGL2 to the third transistor T3.

[0181] The twelfth connection pattern CP12 can be connected to the fourth active pattern AP4, the fifth active pattern AP5, and the first active pattern AP1 in the next row via contact holes. Therefore, the twelfth connection pattern CP12 can electrically connect the seventh transistor T7 and the eighth transistor T8. Furthermore, the twelfth connection pattern CP12 can provide a carry signal to the first transistor T1 in the next row. That is, the twelfth connection pattern CP12, included in the Nth row (where N is a natural number greater than 0), can provide a carry signal to the first transistor T1 included in the (N+1)th row.

[0182] The thirteenth connection pattern CP13 can receive the first low gate voltage VGL1. The thirteenth connection pattern CP13 can be connected to the fourth active pattern AP4 through a contact hole. Therefore, the thirteenth connection pattern CP13 can provide the first low gate voltage VGL1 to the seventh transistor T7.

[0183] The first via insulating layer VIA1 can be disposed on the fifth conductive layer CL5 and can cover the first connection pattern CP1, the second connection pattern CP2, the third connection pattern CP3, the fourth connection pattern CP4, the fifth connection pattern CP5, the sixth connection pattern CP6, the seventh connection pattern CP7, the eighth connection pattern CP8, the ninth connection pattern CP9, the tenth connection pattern CP10, the eleventh connection pattern CP11, the twelfth connection pattern CP12, and the thirteenth connection pattern CP13. For example, the first via insulating layer VIA1 may include an organic insulating material.

[0184] Figure 18 This is a layout diagram showing the sixth conductive layer CL6. Figure 19 The sixth conductive layer CL6 is further set in Figure 17 The layout diagram on the fifth conductive layer CL5.

[0185] Further reference Figure 18 and Figure 19 The sixth conductive layer CL6 can be disposed on the fifth conductive layer CL5. For example, the sixth conductive layer CL6 can be disposed on the first via insulating layer VIA1.

[0186] The sixth conductive layer CL6 may include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. The sixth conductive layer CL6 may include a first low-voltage line VLL1, a first clock line CKL1, a second clock line CKL2, a second low-voltage line VLL2, a high-voltage line VHL, and an initialization signal line FLL. The first low-voltage line VLL1, the first clock line CKL1, the second clock line CKL2, the second low-voltage line VLL2, the high-voltage line VHL, and the initialization signal line FLL may be spaced apart from each other. For example, each of the first low-voltage line VLL1, the first clock line CKL1, the second clock line CKL2, the second low-voltage line VLL2, the high-voltage line VHL, and the initialization signal line FLL may extend in the second direction DR2.

[0187] For example, the first low-voltage line VLL1, the first clock line CKL1, the second clock line CKL2, the second low-voltage line VLL2, the high-voltage line VHL, and the initialization signal line FLL can be connected to... Figure 3 The connecting electrodes LCE are located in the same layer.

[0188] The first gate emitter signal generator 310 and the second gate emitter signal generator 320 can be distinguished based on the first low-voltage line VLL1. For example, the first low-voltage line VLL1 can be disposed between the first gate emitter signal generator 310 and the second gate emitter signal generator 320. The second clock line CKL2 can be spaced apart from the first clock line CKL1 in the first direction DR1, and the first low-voltage line VLL1 can be disposed between the first clock line CKL1 and the second clock line CKL2 in a planar view.

[0189] In an embodiment, the first gate emitter signal generator 310 and the second gate emitter signal generator 320 may be line-symmetrical with respect to the first low-voltage line VLL1. The first gate emitter signal generator 310 and the second gate emitter signal generator 320 may have substantially similar or identical structures that are symmetrical with respect to a virtual line extending in the second direction DR2. However, this disclosure is not limited thereto, and the first gate emitter signal generator 310 and the second gate emitter signal generator 320 may not be line-symmetrical with respect to the first low-voltage line VLL1, and each of the first gate emitter signal generator 310 and the second gate emitter signal generator 320 may have various structures.

[0190] The first low-voltage line VLL1 can be connected to the thirteenth connection pattern CP13 via a contact hole. The first low-voltage line VLL1 can output the first low gate voltage VGL1 to the thirteenth connection pattern CP13.

[0191] In this embodiment, the first gate emitter signal generator 310 and the second gate emitter signal generator 320 can be connected to the same first low-voltage line VLL1. For example, the first low-voltage line VLL1 can be connected to the seventh transistor T7 of the first gate emitter signal generator 310 and the seventh transistor T7 of the second gate emitter signal generator 320 via a thirteenth connection pattern CP13. Therefore, the first low gate voltage VGL1 can be applied to the seventh transistor T7 of the first gate emitter signal generator 310 and the seventh transistor T7 of the second gate emitter signal generator 320 via the first low-voltage line VLL1 and the thirteenth connection pattern CP13.

[0192] In an embodiment, the sixth conductive layer CL6 may include a clock line electrically connected to each of the first gate emitter signal generator 310 and the second gate emitter signal generator 320. For example, the first clock line CKL1 may overlap with the first gate emitter signal generator 310 in a plan view. Figures 7 to 21 This indicates the second level (e.g., Figure 4 The second stage STG2) is included as part of the gate emitter driver (e.g., Figure 4 An example layout diagram of the stage in the gate emitter driver 300), and therefore in Figure 18 and Figure 19 In this case, the first clock line CKL1 may not be connected to other patterns.

[0193] In an embodiment, the first clock line CKL1 may include a first extension portion CKL1_1 extending in the second direction DR2 and a first protruding portion CKL1_2 protruding from the first extension portion CKL1_1. For example, the first protruding portion CKL1_2 may protrude from the first extension portion CKL1_1 in a direction opposite to the first direction DR1.

[0194] For example, the second clock line CKL2 can overlap with the second gate emitter signal generator 320 in the plan view. The second clock line CKL2 can be connected to the second connection pattern CP2 through a contact hole. The second clock line CKL2 can output the second clock signal CLK2 to the second connection pattern CP2.

[0195] In this embodiment, the first gate emitter signal generator 310 and the second gate emitter signal generator 320 can be connected to the same second clock line CKL2. For example, the second clock line CKL2 can be connected to the first gate pattern GP1 via the second connection pattern CP2. Therefore, the second clock signal CLK2 can be applied to the upper gate electrode of the first transistor T1 of the first gate emitter signal generator 310 and the upper gate electrode of the first transistor T1 of the second gate emitter signal generator 320 via the second clock line CKL2 and the second connection pattern CP2.

[0196] In an embodiment, the second clock line CKL2 may include a second extension portion CKL2_1 extending in the second direction DR2 and a second protruding portion CKL2_2 protruding from the second extension portion CKL2_1. For example, the second protruding portion CKL2_2 may protrude from the second extension portion CKL2_1 in the first direction DR1.

[0197] The second low-voltage line VLL2 can be connected to the first connection pattern CP1, the sixth connection pattern CP6, the seventh connection pattern CP7, and the eleventh connection pattern CP11 via contact holes. The second low-voltage line VLL2 can output the second low gate voltage VGL2 to the first connection pattern CP1, the sixth connection pattern CP6, the seventh connection pattern CP7, and the eleventh connection pattern CP11.

[0198] The high-voltage line VHL can be connected to the ninth connection pattern CP9 via a contact hole. The high-voltage line VHL can output a high gate voltage VGH to the ninth connection pattern CP9. Figure 18 and Figure 19 In this circuit, the high-voltage line VHL, which is not connected to other patterns, can output the high gate voltage VGH to stages other than the second stage STG2.

[0199] As mentioned above, Figures 7 to 21 This indicates the second level (e.g., Figure 4 The second stage STG2) is included as part of the gate emitter driver (e.g., Figure 4 An example layout diagram of the stage in the gate emitter driver 300), and therefore in Figure 18 and Figure 19 In this case, the initialization signal line FLL does not need to be connected to other patterns.

[0200] The second via insulating layer VIA2 can be disposed on the sixth conductive layer CL6 and can cover the first low-voltage line VLL1, the first clock line CKL1, the second clock line CKL2, the second low-voltage line VLL2, the high-voltage line VHL, and the initialization signal line FLL. For example, the second via insulating layer VIA2 may include an organic insulating material.

[0201] Figure 20 This is a layout diagram showing the seventh conductive layer CL7. Figure 21 The seventh conductive layer CL7 is further set in Figure 19 The layout diagram on the sixth conductive layer CL6. Figure 22 This is a layout diagram in which the seventh conductive layer CL7 is disposed on the sixth conductive layer CL6.

[0202] Further reference Figure 20 , Figure 21 and Figure 22The seventh conductive layer CL7 can be disposed on the sixth conductive layer CL6. For example, the seventh conductive layer CL7 can be disposed on the second via insulating layer VIA2.

[0203] The seventh conductive layer CL7 may include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive oxides. The seventh conductive layer CL7 can be combined with... Figure 3 The pixel electrodes PE are disposed in the same layer. For example, the seventh conductive layer CL7 can be electrically connected to... Figure 3 The common electrode CME is provided, and a stable voltage can be supplied to the common electrode CME to reduce the voltage drop of the common electrode CME. The seventh conductive layer CL7 can be disposed in the non-display area NDA (see [reference]). Figure 1 In ) around the display area DA (see Figure 1 The seventh conductive layer CL7 can be set in... Figure 4 The seventh conductive layer CL7 can overlap with the first gate emitter signal generator 310 and the second gate emitter signal generator 320 in a planar view.

[0204] In an embodiment, the seventh conductive layer CL7 may be defined by an opening penetrating the seventh conductive layer CL7 in the thickness direction (i.e., the third direction DR3). The seventh conductive layer CL7 may define a first opening OP1 and a second opening OP2. The first opening OP1 may be spaced apart from the second opening OP2. The planar shape of the first opening OP1 may be different from the planar shape of the second opening OP2.

[0205] The seventh conductive layer CL7 may include a first region A1 defining a first opening OP1 and a second region A2 defining a second opening OP2. In an embodiment, the first region A1 may be a region that overlaps with the first clock line CKL1 and the second clock line CKL2 in a plan view, and the second region A2 may be a region other than the first region A1. The first opening OP1 may overlap with the first clock line CKL1 and the second clock line CKL2 in a plan view, and the second opening OP2 may not overlap with the first clock line CKL1 and the second clock line CKL2 in a plan view. The seventh conductive layer CL7 may be exposed through the first opening OP1 and the second opening OP2. Figure 3 At least a portion of the second via insulating layer VIA2.

[0206] The first opening OP1 and the second opening OP2 provide a path through which material in the insulating layer disposed beneath the seventh conductive layer CL7 can be evaporated and discharged to the outside. When a thermal process (e.g., a curing process) is performed after the pixel defining layer PDL is formed on the pixel electrode PE, a portion of the material in the first via insulating layer VIA1 or the second via insulating layer VIA2 beneath the seventh conductive layer CL7 can be evaporated by the heat applied during the thermal process and discharged to the outside through the first opening OP1 and the second opening OP2. Therefore, it is possible to prevent the gases generated from the first via insulating layer VIA1 and the second via insulating layer VIA2 from affecting the external environment. Figure 3 Damage caused by the light-emitting element (LD).

[0207] When the seventh conductive layer CL7 overlaps with the first clock line CKL1 and the second clock line CKL2 in a planar view, the voltage supplied to the seventh conductive layer CL7 may be affected by the parasitic capacitance formed between the first clock line CKL1, the second clock line CKL2, and the seventh conductive layer CL7. In an embodiment, to minimize the impact of parasitic capacitance on the voltage supplied to the seventh conductive layer CL7, the first opening OP1 may overlap with the first clock line CKL1 and the second clock line CKL2 in a planar view. Reducing the parasitic capacitance can lower power consumption.

[0208] In an embodiment, each of the plurality of first openings OP1 may include a first sub-opening SOP1 that overlaps with at least a portion of a first clock line CKL1 in a plan view and a second sub-opening SOP2 that overlaps with at least a portion of a second clock line CKL2 in a plan view.

[0209] Multiple first sub-openings SOP1 may be spaced apart from each other along a second direction DR2, and multiple second sub-openings SOP2 may be spaced apart from each other along a second direction DR2. The second sub-openings SOP2 may be spaced apart from the first sub-openings SOP1 along a first direction DR1. In an embodiment, the first sub-openings SOP1 and the second sub-openings SOP2 may be symmetrical with respect to a virtual line (i.e., a second virtual line) extending along the second direction DR2. For example, the first sub-openings SOP1 and the second sub-openings SOP2 may be linearly symmetrical with respect to a first low-voltage line VLL1.

[0210] In an embodiment, each of the plurality of first sub-openings SOP1 may overlap with a first extension CKL1_1 of the first clock line CKL1 in a plan view, and each of the plurality of second sub-openings SOP2 may overlap with a second extension CKL2_1 of the second clock line CKL2 in a plan view. For example, in a plan view, each of the plurality of first sub-openings SOP1 may at least partially overlap with the first extension CKL1_1, and at least some of the plurality of first sub-openings SOP1 may partially overlap with the first protrusion CKL1_2. For example, in a plan view, each of the plurality of second sub-openings SOP2 may at least partially overlap with the second extension CKL2_1, and at least some of the plurality of second sub-openings SOP2 may partially overlap with the second protrusion CKL2_2.

[0211] Due to the increase in parasitic capacitance formed between the first clock line CKL1 and the seventh conductive layer CL7, the output of the signal transmitted through the first clock line CKL1 may be delayed, and due to the increase in parasitic capacitance formed between the second clock line CKL2 and the seventh conductive layer CL7, the output of the signal transmitted through the second clock line CKL2 may be delayed. Since the first sub-aperture SOP1 and the second sub-aperture SOP2 are formed symmetrically, the area of ​​the first clock line CKL1 overlapping with the first sub-aperture SOP1 in the planar view and the area of ​​the second clock line CKL2 overlapping with the second sub-aperture SOP2 in the planar view can be substantially the same (or equal). Therefore, the deviation between the parasitic capacitance formed between the first clock line CKL1 and the seventh conductive layer CL7 and the parasitic capacitance formed between the second clock line CKL2 and the seventh conductive layer CL7 can be minimized. In other words, the deviation between the output of the signal transmitted through the first clock line CKL1 and the output of the signal transmitted through the second clock line CKL2 can be minimized.

[0212] In an embodiment, each of the plurality of second openings OP2 may include a third sub-opening SOP3 and a fourth sub-opening SOP4 arranged in an offset (or zigzag) manner along a second direction DR2. The plurality of third sub-openings SOP3 may be spaced apart from each other in a first direction DR1 and a second direction DR2, and the plurality of fourth sub-openings SOP4 may be spaced apart from each other in the first direction DR1 and the second direction DR2. The fourth sub-openings SOP4 may be spaced apart from the third sub-openings SOP3 in the first direction DR1 and staggered relative to the third sub-openings SOP3 in the second direction DR2. The third sub-openings SOP3 and the fourth sub-openings SOP4 may be arranged alternately along the first direction DR1, and the centers of the third sub-openings SOP3 and the fourth sub-openings SOP4 may be offset in the second direction DR2.

[0213] The second opening OP2 can be controlled. Figure 3 The flow of the TFE encapsulation layer. When forming Figure 3 When the organic encapsulation layer of the TFE encapsulation layer is used, the third sub-opening SOP3 and the fourth sub-opening SOP4, which are arranged in an offset (or staggered) manner, can prevent the flow of organic material included in the organic encapsulation layer and thus control the contour of the organic encapsulation layer (e.g., the position of the ends).

[0214] Although the first sub-opening SOP1, the second sub-opening SOP2, the third sub-opening SOP3, and the fourth sub-opening SOP4 are shown in the accompanying drawings as having rectangular planar shapes, this disclosure is not limited thereto. For example, the first sub-opening SOP1, the second sub-opening SOP2, the third sub-opening SOP3, and the fourth sub-opening SOP4 can have various shapes such as other polygonal planar shapes, circular planar shapes, or elliptical planar shapes. Furthermore, the dimensions of the first sub-opening SOP1 and the second sub-opening SOP2 can be the same as or different from the dimensions of the third sub-opening SOP3 and the fourth sub-opening SOP4.

[0215] The display device DD according to an embodiment of the present disclosure (see also...) Figure 1 The device may include a seventh conductive layer CL7 defining a first opening OP1 that includes a first sub-opening SOP1 overlapping with a first clock line CKL1 in a planar view and a second sub-opening SOP2 overlapping with a second clock line CKL2 in a planar view. Therefore, parasitic capacitances formed between the first clock line CKL1 and the second clock line CKL2 and the seventh conductive layer CL7 can be reduced, and the power consumption of the display device DD can be reduced. Furthermore, the first sub-opening SOP1 and the second sub-opening SOP2 can be symmetrical with respect to a virtual line extending in the second direction DR2, and the area of ​​the first clock line CKL1 overlapping with the first sub-opening SOP1 in a planar view and the area of ​​the second clock line CKL2 overlapping with the second sub-opening SOP2 in a planar view can be substantially the same. Therefore, the deviation between the parasitic capacitances formed between the first clock line CKL1 and the seventh conductive layer CL7 and the parasitic capacitances formed between the second clock line CKL2 and the seventh conductive layer CL7 can be minimized, and the deviation between the output of the signal transmitted through the first clock line CKL1 and the output of the signal transmitted through the second clock line CKL2 can be minimized.

[0216] Figure 23 , Figure 24 and Figure 25 This is a layout diagram illustrating the stages included in a gate emitter driver according to an embodiment of the present disclosure. Figure 23 and Figure 24 It can be a layout diagram showing the stage included in the gate emitter driver 300'. Figure 25It can be a layout diagram showing a portion of multiple stages included in the gate emitter driver 300'.

[0217] In addition to the seventh conductive layer CL7′, refer to Figure 23 , Figure 24 and Figure 25 The described gate emitter driver 300' can be compared with the reference Figures 2 to 22 The described gate emitter driver 300 is substantially the same as or similar to that described above. For example, refer to... Figure 23 , Figure 24 and Figure 25 The described gate emitter driver 300' may be included in a display device (e.g., Figure 1 The display device (DD) is used. In the following text, redundant descriptions will be omitted or simplified.

[0218] Figure 23 This is a layout diagram showing the seventh conductive layer CL7′. Figure 24 and Figure 25 This is a layout diagram in which the seventh conductive layer CL7′ is further disposed on the sixth conductive layer CL6. Figure 23 It can correspond to Figure 20 , Figure 24 It can correspond to Figure 21 ,and Figure 25 It can correspond to Figure 22 .

[0219] Reference Figure 23 , Figure 24 and Figure 25 Each stage included in the gate emitter driver 300' may include a first gate emitter signal generator 310 and a second gate emitter signal generator 320, the first gate emitter signal generator 310 and the second gate emitter signal generator 320 being substantially symmetrical with respect to a virtual line extending in the second direction DR2.

[0220] The seventh conductive layer CL7′ can be disposed on the sixth conductive layer CL6. The seventh conductive layer CL7′ can be connected to the pixel electrode (e.g., Figure 3 The pixel electrodes (PE) are disposed in the same layer and can overlap with the first gate emission signal generator 310 and the second gate emission signal generator 320 in the plan view.

[0221] The seventh conductive layer CL7′ may be defined by a first opening OP1′ and a second opening OP2 penetrating the seventh conductive film CL7′ in the thickness direction (i.e., the third direction DR3). The seventh conductive layer CL7′ may include a first region A1 defined as the region defining the first opening OP1′ and a second region A2 defined as the region defining the second opening OP2′. The first opening OP1′ may overlap with the first clock line CKL1 and the second clock line CKL2 in the first region A1 in a planar view, and the second opening OP2 may not overlap with the first clock line CKL1 and the second clock line CKL2 in the second region A2 in a planar view.

[0222] Each of the plurality of first openings OP1′ may include a first sub-opening SOP1′ that overlaps at least a portion of the first clock line CKL1 in a plan view and a second sub-opening SOP2′ that overlaps at least a portion of the second clock line CKL2 in a plan view. In an embodiment, the first sub-opening SOP1′ and the second sub-opening SOP2′ may be symmetrical with respect to a virtual line extending in the second direction DR2.

[0223] Since the first sub-aperture SOP1′ and the second sub-aperture SOP2′ are formed symmetrically, the area of ​​the first clock line CKL1 overlapping with the first sub-aperture SOP1′ in the planar view and the area of ​​the second clock line CKL2 overlapping with the second sub-aperture SOP2′ in the planar view can be substantially the same. Therefore, the deviation between the parasitic capacitance formed between the first clock line CKL1 and the seventh conductive layer CL7′ and the parasitic capacitance formed between the second clock line CKL2 and the seventh conductive layer CL7′ can be minimized.

[0224] The lengths of the multiple first sub-openings SOP1′ in the second direction DR2 may be the same or different. Similarly, the lengths of the multiple second sub-openings SOP2′ in the second direction DR2 may be the same or different.

[0225] Each of the plurality of second openings OP2 may include a third sub-opening SOP3 and a fourth sub-opening SOP4 arranged in an offset (or zigzag) manner.

[0226] The planar shapes of the first sub-opening SOP1′ and the second sub-opening SOP2′ may be the same as or different from the planar shapes of the third sub-opening SOP3 and the fourth sub-opening SOP4. For example, the length of at least one of the plurality of first sub-openings SOP1′ in the second direction DR2 and the length of at least one of the plurality of second sub-openings SOP2′ in the second direction DR2 may be greater than the lengths of the third sub-openings SOP3 and the fourth sub-openings SOP4 in the second direction DR2.

[0227] The gate emitter driver 300′ according to an embodiment of the present disclosure may include a seventh conductive layer CL7′ defining a first opening OP1′ that includes a first sub-opening SOP1′ overlapping a first clock line CKL1 in a plan view and a second sub-opening SOP2′ overlapping a second clock line CKL2 in a plan view. Therefore, the parasitic capacitance formed between the first clock line CKL1 and the second clock line CKL2 and the seventh conductive layer CL7′ can be reduced, and the power consumption of the display device can be reduced. Furthermore, the first sub-opening SOP1′ and the second sub-opening SOP2′ may be symmetrical with respect to a virtual line extending in the second direction DR2, and the area of ​​the first clock line CKL1 overlapping the first sub-opening SOP1′ in a plan view and the area of ​​the second clock line CKL2 overlapping the second sub-opening SOP2′ in a plan view may be substantially the same. Therefore, the deviation between the parasitic capacitance formed between the first clock line CKL1 and the seventh conductive layer CL7′ and the parasitic capacitance formed between the second clock line CKL2 and the seventh conductive layer CL7′ can be minimized, and the deviation between the output of the signal transmitted through the first clock line CKL1 and the output of the signal transmitted through the second clock line CKL2 can be minimized.

[0228] Figure 26 , Figure 27 and Figure 28 This is a layout diagram illustrating the stages included in a gate emitter driver according to an embodiment of the present disclosure. Figure 26 and Figure 27 It can be a layout diagram showing the stages included in the gate emitter driver 300". Figure 28 It can be a layout diagram showing a portion of multiple stages included in the gate emitter driver 300".

[0229] In addition to the seventh conductive layer CL7”, refer to Figure 26 , Figure 27 and Figure 28 The described gate emitter driver 300” can be compared with the reference Figures 2 to 22 The described gate emitter driver 300 is substantially the same as or similar to that described above. For example, refer to... Figure 26 , Figure 27 and Figure 28 The described gate emitter driver 300” may be included in a display device (e.g., Figure 1 The display device (DD) is used. In the following text, redundant descriptions will be omitted or simplified.

[0230] Figure 26 This is a layout diagram showing the seventh conductive layer CL7". Figure 27 and Figure 28 This is a layout diagram in which the seventh conductive layer CL7 is further disposed on the sixth conductive layer CL6. Figure 26 It can correspond to Figure 20 , Figure 27 It can correspond to Figure 21 ,and Figure 28 It can correspond to Figure 22 .

[0231] Reference Figure 26 , Figure 27 and Figure 28 Each stage in the gate emitter driver 300 may include a first gate emitter signal generator 310 and a second gate emitter signal generator 320, the first gate emitter signal generator 310 and the second gate emitter signal generator 320 being substantially symmetrical with respect to a virtual line extending in the second direction DR2.

[0232] The seventh conductive layer CL7” can be disposed on the sixth conductive layer CL6. The seventh conductive layer CL7” can be connected to the pixel electrode (e.g., Figure 3 The pixel electrodes (PE) are disposed in the same layer and can overlap with the first gate emission signal generator 310 and the second gate emission signal generator 320 in the plan view.

[0233] The seventh conductive layer CL7” may be defined by a first opening OP1” and a second opening OP2 penetrating the seventh conductive layer CL7” in the thickness direction (i.e., the third direction DR3). The seventh conductive layer CL7” may include a first region A1 defined as the region defining the first opening OP1” and a second region A2 defined as the region defining the second opening OP2. The first opening OP1” may overlap with the first clock line CKL1 and the second clock line CKL2 in the first region A1 in a plan view, and the second opening OP2 may not overlap with the first clock line CKL1 and the second clock line CKL2 in the second region A2 in a plan view.

[0234] Each of the plurality of first openings OP1” can overlap with at least a portion of the first clock line CKL1 and at least a portion of the second clock line CKL2 in a planar view. The area of ​​the first clock line CKL1 overlapping with the first opening OP1” in a planar view and the area of ​​the second clock line CKL2 overlapping with the first opening OP1” in a planar view can be substantially the same. Therefore, the deviation between the parasitic capacitance formed between the first clock line CKL1 and the seventh conductive layer CL7” and the parasitic capacitance formed between the second clock line CKL2 and the seventh conductive layer CL7” can be minimized. The lengths of the plurality of first openings OP1” in the second direction DR2 can be the same or different.

[0235] Each of the plurality of second openings OP2 may include a third sub-opening SOP3 and a fourth sub-opening SOP4 arranged in an offset (or zigzag) manner.

[0236] The planar shape of the first opening OP1” may be the same as or different from the planar shape of the third sub-opening SOP3 and the fourth sub-opening SOP4. For example, the length of at least one of the plurality of first openings OP1” in the first direction DR1 may be longer than the length of the third sub-opening SOP3 and the fourth sub-opening SOP4 in the first direction DR1.

[0237] The gate emitter driver 300” according to an embodiment of the present disclosure may include a seventh conductive layer CL7” defined in a plan view that overlaps with a first opening OP1” with a second clock line CKL1 and a second clock line CKL2. Therefore, the parasitic capacitance formed between the first clock line CKL1 and the second clock line CKL2 and the seventh conductive layer CL7” can be reduced, and the power consumption of the display device can be reduced. Furthermore, the area of ​​the first clock line CKL1 overlapping with the first opening OP1” in the plan view and the area of ​​the second clock line CKL2 overlapping with the first opening OP1” in the plan view can be substantially the same. Therefore, the deviation between the parasitic capacitance formed between the first clock line CKL1 and the seventh conductive layer CL7” and the parasitic capacitance formed between the second clock line CKL2 and the seventh conductive layer CL7” can be minimized, and the deviation between the output of the signal transmitted through the first clock line CKL1 and the output of the signal transmitted through the second clock line CKL2 can be minimized.

[0238] The gate emitter drivers 300, 300', and 300" according to embodiments of the present disclosure, and the display device DD including the gate emitter drivers 300, 300', and 300" can be applied to various electronic devices. Electronic devices according to embodiments of the present disclosure may include a display device comprising the gate emitter drivers described above, and may also include modules or devices with other additional functions in addition to the display device.

[0239] Figure 29 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0240] Reference Figure 29 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0241] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0242] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, it can transmit the input image data signal and / or control signal to the display module 11, and the display module 11 can process the received signal and output image information through the display screen.

[0243] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module, which converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0244] At least one of the plurality of components of the electronic device 10 may include a display device (e.g., according to the embodiments of the present disclosure described above) Figure 1 The display device (DD) is included in the display device. Furthermore, some of the individual modules functionally included in a single module may be included in the display device, while other components may be provided separately from the display device. For example, the display device may include display module 11, and processor 12, memory 13, and power module 14 may be provided as other devices in the electronic device 10 besides the display device.

[0245] Figure 30 This is a schematic diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0246] Reference Figure 30 The various electronic devices to which the display devices according to the embodiments of this disclosure are applied may include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, or vehicle electronic devices including display modules such as central information displays (CIDs) arranged on instrument clusters, central dashboards, and instrument panels of automobiles, and interior mirror displays 10_3, etc.

[0247] This disclosure can be applied to a variety of display devices and electronic devices. For example, this disclosure applies to various display devices such as those used in vehicles, ships and aircraft, portable communication devices, display devices for exhibitions or information dissemination, and medical display devices.

[0248] The foregoing is illustrative of the embodiments and should not be construed as limiting this disclosure. Although some embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. It is therefore to be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting oneself to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, wherein, The display device includes: Display panel, including light-emitting elements; The driver includes a first gate emitter signal generator that generates a first drive signal and a second gate emitter signal generator that generates a second drive signal that is different from the first drive signal; A first conductive layer includes a clock line electrically connected to each of the first gate emitter and the second gate emitter; and A second conductive layer is disposed on the first conductive layer, and the second conductive layer defines a first opening that overlaps with at least a portion of the clock line in a plan view and a second opening spaced apart from the first opening.

2. The display device according to claim 1, wherein, The second gate emitter signal generator is adjacent to the first gate emitter signal generator in a first direction, and The first gate emitter and the second gate emitter are symmetrical with respect to a first virtual line extending in a second direction intersecting the first direction.

3. The display device according to claim 2, wherein, The driver includes multiple levels arranged in rows; Each of the plurality of stages includes the first gate emit signal generator and the second gate emit signal generator, and The clock line includes: The first clock line is connected to the level located in the odd-numbered row among the plurality of levels; as well as The second clock line is connected to the even-numbered row of the plurality of stages.

4. The display device according to claim 3, wherein, The first opening includes: The first sub-opening overlaps at least a portion of the first clock line in the plan view; and The second sub-opening overlaps with at least a portion of the second clock line in the plan view.

5. The display device according to claim 4, wherein, The first sub-opening and the second sub-opening are symmetrical with respect to the second virtual line extending in the second direction.

6. The display device according to claim 4, wherein, The area of ​​overlap between the first sub-aperture and the first clock line in the plan view is equal to the area of ​​overlap between the second sub-aperture and the second clock line in the plan view.

7. The display device according to any one of claims 4 to 6, wherein, The first clock line includes: The first extension portion extends in the second direction; and The first protruding portion protrudes from the first extended portion, and The first sub-opening overlaps with the first extension in the plan view.

8. The display device according to any one of claims 4 to 6, wherein, The second clock line includes: The second extension portion extends in the second direction; and The second protruding portion protrudes from the second extended portion, and The second sub-opening overlaps with the second extension in the plan view.

9. The display device according to any one of claims 4 to 6, wherein, The second opening includes: The third son spoke; and The fourth sub-opening is spaced apart from the third sub-opening in the first direction, and the fourth sub-opening is staggered relative to the third sub-opening in the second direction.

10. The display device according to claim 3, wherein, The first opening overlaps with the first clock line and the second clock line in the plan view.

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