Stacked chip encapsulation digital twin manufacturing execution system management method and system

Abstract

The application discloses a kind of stack chip encapsulation digital twin manufacturing execution system management and control method and system, it is related to the field of intelligent manufacturing, the method: new product import stage resolves product design and process file, generates hierarchical digital twin model, allocates only stack layer identification for each stack layer;Each layer process starts before issuing stack layer identification to production line equipment, collects this layer process parameter and quality data and stores;Call current layer and existing layer history parameter, match cross-level correlation rule base, in turn carry out same layer self-checking, adjacent layer linkage check and whole layer cumulative deviation check, according to deviation level Execute normal release, parameter automatic compensation or lock stop;When finished product test fails, trace all stack layer data and calculate each layer failure contribution probability, screen failure root cause;Failure data are written back to digital twin model to optimize process parameters and update rule base.The application realizes the whole level fine management and control and accurate root cause positioning of stack chip encapsulation.

Description

Technical Field

[0001] This application relates to the field of intelligent manufacturing, and in particular to a digital twin manufacturing execution system control method and system for stacked chip packaging and testing. Background Technology

[0002] Manufacturing Execution Systems (MES) are the core control systems of semiconductor packaging and testing production lines, responsible for production planning, process parameter control, quality data traceability, and yield analysis. However, as 2.5D / 3D stacked packaging becomes a core technology for improving chip performance, traditional MES are designed based on a flat data model of "single chip," lacking the concept of "stacked layers." They cannot express the multi-level hierarchical relationships of "stack body - sub-stacked layer - bare die - microbump - through-silicon via," and can only manage the overall information of the entire stacked chip. They cannot delve into the individual layers within the stack for independent process parameter control and quality data traceability. As a result, when a multi-layer stacked chip fails, it is impossible to determine which layer or process step caused the failure. Engineers need to conduct destructive physical analysis to troubleshoot step by step, resulting in a yield improvement cycle of 3 to 6 months, which seriously affects product time-to-market. Summary of the Invention

[0003] The purpose of this application is to provide a digital twin manufacturing execution system control method and system for stacked chip packaging and testing, which can solve the technical problem that traditional manufacturing execution systems cannot perform fine control over the stacking layers inside 2.5D / 3D stacked chips due to the flattening of data models.

[0004] To achieve the above objectives, this application provides the following solution: Firstly, this application provides a method for controlling a digital twin manufacturing execution system for stacked chip packaging and testing, including: During the new product introduction phase, product design and process documents are analyzed to generate a multi-layered tree-structured hierarchical digital twin model with the stack body identifier as the root node and the stack layer identifier as the child node. A unique stack layer identifier is assigned to each stack layer according to a preset coding rule, and a mapping of the subordinate relationship between the stack body identifier and the stack layer identifier is established. Before each layer of the stacking process starts, the corresponding stacking layer identifier is issued to the production line equipment. The production line equipment collects the process parameters and quality data of this layer. All collected data is bound to the corresponding stacking layer identifier and then uploaded and stored. Retrieve historical parameters of the current layer and all existing layers, match them with the pre-configured cross-level association rule base, and sequentially perform self-verification of the same layer, linkage verification of adjacent layers, and cumulative deviation verification of the entire layer; based on the deviation level, perform three actions: normal release, automatic parameter compensation and early warning, and locking the stack body identifier and stopping alarm. After all stacked layer processes are completed and verified, finished product testing is performed. If no failure is found in the finished product test, the stacked chip is determined to be a good product. If a failure is found in the finished product test, the process data, detection data, historical warning data and compensation data corresponding to all stacked layer identifiers under the failed stacked body are retrieved through the failed stacked body identifier. The failure contribution probability corresponding to the abnormal parameters of each layer is calculated, and the stacked layer with the highest failure contribution probability and its corresponding process parameters are selected as the root cause of the failure. Mass production test data and failure root cause data are written back to the digital twin model. The cross-level process parameters are optimized with the goal of maximizing yield and minimizing defects and deviations. The optimization results are updated to the cross-level association rule base and distributed to the production line equipment.

[0005] Optionally, the multi-layered tree-structured digital twin model includes: The stack is identified by the root node, the stack layer by the first-level node, the die by the second-level node, the microbump by the third-level node, and the through-silicon via by the fourth-level node; the hierarchical relationship of each node is stored in the database.

[0006] Optionally, a physical barcode is laser-engraved on the surface of the wafer or substrate as a physical anchor point, without using an RFID tag; after loading and scanning, a three-level logical mapping relationship is established in the database between the physical serial number, the stack body identifier and the stack layer identifier; the stack layer identifier is not physically engraved on the chip or substrate surface, but is only stored in the manufacturing execution system logic field.

[0007] Optionally, the encoding of the stacking layer identifier is composed of a product code, batch code, layer number, and check digit concatenated together.

[0008] Optionally, the process parameters and quality data of this layer include bonding temperature, bonding pressure, bonding time, interlayer flatness, interlayer warpage, microbump height, through-silicon via resistance, and bonding strength. The detection data is obtained through four methods: automatic optical detection, shear force testing, laser interference profile measurement, and electrical testing. The detection data is uniformly structured and stored with stack body identifier, stack layer identifier, device number, measured value, and judgment identifier.

[0009] Optionally, the cross-level association rule base is jointly determined by the benchmark value determined by the experience of process experts, the initial threshold and compensation coefficient determined by digital twin Monte Carlo simulation, and the statistical iterative correction of mass production historical big data. The cross-level association rule base includes constraint rules for three typical bonding types: Si-Si homogeneous hot-press bonding, Si-InP heterogeneous melt bonding, and Si-silicon interposer hybrid bonding.

[0010] Optionally, the same-layer self-check checks whether the parameters of the current layer are within the allowed range of the current layer; The adjacent layer linkage verification checks the direct impact of the current layer on the next layer, including the prediction that high temperature will lead to increased stress in the next layer, high pressure will lead to the risk of displacement in the next layer, and high warpage will lead to poor bonding in the next layer. The full-layer cumulative deviation check calculates the cumulative deviations of all existing layers, including temperature cumulative deviation, pressure cumulative deviation, warpage cumulative change, and total alignment offset, to determine whether the total deviation exceeds the upper limit that the stacked structure can withstand.

[0011] Optionally, the three actions based on the deviation level—normal release, automatic parameter compensation and early warning, and locking the stack identifier and stopping the machine with an alarm—specifically include: When the deviation is slightly abnormal, the compensation formula is retrieved from the cross-level association rule base, the process parameters of the next layer are automatically calculated and updated, the compensation log is recorded and bound to the stacking layer identifier; When the deviation is moderately abnormal, a yellow warning is issued and the next layer stacking process continues, while the detection efforts of the next layer are strengthened. When the deviation is severe, the stack body identifier and the corresponding stack layer identifier are locked, the next layer process task is prohibited, a red alarm is sent, and a re-inspection and failure analysis are forcibly triggered.

[0012] Optionally, after locking the stack body identifier and the corresponding stack layer identifier, configure the single-layer forced release and designated stack layer rework functions for hierarchical permission control; after approval by an authorized engineer, the faulty layer is specially released and the release history is marked; if rework is required, a new stack layer identifier is assigned to the faulty layer and the process is redone separately, and the original defective layer data is archived and invalidated; if it is determined that it cannot be repaired, the entire batch is marked as scrapped and the data is permanently archived.

[0013] Secondly, this application provides a digital twin manufacturing execution system for stacked chip packaging and testing, comprising: The hierarchical data management module is used to parse product design and process documents, generate a multi-layer tree-structured hierarchical digital twin model with stack body identifier as the root node and stack layer identifier as the child node, assign a unique stack layer identifier to each stack layer, establish a hierarchical mapping between the stack body identifier and the stack layer identifier, and store the full production data bound to the stack layer identifier in a hierarchical manner. The production line equipment interface module is used to send the corresponding stacking layer identifier to downstream production line equipment and receive the process parameters and quality data bound to the stacking layer identifier uploaded by the production line equipment. The process parameter linkage control module is used to retrieve historical parameters of the current layer and all existing layers, match them with the pre-configured cross-level association rule library, and sequentially carry out self-verification of the same layer, linkage verification of adjacent layers and cumulative deviation verification of the whole layer. Based on the deviation level, it performs three actions: normal release, automatic parameter compensation and early warning, and locking the stack body identifier and stopping alarm. The hierarchical yield analysis module is used to retrieve process data, test data, historical warning data and compensation data corresponding to all stacking layer identifiers under the failed stacking body identifier when a failure occurs in the finished product test. It calculates the failure contribution probability corresponding to the abnormal parameters of each layer and selects the stacking layer with the highest failure contribution probability and the corresponding process parameters as the root cause of failure. The digital twin simulation optimization module is used to write back mass production measured data and failure root cause data to the digital twin model, optimize cross-level process parameters with the goal of maximizing yield and minimizing defects and deviations, and then update the optimization results to the cross-level association rule library and send them to the production line equipment.

[0014] Thirdly, this application provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the digital twin manufacturing execution system control method for stacked chip packaging and testing as described above.

[0015] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the digital twin manufacturing execution system control method for stacked chip packaging as described above.

[0016] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the digital twin manufacturing execution system control method for stacked chip packaging as described above.

[0017] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application provides a digital twin manufacturing execution system (MAS) control method and system for stacked chip packaging and testing. During the new product introduction phase, it analyzes product design and process documents to generate a multi-layered, hierarchical digital twin model with the stack body identifier as the root node and stack layer identifiers as child nodes. Based on preset coding rules, it assigns a unique stack layer identifier to each stack layer and establishes a hierarchical mapping between the stack body identifier and the stack layer identifier. This achieves independent identification and digital modeling of each stack layer within the stacked chip, enabling each stack layer to function as an independent control unit for data management. This provides a data foundation for subsequent refined control and precise root cause analysis. Before each stacking process begins, the system issues the corresponding stack layer identifier to the production line equipment. All process parameters and quality data collected by the production line equipment for that layer are bound to the corresponding stack layer identifier before being uploaded and stored. This achieves independent collection and associated storage of process data for each stack layer. Data for each layer can be independently queried and traced using the stack layer identifier, significantly improving data traceability efficiency and reducing human error rates. By retrieving historical parameters of the current layer and all existing layers and matching them with a pre-configured cross-layer association rule base, the system sequentially performs self-verification within the same layer, linkage verification between adjacent layers, and cumulative deviation verification across all layers. This enables cross-layer parameter linkage verification, fully considering the cumulative impact of parameters from previous layers on subsequent layers in the stacking process. Simultaneously, based on the deviation level, the system performs three actions: normal release, automatic parameter compensation and early warning, and locking the stack identifier and stopping the system with an alarm. This achieves automatic graded response to process anomalies, automatically compensating and correcting minor anomalies, providing early warnings for moderate anomalies, and immediately locking and alarming for severe anomalies, effectively reducing the risk of batch scrapping. By performing final product testing after all stacked layers have completed their processes and passed verification, the stacked chip is deemed a good product if no failures are found during the final product test, thus achieving a clear determination of qualified products. When a failure occurs during the final product test, the process data, detection data, historical warning data, and compensation data corresponding to all stacked layers under the failed stack are retrieved through the failed stack identifier. The failure contribution probability corresponding to the abnormal parameters of each layer is calculated, and the stacked layer with the highest failure contribution probability and its corresponding process parameters are selected as the root cause of the failure. This achieves precise location of the root cause, narrowing the scope of root cause location from the entire chip to specific stacked layers and process parameters, significantly shortening the root cause location cycle. By writing back mass production test data and failure root cause data to the digital twin model, the cross-layer process parameters are optimized with the goal of maximizing yield and minimizing defects and deviations. The optimization results are updated to the cross-layer association rule base and distributed to the production line equipment, forming a complete technical closed loop from modeling, control, analysis to optimization. This enables continuous iterative optimization of the stacking process, effectively shortening the development cycle of new stacking processes and reducing physical trial and error costs. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a digital twin manufacturing execution system control method for stacked chip packaging and testing, provided in an embodiment of this application; Figure 2 A flowchart illustrating a digital twin manufacturing execution system control method for stacked chip packaging and testing, provided as another embodiment of this application; Figure 3 A functional module diagram of a digital twin manufacturing execution system for stacked chip packaging and testing provided in one embodiment of this application; Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] In one exemplary embodiment, such as Figure 1 As shown, a digital twin manufacturing execution system control method for stacked chip packaging and testing is provided. This method is executed by computer equipment, specifically by a terminal or server alone, or by both a terminal and a server. In this embodiment, it includes the following steps 101 to 105. Wherein: Step 101, New Product Introduction Stage: Analyze product design and process documents to generate a multi-layered tree-structured hierarchical digital twin model with stack body identifier as the root node and stack layer identifier as the child node. Assign a unique stack layer identifier to each stack layer according to preset coding rules and establish a subordinate relationship mapping between the stack body identifier and the stack layer identifier.

[0023] In this embodiment, when a new product is introduced, the system automatically extracts stacking structure information from the EDA design file, BOM list, and packaging process file. The system reads the number of stacked layers, die type for each layer, die size, stacking order, through-silicon via (TSV) location, and microbump layout from the packaging design file; it reads the bonding method, curing parameters, and inspection points from the process route file; and it reads the wafer batch, die source, and interposer information used for each layer from the product BOM.

[0024] As an optional implementation, the multi-layered tree-structured hierarchical digital twin model includes: The stack is identified by the root node, the stack layer by the first-level node, the die by the second-level node, the microbump by the third-level node, and the through-silicon via by the fourth-level node; the hierarchical relationship of each node is stored in the database.

[0025] In this embodiment, the system automatically creates nodes according to a fixed five-layer tree structure: the root node is the stack identifier, used to uniquely identify the entire stack; the first-level child nodes are the stack layer identifiers, arranged in stacking order L1, L2...Ln; the second-level child nodes are the die identifiers, representing all dies contained in this layer; the third-level child nodes are the microbump identifiers, representing the microbump array; and the fourth-level child nodes are the through-silicon via (TSV) identifiers, representing TSVs. Each layer of nodes automatically inherits the identifiers of the upper-level nodes, forming a hierarchy: stack identifier → stack layer identifier → die identifier → microbump identifier → TSV identifier. The hierarchy of each node is permanently stored in the database; model modifications require the generation of a new version number and cannot be changed in situ.

[0026] In this embodiment, based on the material, thickness, and bonding method of each wafer layer, a preset process parameter template is automatically matched, including bonding temperature, bonding pressure, bonding time, curing temperature profile, alignment accuracy requirements, and inspection items and thresholds. Furthermore, a geometric model (size, position, relative relationships), process attributes (allowable parameter range, associated constraints), quality attributes (inspection items, pass / fail standards), and relationships (dependency rules with the previous and next layers) are generated for each node, ultimately forming a complete digital twin entity that is simulateable, controllable, and traceable.

[0027] As an optional implementation, establishing the dependency mapping between the stack body identifier and the stack layer identifier specifically includes: Physical barcodes are laser-engraved on the surface of the wafer or substrate as physical anchors, without using RFID tags; after loading and scanning, a three-level logical mapping relationship is established in the database between the physical serial number, the stack body identifier and the stack layer identifier; the stack layer identifier is not physically engraved on the chip or substrate surface, but is only stored in the manufacturing execution system logic field.

[0028] In this embodiment, the stacking layer identifier is not directly imprinted on the chip and carrier. Instead, it relies on "carrier or wafer laser physical encoding + multi-level logical mapping of the manufacturing execution system database" to complete the physical and data binding. Before wafer dicing and carrier board assembly, a unique physical QR code or 1D code (batch number + wafer identifier or carrier board serial number) is engraved on the wafer dicing track and carrier board edge using laser marking equipment. This code is permanently imprinted on the physical carrier as a unique physical identity. RFID tags are not used because the high temperature and pressing process environment easily damages RFID tags, and they are costly and not resistant to process conditions. After material loading and scanning, the system receives the physical code and establishes a three-level logical mapping relationship in the database between the physical serial number, the stacking body identifier, and all subordinate stacking layer identifiers. One stacking body on the same carrier board corresponds to one stacking body identifier. This stacking body identifier is associated with all stacking layer identifiers of this product. The stacking layer identifier is not physically imprinted on the chip or carrier board surface; it is only stored in the manufacturing execution system's logical fields. Before a single-layer stacking process begins, the stacking layer identifier corresponding to the current process is sent to the production line equipment (including at least bonding equipment, ball-mounting equipment, thinning equipment, testing equipment, and cleaning equipment) along with the process instructions. The temperature, pressure, and testing data collected by the production line equipment automatically include the stacking layer identifier. Based on the established database mapping of "physical serial number - stack body identifier - stacking layer identifier," a one-to-one correspondence between the physical workpiece and the layer-level data is achieved. For subsequent traceability, the laser code on the carrier board or wafer is scanned, and all associated stacking layer identifiers and full-layer data are retrieved from the database.

[0029] As an optional implementation, the encoding of the stacking layer identifier is composed of a product code, a batch code, a layer number, and a check digit.

[0030] In this embodiment, the system automatically generates stacking layer identifiers according to unified rules to ensure global uniqueness: Stacking layer identifier = Product code (6 digits) + Batch code (8 digits) + Stacking sequence number (2 digits) + Check digit (2 digits). For example, "HB00082405210109" means: High Bandwidth Memory (HBM) product, Batch 240521, Layer 1, Check digit 09.

[0031] By implementing the above-mentioned methods and establishing a hierarchical digital twin model with the stack layer identifier as the core, the "stack layer" is treated as an independent control unit for the first time, realizing full-level data traceability from the stack body to the through-silicon via, laying the foundation for subsequent refined control and accurate root cause localization.

[0032] Step 102: Before each layer of the stacking process starts, the corresponding stacking layer identifier is issued to the production line equipment. The production line equipment collects the process parameters and quality data of this layer, and uploads and stores all collected data after binding the corresponding stacking layer identifier.

[0033] In this embodiment, after the current layer (Layer N) process is completed, three pieces of information are sent to the testing equipment: the stack identifier of the chip under test, the stack identifier of the current layer under test, and the corresponding testing items, testing parameters, and pass / fail thresholds for this layer. Upon receiving the information, the testing equipment automatically binds the stack identifier to this testing task, and all subsequent testing data must carry this stack identifier before it can be uploaded.

[0034] As an optional implementation, the process parameters and quality data of this layer include bonding temperature, bonding pressure, bonding time, interlayer flatness, interlayer warpage, microbump height, through-silicon via resistance, and bonding strength. The detection data is obtained through four methods: automatic optical detection, shear force testing, laser interference profile measurement, and electrical testing. The detection data is uniformly structured and stored with stack body identifier, stack layer identifier, device number, measured value, and judgment identifier.

[0035] In this embodiment, the specific steps of the quality inspection performed by the inspection equipment include four types of tests: (1) The automatic optical inspection equipment performs a full-area scan of the Layer N surface using a high-precision camera, and after acquiring the image, it extracts the bonding layer flatness, die offset (X / Y / θ), microbump exposure status, interlayer foreign matter, cracks and warping through image processing algorithms, and associates the inspection results with the stacked layer identifier to generate an optical inspection report; (2) The bonding strength inspection equipment automatically sets the thrust position and thrust speed according to the process parameters corresponding to the stacked layer identifier, applies shear force to the bonding interface of Layer N, collects the maximum shear force, fracture position and fracture mode in real time, determines whether the strength threshold of this layer is met, and binds the bonding strength data with the stacked layer identifier; (3) The laser interferometer or 3D profilometer inspection equipment inspects the Layer N surface. The N surface is scanned at multiple points to calculate the uniformity of layer thickness, global warpage and local flatness, and output 3D topography data and thickness distribution data. All data are assigned to the current stack layer identifier; (4) The electrical test equipment calls the corresponding test program according to the stack layer identifier to perform contact resistance test, insulation resistance test and continuity test on the silicon via, redistribution layer and pad of this layer, and outputs resistance value, leakage current and failure point. The electrical data is associated with the stack layer identifier and stored.

[0036] In this embodiment, the testing equipment automatically performs judgments based on the process specifications bound to the stacking layer identifier: whether the flatness is within the allowable range, whether the offset is less than the threshold, whether the bonding strength meets the standard, whether the resistance or leakage current is qualified, and whether there are any appearance defects. The judgment results are divided into OK (allowing entry into the next stacking layer) and NG (marking the stacking layer identifier as abnormal, triggering an early warning, and prohibiting entry into the next layer). All test data includes the following fixed fields: stack body identifier, stacking layer identifier, equipment number, test time, test item, measured value, upper or lower limit, judgment result (OK or NG), and original data or image path. The testing equipment uploads the above structured data in real time, automatically, and immutably. The system stores data in a three-level directory: stack body identifier → stacking layer identifier → test item. All process data and test data of the same stacking layer identifier are aggregated into a complete data package. The data cannot be deleted or modified, only appended. It supports one-click tracing of all process and quality history of the current layer by stacking layer identifier.

[0037] By implementing the above-mentioned method, the stacking layer identifier is sent to the testing equipment and all testing data is forcibly bound to the stacking layer identifier. This enables the testing process of each layer to be reproducible, the data to be traceable, and the results to be verifiable, thus completely solving the problem that traditional manufacturing execution systems cannot trace the data of each layer inside the stack.

[0038] Step 103: Retrieve historical parameters of the current layer and all existing layers, match them with the pre-configured cross-level association rule library, and sequentially perform self-verification of the same layer, linkage verification of adjacent layers, and cumulative deviation verification of the entire layer; based on the deviation level, perform three actions: normal release, automatic parameter compensation and early warning, and locking the stack body identifier and stopping alarm.

[0039] As an optional implementation, the cross-level association rule base is jointly determined by the benchmark value determined by the experience of process experts, the initial threshold and compensation coefficient determined by digital twin Monte Carlo simulation, and the statistical iterative correction of mass production historical big data; the cross-level association rule base includes constraint rules for three typical bonding types: Si-Si homogeneous hot-pressing bonding, Si-InP heterogeneous fusion bonding, and Si-silicon interposer hybrid bonding.

[0040] In this embodiment, the cross-level association rule base is determined by a combination of three methods: first, process expert experience combined with industry process specifications determines the initial threshold range as the basic benchmark value; second, digital twin multiphysics simulation calculates the coupling relationship between parameters and the initial compensation coefficient; and third, historical big data statistics from mass production continuously optimize the threshold and compensation coefficient based on mass production yield and failure data, and automatically update the database. These three methods work together to finalize the rules.

[0041] In this embodiment of the application, the cross-level association rule base includes three sets of typical constraint rules: Rule R001 applies to hot-press bonding of Si-Si homogeneous wafers: the input parameter is the measured bonding temperature of the Nth layer. Standard Nominal The allowable temperature range is [245℃, 255℃]; the compensation coefficient is derived from simulation and mass production statistics. For every 1℃ deviation of the temperature from the standard, the bonding pressure of the next layer needs to be corrected by 3%. The judgment logic is: if... If so, it's normal; the N+1 layer will use the standard pressure. No compensation, no warning; if If there is a slight anomaly, the bonding pressure of the N+1th layer during positive overheating is... negative low temperature Yellow alert, record the anomaly, continue production; if If the error occurs, a serious anomaly is detected, a red alert is issued, the stack identifier is locked, and N+1 layer stacking is suspended.

[0042] Rule R002 applies to Si-InP heterogeneous melt bonding: the input parameter is the bonding temperature of the Nth layer. Interlayer measured warpage ,standard Temperature tolerance ±4℃, warpage acceptable threshold For every 1°C increase in temperature, the insulation time compensation increases by 2%; for every 1μm increase in warpage, the alignment tolerance of the next layer decreases by 15%. The judgment logic is: if... and If the parameters are compliant, there will be no compensation or warning; if or If it is a moderate abnormality, the insulation time should be adjusted accordingly. New aligned window = original window Yellow alert, increase the frequency of automatic optical inspection at N+1 layer, normal production resumes; if or If the condition is abnormal, a red alarm will be triggered, and subsequent stacking will be stopped.

[0043] Rule R003 applies to Si die-silicon interposer hybrid bonding: the input parameter is the bonding pressure of the Nth layer. and the flatness between layers of the Nth layer nominal pressure Pressure fluctuation is allowed to be ±1.2N, and the upper limit for flatness is acceptable. For every 1N deviation in pressure, the insulation time for the next layer is adjusted by 5%. The judgment logic is: if... and If the parameters are qualified, there is no compensation or warning; if or If it is a mild abnormality, the insulation time should be adjusted accordingly. Yellow alert, normal production; if or If the condition is found to be abnormal, a red alert will be issued, the stack will be locked, and further stacking will be prohibited.

[0044] As an optional implementation, the same-layer self-check checks whether the parameters of the current layer are within the allowed range of this layer; The adjacent layer linkage verification checks the direct impact of the current layer on the next layer, including the prediction that high temperature will lead to increased stress in the next layer, high pressure will lead to the risk of displacement in the next layer, and high warpage will lead to poor bonding in the next layer. The full-layer cumulative deviation verification calculates the cumulative deviation of all existing layers, including temperature cumulative deviation, pressure cumulative deviation, warpage cumulative change, and total alignment offset, to determine whether it exceeds the upper limit of the total deviation that the stacked structure can withstand.

[0045] In this embodiment, the specific execution steps of cross-level linkage verification are as follows: read the actual process parameters (bonding temperature, bonding pressure, bonding time, alignment accuracy, warpage) of the current layer (Nth layer), the process parameters and quality results of all completed layers of all existing layers (the first N-1 layers), and the rule base number, material combination and stacking structure of the current product. Automatically match the cross-level association rules corresponding to this product and perform chain verification according to the inter-layer influence relationship. The verification is divided into three levels: (1) Self-verification of the same layer - check whether the parameters of the current layer are within the allowable range of the current layer; (2) Linkage verification of adjacent layers - check the direct influence of the current layer on the next layer, including the prediction that the temperature is too high and the stress of the next layer increases, the prediction that the pressure is too high and the risk of the next layer shifts, and the prediction that the warpage is too high and the bonding of the next layer is poor; (3) Verification of the cumulative effect of all historical layers - calculate the cumulative deviation of all existing layers, including the cumulative deviation of temperature, the cumulative deviation of pressure, the cumulative change of warpage and the total cumulative alignment shift, and determine whether it exceeds the upper limit of the total deviation that the stacking structure can withstand.

[0046] As an optional implementation, the three actions based on the deviation level—normal release, automatic parameter compensation and early warning, and locking the stack identifier and stopping the machine with an alarm—specifically include: When the deviation is slightly abnormal, the compensation formula is retrieved from the cross-level association rule base, the process parameters of the next layer are automatically calculated and updated, the compensation log is recorded and bound to the stacking layer identifier; When the deviation is moderately abnormal, a yellow warning is issued and the next layer stacking process continues, while the detection efforts of the next layer are strengthened. When the deviation is severe, the stack body identifier and the corresponding stack layer identifier are locked, the next layer process task is prohibited, a red alarm is sent, and a re-inspection and failure analysis are forcibly triggered.

[0047] In this embodiment, if no abnormalities are found after the current layer's process parameters have undergone self-verification, adjacent layer linkage verification, and full-layer cumulative deviation verification, the process of that layer is deemed qualified and allowed to proceed to the next layer's stacking process. Once all stacked layers have completed their processes and passed verification, the stacking process is complete, and the stack is sent to a finished product testing device for electrical testing. If the finished product test passes, the stacked chip is deemed a good product; if a failure occurs during the finished product test, the failure tracing and root cause localization process in step 104 is triggered.

[0048] By implementing the above-mentioned methods, a cross-level and cross-process process parameter association rule library is established and three-level verification is performed, which realizes the linkage control and automatic verification of heterogeneous integrated processes. It can promptly detect cross-level parameter conflicts and automatically compensate for them, effectively reducing the risk of batch scrap.

[0049] As an optional implementation, after locking the stack body identifier and the corresponding stack layer identifier, configure the single-layer forced release and designated stack layer rework functions with hierarchical permission control; after approval by an authorized engineer, the faulty layer is specially released and the release history is marked; if rework is required, a new stack layer identifier is assigned to the faulty layer and the process is redone separately, and the original defective layer data is archived and invalidated; if it is determined that it cannot be repaired, the entire batch is marked as scrapped and the data is permanently archived.

[0050] In this embodiment, after a serious anomaly is detected and the stack body identifier and corresponding stack layer identifier are locked, the production line is physically isolated, and the process engineer conducts failure determination based on full-level data; a single-layer forced release and designated stack layer rework function with hierarchical permission control are configured; after approval by an authorized engineer, the faulty layer is specially approved for release (i.e., products that do not meet the standards but are allowed to be used after evaluation are released), and the release history is marked; if rework is required, a new stack layer identifier is assigned to the faulty layer and the process is redone separately, and the original defective layer data is archived and invalidated; if it is determined that it cannot be repaired, the entire batch is marked as scrapped and the data is permanently archived, taking into account both the flexibility of the production line process and the traceability of the entire process data.

[0051] Step 104: After all stacked layer processes are completed and verified, finished product testing is performed. If no failure is found in the finished product test, the stacked chip is determined to be a good product. If a failure is found in the finished product test, the process data, detection data, historical warning data, and compensation data corresponding to all stacked layer identifiers under the failed stack are retrieved through the failed stack identifier. The failure contribution probability corresponding to the abnormal parameters of each layer is calculated, and the stacked layer with the highest failure contribution probability and its corresponding process parameters are selected as the root cause of the failure.

[0052] In this embodiment, after the finished product testing equipment reports the failure of a certain unit identifier or stack identifier, a traceability command is initiated based on the stack identifier of the failed chip. The system pulls all stack layer identifiers (L1~Ln), process parameters for each layer, inspection data for each layer (automatic optical inspection, shear force, flatness, electrical properties), equipment information, time, and operator information for each layer from the database at once. Historical anomaly records (which layer experienced temperature, pressure, or offset deviations, which layer performed automatic compensation, and which layer issued warnings) and simulation prediction records (the theoretical power to be achieved for each layer, and the weight of each layer's deviation on the yield) are retrieved to form a complete traceability chain of "one stack, all layers, and all processes": stack identifier → stack layer identifier L1~Ln → process → inspection → linked anomaly → twin simulation. The traceability data package is sent to the yield analysis engine to prepare for root cause calculation.

[0053] The specific implementation process of hierarchical yield analysis is as follows: Grouping by stacked layers, failure characteristics are mapped to each layer. For example, open circuits correspond to vias or poor bonding in a certain layer, leakage current corresponds to poor insulation or filling in a certain layer, and excessive offset corresponds to misalignment in a certain layer. Key feature vectors for each layer are extracted, including temperature deviation. Pressure deviation Time deviation Alignment offset Features include flatness defects, warpage, bond strength, number of cross-layer compensation attempts, and number of anomaly warnings. All layer features are input into a Bayesian network or random forest algorithm to calculate the probability of failure for each layer. The algorithm outputs the identifier of the stacked layer with the highest probability, its process parameters, and the failure mechanism, generating a root cause report.

[0054] Specifically, a Bayesian network is used to calculate the failure contribution probability corresponding to parameter anomalies at each layer: The Bayesian network topology is built based on stacked physical causality—with process parameters and single-layer quality at each layer as parent nodes or intermediate nodes, and finished product failures as top-level child nodes, unidirectional directed causal edges are constructed according to the logic that parameters at the same layer affect the quality of this layer, and the quality of the previous layer affects the yield of the next layer. Nodes are divided into two categories: ① Parent nodes—key process parameter nodes at each layer (the first... i Layer temperature ,pressure Flatness Warp ); ② Child nodes—the quality result node of this layer, the final chip failure node. The directed edge construction rules are based on the heterogeneous integration physical mechanism and rule base constraints: edges in the same layer are... (Process parameters → Topology quality of this layer); Cross-layer edges are quality nodes of the preceding layer → process result nodes of the following layer (warpage anomalies in the preceding layer affect bonding yield of the following layer); All layer quality nodes point to the top-level total node "overall chip failure". The initial topology structure is determined by the process mechanism, and the correlation between edges is subsequently fine-tuned based on mass production failure data and twin simulation results.

[0055] Batch Monte Carlo simulations of single-layer abnormal operating conditions were performed using digital twins, and conditional probabilities were obtained by statistically analyzing failure frequencies. : Fix the first part in the digital twin model i All parameters outside the first layer are standard process values. i layer Perform N Monte Carlo random sampling simulations (N≥1000) within the abnormal interval, and count the final number of chip failure samples in the simulation. ,but This probability is stored in a Bayesian network conditional probability table and subsequently iterated and corrected based on real failure data from mass production.

[0056] The failure weights for each layer are obtained by normalizing the failure condition probabilities for each layer. The formula is: ; in, This represents the total number of chip stacking layers. For the first The probability of chip failure when a layer anomaly occurs. For the first The probability of chip failure when a layer is faulty.

[0057] Among them, the failure weights of each layer The significance lies in transforming the "physical probability of failure caused by anomalies at each level" into the "relative responsibility proportion of each level as the root cause of failure." (Conditional probability) The character represents the first This refers to the probability of chip failure due to layer anomalies; a higher value indicates a more "fatal" anomaly at that layer. However, different stacked layers have varying degrees of "fatality" due to their different locations and manufacturing processes—for example, warping at the bottom layer is inherently more likely to cause chip failure than scratches at the top layer. Directly using this conditional probability for root cause determination would bias the judgment towards the bottom layer due to the different fatality benchmarks for each layer. Therefore, by summing the conditional probabilities corresponding to all stacked layers and using the sum as the denominator, the conditional probabilities of each layer are normalized to ensure that the probability of failure for each layer is consistent. The sum of these values ​​equals 1, thus placing each layer under a unified evaluation metric for comparison. A higher value indicates that, assuming anomalies may occur in all stacked layers, the [missing value] is more likely to occur in the [missing value]. The greater the relative tendency of a layer to be the root cause of failure, the higher the weight of attention given to that layer in the posterior probability estimation.

[0058] All probability and weight parameters are continuously updated iteratively based on simulation data and field production failure data. These parameters are then substituted into the posterior probability formula to calculate the failure probability at each level. The posterior probability formula is: in, For the first The prior probability of anomalies occurring in a layer (historical statistics). The global failure probability is normalized. The stacking layer with the highest posterior probability and its corresponding anomaly parameters are selected as the root cause of the failure. After determining the root cause layer, root cause parameters, and failure mechanism, a report is output: the most likely root cause layer is... The root cause parameters are bonding temperature, bonding pressure, or alignment, and improvement suggestions are provided.

[0059] When using the random forest algorithm to calculate the failure contribution probability corresponding to parameter anomalies in each layer: the bonding temperature deviation, bonding pressure deviation, interlayer warpage, and interlayer flatness of each stack layer are used as input features. The model is trained based on mass-produced labeled failure samples and twin simulation samples, outputting the failure contribution score for each layer. The stack layer with the highest score and its corresponding process parameters are determined as the root cause of the failure. The input feature vector of the random forest... ,in For the first i Layer bonding temperature deviation For the first i Layer pressure deviation, For the first i Layer warping For the first i Layer flatness features are all taken from stored process and inspection data of each stack layer. The training method of random forest is as follows: the training data source includes historical mass production full data (parameters of all layers of normal good stack and parameters of all layers of defective and failed stack) and massive simulation samples generated by digital twin Monte Carlo simulation (used to expand small sample failure data); the sample label marks the true root cause level number (L1, L2...Ln) corresponding to the final failure of the sample. The labels are manually labeled based on the historical destructive physical analysis report of the production line to form a labeled dataset; the dataset is divided into a training set of 70% and a validation set of 30%; multiple decision trees of random forest are trained in parallel, and key abnormal parameters are screened by feature split gain; the validation set is used to fine-tune hyperparameters such as the number of trees and the depth of a single tree; after training, the model is fixed and inference is performed in real time, outputting the failure contribution score of each layer. The stack layer identifier and specific process parameters corresponding to the maximum score are determined as the root cause of failure.

[0060] By implementing the above-mentioned methods, through failure data aggregation analysis based on stacking layer identifiers and Bayesian network inference or random forest algorithm inference, the yield analysis has been transformed from "whole chip" to "specific stacking layer", reducing the root cause location time from several months to several days and significantly improving the yield improvement efficiency.

[0061] Step 105: Write back the mass production test data and failure root cause data to the digital twin model, optimize the cross-level process parameters with the goal of maximizing yield and minimizing defects and deviations, update the optimization results to the cross-level association rule library and send them to the production line equipment.

[0062] In this embodiment, actual production process data and failure data are fed into the digital twin model to ensure consistency between the virtual model and the real production line. Then, different combinations of process parameters are simulated in the virtual environment to identify the set of parameters with the highest yield and greatest stability, which is then automatically updated to the production line.

[0063] In this embodiment of the application, a genetic algorithm can be used for optimization. The specific process is as follows: (1) Determine the optimization target - to make the yield of multi-layer stacking the highest, the defects the fewest, and the offset the smallest. The weighted combination fitness function is used to quantify the optimization target, and the three indicators of yield, defect rate and interlayer offset are converted into a unified fitness value; (2) The process parameters are compiled into a set of "schemes" - the temperature, pressure and time of each layer form a set of parameter schemes; (3) Multiple schemes are generated to start optimization - multiple different parameter schemes are randomly generated and sent to digital twin simulation; (4) The schemes are evaluated - the yield, defects and stress that each scheme can achieve are simulated by digital twin simulation and a score is given; (5) Good schemes are retained and bad schemes are eliminated - the schemes with high scores are retained and the schemes with low scores are eliminated; (6) New schemes are generated by cross - the parameters of good schemes are combined with each other to generate better new schemes; (7) Slight variation to avoid local optima - the parameters are adjusted very slightly to prevent the algorithm from getting stuck in local optima; (8) Repeated iteration until the optimal scheme is found - the cycle is repeated until the yield no longer improves significantly and the optimization is stopped; (9) The optimal parameters are output - the optimal set of multi-layer process parameters obtained from the simulation is updated to the process rule library and distributed to the production line equipment.

[0064] The fitness calculation formula of the genetic algorithm is as follows: ; in, For fitness values, The larger the value, the better the process solution; The overall yield of the stack obtained from digital twin simulation; This is the simulated defect rate; This represents the total cumulative alignment offset across all stacked layers. The yield weighting coefficient is used to calculate the yield. This is the defect rate weighting coefficient. These are offset weighting coefficients; all three are preset fixed constants, determined through process expert experience and simulation calibration. For example, for Si-intermediate hybrid bonding, [the following value is used]. =0.6, =0.3, =0.1, substituting gives Maximizing yield—the higher the yield Y, the better. Positive increase; fewest defects—the higher the defect rate D, Deducted, value decreases; minimum offset – inter-layer cumulative offset The larger, The more deductions are made, the more the three optimization objectives are fully quantified and unified. During the genetic algorithm iteration, combinations of process parameters with high fitness values ​​are retained, ultimately outputting the optimal cross-level process parameters, updating the cross-level association rule base, and distributing them to the production line equipment.

[0065] By implementing the above-mentioned methods, the mass production test data and failure root cause data are written back to the digital twin model and virtual simulation optimization is performed using a genetic algorithm. This forms a complete technical closed loop of "modeling-control-analysis-optimization", which realizes continuous optimization of the stacking process, effectively shortens the development cycle of new processes and reduces the cost of physical trial and error.

[0066] By implementing steps 101 to 105 above, a hierarchical digital twin model centered on stacked layer identifiers is established, enabling full-level data modeling and traceability of the stacked chip from the stack body to the through-silicon via (TSV). Through a cross-level process parameter linkage verification mechanism, automatic verification and adaptive adjustment of the heterogeneous integration process are achieved. Through failure data aggregation and Bayesian network inference based on stacked layer identifiers, precise root cause localization from the "whole chip" to the "specific stacked layer" is achieved. Through virtual-physical combined digital twins and genetic algorithm optimization, virtual debugging and continuous optimization of the stacked process are realized. This application completely solves the industry pain point that traditional manufacturing execution systems cannot manage the internal layers of the stack, forming a complete technical closed loop of "modeling-control-analysis-optimization".

[0067] As an optional implementation method, such as Figure 2 As shown, this method starts with the construction of a hierarchical digital twin model in the new product introduction stage, and then sequentially executes the following steps: hierarchical digital twin model construction, unique identifier stacking layer identifier allocation and subordinate relationship mapping, process data acquisition and associated storage, cross-level process parameter linkage verification, parameter anomaly judgment, finished product testing, hierarchical yield analysis and root cause localization, and digital twin virtual simulation and optimization, forming a complete "modeling-control-analysis-optimization" closed loop.

[0068] Based on the same inventive concept, this application also provides a digital twin manufacturing execution system for stacked chip packaging, used to implement the aforementioned digital twin manufacturing execution system control method for stacked chip packaging. The solution provided by this device is similar to the implementation described in the above method. Therefore, the specific limitations of one or more embodiments of the digital twin manufacturing execution system for stacked chip packaging provided below can be found in the limitations of the digital twin manufacturing execution system control method for stacked chip packaging described above, and will not be repeated here.

[0069] In one exemplary embodiment, such as Figure 3 As shown, a digital twin manufacturing execution system for stacked chip packaging and testing is provided, comprising: The hierarchical data management module is used to parse product design and process documents, generate a multi-layer tree-structured hierarchical digital twin model with stack body identifier as the root node and stack layer identifier as the child node, assign a unique stack layer identifier to each stack layer, establish a hierarchical mapping between the stack body identifier and the stack layer identifier, and store the full production data bound to the stack layer identifier in a hierarchical manner. The production line equipment interface module is used to send the corresponding stacking layer identifier to downstream production line equipment and receive the process parameters and quality data bound to the stacking layer identifier uploaded by the production line equipment. The process parameter linkage control module is used to retrieve historical parameters of the current layer and all existing layers, match them with the pre-configured cross-level association rule library, and sequentially carry out self-verification of the same layer, linkage verification of adjacent layers and cumulative deviation verification of the whole layer. Based on the deviation level, it performs three actions: normal release, automatic parameter compensation and early warning, and locking the stack body identifier and stopping alarm. The hierarchical yield analysis module is used to retrieve process data, test data, historical warning data and compensation data corresponding to all stacking layer identifiers under the failed stacking body identifier when a failure occurs in the finished product test. It calculates the failure contribution probability corresponding to the abnormal parameters of each layer and selects the stacking layer with the highest failure contribution probability and the corresponding process parameters as the root cause of failure. The digital twin simulation optimization module is used to write back mass production measured data and failure root cause data to the digital twin model, optimize cross-level process parameters with the goal of maximizing yield and minimizing defects and deviations, and then update the optimization results to the cross-level association rule library and send them to the production line equipment.

[0070] In this embodiment, the production line equipment interface module hardware adopts a star-shaped industrial Ethernet network, configured with a dual-protocol gateway supporting both OPCUA and SECS / GEM protocols. Internally, it includes a data acquisition unit, a protocol conversion unit, a command issuance unit, and a data caching unit. The production line equipment interface module hardware uses a star topology network, consisting of multiple industrial gateways. These gateways connect to the manufacturing execution system servers in the data center via an industrial Ethernet star topology. New equipment uses OPCUA communication, while older packaging and testing equipment uses SECS / GEM communication. Both protocols are converted to OPCUA format by the gateway's internal protocol conversion unit before uploading. The module's internal data caching unit enables temporary data storage during network outages and subsequent transmission upon network recovery. The command issuance unit sends optimized process parameters back to the corresponding production and testing equipment. The data acquisition unit collects process parameters from each process device and quality data from the testing equipment in real time. The data caching unit temporarily stores data during network outages and ensures continued transmission upon network recovery. The command issuance unit sends optimized process parameters and control commands back to the corresponding production and testing equipment.

[0071] In this embodiment, the hierarchical data management module is deployed on a database server and includes a model building unit, a stacking layer identifier allocation unit, a data association storage unit, and a data query unit. The model building unit is responsible for automatically generating a multi-layered, tree-structured hierarchical digital twin model based on the product design and process data of the 2.5D / 3D stacked chips. The stacking layer identifier allocation unit is responsible for generating unique stacking layer identifiers for each layer of the 2.5D / 3D stack according to preset coding rules. The data association storage unit is responsible for establishing a three-level database logical mapping of "physical carrier board serial number → stacking body identifier → stacking layer identifier," and storing the full production data of the 2.5D / 3D stack according to a three-level directory of "stacking body identifier → stacking layer identifier → detection item." The data query unit supports one-click full data traceability by stacking layer identifier.

[0072] In this embodiment, the process parameter linkage control module is deployed on the application server and includes an iteratively updatable 2.5D / 3D stacking cross-layer parameter association rule library, a real-time verification unit, an anomaly handling unit, and a parameter adaptive adjustment unit. The real-time verification unit automatically triggers a three-level verification process after each 2.5D / 3D stacking layer is completed. The anomaly handling unit performs normal release, yellow warning, or red alarm locking based on the deviation level. The parameter adaptive adjustment unit automatically calculates and distributes the adjustment values ​​of the next layer's 2.5D / 3D stacking process parameters according to the compensation formula in the rule library.

[0073] In this embodiment, the hierarchical yield analysis module is deployed on the application server and includes a data aggregation unit, a hierarchical statistics unit, a multi-algorithm root cause analysis unit, and a report generation unit. The data aggregation unit is responsible for retrieving full data corresponding to all stack layer identifiers based on the identifiers of the failed 2.5D / 3D stack. The hierarchical statistics unit is responsible for performing stratified yield statistics and trend analysis based on the 2.5D / 3D stack layers. The multi-algorithm root cause analysis unit incorporates Bayesian network algorithms and random forest algorithms, which can be flexibly selected according to configuration. The report generation unit is responsible for outputting root cause localization reports and yield analysis dashboards.

[0074] In this embodiment, the digital twin simulation optimization module is deployed on a high-performance computing device, equipped with a multiphysics simulation engine and a genetic algorithm optimization unit. The simulation engine supports coupled thermal-mechanical-electrical multiphysics simulation of 2.5D / 3D stacking processes, while the genetic algorithm optimization unit performs global optimization with the objectives of maximizing 2.5D / 3D stacking yield, minimizing defect rate, and minimizing interlayer offset. The module receives on-site measured data to complete virtual model calibration and iterative optimization, and the optimization results are fed back to the process parameter linkage control module to update the cross-level association rule base.

[0075] As an optional implementation, the digital twin manufacturing execution system for stacked chip packaging and testing includes a low-cost deployment version, a standard deployment version, and a high-performance deployment version, with hardware configurations and functions tailored to each version as needed; wherein: The low-cost deployment version reuses existing server hardware, omits the online simulation optimization function of digital twins, and the cross-level association rule base only supports parameter verification between adjacent two layers. The maximum number of stacked layers to be managed does not exceed 8, and the stacked layer identifier is simplified to the stack body identifier and layer number concatenation format. The unit identifier of the traditional manufacturing execution system is reused as the stack body identifier to achieve data interoperability. This version achieves basic control functions of stacked layers with minimal modification cost, is compatible with existing manufacturing execution systems, and can be quickly deployed and verified. It is suitable for low-to-mid-end advanced packaging production lines with 3 to 8 layers of stacking, such as consumer electronics chip packaging.

[0076] The standard version system is configured with an independent application server, an independent database server, and a single graphics processor simulation server, supporting full-function management of 8 to 16-layer stacking. This version fully implements all the core functions of this invention, meets the mass production requirements of most advanced packaging production lines, and is suitable for mid-to-high-end advanced packaging production lines with 8 to 16-layer stacking, such as 2.5D or 3D packaging of AI chips and server chips.

[0077] The high-performance version employs a distributed cluster and an H100 graphics processor cluster, using a graph-structured data model to support up to 32 layers of heterogeneous stacking and millisecond-level real-time parameter verification. This version offers superior performance and functionality for advanced packaging technologies such as high-bandwidth memory 3E and 3D IC, and is suitable for high-end advanced packaging production lines with stacking layers of 16 or more, such as the R&D and mass production lines for high-bandwidth memory 3E and 3D IC chips.

[0078] This implementation method, through the collaborative work of five major modules, constructs a complete technical closed loop of "modeling-control-analysis-optimization". The system supports three deployment versions to flexibly adapt to different needs from small and medium-sized packaging and testing plants to high-end large-scale mass production lines, combining technological advancement and industrial practicality.

[0079] In an exemplary embodiment, taking a specific 8-layer high-bandwidth memory stacking encapsulation scenario as an example, the execution process is described in detail: ① New Product Introduction and Model Building: When introducing a new product, an 8-layer stacked digital twin model is built based on the high-bandwidth memory design file. The 8-layer stacking structure information from the EDA design file, the wafer batch information for each layer in the BOM list, and the thermosetting bonding process parameter template from the packaging process file are read. A tree-structured hierarchical digital twin model is automatically generated, with the stack body identifier as the root node and stack layer identifiers L1 to L8 as first-level child nodes. A unique stack layer identifier is assigned to each layer, and a three-level logical mapping between the physical carrier board serial number, the stack body identifier, and the stack layer identifiers L1 to L8 is established in the database. A unique physical QR code is laser-engraved on the edge of the carrier board as a physical anchor point.

[0080] ② Layer-by-layer stacking process control: Before executing the L1 layer bonding process, the L1 layer stacking identifier and corresponding process parameter specifications (bonding temperature 250℃, pressure 10N, time 10s) are issued to the bonding equipment and testing equipment. After the bonding equipment completes the L1 layer bonding, the testing equipment performs automatic optical inspection, shear force testing, laser profile measurement, and electrical testing, collecting data such as bonding layer flatness, die offset, bonding strength, and through-silicon via resistance. All data are bound to the L1 stacking identifier and uploaded for storage. If the L1 parameters are verified to be normal, the L2 layer bonding process continues. The L2 layer bonding temperature is collected at 258℃ (exceeding the threshold of 250℃±5℃), automatically triggering cross-layer linkage verification.

[0081] ③ Cross-layer linkage verification and automatic compensation: Retrieve the measured bonding temperature of L2 layer (258℃) and historical parameters of L1 layer, and match them with Si-Si homogeneous hot-pressing bonding rule R001. A slight anomaly is identified: temperature deviation +8℃ (exceeding ±5℃ but within ±10℃). The compensation formula is retrieved from the rule base, and the pressure compensation coefficient is calculated as 1 + deviation ℃ × 0.03. The bonding pressure of L3 layer is adjusted to the original pressure × 1.24. The L3 layer process parameters are automatically updated, the compensation log is recorded and bound to the stacking layer identifier L2, and a yellow warning is sent. L3 layer uses the compensated process parameters for bonding, and the test data is normal.

[0082] ④ Failure Tracing and Root Cause Localization: After completing the 8-layer stack, product testing revealed an open-circuit failure in a chip. A tracing command was initiated based on the stack identifier of the failed chip. All process parameters and test data from L1 to L8 of the stack were retrieved from the database, along with cross-layer anomaly and compensation records (L2 layer temperature anomaly and L3 layer pressure compensation records), to obtain the influence weight of each layer on the failure. Key feature vectors (temperature deviation, pressure deviation, warpage, flatness, number of compensations, etc.) for each layer were extracted and grouped by stack layer. All layer features were input into a Bayesian network to calculate the posterior probability of each layer causing the failure. Bayesian network analysis revealed a 92% correlation probability between the bonding strength of the L3 layer and the failure, further pinpointing the pressure anomaly during L3 layer bonding to be caused by bonding head wear.

[0083] ⑤ Digital Twin Optimization and Closed-Loop Feedback: Root cause data of L3 layer pressure anomalies are fed back to the digital twin model. In a virtual environment, a genetic algorithm is used to optimize the bonding pressure parameters. The genetic algorithm randomly generates multiple sets of different parameter schemes, which are then fed into the digital twin simulation to evaluate the yield, defects, and deviations of each scheme. Schemes with high scores are retained, and new schemes are generated through cross-pollination. This iterative evolution continues until the yield no longer shows significant improvement. The simulation yields an optimal bonding pressure of 11.5N. The optimized parameters are updated to the cross-level association rule base and distributed to the bonding equipment, achieving continuous process optimization.

[0084] As can be seen from the complete embodiment of the above-mentioned 8-layer high-bandwidth memory stack packaging, this application realizes the closed-loop control of the entire process from stack layer identifier allocation, layer-by-layer data acquisition, cross-level linkage verification, accurate root cause location of failure to digital twin virtual optimization, effectively solving the industry pain point that traditional manufacturing execution systems cannot manage the various levels inside the stack.

[0085] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 4As shown, the computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores management data for the digital twin manufacturing execution system (DES) of stacked chip packaging and testing. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a management method for the DES of stacked chip packaging and testing.

[0086] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0087] In one exemplary embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0088] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0089] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0090] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0091] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0092] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for controlling a digital twin manufacturing execution system for stacked chip packaging and testing, characterized in that, The digital twin manufacturing execution system control method for stacked chip packaging and testing includes: During the new product introduction phase, product design and process documents are analyzed to generate a multi-layered tree-structured hierarchical digital twin model with the stack body identifier as the root node and the stack layer identifier as the child node. A unique stack layer identifier is assigned to each stack layer according to a preset coding rule, and a mapping of the subordinate relationship between the stack body identifier and the stack layer identifier is established. Before each layer of the stacking process starts, the corresponding stacking layer identifier is issued to the production line equipment. The production line equipment collects the process parameters and quality data of this layer. All collected data is bound to the corresponding stacking layer identifier and then uploaded and stored. Retrieve historical parameters of the current layer and all existing layers, match them with the pre-configured cross-level association rule base, and sequentially perform self-verification of the same layer, linkage verification of adjacent layers, and cumulative deviation verification of the entire layer; based on the deviation level, perform three actions: normal release, automatic parameter compensation and early warning, and locking the stack body identifier and stopping alarm. After all stacked layer processes are completed and verified, finished product testing is performed. If no failure is found in the finished product test, the stacked chip is determined to be a good product. If a failure is found in the finished product test, the process data, detection data, historical warning data and compensation data corresponding to all stacked layer identifiers under the failed stacked body are retrieved through the failed stacked body identifier. The failure contribution probability corresponding to the abnormal parameters of each layer is calculated, and the stacked layer with the highest failure contribution probability and its corresponding process parameters are selected as the root cause of the failure. Mass production test data and failure root cause data are written back to the digital twin model. The cross-level process parameters are optimized with the goal of maximizing yield and minimizing defects and deviations. The optimization results are updated to the cross-level association rule base and distributed to the production line equipment.

2. The digital twin manufacturing execution system control method for stacked chip packaging and testing according to claim 1, characterized in that, The multi-layered tree-structured hierarchical digital twin model includes: The stack is identified by the root node, the stack layer by the first-level node, the die by the second-level node, the microbump by the third-level node, and the through-silicon via by the fourth-level node; the hierarchical relationship of each node is stored in the database.

3. The digital twin manufacturing execution system control method for stacked chip packaging and testing according to claim 1, characterized in that, The establishment of the dependency mapping between the stack body identifier and the stack layer identifier specifically includes: Physical barcodes are laser-engraved on the surface of the wafer or substrate as physical anchors, without using RFID tags; after loading and scanning, a three-level logical mapping relationship is established in the database between the physical serial number, the stack body identifier and the stack layer identifier; the stack layer identifier is not physically engraved on the chip or substrate surface, but is only stored in the manufacturing execution system logic field.

4. The digital twin manufacturing execution system control method for stacked chip packaging and testing according to claim 1, characterized in that, The encoding of the stacking layer identifier is composed of the product code, batch code, layer number, and check digit.

5. The digital twin manufacturing execution system control method for stacked chip packaging and testing according to claim 1, characterized in that, The process parameters and quality data for this layer include bonding temperature, bonding pressure, bonding time, interlayer flatness, interlayer warpage, microbump height, through-silicon via resistance, and bonding strength. The detection data is obtained through four methods: automatic optical detection, shear force testing, laser interference profile measurement, and electrical testing. The detection data is uniformly structured and stored with stack body identifier, stack layer identifier, device number, measured value, and judgment identifier.

6. The digital twin manufacturing execution system control method for stacked chip packaging and testing according to claim 1, characterized in that, The cross-level association rule base is jointly determined by the benchmark value determined by the experience of process experts, the initial threshold and compensation coefficient determined by digital twin Monte Carlo simulation, and the statistical iterative correction of mass production historical big data. The cross-level association rule base includes constraint rules for three typical bonding types: Si-Si homogeneous hot-press bonding, Si-InP heterogeneous melt bonding, and Si-silicon interposer hybrid bonding.

7. The digital twin manufacturing execution system control method for stacked chip packaging and testing according to claim 1, characterized in that, The same-layer self-check checks whether the parameters of the current layer are within the allowed range of this layer; The adjacent layer linkage verification checks the direct impact of the current layer on the next layer, including the prediction that high temperature will lead to increased stress in the next layer, high pressure will lead to the risk of displacement in the next layer, and high warpage will lead to poor bonding in the next layer. The full-layer cumulative deviation check calculates the cumulative deviations of all existing layers, including temperature cumulative deviation, pressure cumulative deviation, warpage cumulative change, and total alignment offset, to determine whether the total deviation exceeds the upper limit that the stacked structure can withstand.

8. The digital twin manufacturing execution system control method for stacked chip packaging and testing according to claim 1, characterized in that, The three actions based on the deviation level are: normal release, automatic parameter compensation and early warning, and locking the stack identifier and stopping the machine with an alarm. Specifically, these include: When the deviation is slightly abnormal, the compensation formula is retrieved from the cross-level association rule base, the process parameters of the next layer are automatically calculated and updated, the compensation log is recorded and bound to the stacking layer identifier; When the deviation is moderately abnormal, a yellow warning is issued and the next layer stacking process continues, while the detection efforts of the next layer are strengthened. When the deviation is severe, the stack body identifier and the corresponding stack layer identifier are locked, the next layer process task is prohibited, a red alarm is sent, and a re-inspection and failure analysis are forcibly triggered.

9. The digital twin manufacturing execution system control method for stacked chip packaging and testing according to claim 8, characterized in that, After locking the stack body identifier and the corresponding stack layer identifier, configure the single-layer forced release and designated stack layer rework functions for hierarchical permission control; after approval by the authorized engineer, the faulty layer is specially released and the release history is marked; if rework is required, a new stack layer identifier is assigned to the faulty layer and the process is redone separately, and the original defective layer data is archived and invalidated; if it is determined that it cannot be repaired, the entire batch is marked as scrapped and the data is permanently archived.

10. A digital twin manufacturing execution system for stacked chip packaging and testing, used to implement the control method of the digital twin manufacturing execution system for stacked chip packaging and testing as described in any one of claims 1 to 9, characterized in that, The digital twin manufacturing execution system for stacked chip packaging includes: The hierarchical data management module is used to parse product design and process documents, generate a multi-layer tree-structured hierarchical digital twin model with stack body identifier as the root node and stack layer identifier as the child node, assign a unique stack layer identifier to each stack layer, establish a hierarchical mapping between the stack body identifier and the stack layer identifier, and store the full production data bound to the stack layer identifier in a hierarchical manner. The production line equipment interface module is used to send the corresponding stacking layer identifier to downstream production line equipment and receive the process parameters and quality data bound to the stacking layer identifier uploaded by the production line equipment. The process parameter linkage control module is used to retrieve historical parameters of the current layer and all existing layers, match them with the pre-configured cross-level association rule library, and sequentially carry out self-verification of the same layer, linkage verification of adjacent layers and cumulative deviation verification of the whole layer. Based on the deviation level, it performs three actions: normal release, automatic parameter compensation and early warning, and locking the stack body identifier and stopping alarm. The hierarchical yield analysis module is used to retrieve process data, test data, historical warning data and compensation data corresponding to all stacking layer identifiers under the failed stacking body identifier when a failure occurs in the finished product test. It calculates the failure contribution probability corresponding to the abnormal parameters of each layer and selects the stacking layer with the highest failure contribution probability and the corresponding process parameters as the root cause of failure. The digital twin simulation optimization module is used to write back mass production measured data and failure root cause data to the digital twin model, optimize cross-level process parameters with the goal of maximizing yield and minimizing defects and deviations, and then update the optimization results to the cross-level association rule library and send them to the production line equipment.

Images