Semiconductor structure and method of forming the same

Abstract

The application discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: forming a hard mask layer on a substrate; forming a metal trench corresponding to a metal line on the hard mask layer; filling a carbon-oxygen-silicon material in the metal trench and on the hard mask layer to form a size shrinkage layer; sequentially forming a pattern definition layer and a photoresist layer on the size shrinkage layer; and etching the photoresist layer and the pattern definition layer based on a metal cutting trench and a through hole corresponding photo mask to form a semiconductor structure. The metal cutting trench is used for forming a metal layer, and the through hole is used for connecting adjacent metal layers. The process of the application increases the process window of the metal cutting trench, thereby improving the yield of semiconductor products.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Existing metal cutting processes suffer from a small process window. As process nodes advance, the metal wire pitch becomes increasingly smaller, often requiring multiple exposures and developments. Furthermore, metalcutting is increasingly employed to achieve extremely small pitches. Current metal cutting processes utilize metal wires formed through different exposures and developments, often necessitating multiple processes to create the cut. Subsequent processes can negatively impact the already formed metal cutting grooves, further reducing the process window. Summary of the Invention

[0003] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which increases the process window during semiconductor formation and thus improves the yield of semiconductor products.

[0004] To solve the above-mentioned technical problems, the technical solution of this application is as follows:

[0005] According to a first aspect of the embodiments of this application, a method for forming a semiconductor structure is provided, the method comprising:

[0006] A hard mask layer is formed on the substrate;

[0007] Metal trenches corresponding to the metal lines are formed on the hard mask layer;

[0008] A carbon-oxygen-silicon material is filled on the hard mask layer and in the metal trench to form a size shrinkage layer;

[0009] A pattern definition layer and a photoresist layer are sequentially formed on the size shrinkage layer;

[0010] The photoresist layer and the pattern definition layer are etched sequentially using photomasks corresponding to the metal cutting trenches and vias to form a semiconductor structure; the metal cutting trenches are used to form metal layers, and the vias are used to connect adjacent metal layers.

[0011] In an exemplary embodiment, the photomask corresponding to the metal-cut trenches and vias is used to sequentially etch the photoresist layer and the pattern definition layer to form a semiconductor structure, including:

[0012] Based on the positional relationship between the metal cutting groove and the through hole, the metal cutting groove and the through hole are grouped, and multiple photomasks are fabricated according to the grouping results; at least one of the multiple photomasks includes the metal cutting groove and the through hole.

[0013] The photoresist layer and the pattern definition layer are etched sequentially using each photomask to form a semiconductor structure.

[0014] In one exemplary embodiment, the method further includes:

[0015] At least one of the metal cutting grooves and at least one of the through holes are disposed on the same photomask; the etching positions corresponding to the metal cutting grooves and the through holes on the same photomask are different;

[0016] The target number of the photomask is determined based on the first number of the metal cutting grooves and the second number of the through holes.

[0017] In an exemplary embodiment, the photomask corresponding to the metal-cut trenches and vias is used to sequentially etch the photoresist layer and the pattern definition layer to form a semiconductor structure, including:

[0018] The photoresist layer is etched using the same photomask corresponding to the metal cutting grooves and through holes to form initial grooves on the photoresist layer.

[0019] The corresponding position of the initial trench is further etched on the pattern definition layer, and the etching depth is less than the thickness of the pattern definition layer;

[0020] Remove the photoresist layer, and continue etching the initial trench on the size shrinkage layer until the hard mask layer is reached to form the target trench;

[0021] The semiconductor structure is formed based on the target trench.

[0022] In an exemplary embodiment, forming the semiconductor structure based on the target trench includes:

[0023] A thin film layer is formed by filling material on the remaining pattern definition layer and in the target trench; the target trench includes a first target trench corresponding to the metal cutting trench and a second target trench corresponding to the through hole, the size of the first target trench is larger than the size of the second target trench; a cavity is formed at the bottom of the second target trench; the remaining pattern definition layer is a pattern definition layer after etching based on the initial trench;

[0024] The thin film layer, the remaining pattern definition layer and the size shrinkage layer are etched using a full-coverage etching process until the voids corresponding to the vias are exposed, forming the remaining size shrinkage layer and the remaining thin film layer.

[0025] The substrate is etched along the cavity based on the preset size of the via to form the semiconductor structure.

[0026] In an exemplary embodiment, etching the substrate along the cavity based on the preset size of the via to form the semiconductor structure includes:

[0027] The substrate is etched along the cavity based on the preset size of the through hole to form the through hole;

[0028] Etching removes the remaining dimensional shrinkage layer;

[0029] Using the hard mask layer and the remaining thin film layer as a barrier layer, the initial trench corresponding to the metal cutting trench is etched to form the metal cutting trench.

[0030] The semiconductor structure is formed based on the metal cutting trenches.

[0031] In an exemplary embodiment, forming the semiconductor structure based on the metal-cut trench includes:

[0032] Etching removes part of the remaining thin film layer, forming a residual thin film layer between the hard mask layers;

[0033] The hard mask layer is removed by etching;

[0034] A metal material is deposited on the substrate, in the metal cutting grooves, and in the through-holes to form an initial metal layer;

[0035] The initial metal layer is planarized to form the semiconductor structure.

[0036] In one exemplary embodiment, the method further includes:

[0037] A dielectric layer is formed on the bottom metal layer;

[0038] A transition layer is formed on the dielectric layer to form the substrate;

[0039] Wherein, the etching stop layer of the through hole is the dielectric layer, and the etching stop layer of the metal cutting trench is part of the dielectric layer.

[0040] In an exemplary embodiment, planarizing the initial metal layer to form the semiconductor structure includes:

[0041] The initial metal layer is planarized using a chemical mechanical polishing process until the dielectric layer is exposed, thus forming the semiconductor structure.

[0042] In one exemplary embodiment, the thickness of the size shrinkage layer is determined based on the size of the through-hole.

[0043] In an exemplary embodiment, the photoresist layer includes at least one of a spin-coated carbon layer, a silicon-containing anti-reflective coating, and a photoresist layer.

[0044] According to a second aspect of the embodiments of this application, a semiconductor structure is provided, which is prepared by the method described above.

[0045] According to a third aspect of the embodiments of this application, an electronic device is provided, the device including the semiconductor structure described above.

[0046] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0047] This invention forms a size reduction layer in the hard mask layer and the metal trench after forming a metal trench on the hard mask layer. This increases the aspect ratio difference between the metal trench and the via in subsequent processes, making it easier to determine the photomask corresponding to the metal cutting trench and the via. Since the metal cutting trench is formed after the metal trench is formed, the process window of this invention is increased, which can avoid the formation of metal wire adhesion or breakage in the metal cutting trench, thereby improving the yield of semiconductor products. Attached Figure Description

[0048] To more clearly illustrate the technical solution of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figures 1 to 6 This is a schematic diagram of the formation process of a semiconductor structure provided by existing technology;

[0050] Figure 7 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0051] Figures 8 to 19 This is a top view and a cross-sectional structural diagram of the formation process of a semiconductor structure provided in an embodiment of the present invention;

[0052] The corresponding reference numerals in the figure are:

[0053] Metal stack layer 01, CA trench 02, CB trench 03, gate sidewall 04, CB barrier layer 05, bottom metal layer 06, dielectric layer 07, transition layer 08, hard mask layer 09, pattern definition layer 10, silicon layer 11, CA barrier layer 12, size shrinkage layer 13, photoresist layer 14, metal trench 15, metal dicing trench 16, via 17, initial trench 18, target trench 19, thin film layer 20, void 21, metal layer 22. Detailed Implementation

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] As used herein, "an embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that spatial relative terms, such as "below," "under," "lower part," "above," "upper part," "front," "back," "above," and the like, are used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element(s). These are used only for the convenience of describing this application and for simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as limiting this application. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein can be interpreted similarly.

[0056] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0058] As process nodes continue to advance, metal wire pitch becomes smaller and smaller, often requiring multiple exposures and developments, and increasingly employing metal cut processes to achieve extremely small pitches.

[0059] The problems with existing metal cutting processes will now be explained in detail with reference to the accompanying drawings.

[0060] like Figure 1-2 As shown, Figures 1 to 2 This is a schematic diagram of the semiconductor structure formation process corresponding to existing metal cutting technology;

[0061] like Figure 1 As shown in Figure A and Figure a, Figure 1 Figure a is Figure 1 The cross-sectional view along the dashed line MN in Figure A shows the CA groove 02 etched on the metal deposit layer 01;

[0062] like Figure 1 As shown in Figure B and Figure b, Figure 1 Figure b is Figure 1 The cross-sectional view along the dashed line MN in Figure B shows that the CB groove 03 is formed by etching the protrusion of the metal deposit layer 01 using a metal cutting process.

[0063] like Figure 1 As shown in Figure D and Figure d, Figure 1 The middle d figure is Figure 1 The cross-sectional view along the dashed line MN in Figure D shows that the metal deposit layer 01 is etched once or repeatedly using a metal cutting process to form CB grooves 03 with different structures.

[0064] like Figure 2 As shown in Figure A and Figure a, Figure 2 Figure a is Figure 2In the cross-sectional view along the dashed line EF in Figure A, a gate sidewall (spacer) 04 is formed at the edge of the protrusion of the metal stack layer 01, and a CB barrier layer 05 is formed by filling material in the CB groove 03; wherein, the filling material of the gate sidewall 04 and the CB barrier layer 05 is the same. The dashed line EF and the dashed line MN can be located on the same straight line;

[0065] like Figure 2 As shown in Figure B and Figure b, Figure 2 Figure b is Figure 2 Figure B shows a cross-sectional view along the dashed line EF, where the protrusions of the metal deposit layer 01 located between the gate sidewalls 04 are etched away.

[0066] like Figure 3 As shown, Figure 3 for Figure 1 , Figure 2 The transition structure between them; wherein, a dielectric layer 07, a transition layer 08, a hard mask layer 09 and a pattern definition layer 10 can be formed sequentially on the bottom metal layer 06;

[0067] A silicon layer 11 is formed on the pattern definition layer 10. Then, a gate sidewall 04 is formed on the outer surface of the silicon layer using ALD (atomic layer deposition) technology. A CA barrier layer 12 is formed in the trench formed between the silicon layers 11, and a CB barrier layer 05 is formed in the side trench. The CB barrier layer 05 is made of the same material as the gate sidewall 04. ALD is a technology that uses vapor deposition to deposit various thin film materials. It has highly controllable deposition parameters and excellent deposition uniformity, and therefore has broad application potential in the fields of micro-nano electronics and nanomaterials.

[0068] Etching removal using an etch-back process Figure 3 The silicon layer 11 and part of the CA barrier layer 12 can be obtained. Figures 4-6 The schematic diagram of the semiconductor structure of lines A and B is shown. There are spacer lines between lines A and B, and the corresponding areas of lines A and B are set at intervals. Figure 4 This is a diagram of a semiconductor structure formed by normal etching. Figure 5 This is a diagram of the semiconductor structure formed by transition cutting. Figure 6 This is a diagram of a semiconductor structure formed by partial cutting and missing parts. Finally, the trenches corresponding to each metal line are filled with copper to form the metal lines.

[0069] Because metal cutting processes utilize different exposure and development methods to form metal lines, multiple processes are often required to create the cut. Subsequent processes can affect the already formed metal cutting grooves, resulting in a smaller process window. If the CA barrier layer 12 and CB barrier layer 05 are excessively consumed by subsequent processes (cut missing), this can lead to... Figure 6The structure shown will form if the CA barrier layer 12 and CB barrier layer 05 are not fully consumed (overcut) by subsequent processes. Figure 5 The structure shown.

[0070] like Figure 4 As shown, Figure 4 The remaining part of the CA blocking layer 12 in the trench corresponding to the middle part of line A, and the CB blocking layer 05 are retained;

[0071] like Figure 5 As shown, Figure 5 This is a schematic diagram of a semiconductor structure with A-line and B-line; in which, part of the silicon layer 11 on the side of the gate sidewall 04 is not completely etched, leaving residue, resulting in insufficient etching. When the pattern is passed down, the cutting is too severe. Because the A-line is too wide, it will also cut the B-line, causing the B-line to break.

[0072] like Figure 6 As shown, Figure 6 This is a schematic diagram of a semiconductor structure with A-line and B-line; the CA barrier layer 12 and CB barrier layer 05 are over-consumed and have no barrier, which causes the A-line and B-line to be unable to be cut apart when filling with metal, forming a single line.

[0073] Therefore, existing metal cutting processes cannot guarantee the product qualification rate of the two types of metal wires due to the small process window; and in the existing technology, different photomasks are used for metal cutting and through holes, resulting in a large number of photomasks being used.

[0074] Based on this, embodiments of this application provide a semiconductor structure and a method for forming the same, in order to solve the aforementioned problems existing in the prior art.

[0075] Figure 7 This is a method for forming a semiconductor structure according to an exemplary embodiment, such as... Figure 8-19 As shown, Figures 8 to 19 This is a cross-sectional structural schematic diagram of the formation process of a semiconductor structure provided in an embodiment of the present invention; the method includes:

[0076] S1: Form a hard mask layer on the substrate;

[0077] like Figure 8 As shown, Figure 8 Figure A is Figure 8 Figure a is a sectional view along the dashed line; as shown in Figure a. Figure 8 As shown, the method for forming the substrate may include: forming a dielectric layer 07 on a bottom metal layer 06; forming a transition layer 08 on the dielectric layer 07 to form the substrate.

[0078] In the embodiments of this specification, the dielectric layer 07 can be a low-k dielectric layer 07, which can be formed on the bottom metal layer 06; then a transition layer 08 is formed on the dielectric layer 07, thereby forming a substrate based on the bottom metal layer 06, the dielectric layer 07, and the transition layer 08. The material of the dielectric layer 07 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride; wherein, the material of the transition layer 08 can include at least one of silicon oxynitride (SiON) and silicon oxycarbonate (SiOC).

[0079] Continue as Figure 8 As shown, a hard mask layer 09 is formed on the substrate. The material of the hard mask layer 09 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride.

[0080] S2: Form metal trenches corresponding to the metal lines on the hard mask layer;

[0081] Continue as Figure 8 As shown, metal trenches 15 corresponding to the metal lines are formed on the hard mask layer 09. The metal trenches 15 corresponding to the metal lines can include metal trenches 15 corresponding to metal lines A and B respectively. The pattern definition layer 10, the hard mask layer 09, and the transition layer 08 together constitute the pattern transfer layer, and the etching pattern is transferred from top to bottom through the pattern transfer layer.

[0082] S3: Fill the hard mask layer and the metal trench with carbon-oxygen-silicon material to form a size shrinkage layer;

[0083] Continue as Figure 8 As shown, a silicon carbide material is filled on the hard mask layer 09 and in the metal trench 15 to form a size shrinkage layer 13. The size shrinkage layer 13 can be made of silicon carbide material or silicon carbide material that has undergone high-temperature treatment to increase the density of the size shrinkage layer 13; for example, the thickness of the size shrinkage layer 13 is 1000-2000 angstroms.

[0084] like Figure 9 As shown, the method further includes:

[0085] At least one metal cutting groove 16 and at least one through hole 17 are disposed on the same photomask; the etching positions of the metal cutting groove 16 and the through hole 17 on the same photomask are different.

[0086] The target number of the photomask is determined based on the first number of the metal cutting grooves 16 and the second number of the through holes 17.

[0087] In the embodiments of this specification, at least one metal cutting groove 16 and at least one through hole 17 can be grouped together; for example, one metal cutting groove 16 and one through hole 17 can be grouped together; if the number of metal cutting grooves 16 and the number of through holes 17 are the same, each photomask can be configured to include a pattern corresponding to the metal cutting groove 16 and the through hole 17. For example, two metal cutting grooves 16 and three through holes 17 need to be etched. The two metal cutting grooves 16 include a first metal cutting groove 16 and a second metal cutting groove 16, and the three through holes 17 include a first through hole 17, a second through hole 17, and a third through hole 17; wherein, the first through hole 17 corresponds to the position of the first metal cutting groove 16, that is, their projections on the substrate at least partially overlap, and the second through hole 17 corresponds to the second metal cutting groove 16; according to the prior art, two metal cutting grooves 16 require two photomasks, and three through holes 17 require three photomasks; a total of five photomasks are required; Figure 9 This is a schematic diagram of a photomask structure provided by an embodiment of the present invention; the first through hole 17 and the second metal cutting groove 16 can be set on the same photomask, and the remaining third through hole 17 can be set on a separate photomask. It can be seen that the solution of this embodiment only requires three photomasks; compared with the prior art, this embodiment reduces the number of photomasks used.

[0088] like Figure 10 As shown, the thickness of the shrinkage layer 13 is determined based on the size of the through-hole 17. The through-hole 17 is typically an inverted trapezoidal structure, with a larger upper dimension and a smaller lower dimension; for example, if the upper dimension of the through-hole 17 is 50 angstroms and the lower dimension is 20 angstroms, and the upper dimension needs to be shrunk from 50 angstroms to 40 angstroms, the thickness of the shrinkage layer is 1000 angstroms; if the upper dimension needs to be shrunk from 50 angstroms to 30 angstroms, the thickness of the shrinkage layer is 1500 angstroms; and if the upper dimension needs to be shrunk from 50 angstroms to 20 angstroms, the thickness of the shrinkage layer is 2000 angstroms.

[0089] like Figure 10 As shown, by setting the size shrinkage layer 13, the difference in aspect ratio between the metal trench 15 and the via 17 in subsequent processes can be improved, that is, the aspect ratio of the via 17 can be improved, thereby facilitating the formation of voids in the middle and bottom of the via 17 during thin film deposition.

[0090] S4: A pattern definition layer and a photoresist layer are sequentially formed on the size shrinkage layer;

[0091] like Figure 10As shown, a pattern definition layer 10 and a photoresist layer 14 are sequentially formed on the size shrinkage layer 13. The material of the pattern definition layer 10 can be silicon or silicon oxide; for example, the material of the pattern definition layer 10 can be silicon oxide or amorphous silicon. The photoresist layer 14 includes at least one of a spin-on-carbon layer (SOC), a silicon-containing anti-reflective coating (SiARC), and a photoresist layer (PR). For example, the photoresist layer 14 may include a spin-on-carbon layer, a silicon-containing anti-reflective coating, and a photoresist layer stacked sequentially.

[0092] S5: Based on the photomask corresponding to the metal cutting trench and the via, the photoresist layer and the pattern definition layer are etched sequentially to form a semiconductor structure; the metal cutting trench is used to form a metal layer, and the via is used to connect adjacent metal layers.

[0093] In this embodiment of the specification, the step of etching the photoresist layer and the pattern definition layer sequentially using a photomask corresponding to the metal-cut trenches and vias to form a semiconductor structure includes:

[0094] like Figure 10 As shown, Figure 10 Figure A is Figure 10 Figure a shows a cross-sectional view along the dotted line; based on the positional relationship between the metal cutting groove 16 and the through hole 17, the metal cutting groove 16 and the through hole 17 are grouped, and multiple photomasks are fabricated according to the grouping results; at least one of the multiple photomasks includes the metal cutting groove 16 and the through hole 17.

[0095] The photoresist layer 14 and the pattern definition layer 10 are etched sequentially using each photomask to form a semiconductor structure.

[0096] In the embodiments of this specification, the metal cutting groove 16 and the through hole 17 can be grouped according to the positional relationship between them, and the metal cutting groove 16 and the through hole 17 located at different positions can be grouped together; for example, the metal cutting groove 16 and the through hole 17 located at diagonal positions can be grouped together and set on the same photomask.

[0097] Continue as Figure 10As shown, the photoresist layer 14 is etched using the same photomask corresponding to the metal cutting groove 16 and the through hole 17, forming the initial trench 18 corresponding to the metal cutting groove 16 and the through hole 17 on the photoresist layer 14; the initial trench 18 includes a first trench corresponding to the metal cutting groove 16 and a second trench corresponding to the through hole 17. Since the size of the metal cutting groove 16 is larger than the size of the through hole 17, the size of the first trench is larger than the size of the second trench; wherein, the etching process of the trench can be a photolithography process (ETCH).

[0098] like Figure 11 As shown, Figure 11 Figure A is Figure 11 Figure a shows a cross-sectional view along the dashed line; etching is continued at the corresponding positions of the initial trench 18 on the pattern definition layer 10, with the etching depth less than the thickness of the pattern definition layer 10, and the photoresist layer 14 is removed to obtain... Figure 12 The structure shown is as follows: the initial trench 18 corresponds to the metal cutting trench 16 and the through hole 17; the initial trench 18 includes a first trench corresponding to the metal cutting trench 16 and a second trench corresponding to the through hole 17, wherein the size of the first trench is larger than the size of the second trench. After etching the initial trench 18, etching can continue downward along the shape of the initial trench 18, and the etching depth of the pattern definition layer 10 can be controlled to be less than the thickness of the pattern definition layer 10.

[0099] like Figure 12 As shown, Figure 12 Figure A is Figure 12 Figure a shows a cross-sectional view along the dashed line; the initial trench 18 is etched further on the dimensional shrinkage layer 13 until the hard mask layer 09 is reached, forming the target trench 19; then the semiconductor structure is formed based on the target trench 19. For example, etching continues downwards based on the pattern on the pattern definition layer 10 until the upper surface of the hard mask layer 09 is reached, thereby forming the target trench 19. This ensures the precise downward transfer of the etched patterns corresponding to the metal cut trench 16 and the via 17, facilitating further etching to form the metal cut trench 16 and the via 17. The etching stop layer for the via 17 is the dielectric layer 07 of the substrate, and the etching stop layer for the metal cut trench 16 is a portion of the dielectric layer 07.

[0100] In some embodiments, forming the semiconductor structure based on the target trench 19 includes:

[0101] like Figure 13 As shown, Figure 13 Figure A is Figure 13 Figure a is a sectional view along the dashed line; as shown in Figure a. Figure 13As shown, a thin film layer 20 is formed on the remaining pattern definition layer 10 and in the target trench 19 by filling material. The target trench 19 includes a first target trench 19 corresponding to the metal cutting trench 16 and a second target trench 19 corresponding to the via 17. The size of the first target trench 19 is larger than that of the second target trench 19. A cavity 21 is formed at the bottom of the second target trench 19. The remaining pattern definition layer 10 is the pattern definition layer 10 after etching based on the initial trench 18. Since the aspect ratios of the metal cutting trench 16 and the via 17 differ significantly, with the via having a larger aspect ratio, insufficient filling may occur at the bottom of the via 17 during the formation of the thin film layer 20, resulting in a cavity 21 at the bottom of the second target trench 19 corresponding to the via 17. This reduces the subsequent etching process of the via 17 and provides reference information for the next etching step.

[0102] like Figure 14 As shown, Figure 14 Figure A is Figure 14 Figure a is a sectional view along the dashed line; as shown in Figure a. Figure 14 As shown, a full-coverage etching process is used to etch the thin film layer 20, the remaining pattern definition layer 10, and the size shrinkage layer 13 until the cavity 21 corresponding to the via 17 is exposed, forming the remaining size shrinkage layer 13 and the remaining thin film layer 20; then, based on the preset size of the via 17, the substrate is etched along the cavity 21 to form the semiconductor structure.

[0103] In the embodiments of this specification, a full-coverage etching process can be used to etch the thin film layer 20, the remaining pattern definition layer 10, and the size shrinkage layer 13 until the void 21 corresponding to the via 17 is exposed, at which point etching stops. The size shrinkage layer 13 at the end of the current etching process is designated as the remaining size shrinkage layer 13, and the thin film layer 20 at the end of the current etching process is designated as the remaining thin film layer 20. The preset size of the via 17 may include the etching depth of the via 17. The substrate can be etched based on the void 21 to form the semiconductor structure. During the full-coverage etching process, the void 21 serves as reference information for the end of etching, ensuring etching accuracy.

[0104] In some embodiments, etching the substrate along the cavity 21 based on the preset size of the via 17 to form the semiconductor structure includes:

[0105] like Figure 15 As shown, Figure 15 Figure A is Figure 15 Figure a is a sectional view along the dashed line; as shown in Figure a. Figure 15As shown, the substrate is etched along the cavity 21 based on the preset size of the through hole 17 to form the through hole 17;

[0106] For example, the substrate includes a bottom metal layer 06, a dielectric layer 07, and a transition layer 08 in sequence, such as Figure 15 As shown, the substrate is etched along the cavity 21 down to a portion of the dielectric layer 07 to form the via 17; the etching depth of the dielectric layer 07 is less than the thickness of the dielectric layer 07. Figure 17 As shown, etching of the dielectric layer 07 continues until it reaches the upper surface of the bottom metal layer 06, forming a through hole 17. For the metal cutting groove 16, the etching stop layer is a part of the dielectric layer 07. The depth of the metal cutting groove 16 is less than the depth of the through hole 17, and the width of the metal cutting groove 16 is greater than the width of the through hole 17.

[0107] In the embodiments of this specification, through-hole 17 can be formed by further etching based on the hole 21, and the remaining size shrinkage layer 13 can be removed by etching; then, the hard mask layer 09 and the remaining thin film layer 20 are used as a barrier layer to continue etching the initial groove 18 corresponding to the metal cutting groove 16 to form the metal cutting groove 16. Thus, through-hole 17 and metal cutting groove 16 can be formed simultaneously with a single photomask, reducing the number of photomasks used in the etching process.

[0108] like Figure 16 As shown, Figure 16 Figure A is Figure 16 Figure a is a sectional view along the dashed line; as shown in Figure a. Figure 16 As shown, the remaining size shrinkage layer 13 is etched away; specifically, the remaining size shrinkage layer 13 can be etched away using an ashing process.

[0109] like Figure 17 As shown, Figure 17 Figure A is Figure 17 Figure a is a sectional view along the dashed line; as shown in Figure a. Figure 17 As shown, the hard mask layer 09 and the remaining thin film layer 20 are used as barrier layers to continue etching the initial trench 18 corresponding to the metal cutting trench 16 to form the metal cutting trench 16; and then the semiconductor structure is formed based on the metal cutting trench 16.

[0110] In some embodiments, forming the semiconductor structure based on the metal-cut trench 16 includes:

[0111] like Figure 18 As shown, Figure 18 Figure A is Figure 18 Figure a is a cross-sectional view along the horizontal direction; as shown. Figure 18 As shown, etching removes Figure 17 The remaining thin film layer 20 is formed between the hard mask layers 09; the hard mask layers 09 are etched away; metal material is deposited on the substrate, in the metal cutting trenches 16 and the vias 17 to form an initial metal layer 22; the initial metal layer 22 is planarized to form the semiconductor structure.

[0112] In some embodiments, after forming the via 17 and the metal cutting trench 16, metal material can be deposited on the substrate, in the metal cutting trench 16 and the via 17 to form an initial metal layer 22; then the initial metal layer 22 is planarized to form the semiconductor structure.

[0113] In some embodiments, planarizing the initial metal layer 22 to form the semiconductor structure includes:

[0114] like Figure 19 As shown, Figure 19 Figure A is Figure 19 Figure a is a sectional view along the dashed line; as shown in Figure a. Figure 19 As shown, the initial metal layer 22 is planarized using a chemical mechanical polishing process until the dielectric layer 07 is exposed, thus forming the semiconductor structure.

[0115] In the embodiments of this specification, chemical mechanical polishing (CMP) can be used to planarize the initial metal layer 22 until the dielectric layer 07 is exposed to form the semiconductor structure.

[0116] In this embodiment, after forming metal trenches on a hard mask layer, a size reduction layer is formed in both the hard mask layer and the metal trenches to improve the aspect ratio difference between the metal trenches and vias in subsequent processes. This facilitates the determination of the photomasks corresponding to the metal cutting trenches and vias. Furthermore, since the metal cutting trenches are formed after the metal trenches themselves, the process of this invention increases the process window for the metal cutting trenches, which can prevent metal wire adhesion or breakage in the metal cutting trenches, thereby improving the yield of semiconductor products.

[0117] This embodiment also provides a semiconductor structure prepared using the method described above. The semiconductor structure obtained in this embodiment avoids the issues of metal wire adhesion or breakage in the metal cutting trenches, resulting in a high product yield.

[0118] This embodiment also provides an electronic device, which includes the semiconductor structure provided in this embodiment of the invention.

[0119] The electronic device in this embodiment can be a mobile phone, tablet computer, laptop computer, navigator, camera, camcorder, robot vacuum cleaner, virtual reality device, augmented reality device, or any intermediate product including the aforementioned semiconductor structure.

[0120] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0121] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A hard mask layer is formed on the substrate; Metal trenches corresponding to the metal lines are formed on the hard mask layer; A carbon-oxygen-silicon material is filled on the hard mask layer and in the metal trench to form a size shrinkage layer; A pattern definition layer and a photoresist layer are sequentially formed on the size shrinkage layer; The photoresist layer and the pattern definition layer are etched sequentially using photomasks corresponding to the metal cutting trenches and vias to form a semiconductor structure; the metal cutting trenches are used to form metal layers, and the vias are used to connect adjacent metal layers.

2. The method according to claim 1, characterized in that, The photomask, based on metal-cut trenches and vias, sequentially etches the photoresist layer and the pattern definition layer to form a semiconductor structure, including: Based on the positional relationship between the metal cutting groove and the through hole, the metal cutting groove and the through hole are grouped, and multiple photomasks are fabricated according to the grouping results; at least one of the multiple photomasks includes the metal cutting groove and the through hole. The photoresist layer and the pattern definition layer are etched sequentially using each photomask to form a semiconductor structure.

3. The method according to claim 2, characterized in that, The method further includes: At least one of the metal cutting grooves and at least one of the through holes are disposed on the same photomask; the etching positions corresponding to the metal cutting grooves and the through holes on the same photomask are different; The target number of the photomask is determined based on the first number of the metal cutting grooves and the second number of the through holes.

4. The method according to any one of claims 1-3, characterized in that, The photomask, based on metal-cut trenches and vias, sequentially etches the photoresist layer and the pattern definition layer to form a semiconductor structure, including: The photoresist layer is etched using the same photomask corresponding to the metal cutting grooves and through holes to form initial grooves on the photoresist layer. The corresponding position of the initial trench is further etched on the pattern definition layer, and the etching depth is less than the thickness of the pattern definition layer; Remove the photoresist layer, and continue etching the initial trench on the size shrinkage layer until the hard mask layer is reached to form the target trench; The semiconductor structure is formed based on the target trench.

5. The method according to claim 4, characterized in that, The process of forming the semiconductor structure based on the target trench includes: A thin film layer is formed by filling material on the remaining pattern definition layer and in the target trench; the target trench includes a first target trench corresponding to the metal cutting trench and a second target trench corresponding to the through hole, the size of the first target trench is larger than the size of the second target trench; a cavity is formed at the bottom of the second target trench; the remaining pattern definition layer is a pattern definition layer after etching based on the initial trench; The thin film layer, the remaining pattern definition layer and the size shrinkage layer are etched using a full-coverage etching process until the voids corresponding to the vias are exposed, forming the remaining size shrinkage layer and the remaining thin film layer. The substrate is etched along the cavity based on the preset size of the via to form the semiconductor structure.

6. The method according to claim 5, characterized in that, The process of etching the substrate along the cavity based on the preset size of the via to form the semiconductor structure includes: The substrate is etched along the cavity based on the preset size of the through hole to form the through hole; Etching removes the remaining dimensional shrinkage layer; Using the hard mask layer and the remaining thin film layer as a barrier layer, the initial trench corresponding to the metal cutting trench is etched to form the metal cutting trench. The semiconductor structure is formed based on the metal cutting trenches.

7. The method according to claim 6, characterized in that, The process of forming the semiconductor structure based on the metal-cut trench includes: Etching removes part of the remaining thin film layer, forming a residual thin film layer between the hard mask layers; The hard mask layer is removed by etching; A metal material is deposited on the substrate, in the metal cutting grooves, and in the through-holes to form an initial metal layer; The initial metal layer is planarized to form the semiconductor structure.

8. The method according to claim 7, characterized in that, The method further includes: A dielectric layer is formed on the bottom metal layer; A transition layer is formed on the dielectric layer to form the substrate; Wherein, the etching stop layer of the through hole is the dielectric layer, and the etching stop layer of the metal cutting trench is part of the dielectric layer.

9. The method according to claim 8, characterized in that, The planarization process of the initial metal layer to form the semiconductor structure includes: The initial metal layer is planarized using a chemical mechanical polishing process until the dielectric layer is exposed, thus forming the semiconductor structure.

10. The method according to claim 1, characterized in that, The thickness of the size shrinkage layer is determined based on the size of the through-hole.

11. The method according to claim 1, characterized in that, The photoresist layer includes at least one of spin-coated carbon layer, silicon-containing anti-reflective coating, and photoresist layer.

12. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method described in any one of claims 1-11.

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