Method of manufacturing a silicon-on-insulator substrate

Abstract

A method of manufacturing a silicon-on-insulator (SOI) substrate is provided. A method of forming an SOI substrate includes forming a first wafer structure on an upper surface of a first wafer having a notch and a wafer identification (ID). The first wafer structure includes an etch stop layer, a semiconductor layer, a buried insulating layer, and a first bonding insulating layer formed sequentially. An edge of the first wafer structure can be trimmed to form a trimmed region. Residual trimming byproducts on the first bonding insulating layer of the first wafer structure can be removed. The first wafer structure can be bonded to a second wafer structure. The semiconductor layer of the first wafer structure can be transferred onto the second wafer structure. The trimmed region can have a width greater than a recess length of the notch and a depth greater than a depth of the wafer ID.

Description

[0001] Cross-references to related applications This application claims priority to Korean Patent Application No. 10-2025-0020913, filed on February 18, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to semiconductor manufacturing technology, and more specifically, to a method for manufacturing a silicon-on-insulator (SOI) substrate having a semiconductor layer of uniform thickness. Background Technology

[0003] Semiconductor memory devices, such as dynamic random access memory (DRAM) devices, may require high integration density while meeting high operating speed characteristics.

[0004] To improve the integration density of current DRAM devices, techniques using vertical-channel transistors (VCTs) as cell switching elements have been proposed. VCTs may need to be formed on an SOI substrate with a semiconductor layer of uniform thickness to ensure uniform memory cell characteristics and complete isolation between adjacent VCTs. The SOI substrate can be formed by bonding a carrier wafer and a donor wafer, which include the semiconductor layer. Therefore, the uniformity of the semiconductor layer can be affected by the bonding characteristics between the donor wafer and the carrier wafer. Summary of the Invention

[0005] An exemplary embodiment provides a method for manufacturing an SOI substrate with improved bonding properties.

[0006] According to an exemplary embodiment, a method for manufacturing an SOI substrate can be provided. In the method for manufacturing an SOI substrate, an etch stop layer, a semiconductor layer, a buried insulating layer, and a first bonding insulating layer can be sequentially formed on the upper surface of a first wafer to form a first wafer structure, wherein the first wafer includes a notch formed at the edge of the first wafer and a wafer identifier (ID). The edge of the first wafer structure can be trimmed to form a trimmed region. Residual trimmed byproducts on the first bonding insulating layer of the first wafer structure can then be removed. The first wafer structure can be bonded to a second wafer structure. The semiconductor layer of the first wafer structure can be transferred to the second wafer structure. The width of the trimmed region can be greater than the recess length of the notch and the length of the wafer ID. The depth of the trimmed region can be greater than the depth of the wafer ID.

[0007] According to an exemplary embodiment, a method for manufacturing an SOI substrate can be provided. In the method for manufacturing an SOI substrate, an etch stop layer, a semiconductor layer, a buried insulating layer, and a first bonding insulating layer can be sequentially formed on a first wafer to form a first wafer structure. The first wafer has a notch formed on its edge and a wafer identification ID. The edge of the first wafer structure can be removed so that the notch and wafer ID can be removed, thereby forming a trimming region. Residual trimming byproducts of the first bonding insulating layer of the first wafer structure can be removed. A second bonding insulating layer can be formed on a second wafer to form a second wafer structure. The first wafer structure and the second wafer structure can be bonded to each other so that the first bonding insulating layer and the second bonding insulating layer can face each other. The first wafer of the first wafer structure and the etch stop layer can then be removed.

[0008] In some embodiments, the trimming region may have a width of about 2.1 mm to about 2.3 mm. The trimming region may have a depth of about 75 μm to about 85 μm from the first bonding insulating layer to the interior of the first wafer.

[0009] In some embodiments, removing the edge of the first wafer structure may include: irradiating the upper surface of the first wafer structure with a laser beam to form a modification region; and applying a shearing force to the modification region along the thickness direction of the first wafer structure to remove the edge of the first wafer structure.

[0010] In some embodiments, removing trimming byproducts may include: chemically mechanically polishing (CMP) a portion of the thickness of the first bonding insulating layer of the first wafer structure; and cleaning CMP byproducts generated during CMP.

[0011] In some embodiments, CMP is performed using a slurry containing abrasive particles, the abrasive particles comprising at least one of the following metal oxides: silicon dioxide, cerium dioxide, zirconium oxide, aluminum oxide, titanium dioxide, barium titanate, germanium, manganese, and magnesium oxide.

[0012] In some embodiments, a cleaning solution comprising at least one of the following can be used to clean CMP byproducts: a mixture of sulfuric acid peroxides (SPM), hydrogen fluoride (HF), and an SC1 solution (NH4OH:H2O2:H2O = 1:1:5).

[0013] According to an exemplary embodiment, during the edge trimming operation of the first wafer structure, the notches and wafer IDs of the wafer can be removed through the trimming area. Therefore, trimming byproducts can be prevented from getting stuck in the notches and recesses of the wafer IDs, thereby improving poor bonding. Attached Figure Description

[0014] The foregoing and other aspects, features, and advantages of the subject matter of this disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a flowchart illustrating a method for manufacturing an SOI substrate according to an embodiment of the present disclosure; Figure 2 This is a flowchart illustrating a method for forming a first wafer structure according to an embodiment of the present disclosure; Figures 3A to 3C This is a cross-sectional view illustrating each process of a method for forming a first wafer structure according to an embodiment of the present disclosure; Figure 4 This is a perspective view illustrating a wafer fabrication apparatus according to an embodiment of the present disclosure; Figure 5 It is an embodiment of the present disclosure. Figure 4 A magnified planar view of the wafer section marked "A"; Figure 6 This is a cross-sectional view showing a first wafer structure with edge trimming according to an embodiment of the present disclosure; Figure 7 This is a flowchart illustrating an edge trimming process according to an embodiment of the present disclosure; and Figure 8 This is a flowchart illustrating the removal of trimming byproducts according to an embodiment of the present disclosure. Detailed Implementation

[0015] The advantages and features of the invention, as well as the methods of achieving these advantages and features, will become apparent when the embodiments are described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments disclosed herein, but will be practiced in many different forms, and these embodiments are provided merely to make the disclosure of the invention more complete and to give those skilled in the art a full understanding of the scope of the invention, which is defined by the scope of the claims. For clarity, the dimensions and relative sizes of layers and regions in the drawings may be enlarged. Throughout the specification, the same reference numerals denote the same parts.

[0016] refer to Figure 1 SOI substrates can be manufactured by the following steps: forming a first wafer structure including a semiconductor layer (S10), trimming the edges of the first wafer structure (S20), removing trimming byproducts on the first wafer structure (S30), bonding the first wafer structure to a second wafer structure (S40), and transferring the semiconductor layer of the first wafer structure to the second wafer structure (S50).

[0017] More specifically, see reference Figure 1 , Figure 2 and Figure 3A Forming the first wafer structure (S10) may include forming an etch stop layer 110 on the first wafer 100 (S11).

[0018] The first wafer 100 may include opposing first surfaces 100a and second surfaces 100b. For example, the first surface 100a may be the upper surface of the first wafer 100. The first wafer 100 may be a donor wafer to be removed. The first wafer 100 may include at least one material selected from: silicon (Si), germanium (Ge), silicon carbide (SiC), group IV-IV, III-V or II-VI semiconductor compounds, and piezoelectric materials (e.g., lithium niobate (LiNbO3), lithium tantalate (LiTaO3), etc.).

[0019] An etch stop layer 110 may be formed on a first surface 100a of the first wafer 100 to prevent loss of subsequently formed semiconductor layers. The etch stop layer 110 may include materials that have etch selectivity for both the first wafer 100 and the subsequently formed semiconductor layers.

[0020] In an exemplary embodiment, when the first wafer 100 may include a Si material, the etch stop layer 110 may include a silicon-germanium (SiGe) material. The etch stop layer 110 comprising the SiGe material can be formed by an epitaxial growth process. The etch stop layer 110 can be appropriately selected according to the thickness of the subsequently formed semiconductor layer.

[0021] refer to Figure 1 , Figure 2 and Figure 3B Forming the first wafer structure (S10) may include forming a semiconductor layer 120 on the etch stop layer 110 (S13). In an exemplary embodiment, the semiconductor layer 120 may include a region in which channels for transistors included in a semiconductor memory device may be formed. The semiconductor layer 120 may include, for example, a single-crystal Si material.

[0022] For example, an epitaxial growth process can be used to form the semiconductor layer 120. The etch stop layer 110 and the semiconductor layer 120 can be formed in an in-situ process using vacuum interruption. For example, the semiconductor layer 120 can be formed to have a thickness of about 5 nm to about 500 nm, but is not limited thereto.

[0023] refer to Figure 1 , Figure 2 and Figure 3C Forming the first wafer structure (S10) may include forming a buried insulating layer 130 on the semiconductor layer 120 (S15). The buried insulating layer 130 may include, for example, a SiO2 material. However, the material of the buried insulating layer 130 is not limited to SiO2.

[0024] refer to Figure 1 , Figure 2 and Figure 3C Forming the first wafer structure (S10) may include: forming a first bonding insulating layer 140 on the buried insulating layer 130 (S17).

[0025] For example, the first bonding insulating layer 140 may include at least one of silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon nitride (SiN). However, the first bonding insulating layer 140 is not limited to the above-mentioned materials, and may include various insulating layers having bonding properties. Thus, a first wafer structure ST1 can be formed.

[0026] Next, the edge trimming operation S20 of the first wafer structure ST1 can be performed in the wafer processing equipment.

[0027] Figure 4 This is a perspective view showing a wafer fabrication apparatus according to an exemplary embodiment. Figure 5 It is shown Figure 4 A magnified planar view of part of the "A" wafer. Figure 6 This is a cross-sectional view showing the edge trimming of a first wafer structure according to an exemplary embodiment, and Figure 7 This is a flowchart illustrating an edge trimming process according to an exemplary embodiment.

[0028] refer to Figure 1 , Figure 4 and Figure 7 The wafer processing equipment 300 may be, for example, a laser processing equipment. The wafer processing equipment 300 may include a support 310, a laser irradiation block 320, a control block 330, and a compression block (not shown).

[0029] The first wafer structure ST1 can be mounted on the support 310. In other words, the support 310 can support the first wafer structure ST1. For example, the first wafer structure ST1 can be mounted on the support 310 with the first bonding insulating layer 140 facing upwards.

[0030] The support 310 can be configured for horizontal, vertical, and rotary drive. The drive of the support 310 can be controlled by the control block 330.

[0031] The laser irradiation block 320 can irradiate a selected position of the first wafer structure ST1 with a laser beam LB to modify the selected position of the first wafer structure ST1. Figure 4 The reference numeral MR in the attached figure can indicate: the modification area, in which the characteristics of the first wafer structure ST1 can be modified by the laser beam LB.

[0032] The compression block can apply a shear force to the first wafer structure ST1 along the thickness (or depth) direction. Based on the shear force applied by the compression block, the edge of the first wafer structure ST1 along the modification region MR can be removed to form the trimmed (or trimmed) region T.

[0033] In an exemplary embodiment, the edge trimming operation (S20) may include: irradiating the first wafer structure ST1 with a laser beam LB pointing to a selected location of the first wafer structure ST1 to form a modified region MR (S21), as shown. Figure 7 As shown. The edge trimming operation (S20) may include removing the edge region along the modification region MR of the first wafer structure ST1 by applying an external force (e.g., a shear force applied by a compression block) (S23).

[0034] In this way, by removing the edge region of the first wafer structure ST1, a trimming region T can be formed on the edge of the first wafer structure ST1.

[0035] like Figure 5 As shown, the width W of the trimming region T can be greater than the recess length da of the notch N of the first wafer 100 and the length l1 of the wafer identifier (ID) 115. In an exemplary embodiment, when the recess length da of the notch N of the first wafer 100 can be between about 1.0 μm and about 1.5 μm and the length l1 of the wafer ID 115 can be between about 50 μm and about 100 μm, the width W of the trimming region T can be between about 2.1 mm and about 2.3 mm.

[0036] Furthermore, the depth D of the trimmed region T can be between approximately 75 μm and approximately 85 μm when measured relative to the depth of wafer ID 115. In other words, the trimmed region T can be located between approximately 75 μm and approximately 85 μm below the upper surface of wafer ID 115 (i.e., the first bonding insulating layer 140).

[0037] Traditionally, wafer edges can be chamfered. However, in these SOI substrate manufacturing processes, when wafer grinding processes are performed, particularly when the chamfered wafer edges may be ground into a knife-like shape (e.g., a knife edge), adverse effects can occur. Since knife edges can cause cracks in the wafer, wafer edge trimming processes can be suggested (or recommended, desired, etc.) to prevent the formation of knife edges.

[0038] Elsewhere on wafer 100, notches N and wafer ID 115 may be formed on the edge of the first wafer 100.

[0039] The notch N can have a recess length da extending inwards towards the wafer, and the direction of crystal growth of the first wafer 100 can be determined by the recess length da.

[0040] Wafer ID 115 may include information about the first wafer 100. For example, wafer ID 115 may indicate the wafer's manufacturing history, manufacturing conditions, and characteristics, including data on ingot lifting, slicing, and grinding. For example, wafer ID 115 may include letters, numbers, linear codes, or QR codes. In an exemplary embodiment, the letters, numbers, linear codes, or QR codes included in wafer ID 115 may include a dot matrix with a width of about 3 μm to about 5 μm and a depth of about 0.5 μm to about 1 μm. Wafer ID 115 may be formed by a laser marking method. Furthermore, the QR code may be an 8 x 32 dot matrix or a 16 x 16 dot matrix used to display data about the wafer and the product. Wafer ID 115 may be formed, for example, at a predetermined depth on a first surface 100a of the first wafer 100.

[0041] However, when the width of the trimmed area is less than the recess length da of notch N or the length l1 of wafer ID 115, or when the depth of the trimmed area is configured to expose the bottom portion of wafer ID 115 (e.g., the bottom portion marked by laser), trimming byproducts may be trapped in notch N and the recessed portion of wafer ID 115. Even with subsequent CMP and cleaning processes, trimming byproducts trapped in the recessed portion may not be easily removed. Trimming byproducts may be located (e.g., embedded, trapped) between the first wafer structure ST1 and the second wafer structure, resulting in poor bonding.

[0042] In an exemplary embodiment, the trimming region T may be formed with a width W greater than the recess length da of the notch N and the length l1 of the wafer ID115, and a depth D deeper than the bottom position of the wafer ID115, in order to prevent bonding failure as described above.

[0043] Therefore, when the trimmed (or trimmed) area T is formed, the notch N and wafer ID 115 can be removed, thereby eliminating the recesses in which trimming byproducts can be trapped.

[0044] Figure 8 This is a flowchart illustrating the removal of trimming byproducts according to an exemplary embodiment.

[0045] refer to Figure 8 Removing trimming byproducts on the first wafer structure ST1 (S30) may include chemically mechanically polishing (CMP) the surface of the first bonding insulating layer 140 of the first wafer structure ST1 to a certain (e.g., predetermined target) thickness (S31).

[0046] Due to the edge trimming S20 of the first wafer structure ST1, trimming byproducts can remain on the first bonding insulating layer 140. These trimming byproducts remaining on the surface of the first bonding insulating layer 140 may lead to subsequent bonding failures and may cause defects in the first bonding insulating layer 140.

[0047] Therefore, trimming byproducts and defective first bonded insulating layer 140 can be removed by performing a CMP process to reduce the structure to a predetermined thickness and remove trimming particles retained on the first wafer structure ST1. For example, the abrasive particles in the CMP polishing slurry during the CMP process may include at least one of the following metal oxides: silicon dioxide, cerium dioxide, zirconium oxide, aluminum oxide, titanium dioxide, barium titanate, germanium, manganese, and magnesium oxide. In an exemplary embodiment, the polishing slurry may be a material capable of achieving a zero-charge surface zeta potential using various cleaning materials. CMP performed on the first wafer structure ST1 may include a touch CMP method.

[0048] According to an embodiment, removing the trimming byproducts on the first wafer structure ST1 (S30) may further include: cleaning the CMP byproducts on the first wafer structure ST1 (S33). Cleaning the CMP byproducts (S33) may be performed using a cleaning solution containing at least one of the following: a sulfuric acid peroxide mixture (SPM), hydrogen fluoride (HF), and an SC1 solution (NH4OH:H2O2:H2O = 1:1:5 (ammonium hydroxide:hydrogen peroxide:water)).

[0049] Refer again Figure 1 Bonding the first wafer structure to the second wafer structure (S40) may include forming a second bonding insulating layer on the second wafer.

[0050] The second wafer may be a carrier substrate. For example, the second wafer may include at least one of Si, SiC, glass, sapphire, aluminum nitride (AlN), or other materials available in substrate form. The second bonding insulating layer may include a material capable of bonding with the first bonding insulating layer 140, such as an insulator having the same coefficient of thermal expansion as the first bonding insulating layer 140. In an exemplary embodiment, the second bonding insulating layer may include at least one of SiCN, SiO2, and silicon nitride (Si3N4), the same as the first bonding insulating layer 140.

[0051] Subsequently, bonding the first wafer structure ST1 to the second wafer structure may include: stacking the first wafer structure ST1 on the second wafer structure such that the first bonding insulating layer 140 of the first wafer structure ST1 and the second bonding insulating layer of the second wafer structure can face each other, and then bonding the first wafer structure ST1 to the second wafer structure.

[0052] Next, transferring the semiconductor layer 120 onto the second wafer structure (S50) may include sequentially removing the first wafer 100 and the edge stop layer 110 of the first wafer structure ST1. Therefore, the semiconductor layer 120 located on the first wafer structure ST1 can be transferred onto the second wafer structure to complete the SOI substrate.

[0053] According to embodiments of this disclosure, during edge trimming operations of the first wafer structure, the wafer notch and wafer ID can be removed through the trimming area. Therefore, trimming byproducts can be prevented from getting stuck in the notches and recesses of the wafer ID, thereby reducing poor bonding (or bonding barriers) and improving bonding.

[0054] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and those skilled in the art can make many modifications to the present invention within the scope of the technical concept of the present invention.

Claims

1. A method for manufacturing an SOI substrate, where SOI refers to silicon-on-insulator, the method comprising: A first wafer structure is formed by sequentially forming an etch stop layer, a semiconductor layer, a buried insulating layer and a first bonding insulating layer on the upper surface of a first wafer, wherein the first wafer includes a notch formed on the edge of the first wafer and a wafer ID, where ID refers to an identifier; The edges of the first wafer structure are trimmed to form a trimmed area; Residual trimming byproducts from removing the first bonded insulating layer from the first wafer structure; Bonding the first wafer structure to the second wafer structure; and The semiconductor layer of the first wafer structure is transferred to the second wafer structure. The width of the trimming area is greater than the recess length of the notch and the length of the wafer ID, and the depth of the trimming area is greater than the depth of the wafer ID.

2. The method of claim 1, wherein, The trimmed area has a width of 2.1 mm to 2.3 mm and a depth of 75 μm to 85 μm from the first bonding insulating layer to the interior of the first wafer.

3. The method of claim 1, wherein, Trimming the edges of the first wafer structure includes: A laser beam is directed onto the first wafer structure to form a modified region; and Remove the edges of the first wafer structure.

4. The method of claim 3, wherein, Removing the edge of the first wafer structure includes: removing the edge of the first wafer structure by applying a shearing force to the modified region along the thickness direction of the first wafer structure.

5. The method of claim 1, wherein, Removing the residual trimming byproducts includes: A portion of the thickness of the first bonding insulating layer of the first wafer structure is subjected to CMP (chemical mechanical polishing); and Clean the CMP byproducts generated during the CMP process.

6. The method of claim 5, wherein, The CMP includes a light-touch CMP process.

7. The method of claim 5, wherein, The CMP is performed using a slurry containing abrasive particles, the abrasive particles comprising at least one of the following metal oxides: silicon dioxide, cerium dioxide, zirconium oxide, aluminum oxide, titanium dioxide, barium titanate, germanium, manganese, and magnesium oxide.

8. The method of claim 5, wherein, The CMP byproducts are cleaned using a cleaning solution containing at least one of the following: SPM, HF, and SC1 solution (NH4OH:H2O2:H2O = 1:1:5), where SPM refers to a mixture of sulfuric acid peroxides and HF refers to hydrogen fluoride.

9. The method of claim 1, wherein, The second wafer structure includes a second wafer and a second bonding insulating layer formed on the second wafer.

10. The method of claim 9, wherein, Bonding the first wafer structure to the second wafer structure includes: stacking and bonding the first wafer structure to the second wafer structure such that the first bonding insulating layer faces the second bonding insulating layer.

11. The method of claim 1, wherein, Transferring the semiconductor layer onto the second wafer structure includes: sequentially removing the first wafer and the etch stop layer of the first wafer structure.

12. A method for manufacturing an SOI substrate, SOI referring to silicon-on-insulator, the method comprising: A first wafer structure is formed by sequentially forming an etch stop layer, a semiconductor layer, a buried insulating layer, and a first bonding insulating layer on the upper surface of a first wafer, wherein the first wafer includes: a notch formed on the edge of the first wafer and a wafer ID, where ID refers to an identifier; Remove the edge of the first wafer structure so that the notch and the wafer ID are removed to form a trimming area; Residual trimming byproducts from removing the first bonded insulating layer from the first wafer structure; A second bonding insulating layer is formed on the second wafer to form a second wafer structure; The first wafer structure is bonded to the second wafer structure such that the first bonding insulating layer and the second bonding insulating layer face each other; and Remove the first wafer and the etch stop layer from the first wafer structure.

13. The method of claim 12, wherein, The trimmed area has a width of 2.1 mm to 2.3 mm and a depth of 75 μm to 85 μm from the first bonding insulating layer to the interior of the first wafer.

14. The method of claim 12, wherein, Removing the edge of the first wafer structure includes: A laser beam is directed onto the first wafer structure to form a modified region; and Remove the edges of the first wafer structure.

15. The method of claim 14, wherein, Removing the edge of the first wafer structure includes: removing the edge of the first wafer structure by applying a shearing force to the modified region along the thickness direction of the first wafer structure.

16. The method of claim 12, wherein, Removing the residual trimming byproducts includes: A portion of the thickness of the first bonding insulating layer of the first wafer structure is subjected to CMP (chemical mechanical polishing); and Clean the CMP byproducts generated during the CMP process.

17. The method of claim 16, wherein, The CMP is performed using a slurry containing abrasive particles, the abrasive particles comprising at least one of the following metal oxides: silicon dioxide, cerium dioxide, zirconium oxide, aluminum oxide, titanium dioxide, barium titanate, germanium, manganese, and magnesium oxide.

18. The method of claim 16, wherein, The CMP byproducts are cleaned using a cleaning solution containing at least one of the following: SPM, HF, and SC1 solution (NH4OH:H2O2:H2O = 1:1:5), where SPM refers to a mixture of sulfuric acid peroxides and HF refers to hydrogen fluoride.

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