A patterning method suitable for semiconductor processing

Abstract

In a grain region of a layer formed on a support substrate, a pattern is generated by at least two passes performed in adjacent sub-portions of the grain region, each pass comprising a lithography step and an etching step. One or more parallel linear features of the pattern extend from a first sub-portion to a second sub-portion of the grain region, i.e. across a boundary between the grain regions. The mutually aligned and spaced apart first and second portions of the linear features are imprinted in the respective pass steps and transferred to the layer in the form of negative or positive pattern features in the patterned layer, i.e. in the form of trenches in the layer or in the form of lines separated by mutually aligned trenches. In either case, a directional etch is applied thereafter to stretch the aligned trenches and thus obtain the desired linear features extending from one sub-portion to another sub-portion of the grain region.

Description

Technical Field

[0001] This invention relates to semiconductor manufacturing processes, and more particularly to a patterning method for generating linear pattern features. Background Technology

[0002] Semiconductor manufacturing relies on advanced photolithography and etching techniques. Under certain conditions, such as to produce larger die sizes, chip manufacturers may be forced to etch two portions of the chip in separate exposure steps. One portion of the chip is exposed with one mask, and the other with a second mask. If these two portions include line features that intersect from one portion of the chip to the other, a stitching process is applied between the portions, which involves etching overlapping features in the transition area between the etched chip portions.

[0003] However, this technique suffers from errors in feature dimensions due to numerous factors, such as absorber reflection and the transition from absorber to black border. Therefore, sophisticated compensation strategies are applied during the design phase to mitigate these issues. However, these strategies increase design time, cost, and complexity. Summary of the Invention

[0004] This invention relates to a method according to the appended claims. According to the invention, the splicing between adjacent portions of a chip design is achieved by applying directional etching. A pattern is generated in a grain region of a layer formed on a support substrate by at least two processes performed in adjacent sub-portions of that grain region, each process including a photolithography step and an etching step. One or more parallel linear features of the pattern extend from a first sub-portion of the grain region to a second sub-portion, i.e., across the boundary between the grain regions. The mutually aligned and spaced-apart first and second portions of the line features are etched in corresponding process steps and transferred to the layer in the form of negative or positive pattern features in the patterned layer, i.e., in the form of trenches in the layer or in the form of lines separated by mutually aligned trenches. In either case, directional etching is subsequently applied to stretch the aligned trenches, thereby obtaining the desired line features extending from one sub-portion of the grain region to another.

[0005] This method enables the imprinting of adjacent portions of a pattern without overlapping pattern features, thereby avoiding most of the negative effects inherent in existing methods for splicing adjacent grain regions.

[0006] This invention specifically relates to a patterning method suitable for semiconductor manufacturing processes, the method comprising the following steps: - A layer is fabricated on a support substrate, which is patterned according to a predefined pattern in the semiconductor grain region of the layer. - The pattern is produced by at least two consecutive processes, each process including a photolithography step configured to imprint a portion of the pattern in a corresponding sub-region of a grain region, wherein the pattern includes one or more parallel linear features configured to extend from a first sub-region of the grain region to a second sub-region directly adjacent to the first sub-region. in: - The photolithographic exposure step for etching the first portion of the pattern is configured to etch the first portions of the one or more linear features. - The photolithographic exposure step for etching the second portion of the pattern is configured to etch the second portions of the one or more linear features. Its features are: - The second portions of the one or more linear features are aligned with and spaced apart from the first portions of the one or more linear features, such that after performing these two processes and after transferring the first and second portions of the pattern to the layer, the layer is patterned according to a pattern comprising at least a pair of mutually aligned grooves. - Directional etching is applied by scanning an etching beam in a scanning direction parallel to the aligned trenches, thereby merging the aligned trenches into a single trench.

[0007] According to one embodiment, the position of the groove in a direction perpendicular to the groove corresponds to the position of the line feature of the pattern.

[0008] According to one embodiment, the position of the groove in a direction perpendicular to the groove corresponds to the space between the line features of the pattern. Attached Figure Description

[0009] Figure 1 The main components of a tool suitable for directional etching are shown.

[0010] Figure 2a and 2b The process of directional etching is shown.

[0011] Figure 3a and 3b The image shows the grain region distribution on a process wafer and an enlarged image of a grain region applicable to the method according to the invention.

[0012] Figures 4a to 4d A method according to a first embodiment of the present invention is shown.

[0013] Figures 5a to 5d A method according to a second embodiment of the present invention is shown. Detailed Implementation

[0014] For example, patent publication US10790155 describes the basic principles and construction for achieving directional patterning. According to this technique, a plasma beam is scanned relative to a substrate including the layer to be patterned. By adjusting several parameters and conditions, the plasma beam containing the etchant material can be guided such that the beam etches the layer on the wafer at a much higher etch rate in the scanning direction than in a direction orthogonal to the scanning direction. This capability allows an opening in the layer to be 'stretched' by scanning the plasma beam across it.

[0015] Figure 1 A process tool 1 is shown for applying a specific directional etching technique currently known in the prior art. However, the invention is not limited to this technique. The tool includes a plasma chamber 2, which is surrounded by an RF coil 3 and used to generate plasma within the chamber. A gas inlet 4 is capable of supplying gaseous material, while the total pressure in the plasma chamber is maintained at a very low to vacuum level by a suitable vacuum pump device (not shown). The plasma chamber 2 is separated from the process chamber 5 by a separating wall 6 including a slit 7, from which a ribbon plasma beam 8 is emitted. The process chamber is also at a low to vacuum pressure. A meniscus 9 can be mounted near the slit 7 and can be positioned at a distance to control the propagation direction of the emitted beam 8. A wafer stage 15 is mounted in the process chamber 5. The wafer stage 15 can move linearly as indicated by the arrow, such that a wafer 16 held by the wafer stage can be moved relative to one of the beams 8, thereby creating an equivalent scanning of the beam 8 across wafer 16.

[0016] As described above, other directional etching techniques are known and can be applied to the method according to the invention. Ion beam-based techniques include a method in which a collimated beam of charged particles (e.g., Ar+) is accelerated across the entire wafer at a given incident angle. In the latter method, the wafer stage does not move relative to the beam as it irradiates the entire wafer. According to another known ion beam-based technique, a collimated beam of ionized gas clusters is accelerated to a point and scanned across the wafer surface at a given incident angle. In both of these latter techniques, the incident angle of the beam is adjusted by tilting the wafer.

[0017] Figure 2a and 2b The effect of directional etching on layer 17 formed on wafer 16 is shown. This layer 17 is prepared on etch stop layer 18. Before applying the directional etching process, openings 19 are formed in layer 17 by standard photolithography and etching (e.g., by direct ion etching (DIE)). A plasma beam 8 is generated and oriented at an incident angle α, defined as the angle between the beam 8 and a direction perpendicular to the surface of layer 17. Figure 1The wafer stage 15 is moved in the direction shown, scanning the plasma beam 8 relative to layer 17 along the scanning direction X. The angle β between the beam 8 and the scanning direction X is an oblique angle equal to 90° + α. By applying a suitable combination of etching parameters (such as RF power, DC bias connected to the separator 6 and / or wafer stage 15, applied etchant, incident angle α, and scanning speed), scanning the beam across the opening 19 has the effect of stretching the opening in the scanning direction, as... Figure 2b As shown. The directional etching process is selective relative to the etch stop layer 18, ensuring that this layer remains substantially intact and preventing etching of the underlying support substrate 16. The etching rate in the X direction is significantly higher than the etching rates in the Y and Z directions. As a result, the opening 19 elongates in the X direction to form a linear trench 20. Due to the non-zero etching rate in the Y direction, the line can be slightly larger than the original aperture in the Y direction. Etching in the Z direction results in the thinning of layer 17 by reducing the layer thickness a. Further elongation of the trench 20 can be achieved by repeating the directional etching steps in the same direction +X or the opposite direction -X.

[0018] According to the present invention, directional etching is applied to achieve splicing between adjacent portions of a pattern obtained by separate photolithographic exposures.

[0019] Figure 3a A process wafer 16 is shown, comprising multiple semiconductor grain regions 25 (i.e., regions on the wafer where semiconductor grains (such as integrated circuit chips) are to be processed). At the end of processing, the wafer is cut with a dicing tool to obtain individual grains. Figure 3b An enlarged view of a grain region 25 is shown. As is known in the art, the grain region is separated from adjacent grain regions by cleaving channels to facilitate the final cleaving operation. Therefore, in this context, the grain region 25 shown by the dashed line is defined as the region on which a patterned layer is formed during the manufacturing process.

[0020] The grain region 25 is divided into two adjacent sub-regions 25a and 25b. At least some of the layers in the fabrication of the grain require two exposures using separate photomasks, with each sub-region of the grain region exposed once. For example, one layer in the back-end stack of the grain may include a pattern of linear conductors fabricated by etching linear trenches in a dielectric layer and filling the trenches with metal.

[0021] refer to Figure 4a It shows Figure 3b The image shows a magnified view of the rectangular region 26. This rectangular region overlaps with the boundary 27 between the two sub-parts 25a and 25b of the grain region 25. Figure 4aThe image also shows a pattern including a plurality of parallel linear conductors 28 to be fabricated in the rectangular region. These lines are perpendicular to the boundary 27 between sub-parts 25a, 25b of the grain region and extend from one sub-part 25a across the boundary 27 to the other sub-part 25b.

[0022] This invention provides a novel method for realizing the pattern. Figure 4b The diagram illustrates patterns achieved in two sub-regions 25a and 25b of a grain region 25 through corresponding processes, each process including a photolithography step and an etching step. The patterns are formed in a dielectric layer 30, which is formed on an etch stop layer 31. This etch stop layer is located on a support layer 32, which may be, for example, a... Figure 3a The previously processed layer in the BEOL stack of the integrated circuit fabricated on the wafer 16 shown.

[0023] In these two processes, the photolithographic masks are configured to etch corresponding first and second portions of the desired linear feature 28, wherein the first and second portions are aligned with each other. The photolithography step performed in each process may, for example, include forming a positive-tone photoresist layer on the dielectric layer 30, exposing the resist to ultraviolet light through a mask that blocks ultraviolet light except at the location of the line feature, and developing the resist to leave a trench pattern in the resist layer corresponding to the location of the line portion. The trenches are transferred to the dielectric layer 30 by anisotropic etching, resulting in the formation of corresponding trenches 28'a, 28'b in the layer 30, such as... Figure 4b As shown.

[0024] The resulting pattern includes pairs of mutually aligned trenches 28'a, 28'b, with a portion 29 of the layer material separating each pair of trenches at the boundary 27 between sub-portions 25a, 25b of the grain region 25.

[0025] Subsequently, portion 29 is removed by a selective directional etching process relative to the etch stop layer 31. The directional etching steps are as follows: Figure 4c As shown. The plasma beam 35 is scanned along the +X direction indicated by the arrow (i.e., parallel to trenches 28'a, 28'b) and configured to remove material 29 between adjacent tips of the aligned trenches, thereby merging the trenches and obtaining continuous trenches 28' from the first sub-part 25a of the grain region to the second sub-part 25b, as shown. Figure 4d As shown in the figure, the thickness of dielectric layer 30 is reduced due to the specific etch rate in the Z direction. The effect of a potentially small etch rate in the Y direction perpendicular to the trench is not shown in the figure, but may result in a slight increase in trench width after the directional etching process. This effect can be taken into account during the mask design phase.

[0026] As can be seen, the etching beam 35 not only removes the intermediate material 29 between adjacent trenches 28'a and 28'b, but also elongates the trench 28'b it irradiates after removing the intermediate material. This is inherent to directional etching processes. When designing the masks for the two photolithography steps described above, this effect is taken into account; that is, the lengths of the line portions reproduced as trenches 28'a and 28'b are designed such that, after trench merging, the length of the merged trench corresponds to the required length of the corresponding line feature.

[0027] In the foregoing embodiments, the trenches 28'a / 28'b formed in the dielectric layer 30 are positioned in the Y direction to correspond to the positions of the final linear features 28 of the pattern, i.e., by applying directional etching to stretch the existing trenches (i.e., the 'negative' features in the layer). However, the invention also applies when the trenches correspond to the space between 'positive' features.

[0028] Figures 5a-5d One embodiment is shown in which corresponding line patterns in the first and second sub-regions 25a, 25b of the grain region 25 are generated as positive line patterns, for example, by patterning metal lines obtained by forming a metal layer 33 on the etch stop layer 31. Figure 5a ). Reference Figure 5b The line pattern produced in the corresponding processes applied to the two grain regions 25a and 25b includes lines 28a, 28b and blocks 36a, 36b of the metal layer, which together form a metal region 36 that spans the boundary 27 between the sub-parts 25a, 25b of the grain region 25.

[0029] This means that mutually aligned grooves 37a and 37b are now formed between the clearly defined line features 28a and 28b. (Refer to...) Figure 5c Directional etching is applied by using the same scanning direction +X scanning plasma etching beam 35 as in the previous embodiment. The directional etching process now removes metal from the solid metal region 36 along the trench direction, i.e., trenches 37a and 37b merge to form a continuous trench 37, thereby obtaining a continuous line feature 28, such as... Figure 5d As shown. Given the scanning direction of the beam, line 28a may be shortened by this directional etching process, therefore (as shown). Figure 5b As shown, the photomask used to etch the pattern portion in the first grain region 25a is configured to etch a line length 28a that is longer than the design length, thereby obtaining the desired line length of line 28 after directional etching.

Claims

1. A patterning method suitable for semiconductor manufacturing processes, the method comprising the following steps: Layers (30, 33) are fabricated on a support substrate (32), and these layers are patterned according to a predefined pattern in the semiconductor grain region (25) of the layer. The pattern is produced by at least two consecutive processes, each process including a photolithography step configured to imprint a portion of the pattern in a corresponding sub-region (25a, 25b) of the grain region, wherein the pattern includes one or more parallel linear features (28) configured to extend from a first sub-region (25a) of the grain region (25) to a second sub-region (25b) directly adjacent to the first sub-region. in: The photolithographic exposure step for imprinting the first portion of the pattern is configured to imprint the first portions (28a, 28'a) of the one or more linear features. The photolithographic exposure step for imprinting the second portion of the pattern is configured to imprint the second portions (28b, 28'b) of the one or more linear features. Its features are: The second portions (28b, 28'b) of the one or more linear features are aligned and spaced apart from the first portions (28a, 28'a) of the one or more linear features, such that after performing these two steps and after transferring the first and second portions of the pattern to the layer (30, 33), the layer is patterned according to a pattern comprising at least one pair of mutually aligned grooves (28'a, 28'b; 37a, 37b). The directional etching process is applied by scanning an etching beam (35) in a scanning direction parallel to the aligned trenches, thereby merging the aligned trenches into a single trench (28, 37).

2. The method according to claim 1, characterized in that, The position of the grooves (28'a, 28'b) in the direction perpendicular to the grooves corresponds to the position of the line feature (28) of the pattern.

3. The method according to claim 1, characterized in that, The position of the grooves (37a, 37b) in the direction perpendicular to the grooves corresponds to the space between the line features (28) of the pattern.

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