Process method applied to integrated circuit back-end-of-line

Abstract

The application discloses a process method applied to integrated circuit back-end-of-line, comprising: covering photoresist on medium, medium layer is formed on etching stop layer, etching stop layer is formed on substrate, thickness of medium layer is greater than 8 microns; photoresist of target area is removed by exposure and development in turn; first stage etching is carried out, etching to a predetermined depth in medium layer, first via is formed in medium layer, the predetermined depth is greater than 5 microns, reaction gas in first stage etching includes difluoromethane, hexafluorobutadiene, octafluorocyclobutane and oxygen; second stage etching is carried out, etching from first via to etching stop layer exposure, second via is formed, reaction gas in second stage etching includes octafluorocyclobutane and oxygen. The embodiment of the application can reduce the loss of photoresist in the deep hole etching process, thereby improving the sidewall vertical stripe defect in the etching process, improving the reliability and yield of the device product.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a process method applied in the back-end manufacturing process of integrated circuits. Background Technology

[0002] In the back-end of line (BEOL) process of semiconductor integrated circuit manufacturing, a single damask structure with via-trench connections is typically used to conduct electrical signals between inter-metal layers.

[0003] Among related technologies, a deep-hole process has been proposed, in which a deep hole is etched and filled with metal that makes contact with both the device's electrodes and the top pad, replacing the original single damask structure to achieve electrical signal conduction between the interlayer metal layers. This process has the following advantages: 1. It can save 3 to 5 layers of photolithography, reducing production costs; 2. By depositing an ultra-thick dielectric layer on top, it can improve the device's surge voltage resistance, enabling the device to be used in high-voltage scenarios.

[0004] However, due to the deep etching depth (usually greater than 10 micrometers (μm)) of deep hole etching, while the limit thickness of photoresist (about 4 micrometers) is much smaller than the required thickness in etching (about 8 micrometers), traditional photolithography cannot effectively protect the photoresist. As a result, the photoresist is consumed very early in the etching process, which leads to severe vertical stripe defects on the sidewalls of the deep holes formed by etching. This affects the subsequent metal filling and reduces the reliability and yield of the device products. Summary of the Invention

[0005] This application provides a process method for back-end manufacturing of integrated circuits, which can solve the problem that deep hole etching methods provided in related technologies are prone to forming sidewall vertical stripe defects. The method includes: A photoresist layer is formed on a dielectric layer, the dielectric layer being formed on an etch stop layer, the etch stop layer being formed on a substrate, and the thickness of the dielectric layer being greater than 8 micrometers. The photoresist in the target area is removed sequentially through exposure and development. The first stage of etching is performed to a predetermined depth in the dielectric layer to form a first via in the dielectric layer. The predetermined depth is greater than 5 micrometers. The reaction gas introduced in the first stage of etching includes difluoromethane, hexafluorobutadiene, octafluorocyclobutane and oxygen. The second stage of etching is performed, etching downwards from the first via until the etching stop layer is exposed, forming the second via. The reaction gases introduced in the second stage of etching include octafluorocyclobutane and oxygen.

[0006] In some embodiments, the source power during the etching in the first stage is between 2,500 watts and 3,000 watts.

[0007] In some embodiments, the bias power during the etching in the first stage is between 1800 watts and 2500 watts.

[0008] In some embodiments, during the etching in the first stage, the gas pressure in the process chamber is 20 to 30 millitors.

[0009] In some embodiments, the source power during the second stage of etching is between 2000 watts and 2500 watts.

[0010] In some embodiments, the bias power during the second stage of etching is between 1500 watts and 2000 watts.

[0011] In some embodiments, the dielectric layer includes a silicon dioxide layer.

[0012] In some embodiments, the etch stop layer includes an NDC layer.

[0013] The technical solution of this application has at least the following advantages: In the deep hole etching process of the back-end manufacturing process, the main etching is performed by first introducing a reactive gas containing difluoromethane, hexafluorobutadiene, octafluorocyclobutane, and oxygen. Then, the deep via is formed by over-etching with a reactive gas containing octafluorocyclobutane and oxygen. Since hexafluorobutadiene can dissociate to generate cyclic C4F5· radicals and octafluorocyclobutane can dissociate to generate C4F7· radicals, the C4F5· and C4F7· radicals can spontaneously polymerize to form a network polymer. At the same time, difluoromethane can provide hydrogen radicals to form carbon-hydrogen bonds with the network polymer, further enhancing the thermal stability of the network polymer. This network polymer covers the photoresist surface, enhancing the photoresist's resistance to physical bombardment by plasma and reducing the loss of photoresist during the etching process. This improves the sidewall vertical stripe defects during the etching process and improves the reliability and yield of the device products. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a flowchart of a process method applied in the back-end manufacturing process of integrated circuits, provided by an exemplary embodiment of this application; Figure 2 This is a cross-sectional schematic diagram of photoresist after development in a process method applied to the back-end manufacturing process of integrated circuits, provided by an exemplary embodiment of this application. Figure 3 This is a cross-sectional schematic diagram of the process method applied in the back-end manufacturing process of integrated circuits after the first stage of etching, provided by an exemplary embodiment of this application. Figure 4 This is a TEM image after etching in the first stage of a process method applied in the back-end manufacturing process of integrated circuits, provided by an exemplary embodiment of this application. Figure 5 This is a schematic cross-sectional view of the deep hole etching method provided by related technologies after the first stage of etching. Figure 6 This is a TEM image of the deep hole etching method provided by related technologies after the first stage of etching; Figure 7 This is a cross-sectional schematic diagram of the second stage of etching in a process method applied to the back-end manufacturing process of integrated circuits, provided by an exemplary embodiment of this application. Figure 8 This is a cross-sectional schematic diagram of a deep-hole structure formed in a process method applied to the back-end manufacturing process of integrated circuits, provided by an exemplary embodiment of this application. Detailed Implementation

[0016] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0018] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0019] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0020] refer to Figure 1 It illustrates a flowchart of a process method applied in the back-end manufacturing process of integrated circuits according to an exemplary embodiment of this application, such as... Figure 1 As shown, the method includes: Step S1: Cover the dielectric with photoresist, the dielectric layer is formed on the etch stop layer, the etch stop layer is formed on the substrate, and the thickness of the dielectric layer is greater than 8 micrometers.

[0021] Step S2 involves removing the photoresist in the target area through exposure and development.

[0022] refer to Figure 2 It shows a schematic cross-sectional view after development. For example, as shown... Figure 2 As shown, a dielectric layer 220 is formed on the etching stop layer 210, and a photoresist 300 is covered on the dielectric layer 220. After one exposure and development, the photoresist in the target area is removed.

[0023] The etch stop layer 210 is formed on the substrate ( Figure 2 The etch stop layer 210 is typically formed on the inter-layer dielectric (ILD) layer (not shown in the image). Figure 2 (Not shown in the image) An interlayer dielectric layer is formed on the substrate and covers the semiconductor device formed on the substrate.

[0024] The dielectric layer 220 may include a silicon dioxide (SiO2) layer with a thickness h greater than 8 micrometers; the etch stop layer 210 may include a nitride-doped silicon carbide (NDC) layer with a thickness less than that of the dielectric layer 220; the photoresist 300 has a thickness of less than 6 micrometers, typically around 4 micrometers.

[0025] Step S3 involves performing a first-stage etching process, etching to a predetermined depth in the dielectric layer to form a first via in the dielectric layer. The predetermined depth is greater than 5 micrometers. The reaction gases introduced in the first-stage etching process include difluoromethane, hexafluorobutadiene, octafluorocyclobutane, and oxygen.

[0026] refer to Figure 3 It shows a cross-sectional schematic diagram of an embodiment of this application after the first stage of etching; see reference. Figure 4 The image shows a transmission electron microscope (TEM) image of an embodiment of this application after the first stage of etching.

[0027] For example, such as Figure 3 As shown, the first stage of etching is performed using photoresist 300 as a mask, etching to a predetermined depth in the dielectric layer 220, forming a first via 401 in the dielectric layer 220, the predetermined depth being greater than 5 micrometers.

[0028] The first stage of etching is also known as the main etching (ME). This stage involves etching away most of the dielectric layer of the target area. During this etching process, hexafluorobutadiene (C4F6) can dissociate to generate cyclic C4F5· radicals, and octafluorocyclobutane (C4F8) can dissociate to generate C4F7· radicals. These C4F5· and C4F7· radicals can spontaneously polymerize to form a network polymer. Simultaneously, difluoromethane (CH2F2) can provide hydrogen radicals (H·) to form carbon-hydrogen (CH) bonds with the network polymer, further enhancing the thermal stability of the network polymer. This coating on the photoresist surface enhances the photoresist's resistance to physical bombardment by plasma, reduces photoresist loss during etching, and thus improves the sidewall vertical stripe defects during the etching process. Figure 4 As shown.

[0029] Optionally, in the first stage of etching, the flow rate of difluoromethane is 8 to 12 standard cubic centimeters per minute (SCCM), the flow rate of hexafluorobutadiene is 15 to 20 SCCM, the flow rate of octafluorocyclobutane is 10 to 15 SCCM, and the flow rate of oxygen (O2) is 25 to 30 SCCM.

[0030] Optionally, in the first stage of etching, the source power is set to 2500 watts (W) to 3000 watts, the bias power to 1800 watts to 2500 watts, and the gas pressure in the process chamber to 20 millitors (mTorr) to 30 millitors. Under high source power (2500 W to 3000 W), the mixed reactive gas generates a large amount of cyclic polymers on the photoresist surface, significantly reducing photoresist consumption during etching and effectively mitigating the problem of premature photoresist depletion leading to sidewall vertical stripe defects. Simultaneously, the high bias power (1800 W to 2500 W) and low pressure (20 mTorr to 30 mTorr) environment impart extremely high physical bombardment energy to fluorine radicals (F·), ensuring effective etching of the dielectric layer.

[0031] refer to Figure 5 It shows a cross-sectional schematic diagram of the etching method provided in the related art after the first stage of etching; Reference Figure 6 The image shows a TEM image after the first stage of etching in the etching method provided in the related art.

[0032] For example, such as Figure 5 As shown, in related technologies, the reactive gases in the main etching are typically carbon tetrafluoride (CF4), trifluoromethane (CHF3), and oxygen. It is easy to see that, without protection for the photoresist 301, after the main etching of the dielectric layer 221 above the etch stop layer 211, the photoresist 301 is largely consumed, resulting in sidewall vertical stripe defects, such as… Figure 6 The area shown is indicated by the dashed line.

[0033] In addition, in the embodiments of this application, the carbon-fluorine ratio (C / F) of the mixed gas including difluoromethane, hexafluorobutadiene, octafluorocyclobutane and oxygen is higher than that of the mixed gas of tetrafluoromethane, trifluoromethane and oxygen in the related art, which can further reduce the chemical etching of photoresist by fluorine free radicals.

[0034] Step S4 involves the second stage of etching, which involves etching downwards from the first via until the etching stop layer is exposed, forming the second via. The reaction gases introduced in the second stage of etching include octafluorocyclobutane and oxygen.

[0035] refer to Figure 7 It shows a schematic cross-sectional view after the second stage of etching. For example, as shown... Figure 7 As shown, the second stage of etching is performed, etching downwards from the first via 401 until the etching stop layer is exposed, forming the second via 402.

[0036] The second stage of etching is also known as overetch (OE). Optionally, in the second stage of etching, the flow rate of octafluorocyclobutane (C4F8) is 15 SCCM to 20 SCCM, and the flow rate of oxygen is 10 SCCM to 15 SCCM; optionally, in the second stage of etching, the source power is 2000 W to 2500 W, and the bias power is 1500 W to 2000 W. Using the above parameter combination provides a high etching selectivity, ensuring that the etching process stops at the etching stop layer 210.

[0037] Following the second stage of etching, further etching is required from the second via 402 downwards until the etching stop layer 210 in the target area is removed. The reaction gases introduced during this etching process include carbon tetrafluoride and oxygen. Optionally, the flow rate of carbon tetrafluoride is 50 to 100 SCCM, and the flow rate of oxygen is 20 to 30 SCCM; alternatively, the source power is 500 to 1000 watts. Using the above parameters enables rapid removal of the etching stop layer 210.

[0038] refer to Figure 8 This shows a schematic cross-sectional view after the formation of the deep hole structure. For example, such as... Figure 8 As shown, the deep holes formed in the dielectric layer 210 and the etch stop layer 220 are filled with metal layers to form a deep hole structure 202. The depth H of the deep hole structure 202 is typically greater than 10 micrometers. Its top end is disconnected from the top pad 203, and its bottom end is in contact with the metal interconnect 201 in the ILD layer 200.

[0039] In summary, in the embodiments of this application, during the deep hole etching process in the back-end process, the main etching is first performed by introducing a reactive gas containing difluoromethane, hexafluorobutadiene, octafluorocyclobutane, and oxygen, and then the deep via is formed by introducing a reactive gas containing octafluorocyclobutane and oxygen. Since hexafluorobutadiene can dissociate to generate cyclic C4F5· free radicals and octafluorocyclobutane can dissociate to generate C4F7· free radicals, the free radicals C4F5· and C4F7· can spontaneously polymerize to form a network polymer. At the same time, difluoromethane can provide hydrogen free radicals to form carbon-hydrogen bonds with the network polymer, further enhancing the thermal stability of the network polymer. Covering the photoresist surface, it enhances the photoresist's resistance to physical bombardment by plasma, reduces the loss of photoresist during the etching process, thereby improving the sidewall vertical stripe defects during the etching process and improving the reliability and yield of the device products.

[0040] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A process method applied in the back-end manufacturing of integrated circuits, characterized in that, include: A photoresist layer is formed on a dielectric layer, which is formed on an etch stop layer and on a substrate. The thickness of the dielectric layer is greater than 8 micrometers. The photoresist in the target area is removed sequentially through exposure and development. The first stage of etching is performed to a predetermined depth in the dielectric layer to form a first via in the dielectric layer. The predetermined depth is greater than 5 micrometers. The reaction gas introduced in the first stage of etching includes difluoromethane, hexafluorobutadiene, octafluorocyclobutane and oxygen. The second stage of etching is performed, etching downwards from the first via until the etching stop layer is exposed, forming the second via. The reaction gases introduced in the second stage of etching include octafluorocyclobutane and oxygen.

2. The method according to claim 1, characterized in that, In the first stage of etching, the source power is between 2500 watts and 3000 watts.

3. The method according to claim 2, characterized in that, In the first stage of etching, the bias power ranges from 1800 watts to 2500 watts.

4. The method according to claim 3, characterized in that, During the first stage of etching, the gas pressure in the process chamber is 20 to 30 millitors.

5. The method according to claim 1, characterized in that, In the second stage of etching, the source power is between 2000 watts and 2500 watts.

6. The method according to claim 5, characterized in that, In the second stage of etching, the bias power is between 1500 watts and 2000 watts.

7. The method according to any one of claims 1 to 6, characterized in that, The dielectric layer includes a silicon dioxide layer.

8. The method according to claim 7, characterized in that, The etch stop layer includes an NDC layer.

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