Method for manufacturing a semiconductor structure, semiconductor structure and electronic device

Abstract

The application discloses a preparation method of a semiconductor structure, a semiconductor structure and an electronic device, and belongs to the field of semiconductor manufacturing. The method comprises the following steps: providing an intermediate structure, wherein the intermediate structure comprises a substrate, a first dielectric layer, a second dielectric layer and a pattern layer which are sequentially stacked; performing a first etching operation to remove the pattern layer and part of the second dielectric layer, so that the remaining second dielectric layer has a through hole corresponding to an opening; and performing a second etching operation to remove the first dielectric layer between the remaining second dielectric layer and a plurality of metal structures, so as to form an air gap between the plurality of metal structures; wherein the first etching operation and the second etching operation adopt dry etching, and the etching selectivity ratio of the second etching operation to the first dielectric layer and the substrate is greater than that of the first etching operation. The air gap prepared by the method can effectively reduce the parasitic capacitance between the metal structures, the process flow is simple, and the production efficiency is high.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing technology, and in particular relates to a method for preparing a semiconductor structure, a semiconductor structure, and an electronic device. Background Technology

[0002] Metal interconnect structures can provide conductive paths for transistors. As chip manufacturing processes continue to improve, the spacing between metal interconnect structures continues to decrease, leading to an increase in parasitic capacitance between metal interconnect structures. Parasitic capacitance can cause signal delay and crosstalk, directly affecting the chip's operating frequency and power consumption.

[0003] By creating air gaps between metal interconnect structures, the parasitic capacitance between them can be effectively reduced. However, the current fabrication process for air gaps is complex and has low production efficiency. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a method for fabricating a semiconductor structure, a semiconductor structure, and an electronic device, which has a simple process flow and high production efficiency.

[0005] In a first aspect, this application provides a method for fabricating a semiconductor structure, the method comprising: An intermediate structure is provided, the intermediate structure comprising a substrate, a first dielectric layer, a second dielectric layer and a pattern layer stacked sequentially, the first dielectric layer comprising a plurality of metal structures spaced apart from each other, the pattern layer having an opening that exposes the second dielectric layer, the orthographic projection of the opening onto the plane of the first dielectric layer being spaced apart from the orthographic projection of the plurality of metal structures onto the plane of the first dielectric layer. A first etching operation is performed to remove the patterned layer and a portion of the second dielectric layer, so that the remaining second dielectric layer has a via corresponding to the opening; A second etching operation is performed to remove the first dielectric layer between the remaining second dielectric layer and the plurality of metal structures, so as to form an air gap between the plurality of metal structures, the air gap being used to achieve electrical isolation between the plurality of metal structures; Wherein, the first etching operation and the second etching operation are dry etching operations, and the etching selectivity of the second etching operation for the first dielectric layer and the substrate is greater than that of the first etching operation.

[0006] According to the semiconductor structure fabrication method provided in the embodiments of this application, by precisely controlling the position of the pattern layer opening, and performing a first etching operation and a second etching operation on the intermediate structure, the first etching operation and the second etching operation adopt anisotropic dry etching, and the second etching operation has a higher etching selectivity, which can form an air gap between adjacent metal structures without affecting the substrate and metal structure. There is no need to prepare intermediate layers or protective layers during the etching process. The air gap prepared by this method can effectively reduce the parasitic capacitance between metal structures, improve the signal response speed, and the process is simple and has high production efficiency.

[0007] According to one embodiment of this application, the material of the first dielectric layer includes silicon oxide, and the material of the substrate includes silicon; the gas used in the second etching operation includes C4F6, oxygen, and a protective gas.

[0008] According to one embodiment of this application, the second etching operation includes a first etching sub-operation and a second etching operation; The second etching operation, which removes the first dielectric layer between the remaining second dielectric layer and the plurality of metal structures, includes: A first etching operation is performed to remove a portion of the second dielectric layer and a portion of the first dielectric layer located between the plurality of metal structures, such that the thickness of the remaining first dielectric layer located between the plurality of metal structures is less than or equal to a first preset thickness. A second etching sub-operation is performed to remove the remaining second dielectric layer and the first dielectric layer located between the plurality of metal structures to form an air gap between the plurality of metal structures, wherein the etching selectivity ratio of the second etching sub-operation for the first dielectric layer and the substrate is greater than 10.

[0009] According to one embodiment of this application, the material of the first dielectric layer includes silicon oxide, and the material of the substrate includes silicon; The gases used in the first etching operation include C4F8, oxygen, and a protective gas; The gases used in the second etching operation include C4F6, oxygen, and a protective gas.

[0010] According to one embodiment of this application, the first preset thickness is less than or equal to 10% of the thickness of the first dielectric layer.

[0011] According to one embodiment of this application, the intermediate structure further includes a third dielectric layer, the third dielectric layer being located between the substrate and the first dielectric layer; The second etching operation, which removes the first dielectric layer between the remaining second dielectric layer and the plurality of metal structures, includes: The second etching operation is performed to remove the remaining second dielectric layer, the first dielectric layer between the plurality of metal structures, and part of the third dielectric layer, so that the thickness of the remaining third dielectric layer is greater than or equal to the second preset thickness.

[0012] According to one embodiment of this application, the second dielectric layer includes an anti-reflective layer and a mask layer, the mask layer being located on the surface of the first dielectric layer opposite to the substrate, the anti-reflective layer being located on the surface of the mask layer opposite to the substrate, and the opening exposing the anti-reflective layer; The first etching operation includes a third etching sub-operation and a fourth etching sub-operation; The first etching operation, which removes the patterned layer and a portion of the second dielectric layer, includes: The third etching operation is performed to remove a portion of the anti-reflective layer, so that the remaining anti-reflective layer has a first through-hole corresponding to the opening; The fourth etching operation is performed to remove the pattern layer and part of the mask layer, so that the remaining mask layer has a second via corresponding to the first via.

[0013] According to one embodiment of this application, the antireflective layer is made of at least one of silicon oxide, silicon nitride, and silicon oxynitride; the gas used in the third etching operation includes CF4 and CHF3.

[0014] According to one embodiment of this application, the material of the mask layer includes carbon; the gas used in the fourth etching operation includes carbon dioxide, hydrogen, and a protective gas.

[0015] According to one embodiment of this application, the aspect ratio of the air gap is 2-8.

[0016] In a second aspect, this application provides a semiconductor structure that is prepared by the semiconductor structure preparation method described in the first aspect.

[0017] According to the semiconductor structure provided in the embodiments of this application, by precisely controlling the position of the pattern layer opening, and performing a first etching operation and a second etching operation on the intermediate structure, the first etching operation and the second etching operation adopt anisotropic dry etching, and the second etching operation has a higher etching selectivity, which can form an air gap between adjacent metal structures without affecting the substrate and metal structure. There is no need to prepare intermediate layers or protective layers during the etching process. The air gap of this semiconductor structure can effectively reduce the parasitic capacitance between metal structures, improve the signal response speed, and the process is simple and the production efficiency is high.

[0018] Thirdly, this application provides an electronic device that includes the semiconductor structure described in the second aspect.

[0019] According to the electronic device provided in the embodiments of this application, the semiconductor structure in the electronic device precisely controls the position of the pattern layer opening and performs a first etching operation and a second etching operation on the intermediate structure. The first etching operation and the second etching operation adopt anisotropic dry etching, and the second etching operation has a higher etching selectivity. It can form an air gap between adjacent metal structures without affecting the substrate and metal structure. There is no need to prepare intermediate layers or protective layers during the etching process. The air gap of the semiconductor structure can effectively reduce the parasitic capacitance between metal structures, improve the signal response speed, and the process is simple and the production efficiency is high.

[0020] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0021] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic flowchart of the semiconductor structure fabrication method provided in the embodiments of this application; Figure 2 This is one of the schematic diagrams of the semiconductor structure provided in the embodiments of this application; Figure 3 This is a second schematic diagram of the semiconductor structure provided in the embodiments of this application; Figure 4 This is the third schematic diagram of the semiconductor structure provided in the embodiments of this application; Figure 5 This is the fourth schematic diagram of the semiconductor structure provided in the embodiments of this application; Figure 6 This is the fifth schematic diagram of the semiconductor structure provided in the embodiments of this application; Figure 7 This is the sixth schematic diagram of the semiconductor structure provided in the embodiments of this application.

[0022] Figure label: 100 substrates First dielectric layer 210, metal structure 211, second dielectric layer 220, anti-reflective layer 221, mask layer 222, third dielectric layer 230, pattern layer 240, opening 241, first through-hole 251, second through-hole 252. Air gap 300. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0024] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0025] Using low-k materials as insulating layers between metal interconnect structures can reduce capacitance to some extent. However, the best solid-state low-k materials currently available have dielectric constants (k≈2.5-3.0) much higher than air (k≈1), and the potential for improvement in solid-state low-k materials is very limited. Air, on the other hand, is a known and ideal insulator. Using it to replace solid insulating materials and create vacuum or air gaps between metal interconnect structures can significantly improve the interconnect performance of semiconductor devices. However, the fabrication process for air gaps is currently complex and inefficient.

[0026] This application provides a method for fabricating a semiconductor structure. The air gap prepared by this method can effectively reduce the parasitic capacitance between metal structures, improve the signal response speed, and the process is simple and has high production efficiency.

[0027] The method for preparing the semiconductor structure provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0028] like Figure 1 As shown, the method for fabricating this semiconductor structure includes steps 110, 120, and 130.

[0029] Step 110: Provide an intermediate structure, which includes a substrate 100, a first dielectric layer 210, a second dielectric layer 220 and a pattern layer 240 stacked sequentially. The first dielectric layer 210 includes a plurality of metal structures 211 spaced apart from each other. The pattern layer 240 has an opening 241 that exposes the second dielectric layer 220. The orthographic projection of the opening 241 onto the plane of the first dielectric layer 210 is spaced apart from the orthographic projection of the plurality of metal structures 211 onto the plane of the first dielectric layer 210.

[0030] The intermediate structure can serve as the technological basis for subsequent steps, such as... Figure 2 As shown, the intermediate structure includes a substrate 100, a first dielectric layer 210, a second dielectric layer 220 and a pattern layer 240 stacked in sequence. The first dielectric layer 210 can be disposed on the upper surface of the substrate 100, the second dielectric layer 220 can be disposed on the upper surface of the first dielectric layer 210, and the pattern layer 240 can be disposed on the upper surface of the second dielectric layer 220.

[0031] The substrate 100 can serve as a growth platform for the first dielectric layer 210, the second dielectric layer 220, and the pattern layer 240, providing a supporting foundation for the first dielectric layer 210, the second dielectric layer 220, and the pattern layer 240.

[0032] In actual implementation, the substrate 100 can integrate active devices such as transistors, and the transistors can be connected to the metal structure 211 to realize corresponding circuit functions.

[0033] In this step, the first dielectric layer 210 is disposed on the surface of the substrate 100, and the first dielectric layer 210 is provided with a plurality of metal structures 211. The first dielectric layer 210 can provide support for the plurality of metal structures 211, and the plurality of metal structures 211 can be connected to the transistor disposed on the substrate 100.

[0034] In actual implementation, the first dielectric layer 210 can be made of insulating material to reduce the probability of short circuits between multiple metal structures 211.

[0035] In this step, the metal structure 211 can be a conductive element embedded in the first dielectric layer 210. The material of the metal structure 211 can include materials such as copper or aluminum. Multiple metal structures 211 are arranged at a specific interval to serve as current paths while reducing mutual interference.

[0036] In actual implementation, multiple metal structures 211 can extend in a direction away from the substrate 100, for example, as Figure 2 As shown, if the base 100 is set horizontally, multiple metal structures 211 can extend in the vertical direction.

[0037] In this step, the second dielectric layer 220 is disposed on the surface of the first dielectric layer 210 away from the substrate 100, and the pattern layer 240 is disposed on the surface of the second dielectric layer 220 away from the substrate 100. The pattern layer 240 has patterned openings 241 that expose the second dielectric layer 220. In the subsequent etching process, the openings 241 can transfer the pattern to the second dielectric layer 220 and the first dielectric layer 210 and other structures.

[0038] In actual implementation, the pattern layer 240 can be a photoresist layer, and the opening 241 of the pattern layer 240 can be prepared by photolithography. The second dielectric layer 220 can be used to assist the photolithography process of the pattern layer 240, such as reducing light reflection during the photolithography process, improving the clarity of the pattern edge, and protecting the first dielectric layer 210 from the influence of photolithography.

[0039] It should be noted that the materials and thicknesses of the substrate 100, the first dielectric layer 210, the second dielectric layer 220, and the pattern layer 240 can be determined according to the actual design of the semiconductor structure, and are not limited in this embodiment.

[0040] In this step, the orthographic projection of the opening 241 onto the plane of the first dielectric layer 210 is spaced apart from the orthographic projection of the multiple metal structures 211 onto the plane of the first dielectric layer 210. That is, the opening 241 is aligned with the gap between the multiple metal structures 211. These gaps are the areas for the fabrication of the air gap 300. By precisely controlling the position of the opening 241 to avoid the area where the metal structures 211 are located, and by etching the second dielectric layer 220 and the first dielectric layer 210 exposed by the opening 241 in subsequent steps, the air gap 300 can be fabricated between the multiple metal structures 211 without affecting the metal structures 211.

[0041] It should be noted that the specific location, size and shape of the opening 241 can be determined according to the actual design of the semiconductor structure. The opening 241 can be kept in the plane of the first dielectric layer 210 between the metal structures 211. This embodiment of the application does not limit this.

[0042] Step 120: Perform a first etching operation to remove the pattern layer 240 and part of the second dielectric layer 220 so that the remaining second dielectric layer 220 has a through hole corresponding to the opening 241.

[0043] The first etching operation is a process step in which the second dielectric layer 220 is selectively removed through the opening 241 of the pattern layer 240. Through the first etching operation, the pattern layer 240 can be used as a mask to transfer the pattern of the opening 241 onto the second dielectric layer 220, thereby forming a through hole corresponding to the opening 241 in the second dielectric layer 220.

[0044] The via is a through hole formed in the second dielectric layer 220 by the first etching operation. The shape and position of the via correspond to the opening 241 of the pattern layer 240. The via exposes the first dielectric layer 210 located between the second dielectric layer 220 and the substrate 100.

[0045] In this step, the first etching operation removes the pattern layer 240 and the second dielectric layer 220 exposed by the opening 241, resulting in the following: Figure 4 The structure shown includes a via in the second dielectric layer 220 that provides an etching channel for subsequent steps, allowing the subsequent process to further etch the first dielectric layer 210 between the metal structures 211 through the via, thereby forming an air gap 300 between the metal structures 211.

[0046] Step 130: Perform a second etching operation to remove the first dielectric layer 210 between the remaining second dielectric layer 220 and the plurality of metal structures 211, so as to form an air gap 300 between the plurality of metal structures 211. The air gap 300 is used to achieve electrical isolation between the plurality of metal structures 211.

[0047] The second etching operation is a process step of selectively etching the first dielectric layer 210 through the via. Through the second etching operation, the remaining second dielectric layer 220 can be used as a mask to further transfer the pattern of the via to the first dielectric layer 210.

[0048] Air gap 300 (AG) is a cavity region formed between adjacent metal structures 211 after the first dielectric layer 210 is removed by the second etching operation. Air gap 300 can replace the original first dielectric layer 210 to achieve better electrical isolation performance. Air gap 300 can effectively reduce the parasitic capacitance between metal structures 211 and improve the signal transmission speed of semiconductor structure.

[0049] In practice, the depth of the air gap of 300 can be adjusted by modifying the relevant parameters of the second etching operation, such as the specific etching method and etching time.

[0050] In this step, the first and second etching operations are performed using dry etching.

[0051] In practice, dry etching typically generates plasma by applying an electric field to the etching gas, and then uses the plasma to etch the structure to be etched. Dry etching can adjust the etching direction by adjusting the bombardment direction of the plasma, making it an anisotropic etching method.

[0052] It is understandable that the etching selectivity ratio refers to the ratio of the etching rates of different materials or structures for different etching processes.

[0053] In this step, the second etching operation has a greater etching selectivity ratio between the first dielectric layer 210 and the substrate 100 than the first etching operation. This allows the second etching operation to efficiently etch the first dielectric layer 210 without affecting the substrate 100, thereby reducing the risk of damage to the substrate 100 due to over-etching and protecting devices such as transistors disposed on the substrate 100.

[0054] In practice, the etching selectivity of the second etching operation for the first dielectric layer 210 and the substrate 100 can be adjusted by adjusting the gas composition and ratio used in the second etching operation.

[0055] In this step, the second etching operation is anisotropic dry etching with a high etching selectivity. This second etching operation allows for efficient and precise removal of the first dielectric layer 210 between multiple metal structures 211. It also enables the formation of air gaps 300 between adjacent metal structures 211 without affecting the substrate 100 and the metal structures 211, resulting in... Figure 5 The structure shown.

[0056] In this embodiment, the air gap 300 obtained by the first etching operation and the second etching operation can be used to achieve electrical isolation between metal structures 211. This method can effectively reduce the parasitic capacitance between metal structures 211 and improve the signal response speed. In addition, the first etching operation and the second etching operation are both anisotropic dry etching operations. The air gap 300 can be obtained by directly etching the prepared intermediate structure. There is no need to prepare intermediate layer or protective layer during the etching process. This method has a simple process flow and high production efficiency.

[0057] In related technologies, wet etching is typically used to etch the oxide layer between metal interconnect structures to create air cavities between them. However, before etching the oxide layer, the wet etching process requires the preparation of a protective layer on the surface of the metal interconnect structure to protect it from corrosion by the etching solution. This process is complex and has low production efficiency.

[0058] In this embodiment, the intermediate structure includes a substrate 100, a first dielectric layer 210, a second dielectric layer 220, and a pattern layer 240 stacked sequentially. The pattern layer 240 has an opening 241. By precisely controlling the position of the opening 241, a first etching operation and a second etching operation are performed on the intermediate structure. The first etching operation and the second etching operation are anisotropic dry etching, and the second etching operation has a higher etching selectivity than the first etching operation. It can etch the second dielectric layer 220 and the first dielectric layer 210 exposed by the opening 241. It can form an air gap 300 between adjacent metal structures 211 without affecting the substrate 100 and the metal structure 211. There is no need to prepare intermediate layers or protective layers during the etching process. The air gap 300 prepared by this method can effectively reduce the parasitic capacitance between metal structures 211, improve the signal response speed, and the process is simple and has high production efficiency.

[0059] According to the semiconductor structure fabrication method provided in the embodiments of this application, by precisely controlling the position of the opening 241 of the pattern layer 240, and performing a first etching operation and a second etching operation on the intermediate structure, the first etching operation and the second etching operation adopt anisotropic dry etching, and the second etching operation has a higher etching selectivity, which can form an air gap 300 between adjacent metal structures 211 without affecting the substrate 100 and the metal structure 211. There is no need to prepare intermediate layers or protective layers during the etching process. The air gap 300 prepared by this method can effectively reduce the parasitic capacitance between metal structures 211, improve the signal response speed, and the process is simple and has high production efficiency.

[0060] In some embodiments, the first dielectric layer 210 is made of silicon oxide, and the substrate 100 is made of silicon; the gas used in the second etching operation includes C4F6, oxygen, and a protective gas.

[0061] The first dielectric layer 210 is made of silicon oxide (SiO2), which has good insulation and chemical stability and can be used to support and isolate multiple metal structures 211.

[0062] The substrate 100 is made of silicon (Si). The substrate 100 can integrate active devices such as transistors. The silicon substrate 100 can form an electrical connection with the metal structure 211 through transistors while providing mechanical support, thereby realizing circuit functions.

[0063] In this embodiment, the substrate 100 and the first dielectric layer 210 have significantly different materials. The second etching operation uses gases including C4F6, oxygen (O2), and a protective gas. C4F6 can decompose in a plasma environment to generate fluorine-based active substances, which preferentially react with silicon oxide, thereby achieving selective etching. Oxygen is used to adjust the etching rate and remove byproducts, while the protective gas is used to maintain plasma stability. By using C4F6, oxygen, and a protective gas as etching gases, the second etching operation can achieve high selectivity etching, thereby obtaining an air gap 300 with a good morphology without affecting the substrate 100 and the active devices.

[0064] In actual implementation, the protective gas may include at least one of argon (Ar) and nitrogen (N2), or a combination of argon and nitrogen, or other feasible gases. The specific components of the protective gas can be determined according to actual needs, and the embodiments of this application are not limited here.

[0065] In some embodiments, the second etching operation includes a first etching sub-operation and a second etching sub-operation; performing the second etching operation to remove the first dielectric layer 210 between the remaining second dielectric layer 220 and the plurality of metal structures 211 includes: Perform a first etching operation to remove a portion of the second dielectric layer 220 and a portion of the first dielectric layer 210 located between multiple metal structures 211, so that the thickness of the remaining first dielectric layer 210 located between multiple metal structures 211 is less than or equal to a first preset thickness. A second etching operation is performed to remove the remaining second dielectric layer 220 and the first dielectric layer 210 located between the plurality of metal structures 211, so as to form an air gap 300 between the plurality of metal structures 211. The etching selectivity ratio of the second etching operation to the first dielectric layer 210 and the substrate 100 is greater than 10.

[0066] The first etching operation is used to remove a portion of the first dielectric layer 210 between the second dielectric layer 220 and the metal structure 211, reducing the remaining thickness L of the first dielectric layer 210 to below a first preset thickness, resulting in the following... Figure 5 The structure shown.

[0067] The first preset thickness refers to the thickness threshold of the remaining first dielectric layer 210 between the metal structures 211 after the first etching operation. If the thickness of the remaining first dielectric layer 210 between the metal structures 211 is less than or equal to the first preset thickness, the first etching operation can be stopped and the subsequent second etching operation can be performed. This can completely remove the remaining second dielectric layer 220 and reduce the probability of damage to the metal structure 211 or the substrate 100 caused by excessive etching of the first dielectric layer 210.

[0068] The second etching operation can remove the remaining second dielectric layer 220 and the first dielectric layer 210 between the metal structure 211 to form an air gap 300 between the metal structures 211, resulting in... Figure 6 The structure shown achieves electrical isolation between the metal structures 211. The etching selectivity of the second etching sub-operation is greater than 10, which can reduce the impact of the etching process on the substrate 100 and accurately etch the first dielectric layer 210.

[0069] Understandably, after the first etching operation, such as Figure 5 As shown, the thickness of the remaining first dielectric layer 210 refers to the distance L from the bottom of the groove formed by the etching of the first dielectric layer 210 between the metal structures 211 to the side of the first dielectric layer 210 near the substrate 100, rather than the thickness of the un-etched first dielectric layer 210 between the metal structures 211.

[0070] It should be noted that the specific value of the first preset thickness can be determined according to the actual size of the semiconductor structure and can be adjusted according to the actual situation. This application embodiment does not limit it here.

[0071] In this embodiment, the second etching operation is divided into a first etching sub-operation and a second etching sub-operation. The first etching sub-operation can achieve rapid thinning of the first dielectric layer 210 between the metal structures 211, while the second etching sub-operation has a high etching selectivity, which can completely remove the first dielectric layer 210 between the metal structures 211 without affecting the metal structures 211 and the substrate 100, thus balancing the etching rate and etching effect.

[0072] In some embodiments, the first dielectric layer 210 is made of silicon oxide, and the substrate 100 is made of silicon; the gas used in the first etching operation includes C4F8, oxygen, and a protective gas; the gas used in the second etching operation includes C4F6, oxygen, and a protective gas.

[0073] In actual implementation, the protective gas may include at least one of argon (Ar) and nitrogen (N2), or a combination of argon and nitrogen, or other feasible gases. The specific components of the protective gas can be determined according to actual needs, and the embodiments of this application are not limited here.

[0074] In this embodiment, the first etching operation uses C4F8 gas, which has a high polymerization tendency and can form fluorocarbon polymer byproducts during the etching process. These byproducts are deposited on the sidewall surface during the etching process, thereby protecting the sidewall and the metal structure 211 and reducing the probability of over-etching. The second etching operation uses C4F6 gas, which completely removes the first dielectric layer 210 between the metal structures 211 without affecting the substrate 100 through a higher etching selectivity.

[0075] In some embodiments, the first preset thickness is less than or equal to 10% of the thickness of the first dielectric layer 210.

[0076] It is understood that the thickness of the first dielectric layer 210 can refer to the thickness of the first dielectric layer 210 in the direction perpendicular to the surface of the substrate 100.

[0077] It should be noted that the "vertical" in the embodiments of this application includes not only 90 degrees in an absolute sense, but also other approximate vertical situations that are close to 90 degrees.

[0078] In actual implementation, the thickness of the first dielectric layer 210 can be the average thickness or the maximum thickness. The specific calculation method can be determined according to the actual morphology and structure of the first dielectric layer 210. This application embodiment does not limit this.

[0079] In this embodiment, the first preset thickness is less than or equal to 10% of the thickness of the first dielectric layer 210. This ensures that the thickness of the remaining first dielectric layer 210 between the metal structures 211 after the first etching operation is within a reasonable range. This avoids the second etching operation from having too much remaining first dielectric layer 210, which would result in an excessively long etching time. It also reduces the risk of damage to the substrate 100 caused by too little remaining first dielectric layer 210.

[0080] In some embodiments, such as Figure 1 As shown, the intermediate structure also includes a third dielectric layer 230, which is located between the substrate 100 and the first dielectric layer 210; a second etching operation is performed to remove the first dielectric layer 210 between the remaining second dielectric layer 220 and the plurality of metal structures 211, including: performing a second etching operation to remove the remaining second dielectric layer 220, the first dielectric layer 210 between the plurality of metal structures 211 and part of the third dielectric layer 230, so that the thickness of the remaining third dielectric layer 230 is greater than or equal to a second preset thickness.

[0081] The third dielectric layer 230 can be a protective structure located between the substrate 100 and the first dielectric layer 210. The third dielectric layer 230 can serve as an etching termination layer in the second etching operation. When the etching penetrates the first dielectric layer 210, it can reduce the probability of damage to the substrate 100.

[0082] The second preset thickness refers to the minimum thickness threshold of the third dielectric layer 230 remaining after the second etching operation. By setting the second preset thickness, the probability of damage to the substrate 100 caused by excessive etching in the second etching operation can be effectively reduced.

[0083] In actual implementation, the material of the third dielectric layer 230 may include one or more of silicon nitride, silicon oxide and silicon oxynitride, or other feasible materials. The specific material can be determined according to the actual process requirements, and this application embodiment does not limit it.

[0084] Furthermore, the specific value of the second preset thickness can be determined based on the actual size of the semiconductor structure and can be adjusted according to the actual situation. This application embodiment does not limit this value.

[0085] In this embodiment, by introducing a third dielectric layer 230 as an etching stop layer and controlling the thickness of the third dielectric layer 230 to be greater than or equal to a second preset thickness after the second etching operation, the probability of substrate 100 damage caused by over-etching in the second etching operation can be effectively reduced.

[0086] In some embodiments, such as Figure 2 As shown, the second dielectric layer 220 includes an anti-reflective layer 221 and a mask layer 222. The mask layer 222 is located on the surface of the first dielectric layer 210 away from the substrate 100, and the anti-reflective layer 221 is located on the surface of the mask layer 222 away from the substrate 100. The opening 241 exposes the anti-reflective layer 221.

[0087] Among them, the anti-reflection layer 221 can be used to optimize the photolithography process for preparing the opening 241 of the pattern layer 240. During the exposure process of the pattern layer 240, the anti-reflection layer 221 can suppress reflected light through interference effect, reduce the standing wave effect in the pattern layer 240, thereby improving the accuracy of the pattern and the edge clarity.

[0088] The mask layer 222 is disposed on the surface of the first dielectric layer 210 away from the substrate 100. The mask layer 222 can maintain stability during the photolithography process, thereby reducing the impact of the photolithography process on the first dielectric layer 210.

[0089] In this embodiment, the first etching operation includes a third etching sub-operation and a fourth etching sub-operation; performing the first etching operation to remove the pattern layer 240 and a portion of the second dielectric layer 220 includes: A third etching operation is performed to remove part of the anti-reflective layer 221 so that the remaining anti-reflective layer 221 has a first through hole 251 corresponding to the opening 241; A fourth etching operation is performed to remove the pattern layer 240 and part of the mask layer 222 so that the remaining mask layer 222 has a second through hole 252 corresponding to the first through hole 251.

[0090] The third etching operation can be an etching step of the anti-reflective layer 221. This third etching operation can remove the anti-reflective layer 221 exposed by the opening 241 of the pattern layer 240, thereby forming a first through-hole 251 in the anti-reflective layer 221 with the same position and size as the opening 241, resulting in... Figure 3 The structure shown.

[0091] The fourth etching operation can be an etching step of the mask layer 222. This fourth etching operation can remove the mask layer 222 exposed by the pattern layer 240 and the first via 251, thereby forming a second via 252 in the mask layer 222 with the same position and size as the first via 251, resulting in... Figure 4 The structure shown.

[0092] In this embodiment, the second dielectric layer 220 includes an anti-reflection layer 221 and a mask layer 222. The first etching operation adopts a step-by-step etching method including a third etching sub-operation and a fourth etching sub-operation. The third etching sub-operation can remove the anti-reflection layer 221 exposed by the opening 241, thereby forming a first via 251 in the anti-reflection layer 221. The fourth etching sub-operation can remove the mask layer 222 exposed by the first via 251, thereby forming a second via 252 in the mask layer 222. The positions and sizes of the first via 251 and the second via 252 correspond to the opening 241. Subsequent steps can precisely etch the first dielectric layer 210 located between the metal structures 211 through the first via 251 and the second via 252.

[0093] In some embodiments, the antireflective layer 221 is made of at least one of silicon oxide, silicon nitride, and silicon oxynitride; the gas used in the third etching operation includes CF4 and CHF3.

[0094] In this embodiment, the anti-reflective layer 221 can be made of one or more of silicon oxide, silicon nitride, and silicon oxynitride, which can provide excellent optical anti-reflective properties and effectively suppress the standing wave effect during the photolithography stage. The third etching operation uses a CF4 / CHF3 gas combination, and the carbon-fluorine ratio can be adjusted by adjusting the gas ratio, thereby reducing the etching degree of other film structures while efficiently removing the anti-reflective layer 221.

[0095] In some embodiments, the mask layer 222 is made of carbon; the gas used in the fourth etching operation includes carbon dioxide, hydrogen, and a protective gas.

[0096] In this embodiment, the carbon material mask layer 222 has excellent etching resistance and thermal stability. In the third etching operation, it can effectively block the over-etching of the etching gas and reduce the probability of the first dielectric layer 210 being damaged by the third etching operation. The fourth etching operation uses a combination of carbon dioxide, hydrogen and protective gas, which can efficiently remove the mask layer 222 to form the second via 252.

[0097] In some embodiments, the aspect ratio of the air gap 300 is 2-8.

[0098] Among them, such as Figure 7 As shown, the aspect ratio can be the ratio of the depth D to the width W of an air gap of 300.

[0099] In this embodiment, by controlling the aspect ratio of the air gap 300 within the range of 2-8, the air gap 300 can have sufficient depth to achieve effective reduction of parasitic capacitance, while also reducing the risk that excessive depth of the air gap 300 may affect the stability of use.

[0100] The following is a specific example.

[0101] Provide such as Figure 2 The intermediate structure shown includes a substrate 100, a third dielectric layer 230, a first dielectric layer 210, a mask layer 222, an anti-reflection layer 221, and a pattern layer 240 stacked sequentially.

[0102] The substrate 100 is made of silicon and integrates transistors; the third dielectric layer 230 is made of silicon nitride; the first dielectric layer 210 is made of silicon oxide and has multiple spaced-apart metal structures 211; the metal structures 211 extend in a direction perpendicular to the surface of the substrate 100 and are made of copper; the mask layer 222 is made of amorphous carbon; the anti-reflective layer 221 is made of silicon oxide; and the pattern layer 240 is fabricated using photoresist and has multiple openings 241, the orthographic projections of which are located between the multiple metal structures 211 on the plane of the first dielectric layer 210.

[0103] The third etching operation is performed, using CF4 / CHF3 gas in a specific ratio to etch the anti-reflective layer 221 through the opening 241 of the patterned layer 240, to form a first via 251 corresponding to the opening 241 in the anti-reflective layer 221. The etching pressure is <100 mT, and the total RF power is <1000 W, resulting in the following... Figure 3 The structure shown.

[0104] The fourth etching operation was performed using CO2 / H. 2 / N2 gas is used to etch the pattern layer 240 and the mask layer 222 at a specific ratio to remove the pattern layer 240 and form a second via 252 corresponding to the first via 251 in the mask layer 222. The etching pressure is <100 mT and the total RF power is <1500 W, resulting in the following: Figure 4 The structure shown.

[0105] The first etching operation is performed using C4F8 / O2 / Ar / N2 gas in a specific ratio through the first via 251 and the second via 252 to etch the first dielectric layer 210 located between the metal structure 211, while simultaneously removing the anti-reflection layer 221. The etching pressure is <100 mT and the total RF power is <2500 W, resulting in the following: Figure 5 In the structure shown, this step etches the first dielectric layer 210 until the thickness of the remaining first dielectric layer 210 between the metal structures 211 is a first preset thickness.

[0106] The second etching operation is performed, using C4F6 / O2 / Ar gas in a specific ratio through the second via 252 to continue etching the first dielectric layer 210 located between the metal structures 211, while simultaneously removing the mask layer 222. The etching pressure is <100 mT, and the total RF power is <3500 W. This step involves O... x With a SiN etching selectivity > 10, while ensuring the complete removal of the bottom first dielectric layer 210, the etching stops precisely on the third dielectric layer 230, ensuring that the remaining thickness of the third dielectric layer 230 is greater than or equal to the second preset thickness, thus completing the fabrication of the air gap 300, resulting in the desired shape. Figure 6 The structure shown has an air gap of 300 with an aspect ratio in the range of 2-8.

[0107] This fabrication method precisely controls the position of the opening 241 of the pattern layer 240 and performs anisotropic dry etching on the intermediate structure. The second etching sub-operation has a high etching selectivity, which can form an air gap 300 between adjacent metal structures 211 without affecting the substrate 100 and the metal structure 211. There is no need to prepare intermediate layers or protective layers during the etching process. The air gap 300 prepared can effectively reduce the parasitic capacitance between metal structures 211, improve the signal response speed, and the process is simple and has high production efficiency.

[0108] This application also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method described above.

[0109] According to the semiconductor structure provided in the embodiments of this application, by precisely controlling the position of the opening 241 of the pattern layer 240, and performing a first etching operation and a second etching operation on the intermediate structure, the first etching operation and the second etching operation adopt anisotropic dry etching, and the second etching operation has a higher etching selectivity, which can form an air gap 300 between adjacent metal structures 211 without affecting the substrate 100 and the metal structure 211. There is no need to prepare intermediate layers or protective layers during the etching process. The air gap 300 of this semiconductor structure can effectively reduce the parasitic capacitance between metal structures 211, improve the signal response speed, and the process is simple and the production efficiency is high.

[0110] This application also provides an electronic device, which includes the semiconductor structure described above.

[0111] According to the electronic device provided in the embodiments of this application, the semiconductor structure in the electronic device precisely controls the position of the opening 241 of the pattern layer 240 and performs a first etching operation and a second etching operation on the intermediate structure. The first etching operation and the second etching operation adopt anisotropic dry etching, and the second etching operation has a higher etching selectivity. It can form an air gap 300 between adjacent metal structures 211 without affecting the substrate 100 and the metal structure 211. There is no need to prepare intermediate layers or protective layers during the etching process. The air gap 300 of the semiconductor structure can effectively reduce the parasitic capacitance between metal structures 211, improve the signal response speed, and the process is simple and the production efficiency is high.

[0112] This application also provides a chip, which includes the semiconductor structure described above.

[0113] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0114] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0115] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0116] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0117] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0118] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: An intermediate structure is provided, the intermediate structure comprising a substrate, a first dielectric layer, a second dielectric layer and a pattern layer stacked sequentially, the first dielectric layer comprising a plurality of metal structures spaced apart from each other, the pattern layer having an opening that exposes the second dielectric layer, the orthographic projection of the opening onto the plane of the first dielectric layer being spaced apart from the orthographic projection of the plurality of metal structures onto the plane of the first dielectric layer. A first etching operation is performed to remove the patterned layer and a portion of the second dielectric layer, so that the remaining second dielectric layer has a via corresponding to the opening; A second etching operation is performed to remove the first dielectric layer between the remaining second dielectric layer and the plurality of metal structures, so as to form an air gap between the plurality of metal structures, the air gap being used to achieve electrical isolation between the plurality of metal structures; Wherein, the first etching operation and the second etching operation are dry etching operations, and the etching selectivity of the second etching operation for the first dielectric layer and the substrate is greater than that of the first etching operation.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first dielectric layer is made of silicon oxide, and the substrate is made of silicon; the gas used in the second etching operation includes C4F6, oxygen, and a protective gas.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The second etching operation includes a first etching sub-operation and a second etching sub-operation; The second etching operation, which removes the first dielectric layer between the remaining second dielectric layer and the plurality of metal structures, includes: A first etching operation is performed to remove a portion of the second dielectric layer and a portion of the first dielectric layer located between the plurality of metal structures, such that the thickness of the remaining first dielectric layer located between the plurality of metal structures is less than or equal to a first preset thickness. A second etching sub-operation is performed to remove the remaining second dielectric layer and the first dielectric layer located between the plurality of metal structures to form an air gap between the plurality of metal structures, wherein the etching selectivity ratio of the second etching sub-operation for the first dielectric layer and the substrate is greater than 10.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The first dielectric layer is made of silicon oxide, and the substrate is made of silicon. The gases used in the first etching operation include C4F8, oxygen, and a protective gas; The gases used in the second etching operation include C4F6, oxygen, and a protective gas.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that, The first preset thickness is less than or equal to 10% of the thickness of the first dielectric layer.

6. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, The intermediate structure further includes a third dielectric layer, which is located between the substrate and the first dielectric layer; The second etching operation, which removes the first dielectric layer between the remaining second dielectric layer and the plurality of metal structures, includes: The second etching operation is performed to remove the remaining second dielectric layer, the first dielectric layer between the plurality of metal structures, and part of the third dielectric layer, so that the thickness of the remaining third dielectric layer is greater than or equal to the second preset thickness.

7. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, The second dielectric layer includes an anti-reflective layer and a mask layer. The mask layer is located on the surface of the first dielectric layer opposite to the substrate, and the anti-reflective layer is located on the surface of the mask layer opposite to the substrate. The opening exposes the anti-reflective layer. The first etching operation includes a third etching sub-operation and a fourth etching sub-operation; The first etching operation, which removes the patterned layer and a portion of the second dielectric layer, includes: The third etching operation is performed to remove a portion of the anti-reflective layer, so that the remaining anti-reflective layer has a first through-hole corresponding to the opening; The fourth etching operation is performed to remove the pattern layer and part of the mask layer, so that the remaining mask layer has a second via corresponding to the first via.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The anti-reflective layer is made of at least one of silicon oxide, silicon nitride, and silicon oxynitride; the gas used in the third etching operation includes CF4 and CHF3.

9. The method for preparing a semiconductor structure according to claim 7, characterized in that, The mask layer is made of carbon; the gas used in the fourth etching operation includes carbon dioxide, hydrogen, and a protective gas.

10. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, The aspect ratio of the air gap is 2-8.

11. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the semiconductor structure preparation method as described in claims 1-10.

12. An electronic device, characterized in that, The electronic device includes the semiconductor structure as described in claim 11.

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