Semiconductor device and method of manufacturing the same
Patent Information
- Application Number
- CN202510921629.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-02-20
- Filing Date
- 2025-07-04
- Publication Date
- 2026-08-21
Smart Images
Figure CN122622657A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology
[0002] NAND flash memory and other semiconductor memory devices sometimes have a three-dimensional memory cell array that arranges multiple memory cells in three dimensions. Contacts for connecting to word lines are formed in the lead-out area of the three-dimensional memory cell array. It is desirable to reduce the number of steps required to form these contacts. Summary of the Invention
[0003] The problem to be solved by the present invention is to provide a semiconductor device and a method thereof that can reduce the number of processes.
[0004] The semiconductor device of this embodiment includes a first laminate and a plurality of first pillars. A first insulating film and a first conductive film are alternately laminated on the first laminate in a first direction. The plurality of first pillars extend in the first direction through the first laminate and include a conductor electrically connected to any one of the first conductive films. The first laminate has a plurality of protrusions that project in the first direction corresponding to the shape of a plurality of trenches, either at the lower part of the first laminate, within the first laminate, or both at the lower part of the first laminate and within the first laminate. The first pillars penetrate the mating portion of the first conductive film inside the trench structure and are electrically connected to the first conductive film.
[0005] The semiconductor device manufacturing method of this embodiment includes the following steps: forming a plurality of first trenches on a material film; alternately stacking a first insulating film and a first sacrificial film along a first direction on the material film and the plurality of first trenches to form a second laminate; forming a plurality of holes extending along the first direction and penetrating a portion of the mating portion of the first sacrificial film inside the plurality of first trenches and the second laminate; removing a portion of the first sacrificial film from the inner side of the holes; forming a second insulating film on the inner side of the holes; removing the second insulating film until the mating portion is exposed; filling the holes with a second sacrificial film; replacing the first sacrificial film with a first conductive film; and forming a plurality of first columnar bodies by replacing the second sacrificial film with a conductor. Attached Figure Description
[0006] Figure 1 This is a block diagram illustrating a configuration example of a semiconductor memory device according to the first embodiment.
[0007] Figure 2 This is a circuit diagram illustrating an example of the circuit structure of the memory cell array of the semiconductor memory device according to the first embodiment.
[0008] Figure 3This is a top view showing an example of a planar layout of a portion of the memory cell array of the semiconductor memory device according to the first embodiment.
[0009] Figure 4 This is a top view showing an example of the planar layout of a portion of the storage area of the semiconductor memory device according to the first embodiment.
[0010] Figure 5 This is a cross-sectional view showing a portion of the storage region of the semiconductor memory device according to the first embodiment.
[0011] Figure 6 This is a cross-sectional view showing the structure of the storage column of the semiconductor memory device according to the first embodiment.
[0012] Figure 7 This is a top view showing the positional relationship of the support pillars, trenches, and contact plugs of the semiconductor memory device according to the first embodiment.
[0013] Figure 8A This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.
[0014] Figure 8B It continues Figure 8A A cross-sectional view illustrating a method for manufacturing a semiconductor memory device.
[0015] Figure 8C It continues Figure 8B A cross-sectional view illustrating a method for manufacturing a semiconductor memory device.
[0016] Figure 8D It continues Figure 8C A cross-sectional view illustrating a method for manufacturing a semiconductor memory device.
[0017] Figure 8E It continues Figure 8D A cross-sectional view illustrating a method for manufacturing a semiconductor memory device.
[0018] Figure 9 This is a cross-sectional view showing a portion of the lead-out area of a comparative example semiconductor memory device.
[0019] Figure 10A This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.
[0020] Figure 10B It continues Figure 10A A cross-sectional view illustrating a method for manufacturing a semiconductor memory device.
[0021] Figure 10C It continues Figure 10B A cross-sectional view illustrating a method of manufacturing a semiconductor memory device.
[0022] Figure 10D It is next Figure 10C A cross-sectional view illustrating a method of manufacturing a semiconductor memory device.
[0023] Description of Reference Numerals
[0024] 100: Semiconductor memory device
[0025] 10: Memory cell array
[0026] 23: Conductor
[0027] 23a: Sacrificial film
[0028] 231, 231a: Alignment portion (Japanese: Gasshoubu)
[0029] 30 - 37: Insulator
[0030] 50: Core
[0031] 51: Semiconductor
[0032] 52: Stacked body
[0033] 61: Conductor
[0034] 72: Sacrificial film
[0035] 80: Insulator
[0036] CC: Contact plug
[0037] CH: Contact hole
[0038] HA1, HA2: Lead-out area
[0039] P, Pa: Protrusion
[0040] S1, S1a, S11, S11a, S12, S12a: Stacked body
[0041] TR: Trench
[0042] WL: Word line Detailed Description of the Embodiment
[0043] Hereinafter, embodiments of the present invention will be described with reference to the drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of the respective parts are not necessarily the same as in reality. In the specification and the drawings, for elements that are the same as those already described in the drawings, the same reference numerals are given and detailed descriptions are appropriately omitted.
[0044] (First Embodiment)
[0045] (Configuration of the semiconductor memory device 100)
[0046] Figure 1 This is a block diagram illustrating a configuration example of the semiconductor memory device 100 according to the first embodiment. The semiconductor memory device 100 is, for example, a NAND flash memory capable of non-volatile data storage, and is controlled by an external memory controller 1002. Communication between the semiconductor memory device 100 and the memory controller 1002, for example, supports the NAND interface standard.
[0047] like Figure 1 As shown, the semiconductor memory device 100 includes, for example, a memory cell array 10, an instruction register 1011, an address register 1012, a sequence generator 1013, a driver module 1014, a row decoder module 1015, and a sense amplifier module 1016.
[0048] The storage cell array 10 comprises multiple blocks BLK(0) to BLK(n) (n being an integer greater than or equal to 1). A block BLK is a collection of multiple storage cells capable of non-volatile data storage, used, for example, as a data erasure unit. Additionally, the storage cell array 10 includes multiple bit lines and multiple word lines. Each storage cell is associated with, for example, one bit line and one word line. The detailed structure of the storage cell array 10 will be described later.
[0049] The instruction register 1011 holds the instruction CMD received by the semiconductor memory device 100 from the memory controller 1002. The instruction CMD may contain, for example, commands that cause the sequence generator 1013 to perform read operations, write operations, erase operations, etc.
[0050] Address register 1012 holds address information ADD received by semiconductor memory device 100 from memory controller 1002. Address information ADD includes, for example, block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used for selecting block BLK, word lines, and bit lines, respectively.
[0051] The sequence generator 1013 controls the overall operation of the semiconductor memory device 100. For example, the sequence generator 1013 controls the driver module 1014, the row decoder module 1015, and the sense amplifier module 1016 to perform read operations, write operations, erase operations, etc., based on the instruction CMD held in the instruction register 1011.
[0052] The driver module 1014 generates voltages used in read operations, write operations, erase operations, etc. Furthermore, the driver module 1014 applies the generated voltages, for example, to signal lines corresponding to word lines selected based on the page address PA held in the address register 1012.
[0053] The row decoder module 1015 includes multiple row decoders. Each row decoder selects a block BLK within the corresponding memory cell array 10 based on the block address BA held in the address register 1012. Furthermore, the row decoder, for example, transmits a voltage applied to a signal line corresponding to the selected word line to the selected word line within the selected block BLK.
[0054] During a write operation, the read amplifier module 1016 applies the desired voltage to each bit line based on the write data DAT received from the memory controller 1002. Additionally, during a read operation, the read amplifier module 1016 determines the data stored in the memory cell based on the bit line voltage and transmits the determination result as read data DAT to the memory controller 1002.
[0055] The semiconductor memory device 100 and memory controller 1002 described above can also be combined to form a single semiconductor device. Examples of such semiconductor devices include memory cards such as SD™ cards and SSDs (Solid State Drives).
[0056] Figure 2 This is a circuit diagram illustrating an example of the circuit structure of the memory cell array 10. One block BLK is extracted from the plurality of blocks BLK contained in the memory cell array 10. For example... Figure 2 As shown, block BLK contains multiple string units SU(0) to SU(k) (k is an integer greater than or equal to 1).
[0057] Each string cell SU contains multiple NAND strings NS associated with bit lines BL(0) to BL(m) (where m is an integer greater than or equal to 1). Each NAND string NS contains, for example, memory cell transistors MT(0) to MT(15) and select transistors ST(1) and ST(2). The memory cell transistor MT contains a control gate and a charge storage layer, which non-volatilely stores data. The select transistors ST(1) and ST(2) are used to select the string cell SU for various operations.
[0058] In each NAND string NS, memory cell transistors MT(0) to MT(15) are connected in series. The drain of selector transistor ST(1) is connected to the associated bit line BL, and the source of selector transistor ST(1) is connected to one end of the series-connected memory cell transistors MT(0) to MT(15). The drain of selector transistor ST(2) is connected to the other end of the series-connected memory cell transistors MT(0) to MT(15). The source of selector transistor ST(2) is connected to the source line SL.
[0059] In the same BLK, the control gates of the memory cell transistors MT(0) to MT(15) are connected to word lines WL(0) to WL(7). The gates of the selection transistors ST(1) in the serial cells SU(0) to SU(k) are connected to the selection gates SGD(0) to SGD(k). The gates of the selection transistor ST(2) are connected to the selection gate line SGS.
[0060] In the circuit structure of the memory cell array 10 described above, the bit line BL is shared by the NAND strings NS in each string cell SU that are assigned the same column address. The source line SL is shared, for example, among multiple blocks BLK.
[0061] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string cell SU is called a cell group CU. For example, the storage capacity of a cell group CU containing memory cell transistors MT that each store 1 bit of data is defined as "1 page of data". Depending on the number of bits of data stored by the memory cell transistors MT, a cell group CU can have a storage capacity of 2 pages or more.
[0062] Furthermore, the memory cell array 10 included in the semiconductor memory device 100 of this embodiment is not limited to the circuit structure described above. For example, the number of memory cell transistors MT and selection transistors ST(1) and ST(2) included in each NAND string NS can be designed to be any number. The number of string cells SU included in each BLK can be designed to be any number.
[0063] Figure 3 This is a top view showing an example of the planar layout of a portion of the memory cell array 10 of the semiconductor memory device 100 according to the first embodiment. Figure 3 The region consisting of four blocks BLK_0 to BLK_3 is shown along the xy plane. Figure 3 The structure shown is repeatedly set along the y-axis.
[0064] like Figure 3 As shown, the memory cell array 10 includes a memory region MA, a lead-out region HA1, and a lead-out region HA2. The lead-out region HA1, memory region MA, and lead-out region HA2 are arranged in this order along the x-axis. Multiple slots SLT and slots SHE are provided in the memory cell array 10.
[0065] The storage region MA is a region containing multiple NAND strings NS. The lead-out regions HA1 and HA2 are regions where contact plugs are provided, which are connected to the stacked structure in which storage cell transistors are formed.
[0066] A plurality of slits SLT extend along the x-axis and are arranged along the y-axis. Each slit SLT is located at the boundary between adjacent blocks BLK. The slit SLT crosses the storage area MA, the lead-out area HA1, and the lead-out area HA2. The slit SLT has, for example, a structure in which an insulator and / or a plate-like contact member is embedded. Each slit SLT cuts off the stacked structures adjacent to each other across itself.
[0067] A plurality of slits SHE extend along the x-axis and are arranged along the y-axis. The slit SHE is located between every two adjacent slits SLT. Figure 4 An example of four slits SHE is shown. Each slit SHE crosses the storage area MA along the x-axis. Both ends of each slit SHE are respectively located in the lead-out area HA1 and the lead-out area HA2. Each slit SHE includes, for example, an insulator. Each slit SHE cuts off the selection gate lines SGDL adjacent to each other across itself. Each area divided by the slit SLT and the slit SHE is an area for forming one string unit SU.
[0068] Figure 4 It is a top view showing an example of a planar layout of a part of the storage area MA of the semiconductor storage device 100 according to the first embodiment. Figure 4 An example of one block BLK, that is, an area including string units SU0 to SU4 and two slits SLT sandwiching the block BLK is shown. As Figure 4 shown, the memory cell array 10 includes a plurality of memory posts MP, a plurality of contact plugs CV, and a plurality of conductors 25 in the storage area MA. Each slit SLT includes a contact member LI and a separator SP.
[0069] The memory post MP has a structure in which a memory cell transistor MT is formed inside. The memory post MP is an example of the second columnar body. The memory post MP includes one or more of a semiconductor, a conductor, and an insulator. The memory post MP functions as one NAND string NS. A plurality of memory posts MP are distributed in a staggered arrangement (Japanese: chidori arrangement) in the area between two slits SLT. That is, a plurality of memory posts MP are arranged in a plurality of columnar shapes along the y-axis, and each column of the memory posts MP is arranged in a zigzag shape along the y-axis. In other words, each column includes two sub-columns. The coordinates of each memory post MP on the y-axis in one sub-column are located between the coordinates on the y-axis of two adjacent memory posts MP in the other sub-column. Each column includes, for example, 24 memory posts MP.
[0070] The slit SHE overlaps, for example, with Figure 4 the 5th, 10th, 15th, and 20th memory posts MP from the top.
[0071] Each conductor 25 functions as a bit line BL. The conductors 25 extend along the y-axis and are arranged along the x-axis. Each conductor 25 is configured in each string cell SU to overlap with at least one memory column MP. Figure 4 An example is shown where two conductors 25 are arranged to overlap with one memory column MP. Each memory column MP is electrically connected to one of the multiple conductors 25 overlapping with it via a contact plug CV.
[0072] Contact LI contains a conductor. Contact LI extends along the xz plane and has a plate-like shape. The spacer SP is an insulator located on the side of contact LI, for example, covering the side of contact LI.
[0073] Figure 5 This is a cross-sectional view showing a portion of the storage region MA of the semiconductor memory device 100 according to the first embodiment. Figure 5 It is along Figure 4 A cross-sectional view of the CC line.
[0074] like Figure 5 As shown, the memory cell array 10 includes a substrate 20, conductors 21 and 22, multiple conductors 23, conductors 24 and 25, and insulators 30 to 37. Figure 5 An example of eight conductors 23 is shown. Insulators 30-37, in addition to insulator 31, may contain, for example, silicon oxide.
[0075] The substrate 20 is, for example, a p-type semiconductor substrate. An insulator 30 is located on the upper surface of the substrate 20. Circuits (not shown) are formed in the substrate 20 and the insulator 30. The circuits include, for example, an instruction register 1011, an address register 1012, a sequence generator 1013, a driver module 1014, a row decoder module 1015, and a sense amplifier module 1016, and also include transistors (not shown).
[0076] Insulator 31 is located on the upper surface of insulator 30. Insulator 31, for example, inhibits the intrusion of hydrogen from the structure above insulator 31 into substrate 20 and the transistor contained in insulator 30. Insulator 31, for example, contains silicon nitride (SiN).
[0077] Insulator 32 is located on the upper surface of insulator 31.
[0078] Conductor 21 is located on the upper surface of insulator 32. Conductor 21 extends along the xy plane and has a plate-like shape. Conductor 21 functions as at least part of source line SL. Conductor 21 comprises, for example, phosphorus (P)-doped silicon.
[0079] Insulator 33 is located on the upper surface of conductor 21.
[0080] Conductor 22 is located on the upper surface of insulator 33. Conductor 22 extends along the xy plane and has a plate-like shape. Conductor 22 functions as at least a portion of the select gate line SGSL. Conductor 22 contains, for example, tungsten (W).
[0081] Multiple insulators 34 and multiple conductors 23 are alternately arranged one by one along the z-axis on the upper surface of conductor 22. The insulator 34 is an example of a first insulating film, and the conductor 23 is an example of a first conductive film. The z-axis is an example of a first direction. Multiple insulators 34 and multiple conductors 23 are alternately stacked along the z-axis, thereby forming a laminate S1. The laminate S1 is an example of a first laminate. In the laminate S1, the conductors 23 are separated from each other or arranged at intervals along the z-axis. The insulators 34 and conductors 23 extend along the xy-plane and have a plate-like shape. The multiple conductors 23 function as word lines WL0 to WL7 sequentially from one side of the substrate 20. The conductors 23 may contain, for example, tungsten.
[0082] The insulator 35 is located on the upper surface of the uppermost conductor 23.
[0083] Conductor 24 is located on the upper surface of insulator 35. Conductor 24 extends along the xy plane and has a plate-like shape. Conductor 24 functions as at least a portion of the select gate line SGDL. Conductor 24 contains tungsten.
[0084] Insulator 36 is located on the upper surface of conductor 24.
[0085] Conductor 25 is located on the upper surface of insulator 36. Conductor 25 has a linear shape and extends along the y-axis. Conductor 25 functions as at least a portion of a bit line BL. Figure 5 Conductors 25 are also provided in different yz planes shown, and therefore, conductors 25 are arranged at intervals along the x-axis. Conductors 25 may contain, for example, copper.
[0086] Insulator 37 is located on the upper surface of conductor 25.
[0087] The memory pillar MP extends along the z-axis and has a pillar shape. The memory pillar MP is an example of a second pillar-like structure. The memory pillar MP extends along the z-axis within the stack S1. The upper surface of the memory pillar MP is located above conductor 24. The lower surface of the memory pillar MP is located within conductor 21. The portion of the memory pillar MP that connects to conductor 22 functions as a select gate transistor ST. The portion of the memory pillar MP that connects to one conductor 23 functions as a memory cell transistor MT. The portion of the memory pillar MP that connects to conductor 24 functions as a select transistor DT.
[0088] The storage column MP includes, for example, a core 50, a semiconductor 51, and a stack 52. The core 50 is made of an insulator, such as silicon oxide. The core 50 extends along the z-axis and has a columnar shape. The semiconductor 51 includes, for example, silicon. The semiconductor 51 is an example of a first semiconductor portion. The semiconductor 51 covers the surface of the core 50. The stack 52 covers the side and bottom surfaces of the semiconductor 51. The stack 52 is an example of a first insulating portion. The stack 52 has an opening in a conductor 21, which is partially located within the opening. The conductor 21 is connected to the semiconductor 51 within the opening.
[0089] As described above, one storage column MP is connected to one conductor 25 via a contact plug CV.
[0090] The slit SLT cuts off conductors 22-24. The upper surface of the slit SLT is located above the upper surface of the storage column MP. The lower surface of the contact LI is in contact with conductor 21. The separator SP is located between the contact LI and conductors 22-24, insulating the contact LI from the conductors 22-24. The contact LI functions as part of the source line SL.
[0091] The slit SHE cuts off the conductor 24. The lower surface of the slit SHE is located within the insulator 35. The slit SHE may contain an insulator such as silicon oxide.
[0092] Figure 6 The structure of a cross-section of the storage column MP of the semiconductor memory device 100 according to the first embodiment is shown. Figure 6 It shows along Figure 5 The cross-section of the DD line. For example... Figure 6 As shown, the laminate 52 includes, for example, a tunnel insulating film 53, a charge storage film 54, and a block insulating film 55.
[0093] A tunnel insulating film 53 covers the outer periphery of the semiconductor 51. A charge storage film 54 covers the outer periphery of the tunnel insulating film 53. A bulk insulating film 55 covers the outer periphery of the charge storage film 54. A conductor 23 covers the outer periphery of the bulk insulating film 55.
[0094] Semiconductor 51 functions as a channel (current path) for memory cell transistors MT0 to MT7 and selection transistors DT and ST. The tunnel insulating film 53 and the block insulating film 55 each comprise, for example, silicon oxide. The charge storage film 54 stores charge. The charge storage film 54 comprises, for example, silicon nitride.
[0095] (Explanation of support column HR and contact plug CC)
[0096] Here, refer to Figure 7 The support column HR and the contact plug CC are described in detail.
[0097] Figure 7 It is a top view showing the positional relationship between the support post HR, the groove TR, and the contact plug CC. Figure 7 It is Figure 3 The top view of region B is shown in the enlarged illustration.
[0098] Figure 7 The grooves TR1 and TR2 and the contact plugs CC1 and CC2 have structures with different dimensions. Hereinafter, in some cases, the grooves TR1 and TR2 will be collectively referred to as groove TR, and the contact plugs CC1 and CC2 will be collectively referred to as contact plugs CC.
[0099] The contact plug CC is arranged to extend along the z-axis in the laminate S1. The contact plug CC is an example of a first columnar body. The contact plug CC is, for example, arranged between adjacent support columns HR. The contact plug CC and the support column HR can be in contact with each other or separated. The number of contact plugs CC arranged in the lead-out area HA1 is arbitrary.
[0100] When viewed from above in the z-direction, the shape of the contact plug CC is, for example, roughly rectangular. However, the shape of the contact plug CC when viewed from the z-direction is not limited to roughly rectangular; it can also be roughly circular or roughly elliptical, etc.
[0101] The support pillars HR are arranged to extend along the z-axis in the laminate S1. The support pillars HR function as pillars to prevent the laminate S1 (memory cell array 10) from collapsing during the replacement process described later. Therefore, the support pillars HR need to be arranged at intervals below a specified value (intervals below those that can prevent collapse). The support pillars HR have a pillar shape and extend from the insulator 36 along the z-axis to reach the conductor 21. The support pillars HR may contain, for example, an insulator such as silicon oxide. The number of support pillars HR arranged in the lead-out region HA1 is arbitrary.
[0102] like Figure 7 As shown, the support columns HR are installed throughout the entire lead-out area HA1 at intervals below a specified value. Each support column HR has a roughly circular top view shape.
[0103] The groove TR is a groove extending along the z-axis from the bottom surface of the laminate S1. The groove TR is positioned to overlap with the contact plug CC when viewed from above in the z-direction.
[0104] When viewed from above in the z-direction, the shape of the groove TR is, for example, roughly rectangular. However, the shape of the contact plug when viewed from the z-direction is not limited to roughly rectangular.
[0105] exist Figure 7 In China, Figure 3The support post HR, groove TR, and contact plug CC in the lead-out area HA1 have been described. The support post HR, groove TR, and contact plug CC can also be constructed in the lead-out area HA2 in the same way.
[0106] (Manufacturing method of semiconductor memory device 100)
[0107] Next, the manufacturing method of the semiconductor memory device 100 will be described.
[0108] Figures 8A to 8E This is a cross-sectional view illustrating each step of the manufacturing method of the semiconductor memory device 100 according to the first embodiment. Figures 8A to 8E The image above shows the points along... Figure 7 The cross-section of the EE line (the short side of the trench TR) is illustrated. Figures 8A to 8E The following diagram shows the lines along... Figure 7 The cross-section of the FF line (the long side of the groove TR) is illustrated.
[0109] First, such as Figure 8A As shown, an insulator 30 is formed on substrate 20. Insulator 30 is an example of a third insulating film. Then, trenches TR are formed on insulator 30. Substrate 20 is, for example, a semiconductor substrate such as a silicon substrate.
[0110] Next, as Figure 8B As shown, a laminate S1a is formed on the insulator 30 and the trench TR by alternately stacking sacrificial film 23a and insulator 34 along the z-axis direction. Then, an insulator 36 is formed on the laminate S1a. The insulators 34 and 36 are, for example, silicon oxide films, and the sacrificial film 23a is, for example, a silicon nitride film.
[0111] Insulator 34 and sacrificial film 23a are alternately laminated inside the trench TR, and a portion of the sacrificial film 23a closes the trench TR using mating surfaces. The portion of the trench TR closed by the sacrificial film 23a is called mating portion 231a. Corresponding to the shape of the trench TR, a protrusion Pa is formed at the lower part of the laminate S1a.
[0112] Next, as Figure 8C As shown, a contact hole CH is formed for the contact plug CC. The contact hole CH penetrates a portion of the mating portion 231a of the sacrificial film 23a inside the trench TR1 and the laminate S1a. More specifically, a hard mask 70 is formed on the insulator 36. The hard mask 70 may be, for example, silicon nitride. Then, using the hard mask 70 as a mask, an anisotropic etching process based on photolithography and RIE (Reactive Ion Etching) is used to form a contact hole CH that penetrates the laminate S1a along the z-direction.
[0113] like Figure 8C As shown in the diagram above, the width of the contact hole CH in the x-direction is greater than the width of the trench TR in the x-direction (width of the shorter side). Figure 8C As shown in the figure below, the width of the contact hole CH in the y direction is smaller than the width of the trench TR in the y direction (width of the long side).
[0114] Next, as Figure 8D As shown, a portion of the sacrificial film 23a is removed from the inner side of the contact hole CH (making it recessed). This forms a recess in which a portion of the sacrificial film 23a is removed.
[0115] exist Figure 8D In the example shown in the figure below, the width of the recess in the z-direction of the bottommost sacrificial membrane 23a is greater than the width of the recess in the z-direction of the sacrificial membranes 23a other than the bottommost layer.
[0116] Subsequently, an insulator 80 (separator) is formed on the inner surface of the contact hole CH. The insulator 80 is an example of a second insulating film. The insulator 80 is, for example, made of silicon oxide. The recesses of the sacrificial film 23a other than the bottommost layer are filled and sealed by the insulator 80. On the other hand, the recesses of the bottommost sacrificial film 23a have an insulator 80 formed on their surface, but are not sealed.
[0117] Next, a portion of the insulator 80 is removed by etching back. This portion of the insulator 80 is removed, for example, by wet etching. More specifically, the insulator 80 is removed until the mating portion 231a is exposed. The insulator 80 embedded in the recess of the sacrificial film 23a outside the bottom layer is not removed and remains. On the other hand, all the insulator 80 within the recess of the bottom sacrificial film 23a is removed. Therefore, the mating portion 231a is not covered by the insulator 80 but is exposed on the side of the contact hole CH.
[0118] Next, a sacrificial film 72 is embedded in the contact hole CH, and then etched back. The sacrificial film 72 is, for example, made of amorphous silicon.
[0119] Next, as Figure 8E As shown, a slit SLT is formed. Then, the sacrificial film 23a is replaced (replaced) with the conductor 23 (word line WL) via the slit SLT. The mating portion 231a of the sacrificial film 23a becomes the mating portion 231 of the conductor 23 after replacement. Next, a contact plug CC is formed by replacing the sacrificial film 72 with the conductor. The contact plug CC is connected to and electrically connected to the mating portion 231. Then, planarization is performed. Furthermore, the slit SLT is filled after the replacement of the conductor 23. Then, the semiconductor memory device 100 is completed through processes not shown.
[0120] Figures 8A-8E The process shown is performed on multiple trenches TR, not just trench TR1. Figure 8A In the process shown, multiple grooves TR with different widths are formed along a direction intersecting the z-direction (e.g., Figure 7 The trenches TR1 and TR2 shown are arranged so that the central portion of the trench TR is closed by different sacrificial membranes 23a. Figure 7 As shown, multiple contact plugs CC1 and CC2 can also have different widths in the direction intersecting the z-direction. Figure 8C In the process shown, a plurality of contact holes CH are formed such that at least a portion of the outer edge of the mating portion 231a extends beyond the outer edge of the contact hole CH when viewed from the z direction.
[0121] In addition, Figure 7 Two trenches TR1 and TR2 are shown, but more than three trenches can also be formed. By changing the width of the trenches TR1 and TR2 to form the trenches TR, contact plugs CC that are electrically connected to multiple conductors 23 can be formed in a single photolithography process (PEP).
[0122] The semiconductor memory device 100 includes a stack S1 and a plurality of contact plugs CC. The plurality of contact plugs CC extend in the z-direction through the stack S1. The plurality of contact plugs CC includes a conductor electrically connected to any one of the conductors 23. The stack S1 has a plurality of protrusions P in the z-direction at its lower part, corresponding to the shape of the plurality of trenches TR. The contact plugs CC pass through the mating portions 231 of the conductors 23 inside the trenches TR and are electrically connected to the conductors 23.
[0123] Furthermore, around one contact plug CC, the film thickness (film thickness in the z-direction) of the mating portion 231 of the conductor 23 electrically connected to the one contact plug CC is greater than the film thickness of the other conductors 23. Additionally, the mating portion 231 is a part of the conductor that closes the trench TR, which is part of the insulator 34 and conductor 23 stacked along the inner side of the trench TR. Furthermore, the mating portion 231 is located at the center of the trench TR.
[0124] In addition, the multiple trenches TR have different widths in the direction intersecting the z-direction, so that the central part of the trenches TR is closed by different conductors 23.
[0125] Furthermore, when viewed from the z-direction, the contact plug CC can have a generally elliptical or generally rectangular shape. Additionally, when viewed from the z-direction, both the contact plug CC and the groove TR can have a generally rectangular shape. In this case, when viewed from the z-direction, the longer side of the contact plug CC can be longer than the shorter side of the mating portion 231. Furthermore, when viewed from the z-direction, at least a portion of the outer edge of the mating portion 231 preferably extends beyond the outer edge of the contact plug CC.
[0126] Furthermore, the first embodiment is not limited to the semiconductor memory device 100, but can also be applied to semiconductor devices and the like that form contact elements with oriented stacked electrode contacts.
[0127] As described above, according to the first embodiment, the laminate S1 has a plurality of protrusions P that protrude in the z-direction corresponding to the shape of the plurality of trenches TR, either in the lower part of the laminate S1, in the laminate S1, or in both the lower part and the laminate S1. The contact plug CC penetrates the mating portion 231 of the conductor 23 inside the trench TR and is electrically connected to the conductor 23. This reduces the number of steps required to form the contact plug CC.
[0128] In addition, Figure 8C In the process shown, the contact hole CH is formed in such a way that it penetrates a portion of the mating portion 231a of the sacrificial film 23a. Additionally, in Figure 8C In the illustrated process, the contact hole CH is formed such that at least a portion of the outer edge of the mating portion 231a extends beyond the outer edge of the contact hole CH when viewed from above in the z-direction. Thus, the replaced mating portion 231 and the contact plug CC are connected to each other. Consequently, the mating portion 231 and the contact plug CC are electrically connected to each other.
[0129] In addition, Figure 8B In the process shown, the width of the short side (width in the x-direction) of the groove TR is adjusted such that the mating portion 231a is formed by sealing the groove TR with a sacrificial membrane 23a. Figure 8B In the example shown, the mating portion 231a is formed using the bottommost sacrificial film 23a. By changing the width of the short side of the groove TR, for example, the word line WL in word lines WL0 to WL7 that are subsequently formed by replacing the sacrificial film 23a can be adjusted to form the mating portion 231. Figure 7 The trench TR2 shown has a width different from that of the trench TR1. The trench TR2 is closed, for example, by a sacrificial membrane 23a that is one layer higher than the bottom layer.
[0130] In addition, by forming multiple trenches TR with different widths in a single photolithography process, it is easier to form multiple contact plugs CC that are respectively connected to multiple conductors 24.
[0131] Figure 9 This is a cross-sectional view showing a portion of the lead-out region HA1 of the semiconductor memory device of the comparative example. The comparative example differs from the first embodiment in that the laminate S1 is formed into a stepped structure and a contact plug CC is formed through the laminate S1.
[0132] In the comparative example, the following steps are required: forming a stepped structure in the laminate S1a, thickening the sacrificial film 23a to connect the conductor 23 to the contact plug CC, filling the stepped structure, and planarizing. In this case, the number of steps is large, making it difficult to reduce costs.
[0133] In contrast, the first embodiment eliminates the need for processes equivalent to forming a stepped structure and for thickening (thickening) the sacrificial film 23a, which replaces the conductor 23. As a result, the number of processes can be reduced. Furthermore, the density of the contact plugs CC can be increased. Consequently, the lead-out regions HA1 and HA2 can be reduced in size.
[0134] (Second Implementation)
[0135] Figures 10A to 10D This is a cross-sectional view illustrating each step of the manufacturing method of the semiconductor memory device 100 according to the second embodiment. The second embodiment differs from the first embodiment in that the trench TR is provided in the laminate S1 (laminate S1a). Furthermore, Figure 10B and Figure 10C In the diagram, the portion of the cross-section that is inside the contact hole CH is also represented by a dashed line.
[0136] exist Figures 10A to 10D In the example shown, the stacked body S1a is divided into two stacked bodies S11a and S12a. Stacked body S12a is positioned above stacked body S11a. Stacked body S11a is an example of a first or second stacked body. Stacked body S12a is an example of a third stacked body.
[0137] First, such as Figure 10A As shown, an insulator 30 is formed on a substrate 20. Then, trenches TR1 and TR2 are formed on the insulator 30. Next, a laminate S11a is formed on the insulator 30 and trenches TR1 and TR2, in which sacrificial film 23a and insulator 34 are alternately stacked along the z-axis. Then, an insulator 38 is formed on the laminate S11a. The material of the insulator 38 is, for example, the same material as the insulator 36. Then, trenches TR3 and TR4 are formed on the insulator 38 and the laminate S11a. Trenches TR3 and TR4 are formed in the xy-plane at positions different from those of trenches TR1 and TR2. Then, a laminate S12a is formed on the insulator 38 and trenches TR3 and TR4, in which sacrificial film 23a and insulator 34 are alternately stacked along the z-axis. Trenches TR3 and TR4 are grooves extending from the bottom surface of the laminate S12a along the z-axis. Alternatively, the insulator 38 may not be formed. In this case, a laminate S12a is formed on the laminate S11a.
[0138] exist Figure 10AIn the example shown, the mating portion 231a of the bottommost sacrificial membrane 23a of the laminate S11a is formed inside the trench TR1. The mating portion 231a of the third sacrificial membrane 23a from the bottom of the laminate S11a is formed inside the trench TR2. The mating portion 231a of the second sacrificial membrane 23a from the bottom of the laminate S12a is formed inside the trench TR3. The mating portion 231a of the fourth sacrificial membrane 23a from the bottom of the laminate S12a is formed inside the trench TR4.
[0139] Next, as Figure 10B As shown, contact holes CH are formed for forming the contact plug CC. Multiple contact holes CH are formed that penetrate a portion of the mating portion 231a inside the trenches TR1, TR2, TR3, and TR4. The method for forming the contact holes CH is the same as in the first embodiment. Figure 8C The procedures shown are the same.
[0140] Next, as Figure 10C As shown, a portion of the sacrificial film 23a is removed from the inner surface of the contact hole CH (making it recessed). Then, an insulator 80 (separator) is formed on the inner surface of the contact hole CH. Subsequently, a portion of the insulator 80 is removed by etchback.
[0141] like Figure 10C As shown, the mating part 231a is not covered by the insulator 80, but is exposed on the side of the contact hole CH.
[0142] Next, as Figure 10D As shown, a sacrificial film 72 is embedded in the contact hole CH and etched back. Then, a slot SLT is formed. Next, the sacrificial film 23a is replaced with a conductor 23 (word line WL) via the slot SLT. The mating portion 231a of the sacrificial film 23a becomes the mating portion 231 of the conductor 23 after replacement. Then, a contact plug CC is formed by replacing the sacrificial film 72 with a conductor. The contact plug CC is electrically connected to the mating portion 231. Then, planarization is performed to expose the hard mask 70.
[0143] The greater the number of layers in the conductor 23, the wider the short side of the resulting trench TR needs to be. By dividing the stacked body S1 into multiple stacked bodies S11 and S12, and forming trenches TR corresponding to each stacked body S11 and S12, the width of the short side of the trench TR corresponding to the upper part of the stacked body S1 can be reduced. For example, Figure 10A The width of trench TR3 in the x-direction is smaller than the width of trench TR2 in the x-direction. This allows for the reduction of the lead-out regions HA1 and HA2.
[0144] Furthermore, the number of divisions in the stack S1 is not limited to 2. By increasing the number of divisions in the stack S1, the width of the trench TR can be reduced. However, increasing the number of divisions increases the number of photolithography steps (PEP steps) required to form the trench TR. Therefore, the number of divisions in the stack S1 must be determined by considering both the area and the number of steps.
[0145] Alternatively, the groove TR at the bottom of the laminate S1 (laminate S1a) may not be provided. However, the groove TR at the bottom of the laminate S1 (laminate S1a) may be provided for contact of the lower layer of the laminate S1.
[0146] As in the second embodiment, the trench TR can also be provided in the stack S1 (stack S1a). The semiconductor memory device 100 of the second embodiment can achieve the same effect as the first embodiment.
[0147] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the scope of the invention as set forth in the claims and its equivalents.
Claims
1. A semiconductor device, characterized in that, have: A first laminate, wherein a first insulating film and a first conductive film are alternately laminated in a first direction; and A plurality of first columnar bodies extend in the first direction in such a manner as to penetrate the first stack, and include a conductor electrically connected to any one of the first conductive films; The first laminate has a plurality of protrusions that protrude in the first direction corresponding to the shape of the plurality of grooves, either in the lower part of the first laminate, or in the first laminate, or in both the lower part of the first laminate and the first laminate. The first columnar body penetrates the mating portion of the first conductive film inside the trench and is electrically connected to the first conductive film.
2. The semiconductor device according to claim 1, characterized in that, Around one of the first columnar bodies, the thickness of the mating portion of the first conductive film electrically connected to the one of the first columnar bodies is greater than the thickness of the other first conductive films.
3. The semiconductor device according to claim 1, characterized in that, The mating portion is a portion of the first conductive film that closes the groove, which is part of the first insulating film and the first conductive film stacked along the inner side of the groove.
4. The semiconductor device according to claim 1, characterized in that, The mating portion is located in the center of the groove.
5. The semiconductor device according to claim 1, characterized in that, The multiple trenches have different widths in directions intersecting the first direction, such that the central portion of the trenches is closed by different first conductive films.
6. The semiconductor device according to claim 1, characterized in that, The first columnar body has a generally elliptical or generally rectangular shape when viewed from the first direction.
7. The semiconductor device according to claim 1, characterized in that, The first columnar body and the groove have a generally rectangular shape when viewed from the first direction. When viewed from the first direction, the long side of the first column is longer than the short side of the mating portion.
8. The semiconductor device according to claim 1, characterized in that, When viewed from the first direction, at least a portion of the outer edge of the mating portion extends beyond the outer edge of the first columnar body.
9. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a second columnar body, which comprises a first semiconductor portion extending along the first direction within the first stack and a first insulator portion disposed on the outer peripheral surface of the first semiconductor portion.
10. A method for manufacturing a semiconductor device, characterized in that, The following steps are required: Multiple first trenches are formed on the material film. A second laminate is formed by alternately stacking a first insulating film and a first sacrificial film along a first direction on the material film and the plurality of first trenches. Multiple holes are formed that extend along the first direction and penetrate a portion of the mating portion of the first sacrificial membrane inside the plurality of first trenches and the second laminate. Remove a portion of the first sacrificial membrane from the inner side of the hole. A second insulating film is formed on the inner surface of the hole. Remove the second insulating film until the mating portion is exposed. Fill the pores with a second sacrificial membrane. Replace the first sacrificial film with the first conductive film. Multiple first columnar bodies are formed by replacing the second sacrificial film with a conductor.
11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The material film is a third insulating film.
12. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The step of forming a plurality of the first trenches includes: forming a plurality of first trenches with different widths along a direction intersecting the first direction, such that the central portion of the first trenches is closed by different first sacrificial membranes.
13. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The step of forming a plurality of said holes includes forming a plurality of said holes such that at least a portion of the outer edge of the mating portion extends beyond the outer edge of said hole when viewed from the first direction.
14. The method for manufacturing a semiconductor device according to claim 10, characterized in that, After the second layer is formed, the following steps are also performed: Multiple second grooves are formed in the second layer. A third laminate is formed by alternately stacking the first insulating film and the first sacrificial film along the first direction on the material film and the plurality of second trenches. The step of forming a plurality of said holes includes: forming a plurality of said holes that pass through a portion of the mating portion inside a plurality of first trenches and a plurality of second trenches.