Process for silicon bridge encapsulation and encapsulation

Abstract

The process method and the package of the silicon bridge package provided by the present disclosure comprise the following steps: taking a carrier plate, manufacturing a first wiring layer on the carrier plate, attaching a first silicon bridge on the first wiring layer, positioning and manufacturing a copper column on the first wiring layer according to the position of the first silicon bridge, attaching a chip on the side of the first silicon bridge and the copper column away from the first wiring layer, and performing plastic packaging on the structure after the chip is attached to form a package. By moving the attaching process of the first silicon bridge to before the copper column is manufactured, the manufacturing of the copper column is performed according to the position of the attached first silicon bridge, the deviation caused by the patching accuracy can be corrected, the deviation accumulation caused by the material stress and the temperature change in the packaging process is reduced, the package deformation is reduced, and the production cost is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of chip packaging technology, and in particular to a process method and package for silicon bridge packaging. Background Technology

[0002] Silicon bridge packaging is a packaging method that achieves high-density, high-performance, short-distance interconnection between multiple chips by embedding small silicon bridge chips. Compared with traditional silicon interposer technology, silicon bridge packaging technology has lower cost and greater flexibility.

[0003] As advanced packaging evolves towards miniaturization and high density, the reduction in package size and the increase in integration density place more stringent demands on the deviation control of silicon bridge chips. Traditional silicon bridge technology is prone to positional misalignment during chip assembly and mounting. Combined with factors such as material stress and temperature changes during the molding process, this may further exacerbate the structural deformation of the package.

[0004] Therefore, how to reduce the dependence on the mounting accuracy of silicon bridge chips during silicon bridge packaging, reduce package deformation, and reduce production costs has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned technical issues, this disclosure provides a silicon bridge packaging process and package, which reduces the dependence on the mounting accuracy of the silicon bridge chip during the silicon bridge packaging process and minimizes package deformation.

[0006] This disclosure provides a process method for silicon bridge packaging, comprising: taking a carrier board and fabricating a first redistribution layer on the carrier board; mounting a first silicon bridge on the first redistribution layer; positioning and fabricating copper pillars on the first redistribution layer according to the position of the first silicon bridge; mounting a chip on the side of the first silicon bridge and the copper pillars away from the first redistribution layer; and molding the structure after mounting the chip to form a package.

[0007] Optionally, mounting the first silicon bridge on the first redistribution layer includes: the size of the first silicon bridge is preset according to the number, size and arrangement of the chips to be mounted.

[0008] Optionally, after positioning and fabricating the copper pillars on the first redistribution layer, the method further includes: the surface of the first silicon bridge further includes short copper pillars; the first silicon bridge and the copper pillars are encapsulated and thinned until the short copper pillars of the first silicon bridge and the surface of the copper pillars are exposed.

[0009] Optionally, mounting the chip on the side of the first silicon bridge and the copper pillar away from the first redistribution layer includes: fabricating a second redistribution layer on the side of the first silicon bridge and the copper pillar away from the first redistribution layer after molding; fabricating a first solder ball layer on the side of the second redistribution layer away from the first redistribution layer; and mounting the chip on the first solder ball layer.

[0010] Optionally, the chip includes at least two types or sizes of sub-chips; the step of mounting the chip on the first solder ball layer specifically involves mounting each of the sub-chips on the first solder ball layer at a preset position, and in a direction perpendicular to the first redistribution layer, each of the mounted sub-chips overlaps with at least a portion of the first silicon bridge.

[0011] Optionally, the step of molding the structure after mounting the chip to form a package specifically involves: molding and thinning the structure after mounting the chip until the surface of the chip is exposed; removing the carrier board; and fabricating a second solder ball layer on the side of the first redistribution layer opposite to the chip.

[0012] Based on the same inventive concept, this disclosure provides a package fabricated using the silicon bridge packaging process described above, comprising: a first redistribution layer and a first silicon bridge located on one side of the first redistribution layer; copper pillars located on the same side of the first redistribution layer as the first silicon bridge, the copper pillars being fabricated according to the position of the first silicon bridge after mounting; a second redistribution layer located on the side of the first silicon bridge and the copper pillars away from the first redistribution layer; a chip located on the side of the second redistribution layer away from the first silicon bridge and the copper pillars, and the chip being connected to the first silicon bridge and the copper pillars via a first solder ball layer; and a second solder ball layer located on the side of the first redistribution layer away from the first silicon bridge.

[0013] Optionally, one of the packages is provided with one first silicon bridge.

[0014] Optionally, the chip includes at least two types or sizes of sub-chips, and any of the sub-chips overlaps with at least a portion of the first silicon bridge along a direction perpendicular to the plane of the first redistribution layer.

[0015] Optionally, the package further includes a packaging layer, at least a portion of which is located between adjacent sub-chips and at least a portion of which is located between the first silicon bridge and the copper pillar.

[0016] Compared with the prior art, the technical solution provided in this disclosure has the following advantages: A silicon bridge packaging process and package provided in this disclosure include: taking a carrier board and fabricating a first multi-layer wiring layer on the carrier board; mounting a first silicon bridge on the first multi-layer wiring layer; positioning and fabricating copper pillars on the first multi-layer wiring layer according to the position of the first silicon bridge; mounting a chip on the side of the first silicon bridge and copper pillars away from the first multi-layer wiring layer; and molding the structure after chip mounting to form a package. By advancing the mounting process of the first silicon bridge to before the fabrication of the copper pillars, and using the position of the mounted first silicon bridge as a reference for the fabrication of the copper pillars, deviations caused by chip mounting accuracy can be corrected, reducing the accumulation of deviations caused by material stress and temperature changes during the packaging process. This effectively reduces the dependence on the mounting accuracy of the silicon bridge chip during silicon bridge packaging, reduces package deformation, and lowers production costs. It achieves high-density interconnection between chips in a more efficient and economical way, promoting the further development and widespread application of silicon bridge technology, and laying the foundation for advanced packaging to develop towards smaller sizes and higher densities. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 The diagram shows the process steps of a silicon bridge packaging method provided in an embodiment of this disclosure; Figure 2 The diagram shown is a process flow chart of a silicon bridge packaging method provided in an embodiment of this disclosure; Figure 3 The diagram shown illustrates the relative positional relationship between a first silicon bridge and a carrier substrate according to an embodiment of this disclosure. Figure 4 The diagram shown illustrates the relative positional relationship between the first silicon bridge and the carrier board according to another embodiment of this disclosure. Figure 5 The above is a diagram showing the relative positional relationship between a chip and a first silicon bridge according to an embodiment of this disclosure; Figure 6 The image shown is a cross-sectional schematic diagram of a package provided in an embodiment of this disclosure. Detailed Implementation

[0020] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0021] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0022] Traditional 2.5D packaging relies on a single silicon interposer as the connection platform, resulting in high costs and limited design flexibility. 2.5D silicon bridge packaging eliminates the single silicon interposer, instead precisely embedding tiny silicon bridge chips into the packaging substrate. These silicon bridges appear only beneath the chips that need to be connected, acting like bridges to achieve localized high-density electrical interconnections. However, limited by current processes, silicon bridges are prone to positional misalignment during mounting; further structural deformation can be exacerbated during the molding process due to material stress and temperature variations. As package sizes shrink and integration densities increase, the market demands more stringent standards for controlling silicon bridge chip deviations. Relying solely on improving mounting accuracy will lead to an exponential increase in process complexity and overall cost, hindering the large-scale application of silicon bridge technology in high-end packaging.

[0023] To address the aforementioned issues, this disclosure provides a silicon bridge packaging process and package, which controls the offset accuracy between the silicon bridge and the copper pillar structure to the sub-micron level for processing using a photolithography machine. This effectively solves the accuracy problems of traditional silicon bridge technology in chip assembly and mounting processes, reduces production costs, and promotes the further development and widespread application of silicon bridge technology.

[0024] Figure 1 The diagram shows the process steps of a silicon bridge packaging according to an embodiment of this disclosure. Figure 2 The diagram shown is a process flow chart of a silicon bridge packaging according to an embodiment of this disclosure. Please refer to it. Figure 1 and Figure 2 This disclosure provides a silicon bridge packaging process, including: step S1, taking a carrier board 00 and fabricating a first redistribution layer 01 on the carrier board 00; step S2, mounting a first silicon bridge 02 on the first redistribution layer 01; step S3, positioning and fabricating copper pillars 03 on the first redistribution layer 01 according to the position of the first silicon bridge 02; step S4, mounting a chip 10 on the side of the first silicon bridge 02 and copper pillars 03 away from the first redistribution layer 01; step S5, molding the structure after mounting the chip 10 to form a package.

[0025] In step S1, the material of the carrier 00 includes organic materials, such as epoxy resin and polyimide, or it may include inorganic materials, such as silicon, glass, and ceramics. This disclosure does not limit the material of the carrier 00; the material can be selected according to the actual situation. A first multilayer wiring layer 01 is fabricated on the carrier 00. Optionally, the first multilayer wiring layer 01 can be a single layer or multiple layers; this disclosure does not limit this. Figure 2 The diagram only illustrates the relative position of the first wiring layer 01 and the carrier board 00, and does not represent the actual number of film layers or the actual thickness of the first wiring layer 01.

[0026] In step S2, a first silicon bridge 02 is mounted on the first redistribution layer 01. Optionally, the first silicon bridge 02 can be an interconnection of multiple silicon bridges in the relevant process. For example, the first silicon bridge 02 can be an interconnection of two, three, four, etc., silicon bridges in the relevant process. This disclosure does not limit the number of interconnected silicon bridges; the specific number depends on actual needs. Alternatively, the first silicon bridge 02 can also be pre-set to the required size during fabrication. This disclosure does not limit the formation method of the first silicon bridge 02.

[0027] Optionally, one, two, or three first silicon bridges 02 can be mounted in the package. Figure 2 This illustration only takes the mounting of one first silicon bridge 02 in a package as an example, and this disclosure does not limit it. Understandably, the fewer the number of first silicon bridges 02 mounted, the smaller the mounting deviation.

[0028] In step S3, copper pillars 03 are positioned and fabricated on the first redistribution layer 01 according to the position of the first silicon bridge 02. For example, after only one first silicon bridge 02 is mounted on the first redistribution layer 01, the copper pillars 03 are positioned and fabricated according to the position of the first silicon bridge 02. By advancing the process of mounting the first silicon bridge 02, even if there are errors during the mounting process, the relative positional relationship between the copper pillars 03 and the first silicon bridge 02 is determined based on the position of the mounted first silicon bridge 02, thus correcting deviations caused by chip mounting accuracy.

[0029] In related processes, copper pillars are typically fabricated on the first wiring layer, followed by the mounting of multiple silicon bridges. Due to limitations in existing processes, silicon bridges are prone to positional misalignment during mounting. Furthermore, the deformation is exacerbated by material stress and temperature variations during the molding process. This disclosure first designs a larger first silicon bridge 02, allowing multiple chips 10 to share a single first silicon bridge 02, reducing the number of first silicon bridges 02 that can be mounted and minimizing mounting deviations. Then, the mounting process of the first silicon bridge 02 is moved forward to before the fabrication of the copper pillars 03. After the first silicon bridge 02 is mounted, the copper pillars 03 are fabricated using the position of the mounted first silicon bridge 02 as a reference. This corrects deviations caused by mounting precision issues, effectively solving the precision problems of traditional silicon bridge technology in the chip 10 assembly and mounting process.

[0030] In step S4, after the first silicon bridge 02 is mounted and the copper pillar 03 is fabricated, the chip 10 is mounted on the side away from the first redistribution layer 01. Since the fabrication of the copper pillar 03 is based on the position of the mounted first silicon bridge 02, the positional relationship between the copper pillar 03 and the first silicon bridge 02 is determined, which is beneficial to improving the mounting accuracy of the chip 10.

[0031] In step S5, the structure after chip 10 is mounted is encapsulated to form a package. Please refer to... Figure 2 After molding, the molding layer needs to be thinned to expose the surface of the chip 10. After removing the carrier board 00, a second solder ball layer 07 needs to be made on the side of the first wiring layer 01 away from the chip 10 to complete the packaging.

[0032] Thus, by advancing the placement process of the first silicon bridge 02 before the fabrication of the copper pillar 03, and using the position of the first silicon bridge 02 after placement as a reference for the fabrication of the copper pillar 03, the relative position between the first silicon bridge 02 and the copper pillar 03 is determined. This corrects deviations caused by chip placement precision, thereby reducing the accumulation of deviations during the molding process due to factors such as the material and temperature of the encapsulation material. This effectively solves the precision problems of traditional silicon bridge technology in the chip assembly and placement process. The silicon bridge packaging process method provided in this disclosure can minimize deviations generated during silicon bridge packaging, promote the further development and widespread application of silicon bridge technology, and lay the foundation for advanced packaging to develop towards smaller sizes and higher densities.

[0033] Figure 3 The diagram shown illustrates the relative positional relationship between a first silicon bridge and a carrier substrate according to an embodiment of this disclosure. Figure 4 The diagram shown illustrates the relative positional relationship between the first silicon bridge and the carrier substrate according to another embodiment of this disclosure. Figure 5 The above is a diagram showing the relative positions of a chip and a first silicon bridge according to an embodiment of this disclosure. Please refer to it. Figures 3 to 5In the silicon bridge packaging process method provided in this disclosure, step S2, mounting the first silicon bridge 02 on the first redistribution layer 01, includes: the size of the first silicon bridge 02 is preset according to the number, size and arrangement of the chips 10 to be mounted.

[0034] Specifically, to reduce mounting deviation, the number of first silicon bridges 02 mounted on the first wiring layer 01 should be as small as possible. When only one first silicon bridge 02 is mounted on the first wiring layer 01, the functions of multiple silicon bridges in the relevant process can be achieved through one first silicon bridge 02. In this case, the mounted chips 10 need to be concentrated in the area where the first silicon bridge 02 is located. Therefore, the size of the first silicon bridge 02 can be preset according to the number, size and arrangement of the mounted chips 10.

[0035] For example, please refer to Figure 3 and Figure 5 The chip 10 mounted on the first silicon bridge 02 and copper pillar 03 may include two different types of sub-chips 11. For example, the sub-chip 11 may be a logic chip 13 and a memory chip 12. When there are multiple memory chips 12, more memory chips 12 can be laid out on one side by utilizing the long side of the logic chip 13 and the short side of the memory chip 12. The size of the first silicon bridge 02 is designed to be appropriate to meet the mounting of different chips 10. Figure 5 The illustration only shows the installation of two memory chips 12 and one logic chip 13, and does not represent the actual type and number of chips 10 installed. The specific settings can be made according to actual needs.

[0036] Please refer to Figure 2 , Figure 3 and Figure 4 Distinguished from Figure 3 The first silicon bridge 02 is mounted laterally along the plane of the first redistribution layer 01. Figure 4 The first silicon bridge 02 can also be mounted longitudinally along the plane where the first super-wiring layer 01 is located, or it can be mounted diagonally or in other directions along the plane where the first super-wiring layer 01 is located, etc. This disclosure does not limit this. In addition, the first super-wiring layer 01 can also be other sizes or shapes, such as square, pentagon, hexagon, etc. This disclosure does not limit the mounting position of the first silicon bridge 02, and it can be flexibly set according to the size and arrangement of the chip 10.

[0037] Thus, by pre-setting the size of the first silicon bridge 02 according to the required number, size, and arrangement of the chips 10 to be mounted, the flexibility of the manufacturing process can be improved, and it can also be customized according to user needs. The pre-set size of the first silicon bridge 02 can reduce mounting deviations in a single mounting process, meeting the increasingly stringent deviation control requirements in the high-density, miniaturized high-end packaging field.

[0038] Please refer to Figures 1 to 5 In the silicon bridge packaging process method provided in this disclosure, after positioning and fabricating copper pillars 03 on the first redistribution layer 01, step S2 further includes: the surface of the first silicon bridge 02 also includes short copper pillars, and the first silicon bridge 02 and copper pillars 03 are encapsulated and thinned until the surface of the first silicon bridge 02 and copper pillars 03 is exposed.

[0039] Specifically, after the first silicon bridge 02 is mounted and the copper pillar 03 is fabricated, the first silicon bridge 02 and the copper pillar 03 need to be encapsulated. Optionally, the encapsulation material includes epoxy encapsulant; of course, other encapsulation materials can also be used, and this disclosure does not limit this. Please refer to... Figure 2 The surface of the first silicon bridge 02 includes multiple short copper pillars. The first silicon bridge 02 and copper pillars 03 after molding are thinned until the surface of the short copper pillars on the first silicon bridge 02 and the copper pillars 03 is exposed, which facilitates the subsequent packaging process.

[0040] Please continue to refer to this. Figure 1 and Figure 2 In a silicon bridge packaging process method provided in this disclosure, step S4, mounting the chip 10 on the side of the first silicon bridge 02 and copper pillar 03 away from the first superwiring layer 01, includes: fabricating a second superwiring layer 05 on the side of the first silicon bridge 02 and copper pillar 03 away from the first superwiring layer 01 after molding; fabricating a first solder ball layer 06 on the side of the second superwiring layer 05 away from the first superwiring layer 01; and mounting the chip 10 on the first solder ball layer 06.

[0041] As mentioned above, the first silicon bridge 02 and copper pillar 03 are encapsulated, and the encapsulation material is thinned to expose the bumps on the surface of the first silicon bridge 02. A second redistribution layer 05 is formed on the surface of the first silicon bridge 02 including the bumps. The second redistribution layer 05 is located on the side of the first silicon bridge 02 and copper pillar 03 away from the first redistribution layer 01.

[0042] Please continue to refer to this. Figure 2 and Figure 5 In the silicon bridge packaging process method provided in this disclosure, the chip 10 includes at least two types or sizes of sub-chips 11; step S5, mounting the chip 10 on the first solder ball layer 06 specifically involves mounting each sub-chip 11 on the first solder ball layer 06 according to a preset position, and in a direction perpendicular to the first redistribution layer 01, each mounted sub-chip 11 overlaps with at least a portion of the first silicon bridge 02.

[0043] Optionally, the sub-chips 11 mounted on the first solder ball layer 06 may include two different types, three different types, four different types, etc. This disclosure does not limit the types of sub-chips 11 included in the chip 10; the specific type depends on actual needs. Optionally, the different types of sub-chips 11 mounted on the first solder ball layer 06 may include at least two different sizes, three different sizes, four different sizes, etc. This disclosure does not limit the size type of the sub-chips 11. Figure 5 The illustration is based solely on the example of chip 10 comprising two different sizes of sub-chips 11, and this disclosure is not limited thereto.

[0044] The first silicon bridge 02 is pre-mounted on the first super-wiring layer 01. To achieve communication between the first silicon bridge 02 and each sub-chip 11, after mounting, each sub-chip 11 must overlap with at least a portion of the first silicon bridge 02 in a direction perpendicular to the first super-wiring layer 01. That is, after pre-setting the size of the first silicon bridge 02 according to the required number, size, and arrangement of the chips 10, the first silicon bridge 02 is mounted on the first super-wiring layer 01 until the fabrication of the first solder ball layer 06 is completed. Then, sub-chips 11 of different types and sizes are mounted at the preset positions. Since the position of the first silicon bridge 02 is fixed, each sub-chip 11 needs to be concentrated towards the first silicon bridge 02. Each sub-chip 11 overlaps with at least a portion of the first silicon bridge 02 in a direction perpendicular to the first super-wiring layer 01, which ensures the communication between each chip 10 and the first silicon bridge 02.

[0045] Thus, by setting each of the mounted sub-chips 11 to overlap with at least a portion of the first silicon bridge 02 in a direction perpendicular to the first redistribution layer 01, the size of the first silicon bridge 02 can be designed to be larger. By increasing the size of the first silicon bridge 02, the number of silicon bridges that need to be mounted is reduced, thereby reducing mounting deviation. By advancing the mounting process of the first silicon bridge 02 to before the fabrication of the copper pillar 03, deviations caused by mounting can be further corrected, which is conducive to the accurate mounting of the chip 10 and realizes the connection between the first silicon bridge 02 and each sub-chip 11.

[0046] Please refer to Figure 2 In the silicon bridge packaging process method provided in this disclosure, the process of molding the structure after mounting the chip 10 to form a package specifically involves: molding and thinning the structure after mounting the chip 10 until the surface of the chip 10 is exposed; removing the carrier board 00; and forming a second solder ball layer 07 on the side of the first wiring layer 01 away from the chip 10.

[0047] Specifically, after mounting various types and sizes of sub-chips 11 onto the first solder ball layer 06 according to preset positions, the structure after chip mounting 10 can be encapsulated to fix the mounting positions and protect the chips 10. Thinning the encapsulation layer can reduce its thickness, reduce the impact of thermal stress on the encapsulation layer, and reduce package warpage. Optionally, the process of removing the carrier board 00 includes laser debonding, thermal debonding, etc., which can remove the temporary carrier board 00 in a non-contact manner. After fabricating the second solder ball layer 07 on the side where the carrier board 00 has been removed from the first redistribution layer 01, the package fabrication is completed.

[0048] Figure 6 The image shown is a cross-sectional schematic diagram of a package provided in an embodiment of this disclosure. Please refer to... Figure 6 Based on the same inventive concept, this disclosure provides a package 100, manufactured using the silicon bridge packaging process described above, comprising: a first redistribution layer 01, and a first silicon bridge 02 located on one side of the first redistribution layer 01; copper pillars 03 located on the same side of the first redistribution layer 01 as the first silicon bridge 02, the copper pillars 03 being manufactured according to the position of the first silicon bridge 02 after mounting; a second redistribution layer 05 located on the side of the first silicon bridge 02 and copper pillars 03 away from the first redistribution layer 01; a chip 10 located on the side of the second redistribution layer 05 away from the first silicon bridge 02 and copper pillars 03, and the chip 10 being connected to the first silicon bridge 02 and copper pillars 03 through a first solder ball layer 06; and a second solder ball layer 07 located on the side of the first redistribution layer 01 away from the first silicon bridge 02.

[0049] Specifically, in the package 100 provided in this disclosure, a first silicon bridge 02 is mounted on one side of the first multi-layer wiring 01. Optionally, only one first silicon bridge 02 is mounted in a package 100. The size of the first silicon bridge 02 can be preset according to the number, size, and arrangement of the sub-chips 11 to be packaged. After the first silicon bridge 02 is mounted, a copper pillar 03 is provided on the same side of the first multi-layer wiring 01 as the first silicon bridge 02. The copper pillar 03 is positioned according to the actual position of the mounted first silicon bridge 02, thus correcting the mounting deviation of the first silicon bridge 02. The first silicon bridge 02 and copper pillar 03 are encapsulated and thinned to expose the surface bumps of the first silicon bridge 02. A second redistribution layer 05 is provided on one side of the first silicon bridge 02 including the surface bumps. The second redistribution layer 05 can be made using laser direct writing technology. The laser direct writing exposure area of ​​the second redistribution layer 05 can be flexibly adjusted according to the actual position of the first silicon bridge 02 and copper pillar 03, which can further correct the mounting deviation of the first silicon bridge 02 and effectively reduce the mounting deviation generated during the silicon bridge mounting process of traditional silicon bridge technology.

[0050] A first solder ball layer 06 is formed on the second wiring layer 05, and a chip 10 is mounted on the side of the first solder ball layer 06 away from the second wiring layer 05. The chip 10 includes at least two types or sizes of sub-chips 11. The sub-chips 11 are mounted on the first solder ball layer 06 at preset positions. Along the direction perpendicular to the plane of the first wiring layer 01, any sub-chip 11 overlaps with at least a portion of the first silicon bridge 02, thereby enabling communication with multiple types of sub-chips 11 through a single first silicon bridge 02. A second solder ball layer 07 is disposed on the side of the first wiring layer 01 away from the first silicon bridge 02 to facilitate subsequent connection between the package 100 and the PCB (Printed Circuit Board), etc.

[0051] The package 100 provided in this disclosure can control the offset accuracy between the first silicon bridge 02 and the copper pillar 03 at the sub-micron level of a photolithography machine, effectively solving the accuracy problems of traditional silicon bridge technology in chip assembly and mounting processes. With the reduction in package size and the increase in integration density, the requirements for controlling silicon bridge mounting deviations on production lines are becoming increasingly stringent. The first silicon bridge 02 process route provided in this disclosure has a significant cost advantage compared to the through-silicon via (TSV) technology route, improves compatibility, and possesses process iteration advantages, laying the foundation for further development of silicon bridge technology.

[0052] Please continue to refer to this. Figures 3 to 6 In a package 100 provided in this disclosure, one package 100 is provided with one first silicon bridge 02.

[0053] Specifically, when a package 100 is fitted with only one first silicon bridge 02, even if there is a fitting deviation, since the manufacturing process of the copper pillar 03 is after the process of fitting the first silicon bridge 02, the copper pillar 03 can be positioned and manufactured based on the actual position of the fitted first silicon bridge 02. That is, the positioning and manufacturing process of the copper pillar 03 can correct the fitting deviation of the first silicon bridge 02, which can minimize the accumulation of fitting deviation and its impact on subsequent packaging.

[0054] Optionally, in some other embodiments, a package 100 may also be provided with two first silicon bridges 02. This disclosure is not limited thereto. It is understood that the number of first silicon bridges 02 should not be too large, and there will inevitably be a mounting deviation when multiple first silicon bridges 02 are mounted.

[0055] Thus, by increasing the size of the first silicon bridge 02 and reducing the number of first silicon bridge 02 in this disclosure, the mounting deviation can be effectively controlled, adapting to the mass production of silicon bridge packages.

[0056] Please continue to refer to this. Figure 6In a package 100 provided in this disclosure, the package 100 further includes a package layer 08, at least a portion of the material of the package layer 08 is located between adjacent sub-chips 11, and at least a portion of the material of the package layer 08 is located between the first silicon bridge 02 and the copper pillar 03.

[0057] Specifically, at least a portion of the encapsulation layer 08 material is located between adjacent sub-chips 11. The material of the encapsulation layer 08 serves as an electromagnetic shielding layer, reducing signal crosstalk between adjacent sub-chips 11 and improving signal integrity. At least a portion of the encapsulation layer 08 material is located between the first silicon bridge 02 and the copper pillar 03, which can fix the mounted first silicon bridge 02 and reduce displacement or detachment of the first silicon bridge 02 under vibration or impact. Furthermore, the material of the encapsulation layer 08 can also cover the interconnection area between the sub-chips 11, the first silicon bridge 02, and the copper pillar 03, preventing external environmental factors such as moisture and dust from corroding the interconnection structure. In other words, the encapsulation layer 08 can form a protective layer, extending the service life of the interconnection structure.

[0058] In the silicon bridge package structure, the material of the packaging layer 08 fills the gaps between the sub-chip 11, the first silicon bridge 02, and the copper pillar 03, forming a stable support structure to prevent the sub-chip 11 from falling off or breaking under vibration or impact. By integrating different functional sub-chips 11 into a package 100 using the material of the packaging layer 08, flexible combinations of different types of sub-chips 11 can be achieved, supporting modular design and meeting diverse user needs.

[0059] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A process method for silicon bridge packaging, characterized in that, include: Take a carrier board and fabricate the first wiring layer on the carrier board; A first silicon bridge is mounted on the first wiring layer; Based on the position of the first silicon bridge, copper pillars are positioned and fabricated on the first redistribution layer; A chip is mounted on the side of the first silicon bridge and the copper pillar that is away from the first redistribution layer. The structure after the chip is mounted is encapsulated to form a package.

2. The silicon bridge packaging process method as described in claim 1, characterized in that, The mounting of the first silicon bridge on the first redistribution layer includes: The size of the first silicon bridge is preset according to the number, size and arrangement of the chips to be mounted.

3. The silicon bridge packaging process method as described in claim 1, characterized in that, After positioning and fabricating the copper pillars on the first redistribution layer, the process further includes: The surface of the first silicon bridge also includes short copper pillars; The first silicon bridge and the copper pillar are encapsulated and thinned until the surface of the short copper pillar of the first silicon bridge and the copper pillar is exposed.

4. The silicon bridge packaging process method as described in claim 3, characterized in that, The mounting of chips on the side of the first silicon bridge and the copper pillar opposite to the first redistribution layer includes: A second wiring layer is fabricated on the side of the first silicon bridge and the copper pillar that are opposite to the first wiring layer after molding; A first solder ball layer is fabricated on the side of the second overlay layer opposite to the first overlay layer, and the chip is mounted on the first solder ball layer.

5. The silicon bridge packaging process method as described in claim 4, characterized in that, The chip includes at least two types or sizes of sub-chips; Specifically, mounting the chip onto the first solder ball layer involves: Each of the sub-chips is mounted on the first solder ball layer at a preset position, and each of the mounted sub-chips overlaps with at least a portion of the first silicon bridge in a direction perpendicular to the first redistribution layer.

6. The silicon bridge packaging process method as described in claim 1, characterized in that, The specific steps of molding and encapsulating the structure after mounting the chip to form a package are as follows: The structure after the chip is mounted is encapsulated and thinned until the surface of the chip is exposed. Remove the carrier plate; A second solder ball layer is fabricated on the side of the first redistribution layer opposite to the chip.

7. A package, characterized in that, The product is manufactured using the silicon bridge packaging process described in any one of claims 1-6, comprising: A first wiring layer, and a first silicon bridge located on one side of the first wiring layer; The copper pillar is located on the same side as the first silicon bridge on the first redistribution layer. The copper pillar is manufactured according to the position of the first silicon bridge after it is mounted. The second wiring layer is located on the side of the first silicon bridge and the copper pillar that is away from the first wiring layer. The chip is located on the side of the second redistribution layer away from the first silicon bridge and the copper pillar, and the chip is connected to the first silicon bridge and the copper pillar through a first solder ball layer; The second solder ball layer is located on the side of the first redistribution layer opposite to the first silicon bridge.

8. The package as described in claim 7, characterized in that, One of the aforementioned packages is provided with one first silicon bridge.

9. The package as described in claim 7, characterized in that, The chip includes at least two types or sizes of sub-chips, and any of the sub-chips overlaps with at least a portion of the first silicon bridge along a direction perpendicular to the plane of the first redistribution layer.

10. The package as claimed in claim 9, characterized in that, The package further includes a packaging layer, at least a portion of the material of the packaging layer being located between adjacent sub-chips, and at least a portion of the material of the packaging layer being located between the first silicon bridge and the copper pillar.

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