High aspect ratio adapter plate and method of making same

Abstract

The application relates to a high-aspect-ratio adapter plate and a manufacturing method thereof, and relates to the technical field of microelectronic packaging. The manufacturing method of the adapter plate comprises the following steps: S1, setting a temporary carrier plate; S2, manufacturing a planar wiring layer on the temporary carrier plate, wherein the planar wiring layer comprises a medium layer and a plurality of metal wirings arranged on the medium layer; S3, sequentially stacking and manufacturing a plurality of layers of planar wiring layers on the planar wiring layer, wherein all the planar wiring layers form an adapter plate main body; S4, separating the adapter plate main body from the temporary carrier plate; S5, post-processing the adapter plate main body, manufacturing a surface solder pad on the adapter plate main body, and electrically connecting the surface solder pad with the metal wirings, so as to form a three-dimensional adapter plate; and the aspect ratio of the metal wirings in the adapter plate is not less than 10:1. The application converts the aspect ratio of the vertical structure of the adapter plate into the aspect ratio of the metal wirings in the two-dimensional plane, which is convenient for manufacturing the high-aspect-ratio adapter plate.

Description

Technical Field

[0001] This application relates to the technical field of microelectronic packaging, and in particular to a high aspect ratio adapter board and its manufacturing method. Background Technology

[0002] In the semiconductor industry, the technical difficulty and cost of maintaining Moore's Law by shrinking transistor size are increasing exponentially, making the conventional approach to extending Moore's Law increasingly uneconomical. Therefore, the microelectronics packaging industry has begun to develop towards 3D packaging technology. Using 3D packaging technology, chips and passive components are vertically stacked, which can significantly reduce the total projected area of ​​the chips and substantially shorten the interconnect length between chips, resulting in a series of advantages such as smaller device size, lower signal delay, and lower system power consumption.

[0003] In 3D packaging technology, the adapter board plays a crucial role as a key component for achieving high-density electrical interconnection between different layers.

[0004] Currently, the mainstream adapter boards mainly include Through-Silicon Via (TSV) adapter boards, Through-Glass Via (TGV) adapter boards, and Through-Mold Via (TMV) adapter boards. Among them, TSV adapter boards have the highest aspect ratio and interconnect density, so they are the most widely used.

[0005] The existing manufacturing process for TSV adapter boards is typically as follows: First, a high aspect ratio vertical via is fabricated on a silicon wafer using deep reactive ion etching (DRIE) technology; then, a dielectric layer, a barrier layer, and a seed layer are deposited sequentially on the inner wall of the via; finally, an electroplating process is used to fill the via with conductive metals such as copper to form a vertical conductive path.

[0006] However, as the aspect ratio of TSV adapter boards continues to increase, the inherent defects in the manufacturing process of the aforementioned TSV adapter boards become increasingly prominent, especially after the aspect ratio of the TSV adapter boards exceeds 10:1. Specifically, the defects are as follows: In the deposition stage, due to the shielding effect and mass transport limitations of the deep-hole structure, functional films such as the dielectric layer, barrier layer, and seed layer are difficult to achieve uniform and comprehensive coverage on the inner wall of the via. Furthermore, in the electroplating filling stage, poor seed layer quality can cause abnormal current concentration at the via opening, resulting in a much faster metal deposition rate near the opening than inside the via, thus prematurely closing the via (i.e., the "sealing effect"), which easily leads to void defects inside the via.

[0007] Therefore, the existing manufacturing methods for TSV adapter boards, due to their inherent non-conformal deposition and plating voids, severely limit the further improvement of the aspect ratio of TSV adapter boards, thereby hindering the improvement of the interconnect density between three-dimensional packaging layers and the further miniaturization of package size. Summary of the Invention

[0008] This application provides a high aspect ratio adapter board and its manufacturing method. The purpose is to improve the manufacturing method of the adapter board so that the aspect ratio of the adapter board can be further improved, thereby facilitating the increase of the interconnection density between three-dimensional packaging layers and the further miniaturization of the package size.

[0009] Firstly, the high aspect ratio adapter board manufacturing method provided in this application adopts the following technical solution: A method for manufacturing a high aspect ratio adapter board includes the following steps: S1, setting a temporary carrier board; S2, fabricating a planar wiring layer on the temporary carrier board, the planar wiring layer including a dielectric layer and a plurality of metal wirings disposed on the dielectric layer; S3, sequentially stacking a plurality of planar wiring layers on the planar wiring layer, all the planar wiring layers forming the adapter board body; S4, separating the adapter board body from the temporary carrier board; S5, performing post-processing on the adapter board body, fabricating surface pads on the adapter board body, and electrically connecting the surface pads to the metal wirings to form a three-dimensional adapter board; and the aspect ratio of the metal wirings in the adapter board is not less than 10:1.

[0010] By adopting the above technical solution and fabricating the adapter board based on the above method, the aspect ratio of the vertical structure of the adapter board is transformed into the aspect ratio of the metal wiring on a two-dimensional plane. Since fabricating long and thin metal wiring on a two-dimensional plane is much simpler than etching deep and narrow vias on a silicon wafer, it is convenient to use metal wiring with a larger aspect ratio during the fabrication of the adapter board, thereby significantly improving the aspect ratio of the fabricated adapter board. Therefore, the fabrication method of this application can effectively reduce the fabrication difficulty of high aspect ratio adapter boards, eliminate the defects in the fabrication of high aspect ratio TSV adapter boards, and thus facilitate the improvement of the interconnection density between three-dimensional packaging layers and the further miniaturization of the package size.

[0011] Optionally, in step S2, the planar wiring layer is fabricated on both sides of the temporary carrier board; in step S3, several layers of the planar wiring layer are sequentially superimposed on the planar wiring layer on both sides of the temporary carrier board, and all the planar wiring layers located on the same side of the temporary carrier board form a main body of the adapter board.

[0012] By adopting the above technical solution, planar wiring layers are stacked on both opposite sides of the temporary carrier board, enabling the simultaneous fabrication of two adapter board bodies. Based on this design, on the one hand, the fabrication of dual adapter board bodies improves the efficiency of adapter board production. On the other hand, the internal stress generated on the temporary carrier board during the fabrication of one adapter board body can be offset by the internal stress generated on the temporary carrier board during the fabrication of the other adapter board body. This reduces warping deformation of the temporary carrier board, ensures its stability, and thus improves the yield rate of adapter board fabrication.

[0013] Optionally, in step S2, the planar wiring layer is simultaneously fabricated on opposite sides of the temporary carrier board.

[0014] By adopting the above technical solution, since the first planar wiring layer is made on both sides of the temporary carrier at the same time, the internal stress generated on the temporary carrier during the fabrication of the planar wiring layer on one side is synchronously canceled out by the internal stress generated on the temporary carrier during the fabrication of the planar wiring layer on the other side. This allows the temporary carrier to remain in a flat state when the planar wiring layers are made on both sides of the temporary carrier at the same time.

[0015] Optionally, in step S3, the two adapter plate bodies are symmetrically arranged on both sides of the temporary carrier plate.

[0016] By adopting the above technical solution, in step S3, planar wiring layers are superimposed on opposite sides of the temporary carrier plate. This makes the internal stress generated by the planar wiring layer on one side of the temporary carrier plate symmetrical and equal to the internal stress generated by the planar wiring layer on the other side of the temporary carrier plate, and they can cancel each other out. This can prevent the temporary carrier plate from warping and deforming during the manufacturing process of the two adapter plates, and keep the temporary carrier plate in a flat state.

[0017] Optionally, in step S3, the metal wiring in two adjacent planar wiring layers is arranged in an alternating manner.

[0018] By adopting the above technical solution, since the metal wiring in the adjacent two planar wiring layers is arranged alternately, it can prevent the lower metal wiring from protruding and affecting the flatness of the upper metal wiring. This reduces the risk of structural deformation or breakage of the upper metal wiring, thereby reducing the interference between the metal wiring in the two planar wiring layers, and thus improving the overall reliability and yield of the manufactured adapter board.

[0019] Optionally, steps S2 and S3 both include: grinding the dielectric layer until the surface of the dielectric layer is flat.

[0020] By adopting the above technical solution, the dielectric layer is ground to make the surface of the dielectric layer flat, providing a flat base for the subsequent metal wiring. This avoids the deformation or breakage of the corresponding metal wiring due to uneven stress caused by the uneven dielectric layer, thereby improving the yield of the final adapter board.

[0021] Optionally, step S1 further includes: applying a temporary bonding coating to the surface of the temporary carrier plate.

[0022] By adopting the above technical solution, the temporary bonding coating acts as a temporary adhesive, thereby increasing the stability of the first planar wiring layer on the temporary carrier during the fabrication of the adapter board.

[0023] Optionally, in step S4, a debonding process is used to separate the adapter plate body from the temporary carrier plate.

[0024] By adopting the above technical solution, the temporary bonding coating and the bonding process work together to facilitate the separation of the adapter board body and the temporary carrier board, thereby reducing the impact of the separation process on the adapter board body and the temporary carrier board.

[0025] Secondly, this application also provides a high aspect ratio adapter board with the following technical solution: A high aspect ratio adapter board includes: a plurality of planar wiring layers, wherein the plurality of planar wiring layers are stacked sequentially, each planar wiring layer includes a dielectric layer and a plurality of metal wirings disposed on the surface of the dielectric layer, and the plurality of metal wirings between adjacent planar wiring layers are electrically connected, wherein the aspect ratio of the metal wirings is not less than 10:1; and a surface pad, wherein the surface pad is located on one side of the planar wiring layers, and the plurality of planar wiring layers are all connected to the surface pad, and the surface pad is electrically connected to the plurality of metal wirings.

[0026] By adopting the above technical solution, the structural design of the adapter board transforms the adapter board structure into a layered structure of two-dimensional planes. Furthermore, the adapter board transforms the original metal wiring extending along the length direction on the two-dimensional plane into a vertical conductive path penetrating the thickness direction of the adapter board. This allows the aspect ratio of the metal wiring to directly determine the effective aspect ratio of the adapter board, thereby improving the overall aspect ratio of the adapter board.

[0027] In summary, this application includes at least one of the following beneficial technical effects: 1. This application converts the aspect ratio of the vertical structure of the adapter board into the aspect ratio of the metal wiring on a two-dimensional plane. Since it is much simpler to fabricate long and thin metal wiring on a two-dimensional plane than to etch deep and narrow vias on a silicon wafer, it is convenient to use metal wiring with a larger aspect ratio during the fabrication of the adapter board, thereby significantly improving the aspect ratio of the fabricated adapter board.

[0028] 2. This application effectively balances the internal stress generated by the planar wiring layers on the temporary carrier board during the manufacturing process by simultaneously and symmetrically stacking the planar wiring layers on both sides of the temporary carrier board, thereby reducing the warping deformation of the temporary carrier board, ensuring the stability of the temporary carrier board, and thus improving the pass rate of the adapter board manufacturing.

[0029] 3. This application reduces the risk of metal wiring deformation and breakage and improves the overall reliability of the adapter board by designing the arrangement of metal wiring within two adjacent planar wiring layers.

[0030] 4. This application improves the bonding strength of the temporary carrier plate through the design of the temporary bonding coating and the debonding process, and also facilitates the separation of the adapter plate body from the temporary carrier plate. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating the manufacturing method of Embodiment 1 of this application.

[0032] Figure 2 This is a schematic diagram of the overall structure of the temporary carrier plate in Embodiment 1 of this application.

[0033] Figure 3 This is a schematic diagram of the overall structure of the temporary carrier board and planar wiring layer in Embodiment 1 of this application.

[0034] Figure 4 This is a front view of the temporary carrier board and planar wiring layer of Embodiment 1 of this application.

[0035] Figure 5 This is a schematic diagram of the overall structure of the temporary carrier plate and the adapter plate of Embodiment 1 of this application.

[0036] Figure 6 This is a cross-sectional structural diagram of the temporary carrier plate and the main body of the adapter plate in Embodiment 1 of this application.

[0037] Figure 7 This is a schematic diagram of the separation structure of the temporary carrier plate and the main body of the adapter plate in Embodiment 1 of this application.

[0038] Figure 8 This is a structural schematic diagram of the vertically arranged adapter plate body of Embodiment 1 of this application.

[0039] Figure 9 This is a cross-sectional view of the adapter plate of Embodiment 1 of this application.

[0040] Figure 10 This is a schematic diagram of the overall structure of the temporary carrier board and planar wiring layer in Embodiment 2 of this application.

[0041] Figure 11 This is a front view of the temporary carrier board and planar wiring layer of Embodiment 2 of this application.

[0042] Figure 12 This is a schematic diagram of the overall structure of the temporary carrier plate and the adapter plate of Embodiment 2 of this application.

[0043] Figure 13 This is a schematic diagram of the separation structure of the temporary carrier plate and the main body of the adapter plate in Embodiment 2 of this application.

[0044] In the diagram, 1 is the temporary carrier board; 2 is the temporary bonding coating; 3 is the planar routing layer; 31 is the dielectric layer; 32 is the metal line layer; 321 is the metal routing; 4 is the main body of the adapter board; 5 is the redistribution layer; and 6 is the surface pad. Detailed Implementation

[0045] The following is in conjunction with the appendix Figure 1 - Appendix Figure 13 This application will be described in further detail below.

[0046] Example 1: A method for manufacturing a high aspect ratio adapter plate, referring to... Figure 1 This includes the following steps: S1. Set temporary carrier board 1.

[0047] Reference Figure 2 Specifically, the temporary carrier 1 is made of silicon or glass material, specifically silicon wafers, glass wafers, silicon wafers, or glass plates.

[0048] This ensures that the temporary carrier plate 1 has a smooth surface and sufficient mechanical strength and rigidity, thus enabling the temporary carrier plate 1 to serve as a structural support during the fabrication of the transition plate.

[0049] Reference Figure 2 Specifically, in step S1, the temporary carrier plate 1 is set horizontally, and one or more temporary bonding coatings 2 are coated on the upper side of the temporary carrier plate 1.

[0050] The temporary bonding coating 2 uses a temporary bonding adhesive and is attached to the temporary carrier plate 1 by spin coating or lamination. The specific material of the temporary bonding adhesive is directly related to the subsequent debonding process. In this embodiment, the temporary bonding adhesive can be a thermoplastic polymer, a photosensitive polymer, or other materials that can achieve controlled debonding.

[0051] The temporary bonding coating 2 acts as a temporary adhesive, thereby increasing the stability of the layer structure superimposed on the temporary carrier plate 1 during the fabrication of the adapter plate.

[0052] S2. Create a planar wiring layer 3 on the temporary carrier board 1.

[0053] Reference Figure 3 and Figure 4 Specifically, the planar wiring layer 3 includes a dielectric layer 31 and a metal wire layer 32. The metal wire layer 32 is superimposed on the dielectric layer 31, and the dielectric layer 31 is superimposed on the temporary bonding coating 2, which makes the planar wiring layer 3 fixed on the temporary carrier board 1.

[0054] Reference Figure 3 and Figure 4 The metal wiring layer 32 includes a plurality of metal wirings 321, which are disposed on the side of the dielectric layer 31 away from the temporary carrier board 1. The metal wirings 321 are connected to the dielectric layer 31, and the plurality of metal wirings 321 are all horizontally disposed on the dielectric layer 31. Furthermore, the aspect ratio of the metal wirings 321 is not less than 10:1.

[0055] The dielectric layer 31 is used for electrical insulation, so the dielectric layer 31 can be made of inorganic materials such as silicon dioxide or silicon nitride, or organic materials such as photosensitive polyimide or molding compound; the metal wiring 321 is used for conductivity, so the metal wiring 321 can be made of high-purity metal elements, alloys, conductive adhesives, etc.

[0056] Specifically, refer to Figure 3 and Figure 4 The fabrication process for planar wiring layer 3 adopts the following steps: Dielectric layer 31 deposition: Dielectric layer 31 is deposited on temporary bonding coating 2.

[0057] The specific steps are as follows: a dielectric layer 31 is uniformly deposited on the temporary bonding coating 2 by plasma enhanced chemical vapor deposition (PECVD) or spin coating process.

[0058] Planarization of dielectric layer 31: Planarization is performed on the surface of dielectric layer 31.

[0059] The specific steps are as follows: the surface of the dielectric layer 31 is ground using mechanical grinding or chemical mechanical polishing (CMP) until the surface of the dielectric layer 31 is flat. This achieves the planarization treatment of the dielectric layer 31, and the planarization treatment can be performed selectively.

[0060] Metal layer deposition: A metal material layer is deposited on the surface of dielectric layer 31.

[0061] The specific steps are as follows: First, a barrier layer, made of titanium or tantalum, is deposited on the surface of the dielectric layer 31 using a physical vapor deposition (PVD) process. This barrier layer enhances the adhesion between the subsequently deposited main conductive metal layer and the dielectric layer 31, and prevents metal atoms from the main conductive metal layer from diffusing into the dielectric layer 31. Second, a seed layer, made of copper or gold, is deposited on the surface of the barrier layer using another PVD process. This seed layer provides a conductive substrate for the subsequent electroplating process. Finally, using the seed layer as the conductive substrate, a conductive metal layer of the required thickness is deposited on the surface of the seed layer using an electroplating process. This conductive metal layer is made of copper. At this point, the conductive metal layer, the seed layer, and the barrier layer constitute a metal material layer.

[0062] Patterning of metal line layer 32: Metal line layer 32 is fabricated on the metal material layer.

[0063] The specific steps are as follows: First, photoresist is coated: a layer of photoresist is uniformly coated on the surface of the conductive metal layer as the photosensitive material for subsequent pattern transfer; second, exposure: using an exposure machine, the photoresist layer is selectively exposed through a mask printed with a preset circuit pattern; then, development: a developer is used to remove part of the photoresist, thereby forming a patterned photoresist mask on the metal material layer; next, metal etching: using the patterned photoresist mask as a protective layer, the portion of the metal material layer not covered by the photoresist mask is removed by wet etching or dry etching techniques; finally, photoresist removal: the remaining photoresist mask covering the formed metal material layer is completely removed by wet processes such as chemical stripping or plasma ashing. Thus, a plurality of metal wirings 321 arranged according to a predetermined circuit pattern are obtained on the dielectric layer 31, thereby fabricating the metal line layer 32.

[0064] In this embodiment, the fabrication process of the planar wiring layer 3 described above enables wiring to be performed on the two-dimensional plane of the dielectric layer 31. Therefore, extending the length of the metal wiring 321 at the wafer level does not increase the technical difficulty.

[0065] Specifically, taking the conventional 10µm / 10µm linewidth / spacing in wafer-level packaging as an example, the aforementioned "fabrication process of planar wiring layer 3" allows for the precise fabrication of metal wiring 321 with a width of 10µm and a spacing of 10µm. Simultaneously, in the "patterning of metal wiring layer 32" step, due to the absence of obstructions, metal wiring 321 with a length exceeding 1mm can be easily generated on the dielectric layer 31. This allows the aspect ratio of the adapter board in this application to easily reach or even exceed 1000µm:10µm, i.e., 100:1. This value is more than 10 times that of conventional TSV adapter boards (with an aspect ratio typically of 10:1). Therefore, the aspect ratio of the metal wiring 321 in this application can reach or even exceed 100:1, which greatly improves the performance and integration potential of the adapter board.

[0066] In addition, as a preferred embodiment, to achieve finer wiring, the "fabrication process of the planar wiring layer 3" can also employ a damascene process. The specific steps can be replaced as follows: first, a preset trench pattern is formed on the dielectric layer 31 (preferably an inorganic dielectric layer such as silicon dioxide) through photolithography and etching; then, a barrier layer / seed layer is deposited, and metal (such as copper) is filled through electroplating; finally, excess metal on the surface of the dielectric layer 31 is removed through chemical mechanical polishing (CMP), thereby forming metal wiring 321 embedded within the dielectric layer 31. Using this damascene process, the width of the metal wiring 321 within the metal wiring layer 32 and the spacing between adjacent metal wiring 321 can be further reduced, resulting in a final interconnect board with a metal wiring 321 diameter of 2µm or less, thus meeting the requirements for higher density interconnects.

[0067] S3. Several planar wiring layers 3 are sequentially stacked on the planar wiring layer 3, and all planar wiring layers 3 form the main body of the adapter board 4.

[0068] Reference Figure 5 and Figure 6 Specifically, based on step S2, several more planar wiring layers 3 are stacked sequentially on the first planar wiring layer 3 to form the main body 4 of the adapter board with a three-dimensional structure.

[0069] Reference Figure 5 and Figure 6 Specifically, in step S3, after several planar wiring layers 3 are sequentially stacked and fabricated, the metal wire layer 32 of the uppermost planar wiring layer 3 is exposed. Therefore, step S3 also includes: after several planar wiring layers 3 are sequentially stacked and fabricated, a dielectric layer 31 is stacked and fabricated on the uppermost planar wiring layer 3. The addition of this dielectric layer 31 can insulate and seal the exposed metal wire layer 32 at the top.

[0070] Reference Figure 5 and Figure 6 Specifically, in two adjacent planar routing layers 3, the dielectric layer 31 in the upper planar routing layer 3 completely covers the metal wire layer 32 in the lower planar routing layer 3 and fills the gap between two adjacent metal wires 321 in the lower metal wire layer 32. Furthermore, the uppermost dielectric layer 31 also completely covers the metal wire layer 32 in the uppermost planar routing layer 3 and fills the gap between two adjacent metal wires 321 in the uppermost metal wire layer 32.

[0071] Reference Figure 5 and Figure 6 Specifically, by repeating the "fabrication process of planar wiring layer 3" in step S2 above, several planar wiring layers 3 can be successively superimposed on the first planar wiring layer 3.

[0072] In this embodiment, to establish electrical interconnections between adjacent planar wiring layers 3, conductive vias are first fabricated on the current dielectric layer 31 using photolithography, etching, and other processes before the metal wiring 321 is arranged on the dielectric layer 31. These conductive vias expose the pre-defined connection points of the metal wiring 321 within the underlying planar wiring layer 3. Subsequently, when the metal wiring 321 is deposited and patterned on the dielectric layer 31, the conductive vias are filled, thereby depositing copper metal within the vias. This allows the copper metal within the vias to achieve electrical connections between corresponding metal wiring 321 between two adjacent planar wiring layers 3, thus enabling conductive interconnection between two adjacent metal wiring layers 32. With this design, a three-dimensional wiring network can be established between several planar wiring layers 3.

[0073] Reference Figure 5 and Figure 6 Specifically, in two adjacent planar wiring layers 3, several metal wires 321 in the lower metal wire layer 32 and several metal wires 321 in the upper metal wire layer 32 are arranged alternately, that is, the metal wires 321 in the lower metal wire layer 32 are located between two corresponding adjacent metal wires 321 in the upper metal wire layer 32. Based on the arrangement of the metal wires 321 in the two adjacent planar wiring layers 3, the impact of the protrusion of the lower metal wires 321 on the flatness of the upper metal wires 321 can be effectively reduced, avoiding the risk of structural deformation or breakage of the upper metal wires 321, thereby improving the overall reliability and yield of the manufactured adapter board.

[0074] S4. Separate the adapter plate body 4 from the temporary carrier plate 1.

[0075] Reference Figure 7 Specifically, after the main body 4 of the adapter plate is fabricated on the temporary carrier plate 1, the adapter plate main body 4 is separated from the temporary carrier plate 1 by a debonding process.

[0076] Specifically, the debonding process can be carried out using thermal, laser, mechanical, or chemical methods. In this embodiment, the choice of debonding process is determined by the material used in the temporary bonding coating 2. For example, if the temporary bonding coating 2 is made of a thermoplastic polymer material, the debonding process can be carried out by heating. Under heating, the temporary bonding coating 2 will lose its adhesiveness, thereby achieving the separation of the adapter plate body 4 from the temporary carrier plate 1. If the temporary bonding coating 2 is made of a photosensitive polymer material, the debonding process can be carried out by laser irradiation. Under laser irradiation, the temporary bonding coating 2 will lose its adhesiveness, thereby achieving the separation of the adapter plate body 4 from the temporary carrier plate 1.

[0077] S5. Post-process the main body 4 of the adapter plate to form a complete adapter plate.

[0078] Reference Figure 8 and Figure 9 Specifically, in step S5, the adapter board body 4 is post-processed to create surface pads 6 on the adapter board body 4, and the surface pads 6 are electrically connected to several metal wirings 321 to form a complete adapter board with a three-dimensional structure. Furthermore, the aspect ratio of the metal wirings 321 within the adapter board is not less than 10:1.

[0079] Specifically, the post-processing steps are as follows: Fabrication of redistribution layer 5: A redistribution layer 5 is provided on the main body 4 of the adapter board, and the redistribution layer 5 is connected to the metal wiring 321 inside the main body 4 of the adapter board.

[0080] The specific steps are as follows: First, adjust the position of the adapter board body 4 so that the metal wiring 321 inside the adapter board body 4 is vertically positioned. Second, deposit an insulating protective layer on the top surface of the adapter board body 4. Then, using photolithography and etching techniques, etch windows into the insulating protective layer and / or the adapter board body 4 to expose the metal wiring 321. Subsequently, deposit and pattern a conductive metal layer on the insulating protective layer using physical vapor deposition (PVD) and electroplating processes. This conductive metal layer is connected to the exposed metal wiring 321 through the windows, thereby forming the rewiring layer 5.

[0081] Surface pad 6 processing: Surface pad 6 is set on redistribution layer 5.

[0082] The specific steps are as follows: First, a solder mask or passivation layer is deposited or coated onto the redistribution layer 5. Then, windows are etched into the solder mask or passivation layer using photolithography. Next, the solder mask or passivation layer within the windows is selectively removed using dry or wet etching techniques, thus exposing the metal within the redistribution layer 5. At this point, the window becomes the surface pad 6 area; the position and shape of the window define the shape and position of the surface pad 6 area. Finally, the surface pad 6 area undergoes final surface treatment to fabricate the surface pad 6. Specifically, the surface pad 6 can be formed using processes such as electroless nickel-palladium-gold plating (ENEPIG) or electroless nickel-gold plating (ENIG) to create a metal-under-bump (UBM) structure, or directly through solder balling.

[0083] Overall thinning: Selectively thin the main body 4 of the adapter plate.

[0084] The specific steps are as follows: using mechanical grinding equipment, such as a wafer thinner, the main body 4 of the adapter board is ground to remove excess material until the thickness of the main body 4 of the adapter board reaches the preset target thickness, which ensures that the thickness of the final adapter board meets the requirements. Thinning can be performed selectively, using either mechanical grinding or chemical mechanical polishing (CMP) processes.

[0085] Slicing: The main body 4 of the adapter plate is slicing.

[0086] The specific steps are as follows: the main body 4 of the adapter board is precisely cut using a dicing machine, thereby dividing the entire main body 4 of the adapter board into several independent small adapter board chips with sizes that meet the design requirements, thus forming a complete adapter board.

[0087] Reference Figure 8 and Figure 9 Specifically, in step S5, by performing post-processing on opposite sides of the adapter board body 4 in sequence, a redistribution layer 5 and a surface pad 6 can be set on opposite sides of the adapter board body 4.

[0088] In this embodiment, the metal wiring 321 is not further processed in steps S3-S5, so that the aspect ratio of the metal wiring 321 in the final adapter board is not less than 10:1, and thus the aspect ratio of the manufactured adapter board is the aspect ratio of the metal wiring 321, that is, the aspect ratio of the adapter board is not less than 10:1.

[0089] The implementation principle of this application embodiment is as follows: by superimposing multiple planar wiring layers 3 on the temporary carrier board 1 to form the adapter board body 4, the adapter board body 4 is then separated from the temporary carrier board 1, and finally, the adapter board body 4 is post-processed to obtain a complete adapter board.

[0090] The adapter board fabricated by this method has a final aspect ratio equal to the length-to-width ratio of the metal wiring 321. Fabricating long and thin metal wiring 321 on a two-dimensional plane is much simpler than etching deep and narrow vias on a silicon wafer. Furthermore, metal wiring 321 with a length exceeding 1 mm and a width of only 10 µm can be easily fabricated on a wafer-level plane. This allows the aspect ratio of the adapter board fabricated in this application to reach or even exceed 100:1.

[0091] Therefore, this application effectively reduces the manufacturing difficulty of high aspect ratio adapter boards by converting the aspect ratio of the vertical structure of the adapter board into the aspect ratio of the metal wiring 321 on a two-dimensional plane.

[0092] This embodiment also discloses a high aspect ratio adapter board, see reference. Figure 8 and Figure 9 The system includes an adapter board body 4, which comprises several planar routing layers 3 stacked sequentially. Each planar routing layer 3 includes a dielectric layer 31 and a metal wire layer 32, with the metal wire layer 32 superimposed on the dielectric layer 31. The metal wire layer 32 includes several metal wires 321, with an aspect ratio of not less than 10:1. Surface pads 6 are provided on opposite sides of the adapter board body 4, with the spacing between two surface pads 6 along the length of the metal wires 321. Thus, the surface pads 6 are located on one side of the planar routing layers 3, and all planar routing layers 3 are fixedly connected to the surface pads 6. The surface pads 6 are electrically connected to the several metal wires 321.

[0093] In this embodiment, to establish interlayer electrical interconnections within the main body 4 of the adapter board, conductive vias are provided on the dielectric layer 31, and conductive materials, such as copper, are deposited within the conductive vias. This allows corresponding metal wirings 321 between adjacent planar wiring layers 3 to be electrically connected, thereby enabling selective electrical connections between the metal wirings 321 of adjacent planar wiring layers 3. Therefore, the surface pads 6 do not need to be electrically connected to all metal wirings 321; they only need to be electrically connected to a portion of the metal wirings 321 to form an adapter board with a complete three-dimensional wiring network.

[0094] The implementation principle of this application embodiment is as follows: the structural design of the adapter board transforms the manufacturing of the existing three-dimensional vertical interconnect structure into a layer-by-layer superposition of two-dimensional planar processes. Furthermore, the adapter board transforms the metal wiring 321, which originally extended along the length direction on the two-dimensional plane, into a vertical conductive path penetrating the thickness direction of the adapter board. This allows the aspect ratio of the metal wiring 321 to directly determine the effective aspect ratio of the adapter board, thereby improving the aspect ratio of the adapter board.

[0095] Example 2: A method for manufacturing a high aspect ratio adapter plate. The difference between Example 1 and Example 2 is as follows: In step S1, one or more temporary bonding coatings 2 are applied to both sides of the temporary carrier plate 1.

[0096] In step S2, planar wiring layers 3 are fabricated on both sides of the temporary carrier board 1.

[0097] In step S3, several planar wiring layers 3 are sequentially superimposed on the planar wiring layers 3 on both sides of the temporary carrier board 1, and all the planar wiring layers 3 on the same side of the temporary carrier board 1 form a transition board body 4.

[0098] In step S4, the main bodies 4 of the adapter plates on both sides of the temporary carrier plate 1 are separated from the temporary carrier plate 1.

[0099] Reference Figure 10 and Figure 11 Preferably, in step S2, planar wiring layers 3 are sequentially fabricated on opposite sides of the temporary carrier board 1.

[0100] Reference Figure 11 and Figure 12 Preferably, in step S3, several planar wiring layers 3 are simultaneously stacked on opposite sides of the temporary carrier board 1.

[0101] Reference Figure 12 and Figure 13 Preferably, in step S4, the adapter plate bodies 4 on both sides of the temporary carrier plate 1 are separated from the temporary carrier plate 1.

[0102] Reference Figure 12 Specifically, in step S3, the two adapter plate bodies 4 are symmetrically arranged on both sides of the temporary carrier plate 1. At this time, the arrangement of the metal wiring 321 within the two adapter plate bodies 4 is symmetrical about the temporary carrier plate 1.

[0103] The implementation principle of this application embodiment is as follows: by simultaneously and symmetrically stacking several planar wiring layers 3 on opposite sides of a temporary carrier plate 1, two adapter board bodies 4 are manufactured at once, and the two adapter board bodies 4 are simultaneously separated from the temporary carrier plate 1. This manufacturing method has the following technical effects: On the one hand, since the adapter board bodies 4 can be manufactured simultaneously on opposite sides of the temporary carrier plate 1, the manufacturing efficiency of the adapter board can be increased. On the other hand, since the manufacturing and separation of the adapter board bodies 4 are carried out simultaneously on opposite sides of the temporary carrier plate 1, the internal stress generated by the manufacturing and separation of one adapter board body 4 on the temporary carrier plate 1 is offset by the internal stress generated by the manufacturing and separation of the other adapter board body 4 on the temporary carrier plate 1. This can effectively reduce the warping deformation of the temporary carrier plate 1, thus ensuring the flatness and stability of the temporary carrier plate 1 throughout the entire manufacturing process, thereby improving the yield rate of the final manufactured adapter board.

[0104] The embodiments described in this specific implementation are preferred embodiments of this application and are not intended to limit the scope of protection of this application. Identical components are represented by the same reference numerals. Therefore, all equivalent changes made to the structure, shape, and principle of this application should be covered within the scope of protection of this application.

Claims

1. A method for manufacturing a high aspect ratio adapter plate, characterized in that, Includes the following steps: S1. Set up a temporary carrier board (1); S2. A planar wiring layer (3) is fabricated on the temporary carrier board (1). The planar wiring layer (3) includes a dielectric layer (31) and a plurality of metal wirings (321) disposed on the dielectric layer (31). S3. Several layers of the planar wiring layer (3) are sequentially stacked on the planar wiring layer (3), and all the planar wiring layers (3) form the main body of the adapter board (4). S4. Separate the adapter plate body (4) from the temporary carrier plate (1); S5. Post-process the adapter board body (4) to create surface pads (6) on the adapter board body (4) and make the surface pads (6) electrically connected to the metal wiring (321) to form an adapter board with a three-dimensional structure. Furthermore, the aspect ratio of the metal wiring (321) within the adapter board is not less than 10:1; Specifically, step S5 includes: Adjust the position of the adapter plate body (4) so ​​that the metal wiring (321) inside the adapter plate body (4) is vertically arranged; The surface pads (6) are made on both the top and bottom surfaces of the adapter board body (4), and the surface pads (6) are electrically connected to the metal wiring (321).

2. The method for manufacturing a high aspect ratio adapter plate according to claim 1, characterized in that, In step S2, the planar wiring layer (3) is fabricated on both sides of the temporary carrier board (1). In step S3, several layers of planar wiring layers (3) are sequentially stacked on the planar wiring layers (3) on both sides of the temporary carrier board (1), and all the planar wiring layers (3) on the same side of the temporary carrier board (1) form a main body of the adapter board (4).

3. The method for manufacturing a high aspect ratio transition plate according to claim 2, characterized in that, In step S2, the planar wiring layer (3) is simultaneously fabricated on both sides of the temporary carrier board (1).

4. The method for manufacturing a high aspect ratio adapter plate according to claim 2, characterized in that, In step S3, several layers of the planar wiring layer (3) are simultaneously stacked on opposite sides of the temporary carrier board (1).

5. The method for manufacturing a high aspect ratio adapter plate according to claim 2, characterized in that, In step S3, the two adapter plate bodies (4) are symmetrically arranged on both sides of the temporary carrier plate (1).

6. The method for manufacturing a high aspect ratio adapter plate according to claim 1, characterized in that, In step S3, the metal wiring (321) in the two adjacent planar wiring layers (3) are arranged alternately.

7. The method for manufacturing a high aspect ratio adapter plate according to claim 1, characterized in that, In both steps S2 and S3, the dielectric layer (31) is ground until the surface of the dielectric layer (31) is flat.

8. The method for manufacturing a high aspect ratio adapter plate according to claim 1, characterized in that, Step S1 further includes: applying a temporary bonding coating (2) to the surface of the temporary carrier plate (1).

9. A method for manufacturing a high aspect ratio adapter plate according to claim 8, characterized in that, In step S4, the adapter plate body (4) is separated from the temporary carrier plate (1) by a debonding process.

10. A high aspect ratio adapter board, manufactured using the high aspect ratio adapter board manufacturing method described in any one of claims 1-9, characterized in that, include: A plurality of planar wiring layers (3) are stacked sequentially to form a main body of the adapter board (4). The planar wiring layer (3) includes a dielectric layer (31) and a plurality of metal wirings (321) disposed on the surface of the dielectric layer (31). The plurality of metal wirings (321) between two adjacent planar wiring layers (3) are electrically connected. The aspect ratio of the metal wirings (321) is not less than 10:

1. The surface pads (6) are provided on both sides of the main body (4) along the length of the metal wiring (321). Several planar wiring layers (3) are connected to the surface pads (6), and the surface pads (6) are electrically connected to several metal wirings (321).

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