Cob package module and packaging method thereof

Abstract

This application provides a COB (Chip-on-Board) packaged module and its packaging method, relating to integrated packaging of semiconductor devices. The COB packaged module includes a COB substrate and three sets of MOSFETs attached to the COB substrate. Each set of MOSFETs, one output via, and one conductive pin bonding area corresponds to one phase. Each set includes an upper arm MOSFET and a lower arm MOSFET, evenly distributed on both sides of the corresponding output via. The MOSFETs are all bare chips, with their drain (D) located on the bottom surface and their gate (G) and source (S) located on the top surface. The bottom surface is attached to the base island region of the COB substrate. The gate and source are respectively connected to the gate bonding area and source bonding area of ​​the COB substrate via different bonding wires. The gate bonding area is connected to the corresponding control pin soldered in the corresponding conductive pin bonding area through internal circuitry of the COB substrate. The packaging method includes: applying solder paste, surface mounting, reflow soldering, wire bonding, soldering conductive pillars, encapsulation, potting, and baking. This application's solution achieves the function of a full-bridge three-phase power module with a smaller size and higher integration, offering better heat dissipation and higher reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor device packaging technology, and in particular to a COB packaging module and its packaging method. Background Technology

[0002] Full-bridge three-phase power modules are core components in the field of power electronics, used to achieve efficient conversion between DC and three-phase AC. Generally, they integrate six power switching devices (such as MOSFETs or IGBTs) and their driver devices, protection circuits, and other discrete components, assembling them within a circuit board and device housing. However, with the rapid development of next-generation electronic information technology industries such as electric vehicles, industrial drives, new energy power generation, and home appliances, application scenarios are constantly driving the development of full-bridge three-phase power modules towards lower conduction losses, lower switching losses, lower thermal resistance, higher reliability, and higher integration. Wide-bandgap semiconductor materials such as SiC and advanced packaging technologies are the two core driving forces for their performance improvement. Modules integrated and packaged from discrete components are relatively large and have poor heat dissipation, which is not conducive to the spatial layout of downstream applications with higher integration levels; moreover, the reliability and stability of this type of packaging are not ideal, and cannot adequately meet the long-term stable operation requirements under complex conditions in automobiles and industry. Therefore, how to achieve a smaller module size to meet the needs of higher power application scenarios through packaging technology, and how to utilize the limited PCB space for circuit integration, has become a research direction for the development of this module. Summary of the Invention

[0003] To address the shortcomings of the prior art, this application provides a COB packaged module and its packaging method, which achieves the function of a full-bridge three-phase power module with a smaller size and higher integration, and has better heat dissipation and higher reliability.

[0004] To achieve the above objectives, the present invention employs the following techniques: COB-packaged modules are used to implement three-phase full-bridge inverter functions, including: The COB substrate has power vias for mounting VDD conductive pillars and ground vias for mounting GND conductive pillars at one end, and three output vias for mounting phase conductive pillars at the middle. Each output via is provided with a conductive pin soldering area at the interval, and each conductive pin soldering area is used to solder multiple conductive pins. Three groups of MOSFETs, each group corresponding to an output via and a conductive pin soldering area. One group of MOSFETs, one output via, and one conductive pin soldering area corresponds to one phase. Each group includes an upper arm MOSFET and a lower arm MOSFET that are spaced apart on both sides of the corresponding output via and are equal in number. The conductive pins in a single conductive pin soldering area include two sets of control pins of equal number. The two sets of control pins are independent of each other and correspond to all upper arm MOSFETs and all lower arm MOSFETs of a single group of MOSFETs, respectively. All MOSFETs are bare chips with their drain (D) on the bottom surface and their gate (G) and source (S) on the top surface. The bottom surface is attached to the base island region of the COB substrate. The gate and source are connected to the gate bonding area and source bonding area of ​​the COB substrate respectively through different bonding wires. The gate bonding area is connected to the corresponding control pins soldered in the corresponding conductive pin bonding area through the internal circuit of the COB substrate. The drain (D) of the upper arm MOS is connected to the VDD conductive pillar assembled at the power via through the internal circuitry of the COB substrate, and the source (S) is connected to the phase conductive pillar assembled at the corresponding output via through the internal circuitry of the COB substrate via the source soldering area. The drain (D) of the lower arm MOS is connected to the phase conductor post mounted at the corresponding output via through the internal circuitry of the COB substrate, and the source (S) is connected to the GND conductor post mounted at the ground via through the internal circuitry of the COB substrate via the source soldering area.

[0005] Furthermore, each group of MOSFETs has 3 upper arm MOSFETs arranged side by side with spacing, and 3 lower arm MOSFETs arranged side by side with spacing. The output vias and conductive pin soldering areas are located in the area between the upper arm MOSFETs and the lower arm MOSFETs.

[0006] Furthermore, the gate bonding area and source bonding area corresponding to each MOSFET are located on the same side of the MOSFET.

[0007] Furthermore, the gate (G) of each MOSFET is connected to the gate bonding area via a single bonding wire, and the source (S) is connected to the source bonding area via multiple bond wires spaced apart side by side. The bond wires of the S are thicker than the bond wires of the G.

[0008] Furthermore, the COB substrate has a copper-clad area, which is spaced around the ground via and the power via. The copper-clad area where the ground via is located is separate from the copper-clad area where the power via is located.

[0009] Furthermore, two rows of nickel-gold sheets are attached to the COB substrate, with the two rows of nickel-gold sheets respectively arranged on both sides of the COB substrate. Each conductive pin soldering area, each MOSFET, and each output via are arranged in the area between the two rows of nickel-gold sheets.

[0010] Furthermore, three pairs of shunt resistors are mounted on the COB substrate, with one pair spaced apart at the lower arm MOS of each group of MOS transistors. Each pair of shunt resistors is connected in parallel through the internal circuitry of the COB substrate, and then connected in series between the source soldering area connected to the S terminal of the lower arm MOS of the corresponding group of MOS transistors and the GND conductive post mounted at the grounding via.

[0011] Furthermore, at least one conductive pin soldering area is provided with a thermistor attached to the COB substrate at intervals. The conductive pin of the conductive pin soldering area with the thermistor also includes an independent pin. One end of the thermistor is connected to the GND conductive post assembled at the grounding through hole through the internal circuit of the COB substrate, and the other end is connected to the independent pin through the internal circuit of the COB substrate.

[0012] Furthermore, each MOS transistor has a protective resistor attached to the COB substrate at a time interval at its corresponding gate bonding area. The two ends of the resistor are connected in series between the corresponding gate bonding area and the corresponding control pin through the internal circuitry of the COB substrate.

[0013] Furthermore, each set of RC filter units is provided at intervals at the upper arm MOS and the lower arm MOS of each set of MOS transistors. The RC filter unit includes a filter capacitor and a filter resistor connected in series and attached to the COB substrate. The RC filter unit at the upper arm MOS has one end of its filter capacitor connected to the drain of the upper arm MOS through the internal circuit of the COB substrate, and the other end connected to one end of the filter resistor through the internal circuit of the COB substrate. The other end of the filter resistor is connected to the phase line conductive post assembled at the corresponding output via through the internal circuit of the COB substrate. The RC filter unit at the lower arm MOS has one end of its filter capacitor connected to the phase line conductive post mounted at the corresponding output via through the internal circuit of the COB substrate, and the other end connected to one end of the filter resistor through the internal circuit of the COB substrate. The other end of the filter resistor is connected to the GND conductive post mounted at the ground via through the internal circuit of the COB substrate.

[0014] Furthermore, each group of MOSFETs has a buffer unit spaced apart at the upper arm MOSFET. The buffer unit includes at least one buffer capacitor attached to the COB substrate. When the buffer unit includes multiple buffer capacitors, the multiple buffer capacitors are connected in parallel. One end of the buffer unit is connected to the VDD conductive pillar assembled at the power via through the internal circuit of the COB substrate, and the other end is connected to the source soldering area connected to the S terminal of the upper arm MOSFET through the internal circuit of the COB substrate.

[0015] Furthermore, each group of MOSFETs has an absorption capacitor attached to the COB substrate at intervals at the lower arm MOSFET. One end of the capacitor is connected to the drain of the lower arm MOSFET through the internal circuitry of the COB substrate, and the other end is connected to the GND conductive post assembled at the grounding via through the internal circuitry of the COB substrate.

[0016] The packaging method for the COB packaging module includes the following steps: Apply solder paste to the base island area of ​​the COB substrate; Place each bare MOSFET chip on the base island area with its bottom surface facing down in contact with the solder paste; Perform IR reflow soldering to complete the die bonding and drain conduction of the bare MOSFET chip; Perform wire bonding, completing the connection of specified bond wires through a bonding operation; Assemble and weld VDD conductive posts at the power through holes, assemble and weld GND conductive posts at the ground through holes, assemble and weld phase conductor conductive posts at the output through holes, and weld conductive pins at each conductive pin soldering area. The components are housed within the casing, and then potted with adhesive and baked to cure, completing the encapsulation. After encapsulation, the VDD conductive post, GND conductive post, phase conductor conductive post, and conductive pin are exposed outside the casing.

[0017] The beneficial effects of this invention are as follows: 1. A three-phase full-bridge integration in COB (Chip-on-Board) packaging is achieved, which improves reliability and enables layout in limited substrate space. It adopts bare chip and surface-mount resistor and capacitor packaging, which only requires bonding the gate and source of MOSFETs, greatly reducing the number of bonding wires, reducing the probability of bonding failure, and improving heat conduction efficiency. Each upper / lower arm uses 3 MOSFETs in parallel, which enables the carrying capacity of larger currents and meets the requirements of downstream high-current applications. 2. Arrange the GND and VDD positions on the substrate in a reasonable manner to facilitate the internal substrate traces connecting the drain of all upper arm MOS to VDD and the source of all lower arm MOS to GND; at the same time, distribute the U-phase, V-phase, and W-phase outputs in the middle and between the upper arm MOS and the lower arm MOS to facilitate the connection between the source of the upper arm MOS and the drain of the lower arm MOS and the phase line, so as to minimize the length of the conduction line and save overall space while ensuring effective conduction; 3. By setting up nickel-gold sheet arrays on both sides, a shielding effect against external signals is achieved from both sides, improving the performance stability of the module. The reasonable setting of the copper-clad area provides good heat dissipation at the ends connecting VDD and GND, which is conducive to ensuring the reliability of the module's long-term operation. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the packaging layout of the COB packaging module according to an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of a single-phase circuit of a COB packaged module according to an embodiment of this application.

[0020] Figure 3 This is a flowchart of the packaging method steps of the COB packaging module according to an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the implementation methods of the present invention will be described in detail below with reference to the accompanying drawings. However, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments.

[0022] This application provides a COB packaged module and its packaging method. The COB packaged module is a module that implements a three-phase full-bridge inverter function, such as... Figure 1 The diagram shows an example layout of the COB packaged module in this instance, which includes a COB substrate and three sets of MOS transistors attached to the COB substrate.

[0023] Specifically, one end of the COB substrate has a power via for mounting the VDD conductive post and a ground via for mounting the GND conductive post. The middle section has three output vias for mounting phase conductors. The power and ground vias are spaced apart along the width of the COB substrate, while the three output vias are spaced apart along the length of the COB substrate. However, this arrangement and position are not unique and can be adjusted according to the substrate shape. The three output vias mount three phase conductors, serving as the three-phase (U-phase, V-phase, and W-phase) output terminals.

[0024] Each output via is spaced out with a conductive pin soldering area. There are three conductive pin soldering areas in total: conductive pin soldering area J1, conductive pin soldering area J2, and conductive pin soldering area J3, as shown below. Figure 1 In the example shown, the output through-hole of the phase conductor post assembly of phase U corresponds to the conductive pin soldering area J1, the output through-hole of the phase conductor post assembly of phase V corresponds to the conductive pin soldering area J2, and the output through-hole of the phase conductor post assembly of phase W corresponds to the conductive pin soldering area J3. Each conductive pin soldering area is used to solder multiple conductive pins.

[0025] Each group of MOSFETs corresponds to one output via and one conductive pin solder pad, that is, one group of MOSFETs, one output via, and one conductive pin solder pad corresponds to one phase.

[0026] Each group of MOSFETs includes an upper arm MOSFET and a lower arm MOSFET, which are spaced apart on both sides of the corresponding output via and are of equal number. Optionally, each group of MOSFETs includes one upper arm MOSFET and one lower arm MOSFET. The upper arm MOSFET and the lower arm MOSFET may also each include multiple equal numbers. Preferably, as shown below... Figure 1The example shown illustrates that each group of MOSFETs includes three upper-arm MOSFETs and three lower-arm MOSFETs. The three upper-arm MOSFETs are connected in parallel and arranged side-by-side with spacing, while the three lower-arm MOSFETs are connected in parallel and arranged side-by-side with spacing. In each phase, the output vias and conductive pin solder pads are located in the area between the upper-arm and lower-arm MOSFETs. By optimizing the number and arrangement, the conduction losses and heat generation of the upper and lower arms are reduced, and the output current is significantly increased. This allows the module to be used in scenarios with higher current output, improves the module's fault tolerance, and extends the lifespan of individual transistors. Specifically, as shown... Figure 1 As shown, for phase U, the upper arm MOSFETs include MOSFETs Q1, Q2, and Q3, and the lower arm MOSFETs include MOSFETs Q10, Q11, and Q12; for phase V, the upper arm MOSFETs include MOSFETs Q4, Q5, and Q6, and the lower arm MOSFETs include MOSFETs Q13, Q14, and Q15; for phase W, the upper arm MOSFETs include MOSFETs Q7, Q8, and Q9, and the lower arm MOSFETs include MOSFETs Q16, Q17, and Q18.

[0027] Each conductive pin solder area comprises two sets of control pins of equal number. These two sets of control pins are independent of each other, corresponding to all upper-arm MOSFETs and all lower-arm MOSFETs of a single MOSFET group, respectively. That is, in each phase, the upper-arm MOSFETs can share one set of control pins, which is connected to the same external PWM control signal during application. The lower-arm MOSFETs can share another set of control pins, which is connected to a different external PWM control signal during application. A total of 6 sets of control pins are used across the three phases to connect to 6 different PWM control signals.

[0028] Preferably, in such Figure 1 In the example shown, a thermistor R31 is installed at intervals in the conductive pin soldering area J3 of phase W, attached to the COB substrate. The conductive pins to be soldered in area J3 include two sets of control pins and one independent pin. One end of the thermistor R31 is connected to the GND conductive post mounted at the grounding via the internal wiring of the COB substrate, and the other end is connected to the independent pin through the internal wiring of the COB substrate. The addition of the thermistor R31 allows for temperature monitoring of the COB substrate, especially near the phase conductive posts and conductive pins. Similarly, thermistors can be added in phases U and V.

[0029] In this example, all MOSFETs are bare chips with their drain (D) on the bottom surface and their gate (G) and source (S) on the top surface. The bottom surface is attached to the base island region of the COB substrate. The gate and source are connected to the gate bonding area and source bonding area of ​​the COB substrate respectively through different bonding lines. The gate bonding area is connected to the corresponding control pins soldered in the corresponding conductive pin bonding area through the internal circuitry of the COB substrate.

[0030] In each group of MOSFETs, the drain (D) of the upper arm MOSFET is connected to the VDD conductive post mounted at the power via through the internal circuitry of the COB substrate, and the source (S) is connected to the phase conductive post mounted at the corresponding output via through the source solder joint connected to the COB substrate's internal circuitry. Similarly, the drain of the lower arm MOSFET is connected to the phase conductive post mounted at the corresponding output via through the internal circuitry of the COB substrate, and the source (S) is connected to the GND conductive post mounted at the ground via through the source solder joint connected to the COB substrate's internal circuitry. This bonding and internal conductivity form the electrical connection between each phase, as shown below. Figure 2 The circuit diagram shown is for phase U. Phase V and phase W are similar and will not be shown separately.

[0031] Each MOSFET's gate (G) is connected to the gate bonding area via a single thin bonding wire, sufficient to carry a small voltage amplitude control signal, facilitating bonding control in confined spaces. The source (S) bonding wire is thicker than the gate bonding wire. For the source (S) of each MOSFET, which is related to phase line output and ground connection conduction, it needs to carry a larger current. Multiple parallel, spaced thick bonding wires are used to connect to the source bonding area, improving reliability, reducing IR drop (voltage drop caused by conduction resistance and current flow in the internal power grid of the chip), and also facilitating heat conduction from the chip to the COB substrate. Figure 1 The example shown has 5 thick bond wires side by side.

[0032] Preferred, such as Figure 1 As shown, the gate and source bonding areas of each MOS transistor are located on the same side, so that the bonding wires can be routed and bonded from the same direction during bonding, which facilitates the routing of the wiring program with the automated wire bonding machine. In phase U, MOSFETs Q1, Q2, and Q3 correspond to gate bonding regions G1, G2, and G3, respectively; MOSFETs Q10, Q11, and Q12 correspond to gate bonding regions G10, G11, and G12, respectively. In phase V, MOSFETs Q4, Q5, and Q6 correspond to gate bonding regions G4, G5, and G6, respectively; MOSFETs Q13, Q14, and Q15 correspond to gate bonding regions G13, G14, and G15, respectively. In phase W, MOSFETs Q7, Q8, and Q9 correspond to gate bonding regions G7, G8, and G9, respectively; MOSFETs Q16, Q17, and Q18 correspond to gate bonding regions G16, G17, and G18, respectively.

[0033] Each MOSFET has a protective resistor attached to the COB substrate at a distance from its gate bonding area. The resistor's two ends are connected in series between the corresponding gate bonding area and the corresponding control pin via internal circuitry on the COB substrate. This resistor is used for current limiting, suppressing gate oscillation, and preventing false turn-on. Specifically, for example... Figure 1 As shown, protective resistors R1, R2, R3, R4, R5, R6, R7, R8, and R9 are placed next to gate soldering area G1 at intervals. A protective resistor R10 is placed next to the gate soldering area G11, the gate soldering area G12, the gate soldering area G13, the gate soldering area G14, the gate soldering area G15, the gate soldering area G16, the gate soldering area G17, and the gate soldering area G18.

[0034] Three pairs of shunt resistors are mounted on the COB substrate, with one pair spaced apart at the lower arm MOSFET of each group to enhance power capacity. Each pair of shunt resistors is connected in parallel through the internal circuitry of the COB substrate, and then connected in series between the source solder area connected to the source of the corresponding lower arm MOSFET and the GND conductive post mounted at the ground via. Figure 1 As shown, phase U has shunt resistors R25 and R26, phase V has shunt resistors R27 and R28, and phase W has shunt resistors R29 and R30; Figure 2 As shown, the connection relationship of shunt resistors R25 and R26 in phase U is illustrated in the circuit.

[0035] To improve the heat dissipation effect of the COB substrate, preferably, a copper-clad area J5 is provided on the COB substrate. The copper-clad area J5 is spaced around the grounding via and the power via. The copper-clad area J5 where the grounding via is located and the copper-clad area J5 where the power via is located are spaced independently from each other and are spaced apart from the chips and components on the COB substrate.

[0036] Preferably, two rows of nickel-gold sheets J4 are mounted on the COB substrate, and the two rows of nickel-gold sheets J4 are respectively arranged on both sides of the COB substrate, such as... Figure 1As shown, there are 8 in each row. Each conductive pin solder area, each MOSFET, and each output via are arranged in the area between the two rows of nickel-gold plates J4. The two rows of nickel-gold plates J4 can improve the shielding effect of the module against external signals.

[0037] Preferably, each group of MOSFETs has an RC filter unit spaced apart at the upper and lower arm MOSFETs. The RC filter unit includes a filter capacitor and a filter resistor connected in series and mounted on the COB substrate. These are used to suppress high-frequency oscillations and voltage ringing caused by MOSFET switching, reduce electromagnetic interference (EM), and smooth voltage jumps. In the upper arm MOSFET, one end of the filter capacitor is connected to the drain (D) terminal of the upper arm MOSFET through internal circuitry on the COB substrate, and the other end is connected to one end of the filter resistor through internal circuitry on the COB substrate. The other end of the filter resistor is connected to the phase conductor at the corresponding output via through internal circuitry on the COB substrate. Similarly, in the lower arm MOSFET, one end of the filter capacitor is connected to the phase conductor at the corresponding output via through internal circuitry on the COB substrate, and the other end is connected to one end of the filter resistor through internal circuitry on the COB substrate. The other end of the filter resistor is connected to the GND conductor at the grounding via through internal circuitry on the COB substrate. The RC filter unit absorbs voltage spikes and protects the MOSFETs. Specifically, for example… Figure 1 As shown, the RC filter unit corresponding to the upper arm MOS in phase U includes a filter capacitor C1 and a filter resistor R19, and the RC filter unit corresponding to the lower arm MOS includes a filter capacitor C4 and a filter resistor R22, as follows. Figure 2 The diagram shows the connection positions and relationships of filter capacitor C1, filter resistor R19, filter capacitor C4, and filter resistor R22 in the circuit. Through the internal circuitry of the COB substrate, one end of filter capacitor C1 is connected to the drain (D) of the upper arm MOS, and the other end is connected to one end of filter resistor R19. The other end of filter resistor R19 is connected to the conductive post of phase U. One end of filter capacitor C4 is connected to the conductive post of phase U, and the other end is connected to one end of filter resistor R22. The other end of filter resistor R22 is connected to the GND conductive post. Similarly, for phase V, the RC filter unit at the upper arm MOS includes filter capacitor C2 and filter resistor R20, and the RC filter unit at the lower arm MOS includes filter capacitor C5 and filter resistor R23. For phase W, the RC filter unit at the upper arm MOS includes filter capacitor C3 and filter resistor R21, and the RC filter unit at the lower arm MOS includes filter capacitor C6 and filter resistor R24. Based on the same principle as the RC filter element for phase U, the connection relationships of the RC filter elements for phase V and phase W are not described further.

[0038] Each MOSFET has a buffer unit spaced apart at the upper arm of the MOSFET. Each buffer unit includes at least one buffer capacitor mounted on the COB substrate. When a buffer unit includes multiple buffer capacitors, these capacitors are connected in parallel. Figure 1As shown, each buffer unit uses two buffer capacitors. For phase U, the buffer unit includes two buffer capacitors C10 connected in parallel; for phase V, the buffer unit includes two buffer capacitors C11 connected in parallel; and for phase W, the buffer unit includes two buffer capacitors C12 connected in parallel. Figure 2 The diagram shows the circuit connection of the buffer unit in phase U. One end of the buffer capacitor C10 is connected to the VDD conductive post mounted at the power via through the internal circuitry of the COB substrate, and the other end is connected to the source solder joint of the upper arm MOSFET connected to the S terminal through the internal circuitry of the COB substrate. The connection method of the buffer unit in phases V and W can be implemented based on the same principle as in phase U, and will not be described further. By adding the buffer unit, instantaneous high voltage spikes can be absorbed, surge voltages can be suppressed, forming double redundancy protection to prevent the MOSFET from being broken down by high voltage.

[0039] Each group of MOSFETs has a snubber capacitor attached to the COB substrate at intervals at the lower arm MOSFET location, such as... Figure 1 As shown, phase U has an absorption capacitor C7, phase V has an absorption capacitor C8, and phase W has an absorption capacitor C9. Figure 2 As shown, one end of the absorption capacitor C7 is connected to the drain (D) of the lower arm MOSFET through the internal circuitry of the COB substrate, and the other end is connected to the GND conductive post mounted at the grounding via through the internal circuitry of the COB substrate. The connection principle of the absorption capacitors C8 (V phase), C9 (W phase), and C7 (U phase) is the same and will not be described again. The connection of absorption capacitors C7, C8, and C9 can suppress EMI interference, absorb high voltage spikes between the phase lines and ground, and protect the lower arm MOSFET.

[0040] like Figure 1 As shown, the COB substrate also has a row of bus capacitors C13, and multiple capacitors can be set according to actual application requirements. For example, eight capacitors are set in this example. Their two ends are connected in parallel through the internal circuit of the COB substrate and connected between the VDD conductive post mounted at the power supply through hole and the GND conductive post mounted at the grounding through hole. They are used for energy storage, instantaneous large current replenishment, and filtering of high frequency ripple of the bus.

[0041] In this example, all resistors are surface mount resistors, and all capacitors are MLCCs.

[0042] The COB encapsulation module encapsulation method described in this example is as follows: Figure 3 As shown, the steps include: (1) Apply solder paste to the base island area of ​​the COB substrate. Specifically, the unwanted areas can be covered in advance by screen printing. (2) Place each bare MOSFET chip on the base island area with the bottom surface facing down in contact with the solder paste; (3) Perform IR reflow soldering to complete the die bonding and D-terminal conduction of the bare MOS transistor chip; (4) Perform wire bonding. Complete the connection of the specified bonding wire through the bonding operation. During wire bonding, pay attention to the normality of the solder joint and avoid the phenomenon of poor soldering or pressure deviation. Among them, for the fine bonding wire bonded to the gate of the MOSFET, 5MIL aluminum wire can be used, and for the thick bonding wire bonded to the source of the MOSFET, 20MIL aluminum wire can be used. (5) After the wire bonding is completed, the wire is transferred to prepare for welding of conductive posts and conductive pins. During the transfer, the wire is picked up and transferred by an automated machine or handled by an operator wearing finger cots or carrying fixtures. Then, the VDD conductive post is assembled and welded at the power through hole, the GND conductive post is assembled and welded at the grounding through hole, the phase wire conductive post is assembled and welded at the output through hole, and the conductive pins are welded at each conductive pin welding area. (6) Place it inside the housing and fill the housing with glue. Bake and cure it. During baking, ensure that the encapsulated gel solidifies and avoid any uncured flow. After encapsulation, the VDD conductive post, GND conductive post, phase wire conductive post, and conductive pin are exposed outside the housing.

[0043] When mounting RC filter units, buffer units, absorption capacitors, nickel-gold plates, protective resistors, thermistors, shunt resistors, etc. on a COB substrate, these components can be pre-mounted on the COB substrate or mounted together during the MOSFET bare chip mounting process. In this case, solder paste needs to be applied to the soldering areas / pads where capacitors and resistors will be mounted during the soldering process. Then, after the MOSFET bare chip is mounted, components can be mounted sequentially according to their type, or functional units and components can be mounted sequentially according to different phases or functions. Specific mounting methods include manual mounting (using a pick-and-place pen), manual mounting of some components and / or chips while automatic mounting of others (SMT pick-and-place machine), or automatic mounting sequentially using different pick-and-place machines. During mounting, care must be taken to avoid solder paste overflow.

[0044] The COB packaged module obtained through this example for implementing a three-phase full-bridge function has a smaller size, higher integration, better heat dissipation, and higher reliability.

[0045] In application, the above description is only a preferred embodiment of this application and is not intended to limit this application. Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application.

Claims

1. A COB packaged module, characterized in that, Used to implement three-phase full-bridge inverter function, including: The COB substrate has power vias for mounting VDD conductive pillars and ground vias for mounting GND conductive pillars at one end, and three output vias for mounting phase conductive pillars at the middle. Each output via is provided with a conductive pin soldering area at the interval, and each conductive pin soldering area is used to solder multiple conductive pins. Three groups of MOSFETs, each group corresponding to an output via and a conductive pin soldering area. Each group includes an upper arm MOSFET and a lower arm MOSFET that are equally distributed on both sides of the corresponding output via. The conductive pins in a single conductive pin soldering area include two sets of control pins of the same number. The two sets of control pins are independent of each other and correspond to all upper arm MOSFETs and all lower arm MOSFETs of a single MOSFET group, respectively. All MOSFETs are bare chips with their drain (D) on the bottom surface and their gate (G) and source (S) on the top surface. The bottom surface is attached to the base island region of the COB substrate. The gate and source are connected to the gate bonding area and source bonding area of ​​the COB substrate respectively through different bonding wires. The gate bonding area is connected to the corresponding control pins soldered in the corresponding conductive pin bonding area through the internal circuit of the COB substrate. The drain (D) of the upper arm MOS is connected to the VDD conductive pillar assembled at the power via through the internal circuitry of the COB substrate, and the source (S) is connected to the phase conductive pillar assembled at the corresponding output via through the internal circuitry of the COB substrate via the source soldering area. The drain (D) of the lower arm MOS is connected to the phase conductor post mounted at the corresponding output via through the internal circuitry of the COB substrate, and the source (S) is connected to the GND conductor post mounted at the ground via through the internal circuitry of the COB substrate via the source soldering area.

2. The COB packaging module according to claim 1, characterized in that, Each group of MOSFETs has 3 upper arm MOSFETs arranged side by side with spacing, and 3 lower arm MOSFETs arranged side by side with spacing. The output vias and conductive pin soldering areas are located in the area between the upper arm MOSFETs and the lower arm MOSFETs. The gate and source bonding areas of each MOSFET are located on the same side of the MOSFET. The gate (G) of each MOSFET is connected to the gate bonding area via a single bonding wire, and the source (S) is connected to the source bonding area via multiple bond wires spaced apart side by side. The bond wires of the S are thicker than those of the G.

3. The COB packaging module according to claim 1, characterized in that, Three pairs of shunt resistors are mounted on the COB substrate. A pair of shunt resistors is spaced apart at the lower arm MOS of each group of MOS transistors. Each pair of shunt resistors is connected in parallel through the internal circuitry of the COB substrate and then connected in series between the source soldering area connected to the S terminal of the lower arm MOS of the corresponding group of MOS transistors and the GND conductive post mounted at the grounding via.

4. The COB packaging module according to claim 1, characterized in that, At least one conductive pin soldering area is provided with a thermistor attached to the COB substrate at intervals. The conductive pin of the conductive pin soldering area with the thermistor also includes an independent pin. One end of the thermistor is connected to the GND conductive post assembled at the grounding through hole through the internal circuit of the COB substrate, and the other end is connected to the independent pin through the internal circuit of the COB substrate.

5. The COB packaging module according to claim 1, characterized in that, Each MOS transistor has a protective resistor attached to the COB substrate at a time interval at its gate soldering area. The two ends of the resistor are connected in series between the corresponding gate soldering area and the corresponding control pin through the internal circuitry of the COB substrate.

6. The COB packaging module according to claim 1, characterized in that, Each set of MOSFETs has an RC filter unit spaced apart at the upper arm MOSFET and the lower arm MOSFET. The RC filter unit includes a filter capacitor and a filter resistor connected in series and attached to the COB substrate. The RC filter unit at the upper arm MOS has one end of its filter capacitor connected to the drain of the upper arm MOS through the internal circuit of the COB substrate, and the other end connected to one end of the filter resistor through the internal circuit of the COB substrate. The other end of the filter resistor is connected to the phase line conductive post assembled at the corresponding output via through the internal circuit of the COB substrate. The RC filter unit at the lower arm MOS has one end of its filter capacitor connected to the phase line conductive post mounted at the corresponding output via through the internal circuit of the COB substrate, and the other end connected to one end of the filter resistor through the internal circuit of the COB substrate. The other end of the filter resistor is connected to the GND conductive post mounted at the ground via through the internal circuit of the COB substrate.

7. The COB packaging module according to claim 1, characterized in that, Each group of MOSFETs has a buffer unit spaced apart at the upper arm MOSFET. The buffer unit includes at least one buffer capacitor attached to the COB substrate. When the buffer unit includes multiple buffer capacitors, the multiple buffer capacitors are connected in parallel. One end of the buffer unit is connected to the VDD conductive pillar assembled at the power via through the internal circuitry of the COB substrate, and the other end is connected to the source soldering area connected to the S terminal of the upper arm MOS through the internal circuitry of the COB substrate.

8. The COB packaging module according to claim 1, characterized in that, Each group of MOSFETs has an absorption capacitor attached to the COB substrate at intervals at the lower arm MOSFET. One end of the capacitor is connected to the drain of the lower arm MOSFET through the internal circuitry of the COB substrate, and the other end is connected to the GND conductive post mounted at the grounding via through the internal circuitry of the COB substrate.

9. The COB packaging module according to claim 1, characterized in that, Two rows of nickel-gold sheets are attached to the COB substrate, with the two rows of nickel-gold sheets arranged on both sides of the COB substrate. Each conductive pin solder area, each MOSFET, and each output via are arranged in the area between the two rows of nickel-gold sheets.

10. The packaging method for the COB packaging module as described in any one of claims 1-9, characterized in that, Including the following steps: Apply solder paste to the base island area of ​​the COB substrate; Place each bare MOSFET chip on the base island area with its bottom surface facing down in contact with the solder paste; Perform IR reflow soldering to complete the die bonding and drain conduction of the bare MOSFET chip; Wire bonding is performed to complete the connection of the bonding wires through a bonding process. Assemble and weld VDD conductive posts at the power through holes, assemble and weld GND conductive posts at the ground through holes, assemble and weld phase conductor conductive posts at the output through holes, and weld conductive pins at each conductive pin soldering area. It is placed inside the housing, glue is poured into the housing, and then baked and cured to complete the encapsulation.

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