Chip package structure and method of manufacturing the same

Abstract

The application discloses a chip packaging structure and a preparation method thereof, and relates to the technical field of semiconductors. The chip packaging structure comprises a substrate with a conductive column, a first dielectric layer arranged on the substrate, a wiring layer embedded in the first dielectric layer, a second dielectric layer arranged on the first dielectric layer, and a pad arranged on the second dielectric layer, and the conductive column is electrically connected with the pad through the wiring layer; the pad comprises a first metal layer, a second metal layer and a third metal layer arranged in layers, the width of the second metal layer is smaller than the width of the first metal layer and the width of the third metal layer, so that a side wall groove is formed between the first metal layer, the second metal layer and the third metal layer. The chip packaging structure can improve the flow path of the underfill adhesive by using capillary action, improve the filling efficiency and uniformity of the underfill adhesive, and reduce the void defects; meanwhile, the contact area and mechanical interlocking action of the underfill adhesive and the pad can be increased, and the bonding force between the pad and the underfill adhesive can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a chip packaging structure and its fabrication method. Background Technology

[0002] With the rapid development of the semiconductor industry, chip technology has been used to package small chips with different functions together to form heterogeneous integrated chip package structures. As chip input / output densities increase and the number of chips integrated within a single package increases significantly, various 2.5D and 3D packaging technologies have been proposed as multi-chip packaging solutions to connect adjacent chip pads within a single package. Among these, through-silicon via (TSV) technology has been used to form heterogeneous integrated chip package structures to achieve multi-chip integration and reduce package size.

[0003] In 2.5D packaging technology, an adapter board is typically used as an intermediate layer to stack small chips with different functions. After stacking, dispensing or molding processes are required to form a molded enclosure to protect the stacked structure. However, the mold flow can only flow through the gaps between the solder balls to the surface between the bottom flip chip and the adapter board. With the trend of increasingly smaller solder ball gaps and diameters to increase I / O count, excessively small bottom gaps between solder balls can easily lead to voids due to insufficient filling. Therefore, how to improve the flowability of the underfill adhesive, reduce void defects, improve filling efficiency, and enhance the adhesion between the pads and the underfill adhesive without increasing process complexity and cost has become a pressing technical problem to be solved in this field. Summary of the Invention

[0004] The purpose of this application is to provide a chip packaging structure and its fabrication method. By setting sidewall grooves on the pads, the flow path of the underfill adhesive can be improved by capillary action, thereby increasing the filling efficiency and uniformity of the underfill adhesive and reducing void defects. At the same time, it can also increase the contact area and mechanical interlocking effect between the underfill adhesive and the pads, and improve the bonding force between the pads and the adhesive, thereby effectively improving the reliability and yield of the chip packaging structure.

[0005] The embodiments of this application are implemented as follows: A first aspect of this application provides a chip packaging structure, including a substrate with conductive pillars, a first dielectric layer disposed on the substrate, a wiring layer embedded in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and pads disposed on the second dielectric layer. The conductive pillars are electrically connected to the pads through the wiring layer. The pads include a first metal layer stacked on top of each other, a second metal layer disposed on the side of the first metal layer away from the substrate, and a third metal layer disposed on the side of the second metal layer away from the substrate. The width of each of the second metal layers is smaller than the width of the first metal layer and the width of the third metal layer, so that a sidewall groove is formed between the first metal layer, the second metal layer, and the third metal layer.

[0006] In one possible implementation, the surface of the third metal layer facing the first metal layer is provided with a protrusion, and the protrusion is at least partially located within the sidewall groove.

[0007] As one possible implementation, the protrusion includes a vertical section that extends in a direction perpendicular to the surface of the third metal layer, and the end of the vertical section is in contact with or has a predetermined gap with the surface of the first metal layer facing the third metal layer.

[0008] In one possible implementation, the protrusion includes a vertical section and a horizontal section, the vertical section extending in a direction perpendicular to the surface of the third metal layer, and the horizontal section bending from the end of the vertical section and extending to the outside of the sidewall groove.

[0009] As one possible implementation, it also includes solder balls, wherein a recess is provided on the surface of the pad away from the substrate, the solder balls are disposed on the side of the pad away from the substrate, and the solder balls at least partially fill the recess.

[0010] In one possible implementation, the substrate has a first surface and a second surface opposite to each other, and the first surface and the second surface of the substrate are each provided with the first dielectric layer, the wiring layer, the second dielectric layer and the pads.

[0011] As one possible implementation, a first substrate is further provided on one side of the second surface of the substrate, and the first substrate is soldered to the pads on the second surface of the substrate so that the first chip provided on the first substrate is electrically connected to the second chip provided on the pads on the first surface of the substrate.

[0012] As one possible implementation, the package further includes a third substrate and a fourth substrate disposed on opposite sides of the substrate. The third substrate and the fourth substrate are respectively soldered to pads on the first surface and the second surface of the substrate, so that a third chip disposed on the third substrate and a fourth chip disposed on the fourth substrate are electrically connected. The substrate includes two substrates, which are respectively disposed on the left and right sides of the third chip and the fourth chip. A first groove and a second groove are respectively disposed on the side of the two substrates near the third chip and the fourth chip. A preset distance is provided between the first groove and the second groove to form a connection portion. The chip packaging structure further includes a fifth chip, the two ends of which are respectively soldered to the connection portion of the two substrates.

[0013] In one possible implementation, the fifth chip is disposed on the surface of the connecting portion facing the fourth substrate, the vertical projection of the fourth chip on the fourth substrate is located within the vertical projection range of the fifth chip on the fourth substrate, a coating layer is disposed between the fifth chip and the fourth substrate, and the coating layer covers the fourth chip.

[0014] As one possible implementation, the edge of the substrate has a cut surface that is exposed to the sidewall of the substrate.

[0015] A second aspect of this application provides a method for fabricating a chip packaging structure, the method comprising: Provide a substrate with conductive pillars; A first dielectric layer is formed on the substrate, and a wiring pattern is formed on the first dielectric layer, wherein the bottom of the wiring pattern exposes the conductive pillars; A wiring layer is formed by electroplating within the wiring pattern; A second dielectric layer is formed on the first dielectric layer and the wiring layer, and a first opening is formed on the second dielectric layer, the bottom of the first opening exposing the wiring layer; A first metal layer is formed by electroplating within the first opening; A first sacrificial layer is formed on the second dielectric layer and the first metal layer, and a second opening is formed on the first sacrificial layer, wherein the width of the second opening is smaller than the width of the first opening; A second metal layer is electroplated within the second opening, such that the width of the second metal layer is smaller than the width of the first metal layer; Remove the first sacrificial layer; A second sacrificial layer is formed on the second dielectric layer, the first metal layer, and the second metal layer, and a third opening is formed on the second sacrificial layer, wherein the width of the second opening is smaller than the width of the third opening; A third metal layer is electroplated within the third opening, such that the width of the second metal layer is smaller than the width of the third metal layer. Remove the second sacrificial layer to form a sidewall groove between the first metal layer, the second metal layer, and the third metal layer.

[0016] The beneficial effects of the embodiments of this application include: The pads of this chip packaging structure include a first metal layer, a second metal layer, and a third metal layer stacked together. The width of the second metal layer is smaller than the width of both the first and third metal layers, forming sidewall grooves between them. On one hand, these sidewall grooves alter the capillary flow path of the underfill adhesive between the chip and the substrate. This change in the cross-section of the flow path generates additional capillary driving force, improving the uniformity of the adhesive flow, effectively reducing voids and bubbles, and increasing underfill efficiency. On the other hand, after the underfill adhesive cures, these sidewall grooves form a mechanical interlock between the adhesive and the pads, increasing the contact area and significantly improving the adhesion between the underfill adhesive and the pads. This resists shear stress caused by differences in thermal expansion coefficients during thermal cycling and mechanical impact, effectively preventing delamination and peeling, thereby comprehensively improving the reliability and yield of the chip packaging structure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the schematic diagrams of the chip packaging structure provided in the first embodiment of this application; Figure 2 This is a second schematic diagram of the state of the chip packaging structure provided in the first embodiment of this application; Figure 3 This is one of the schematic diagrams of the chip packaging structure provided in the second embodiment of this application; Figure 4 This is a second schematic diagram of the chip packaging structure provided in the second embodiment of this application; Figure 5 This is one of the schematic diagrams of the chip packaging structure provided in the third embodiment of this application; Figure 6 This is a second schematic diagram of the chip packaging structure provided in the third embodiment of this application; Figure 7This is a schematic diagram of the chip packaging structure provided in the fourth embodiment of this application; Figure 8 This is a schematic diagram of the chip packaging structure provided in the fifth embodiment of this application; Figure 9 One of the schematic flowcharts for the fabrication method of the chip packaging structure provided in this application; Figure 10 The second schematic diagram of the process for fabricating the chip packaging structure provided in this application; Figure 11 The third schematic diagram of the process for fabricating the chip packaging structure provided in this application.

[0019] Icons: 00-Carrier; 01-Adhesive layer; 10-Substrate; 101-Conductive pillar; 102-First dielectric layer; 1020-Wiring pattern; 1021-Wiring layer; 103-Second dielectric layer; 1030-First opening; 104-First sacrificial layer; 1040-Second opening; 105-Second sacrificial layer; 1050-Third opening; 106-Third dielectric layer; 1060-Fourth opening; 1061-Conductive structure; 107-Third sacrificial layer; 1070-Fifth opening; 108-Fourth sacrificial layer; 1080-Sixth opening; 1081 - Metal layer; 109 - Cut surface; 11 - Second chip; 12 - First groove; 13 - Second groove; 14 - Connector; 141 - Fifth chip; 20 - Pad; 21 - First metal layer; 22 - Second metal layer; 23 - Third metal layer; 25 - Side wall groove; 251 - Protrusion; 27 - Recess; 30 - First substrate; 31 - First chip; 40 - Third substrate; 41 - Third chip; 50 - Fourth substrate; 51 - Fourth chip; 60 - Coating layer; 70 - Filler adhesive; 80 - Molding layer; 90 - Solder ball. Detailed Implementation

[0020] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0021] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending to another element," it may be directly on another element or directly extending to another element, or there may be an intermediate element. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending over another element," it may be directly on another element or directly extending to another element, or there may be an intermediate element.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that, when used herein, the term “comprising” indicates the presence of the stated feature, integer, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein should be interpreted as having the same meaning as they would in the context of this specification and the relevant field, and not in an idealized or overly formal sense, unless expressly defined herein.

[0024] Please refer to the reference. Figures 1 to 11 This application provides a chip packaging structure and its fabrication method. The pad 20 includes a first metal layer 21, a second metal layer 22, and a third metal layer 23 stacked together. The width of the second metal layer 22 is smaller than the width of both the first metal layer 21 and the third metal layer 23, forming a sidewall groove 25 between the first metal layer 21, the second metal layer 22, and the third metal layer 23. On one hand, this sidewall groove 25 alters the capillary flow path of the underfill adhesive 70 between the chip and the substrate 10. The change in the cross-section of the flow path generates additional capillary driving force, improving the flow uniformity of the adhesive, effectively reducing voids and bubbles, and increasing underfill efficiency. On the other hand, after the underfill adhesive 70 cures, the sidewall groove 25 forms a mechanical interlock between the adhesive and the pad 20, increasing the contact area and significantly improving the bonding force between the underfill adhesive 70 and the pad 20. This resists shear stress caused by differences in thermal expansion coefficients during thermal cycling and mechanical impact, effectively preventing delamination and peeling, thereby comprehensively improving the reliability and yield of the chip packaging structure.

[0025] Specifically, such as Figures 1 to 11As shown, in a first aspect of this application, a chip packaging structure is provided, including a substrate 10 having conductive pillars 101, a first dielectric layer 102 disposed on the substrate 10, a wiring layer 1021 embedded in the first dielectric layer 102, a second dielectric layer 103 disposed on the first dielectric layer 102, and pads 20 disposed on the second dielectric layer 103. The conductive pillars 101 are electrically connected to the pads 20 through the wiring layer 1021. The pads 20 are used to form electrical and mechanical connections with chips, substrates, or other electronic components. The pads 20 include a first metal layer 21 stacked on top of each other, a second metal layer 22 disposed on the side of the first metal layer 21 away from the substrate 10, and a third metal layer 23 disposed on the side of the second metal layer 22 away from the substrate 10. The width of the second metal layer 22 is smaller than the width of the first metal layer 21 and the width of the third metal layer 23, so that a sidewall groove 25 is formed between the first metal layer 21, the second metal layer 22, and the third metal layer 23.

[0026] It should be noted that the chip packaging structure provided in this application employs a three-layer metal stack design for the pads 20. The first metal layer 21 is embedded in the second dielectric layer 103, serving as the bottom base layer of the pads 20. The surface of the first metal layer 21 away from the substrate 10 is flush with the upper surface of the second dielectric layer 103. The first metal layer 21 forms an electrical connection with the conductive pillars 101 within the substrate 10 through the wiring layer 1021 in the first dielectric layer 102. Those skilled in the art can, according to actual needs, connect the conductive pillars 101 and the wiring layer 1021, and the wiring layer 1021 and the pads 20, through the third dielectric layer 1021. The fourth opening 1060 on 6 is plated with an additional conductive structure 1061, which is not specifically limited here; the second metal layer 22 is disposed on the side of the first metal layer 21 away from the substrate 10 (as above, the following will be described in detail with the second metal layer 22 disposed above the first metal layer 21), serving as the middle recess layer of the pad 20; the third metal layer 23 is disposed on the side of the second metal layer 22 away from the substrate 10, serving as the top functional layer of the pad 20, used to receive the solder ball 90 or directly connect to the bump of the chip.

[0027] In the first embodiment, the width of the second metal layer 22 is smaller than the width of the first metal layer 21 and the width of the third metal layer 23. Specifically, the width of the second metal layer 22 is smaller than the width of the first metal layer 21 and also smaller than the width of the third metal layer 23. Therefore, the first metal layer 21, the second metal layer 22, and the third metal layer 23 together form a sidewall groove 25 located laterally to the second metal layer 22. Specifically, the upper surface portion of the first metal layer 21, the entire sidewall of the second metal layer 22, and the lower surface portion of the third metal layer 23 together form a laterally open groove space. This groove space has an inwardly concave shape in cross-section, i.e., the sidewall groove 25. The sidewall groove 25 can be an annular groove extending continuously around the pad 20, or it can be multiple independent grooves spaced apart along the circumference of the pad 20. The specific shape can be flexibly adjusted through photolithography pattern design according to actual packaging requirements.

[0028] When the underfill adhesive 70 flows between the flip chip and the substrate 10 via capillary action, the sidewall groove 25 alters the geometry of the adhesive flow path. Compared to conventional straight-wall pads 20, the sidewall groove 25 provides additional capillary driving force. As the adhesive flows through this groove region, the sudden change in channel cross-section generates an additional capillary pressure gradient at the flow front, thereby accelerating the filling rate and improving the flow uniformity of the adhesive in narrow gaps. Simultaneously, after the adhesive cures, the cured adhesive embeds itself within the groove, forming a mechanical interlocking structure. Specifically, a portion of the cured adhesive fills and solidifies within the groove space, physically engaging with the groove wall of the pad 20. This interlocking structure significantly improves the adhesion between the underfill adhesive 70 and the pad 20, resisting shear stress caused by differences in thermal expansion coefficients during thermal cycling, effectively preventing delamination and peeling.

[0029] As one possible implementation method, such as Figures 3 to 6 As shown, in the second and third embodiments, a protrusion 251 is provided on the surface of the third metal layer 23 facing the first metal layer 21 (i.e., the lower surface of the third metal layer 23), and the protrusion 251 is at least partially located in the space of the sidewall groove 25.

[0030] It should be noted that, based on the fact that the sidewall groove 25 provides ample flow path and anchoring space for the bottom filler adhesive 70, the protrusion 251 on the lower surface of the third metal layer 23 further increases the complexity of the inner surface of the groove space, that is, increases the contact area and roughness inside the groove. On the one hand, this further enhances the capillary force, which is conducive to the rapid filling of the adhesive; on the other hand, a more complex mechanical interlocking structure is formed between the cured adhesive and the protrusion 251. The adhesive wraps around the protrusion 251, and after curing, it forms a locking effect similar to a "barb" or "anchor", which significantly improves the bonding force between the pad 20 and the bottom filler adhesive 70.

[0031] In the actual use of chip packaging structures, due to the differences in the coefficients of thermal expansion between different materials such as substrate 10, pads 20, chip, and molding compound 80, substrate 10 will inevitably undergo a certain degree of warping deformation during thermal cycling and temperature changes. When substrate 10 warps, complex tensile and compressive stresses will be generated between the metal layers of pads 20 and between pads 20 and substrate 10. These stresses are concentrated at the interface of pads 20, which can easily lead to delamination or cracking.

[0032] In this application, the protrusion 251 extends from the lower surface of the third metal layer 23 into the sidewall groove 25. When the substrate 10 warps, the protrusion 251 can generate a small relative displacement within the space of the sidewall groove 25, thereby absorbing and buffering the mechanical stress caused by warping and avoiding stress concentration. When the vertical section of the protrusion 251 contacts the upper surface of the second metal layer 22, the protrusion 251 acts as a support pillar between the third metal layer 23 and the second metal layer 22, directly transmitting and dispersing stress, thus enhancing the ability of the pad 20 to resist warping deformation. When there is a preset gap between the vertical section of the protrusion 251 and the upper surface of the second metal layer 22, this gap provides a buffer space for the mechanical displacement when the substrate 10 warps, preventing warping stress from acting directly on the interface of the pad 20, thereby effectively reducing the risk of delamination or cracking of the pad 20 when the substrate 10 warps, and further improving the reliability and mechanical shock resistance of the packaging structure.

[0033] Furthermore, in chip packaging structures, pads, as critical paths for current transmission, face severe reliability challenges due to electromigration and thermal migration under high-current conditions. When a large current flows through the pads, Joule heating occurs in localized areas due to excessive current density, causing a rapid rise in local temperature. Under alternating current on / off conditions, a repeatedly changing temperature gradient forms within the pads, and electromigration and thermal migration couple: electromigration drives metal atoms to migrate along the electron wind direction, while thermal migration drives atoms to migrate along the temperature gradient direction. This coupling disrupts the direction of atomic migration, forming irregularly shaped stress voids and cracks within the pads. These voids and cracks continue to expand during thermal cycling and mechanical impact, ultimately leading to pad cracking and failure, severely impacting the long-term reliability of the packaging structure.

[0034] In this application, the protrusion 251 is made of a metallic material and is electrically connected to the third metal layer 23. When a large current flows through the pad 20, the protrusion 251, as a protruding structure on the surface of the third metal layer 23, can effectively improve the current density distribution of the pad 20. Specifically, the protrusion 251 increases the local conductive cross-sectional area of ​​the third metal layer 23, allowing the high-density current originally concentrated on the lower surface of the third metal layer 23 to be diverted in the protrusion 251 area, reducing the local current density on the lower surface of the third metal layer 23, thereby suppressing excessive Joule heating and a sharp rise in local temperature. At the same time, the protrusion 251 increases the contact area between the pad 20 and the underfill adhesive 70, which is beneficial for conducting the Joule heat generated by the pad 20 to the molding compound 80 and the external environment through the underfill adhesive 70, thus reducing the operating temperature of the pad 20. By reducing current density and improving heat dissipation, the protrusion 251 effectively suppresses the coupling effect of electromigration and thermal migration, reduces the generation and propagation of stress voids and cracks, and significantly improves the electromigration resistance and long-term reliability of the pad 20.

[0035] As one possible implementation method, such as Figure 3 and Figure 4 As shown, in the second embodiment, the protrusion 251 includes a vertical section that extends in a direction perpendicular to the surface of the third metal layer 23. The end of the vertical section is in contact with or has a predetermined gap with the surface of the first metal layer 21 facing the third metal layer 23 (i.e., the upper surface of the first metal layer 21).

[0036] It should be noted that when the end of the vertical section contacts the upper surface of the first metal layer 21, the protrusion 251 acts as a bridge connecting the third metal layer 23 and the first metal layer 21, further improving interlayer conductivity and thermal conductivity, while enhancing the overall structural strength of the pad 20. When there is a preset gap between the end of the vertical section and the upper surface of the first metal layer 21, this gap provides additional flow space for the bottom filler 70. The filler can pass through this gap to form a more continuous filling pattern within the sidewall groove 25, which helps to eliminate filling voids and improve filling quality. The specific size of the preset gap can be determined according to actual process requirements, for example, it can be set to 1 micrometer to 20 micrometers. A gap within this size range allows the filler to pass through without significantly affecting the structural integrity of the pad 20.

[0037] As one possible implementation method, such as Figure 5 and Figure 6 As shown, in the third embodiment, the protrusion 251 includes a vertical section and a horizontal section. The vertical section extends in a direction perpendicular to the surface of the third metal layer 23, and the horizontal section bends from the end of the vertical section and extends to the outside of the sidewall groove 25.

[0038] It should be noted that the horizontal segment bends from the end of the vertical segment and extends beyond the sidewall groove 25, further increasing the contact area between the protrusion 251 and the bottom filler 70. During the bottom filling process, the horizontal segment extending beyond the sidewall groove 25 effectively provides a raised guiding surface outside the sidewall groove 25. The adhesive is subjected to additional capillary force on the surface of the horizontal segment, resulting in a larger and more uniform filling range, further improving the bottom filling efficiency. Simultaneously, the horizontal segment extending beyond the sidewall groove 25 further increases the local conductive cross-sectional area of ​​the third metal layer 23, allowing the current to obtain a more sufficient shunt path in the horizontal segment region, further reducing the local current density on the lower surface of the third metal layer 23, thereby more effectively suppressing the generation of Joule heating and electromigration. Furthermore, the horizontal segment increases the contact area between the protrusion 251 and the bottom filler 70, further improving heat dissipation and facilitating the more efficient conduction of Joule heat generated by the pads 20 to the external environment.

[0039] As one possible implementation method, such as Figures 1 to 6 As shown, the chip packaging structure also includes solder balls 90. A recess 27 is provided on the surface of the pad 20 away from the substrate 10. The solder balls 90 are provided on the side of the pad 20 away from the substrate 10, and the solder balls 90 at least partially fill the recess 27.

[0040] It should be noted that a recess 27 is provided on the surface of the third metal layer 23 away from the substrate 10. The solder ball 90 is disposed on the side of the third metal layer 23 away from the substrate 10, and the solder ball 90 at least partially fills the recess 27. The function of the recess 27 is to serve as a positioning and anchoring structure between the solder ball 90 and the pad 20. The solder ball 90 is disposed on the side of the pad 20 away from the substrate 10, and part of the material of the solder ball 90 fills the recess 27. When the solder ball 90 is formed by the reflow soldering process, the molten solder flows into the recess 27. After solidification, a tenon-and-mortise mechanical connection is formed between the solder ball 90 and the pad 20, which effectively improves the resistance of the solder ball 90 to horizontal shear force or vertical pull-out force, and reduces the probability of the solder ball 90 cracking or falling off when subjected to external stress.

[0041] In summary, the chip packaging structure provided in this application has the following technical effects: First, by setting the sidewall grooves 25 on the pads 20, the capillary flow path of the underfill adhesive 70 between the chip and the substrate 10 is changed, increasing the driving force of capillary flow, improving the flow uniformity of the adhesive, reducing the generation of voids and bubbles, and improving the quality and yield of the underfill. Second, after the underfill adhesive 70 is cured, the sidewall grooves 25 form a mechanical interlocking structure, that is, the cured adhesive is embedded in the sidewall grooves 25 and forms a physical interlock with the pads 20. This interlocking structure significantly improves the bonding force between the underfill adhesive 70 and the pads 20, resists the shear stress generated by the difference in thermal expansion coefficients during thermal cycling and mechanical impact, effectively prevents delamination and peeling, and improves the long-term reliability of the chip packaging structure. Third, the recessed portion 27 set on the top surface of the pads 20 (i.e., the third metal layer 23) forms a tenon-and-mortise mechanical connection between the solder balls 90 and the pads 20, improving the shear resistance and pull-out resistance of the solder balls 90. During reflow soldering, molten solder flows into the recess 27 and solidifies within it after cooling, forming a strong connection between the solder ball 90 and the pad 20, reducing the probability of the solder ball 90 cracking or falling off under external stress. Fourth, the sidewall groove 25 of this application can be achieved using existing semiconductor manufacturing processes, such as a combination of standard processes like photolithography, electroplating, and etching, without the need for additional special materials or complex equipment, making it cost-effective and easy to mass-produce.

[0042] As one possible implementation method, such as Figures 1 to 8 As shown, substrate 10 has opposing first and second surfaces, both of which are provided with the aforementioned first dielectric layer 102, wiring layer 1021, second dielectric layer 103, and pads 20. This double-sided pad 20 structure allows substrate 10 to be used as an interposer board, enabling electrical signal interconnection between upper and lower chips or substrates. The double-sided pads 20 can employ the same sidewall recess 25 structure design.

[0043] As one possible implementation method, such as Figure 7 As shown, in the fourth embodiment, the chip packaging structure further includes a first substrate 30 disposed on one side of the second surface of the substrate 10. The first substrate 30 is soldered to the pads 20 on the second surface of the substrate 10 so that the first chip 31 disposed on the first substrate 30 is electrically connected to the second chip 11 disposed on the pads 20 on the first surface of the substrate 10.

[0044] It should be noted that this structure enables stacked chip packaging, where the second chip 11 is flip-chip disposed on the first surface of the substrate 10, and the first chip 31 is disposed on the side of the second surface of the substrate 10 via the first substrate 30. The first chip 31 and the second chip 11 are electrically connected through conductive lines within the substrate 10, achieving heterogeneous integration. Furthermore, in this embodiment, since the pads 20 on the second surface of the substrate 10 also have sidewall grooves 25, when the first chip 31 is underfilled, the sidewall grooves 25 can also improve the flow path of the filler adhesive 70 through capillary effect as it flows through the pads 20 on the second surface of the substrate 10, thereby improving the filling efficiency and uniformity of the underfill of the first chip 31 and reducing void defects.

[0045] As one possible implementation method, such as Figure 8 As shown, in the fifth embodiment, the chip packaging structure further includes a third substrate 40 and a fourth substrate 50 disposed on opposite sides of the substrate 10. The third substrate 40 and the fourth substrate 50 are respectively soldered to the pads 20 on the first surface and the second surface of the substrate 10, so that the third chip 41 disposed on the third substrate 40 and the fourth chip 51 disposed on the fourth substrate 50 are electrically connected. The substrate 10 includes two substrates, which are respectively disposed on the left and right sides of the third chip 41 and the fourth chip 51. The two substrates 10 are respectively provided with a first groove 12 and a second groove 13 on the side of the two substrates 10 closest to the third chip 41 and the fourth chip 51. The first groove 12 and the second groove 13 have a preset distance to form a connection portion 14. The chip packaging structure also includes a fifth chip 141, and the two ends of the fifth chip 141 are respectively soldered to the connection portion 14 of the two substrates 10. This bridging structure realizes the interconnection and support between multiple chips, further enriching the integration methods of the chip packaging structure.

[0046] As one possible implementation method, such as Figure 8As shown, the third chip 41 can be a MEMS chip. The first groove 12 and the second groove 13 on the two substrates 10 are arranged opposite each other, together enclosing the cavity of the MEMS chip. This cavity provides space for the movable structure of the MEMS chip. The fourth substrate 50 has a larger dimension on the horizontal plane than the third substrate 40. When the filler adhesive 70 is formed by dispensing, the filler adhesive 70 can cover the sidewalls of the third substrate 40, providing a sealed protection for the MEMS chip. The first groove 12 and the second groove 13 not only serve as components of the bridging structure but also function as MEMS chip cavity forming devices, achieving multifunctional integration of the structure.

[0047] As one possible implementation method, such as Figure 8 As shown, in the fifth embodiment, the fifth chip 141 is disposed on the surface of the connecting portion 14 facing the fourth substrate 50. The vertical projection of the fourth chip 51 on the fourth substrate 50 is located within the vertical projection range of the fifth chip 141 on the fourth substrate 50. A coating layer 60 is disposed between the fifth chip 141 and the fourth substrate 50, and the coating layer 60 covers the fourth chip 51 to protect and support the fourth chip 51, preventing the fourth chip 51 from being mechanically damaged or contaminated in subsequent processes.

[0048] As one possible implementation method, such as Figures 9 to 11 As shown, the edge of the substrate 10 has a cut surface 109 that is exposed to the sidewall of the substrate 10.

[0049] It should be noted that the cut surface 109 is formed by circumferentially cutting the edge of the substrate 10 after wafer-level packaging is completed, using laser cutting or mechanical cutting processes. Through circumferential cutting, the sidewalls of the substrate 10 are exposed. In subsequent molding processes, the molding layer 80 can fill and wrap the cut surface 109, meaning the molding layer 80 covers the sidewalls of the substrate 10, providing lateral protection and sealing. In conventional processes, the edges of the substrate 10 are usually left untouched, and the molding layer 80 only covers the upper surface of the substrate 10. The sidewalls of the substrate 10 are exposed to the external environment for extended periods, making them susceptible to moisture intrusion, physical impact, and thermal stress concentration. This application, through the circumferential cutting process, exposes the sidewalls of the substrate 10 and covers them with the molding layer 80, effectively protecting the sidewall structure of the substrate 10, improving the overall hermeticity and mechanical strength of the chip packaging structure, and reducing reliability failures caused by sidewall cracking or delamination.

[0050] like Figures 1 to 11 As shown, in a second aspect of this application, a method for fabricating a chip packaging structure is provided, for fabricating the aforementioned chip packaging structure, the method comprising: S100, Provide a substrate 10 having conductive pillars 101; It should be noted that a relatively thick substrate 10 (such as silicon-based material, germanium-based material, silicon oxide, phosphosilicate glass, fluorine-containing glass, or glass) can be taken first (e.g., 600μm-1500μm). Then, the substrate 10 can be thinned to the target thickness (e.g., 200μm-300μm) through grinding. Thinning allows the entire chip packaging structure to be thinner and smaller. Simultaneously, the thinned substrate 10 is easier to process in subsequent etching processes. The thinned substrate 10 is then attached to a carrier 00 (e.g., metal, ceramic, or glass), with a layer of adhesive 01 that can be debonded by UV or laser applied in between. The carrier 00 supports the substrate 10 and prevents it from breaking during subsequent processing. Layer 01 ensures that the chip package structure can be separated from the carrier 00 without damage after the process is completed. Holes are drilled on the substrate 10 by dry etching or chemical etching, and then an insulating layer (such as silicon dioxide or silicon nitride) is deposited by PVCD, PVD, CVD, MOCVD, ALD, LPCVD or PECVD. Finally, conductive pillars 101 are filled by electroplating (or sputtering, chemical plating) and then subjected to high-temperature annealing (such as 500℃-1000℃) to eliminate stress. The function of the insulating layer is to prevent leakage or short circuit between the conductive pillars 101 and the substrate 10. The filling metal and annealing are to make the metal denser and more conductive, and to avoid stress-induced cracking.

[0051] S101. A first dielectric layer 102 is formed on the substrate 10, and a wiring pattern 1020 is formed on the first dielectric layer 102, with conductive pillars 101 exposed at the bottom of the wiring pattern 1020. S102, Electroplating is performed to form a wiring layer 1021 within the wiring pattern 1020; It should be noted that a dielectric material (such as silicon nitride, silicon oxynitride, polyimide, or benzocyclobutene) is spin-coated on the substrate 10, and a wiring pattern 1020 is formed on the first dielectric layer 102 formed by the dielectric material through exposure and development. Then, a wiring layer 1021 is formed in the wiring pattern 1020 by electroplating (or sputtering, chemical plating). The dielectric layer is used to isolate the circuits of the upper and lower layers. The wiring layer 1021 and the conductive pillar 101 are electrically connected to transmit electrical signals between different layers.

[0052] S103, A second dielectric layer 103 is formed on the first dielectric layer 102 and the wiring layer 1021, and a first opening 1030 is formed on the second dielectric layer 103, with the bottom of the first opening 1030 exposing the wiring layer 1021. S104. Electroplating to form a first metal layer 21 within the first opening 1030; It should be noted that a dielectric material (such as silicon nitride, silicon oxynitride, polyimide, or benzocyclobutene) is spin-coated on the first dielectric layer 102 and the wiring layer 1021, and a first opening 1030 is formed on the second dielectric layer 103 formed by the dielectric material through exposure and development. Then, a first metal layer 21 is formed in the first opening 1030 by electroplating (or sputtering, chemical plating). The dielectric layer is used to isolate the circuits of the upper and lower layers. The first metal layer 21 is electrically connected to the wiring layer 1021 and the conductive pillar 101 to transmit electrical signals between different layers.

[0053] S105. A first sacrificial layer 104 is formed on the second dielectric layer 103 and the first metal layer 21, and a second opening 1040 is formed on the first sacrificial layer 104, wherein the width of the second opening 1040 is smaller than the width of the first opening 1030. S106. A second metal layer 22 is formed by electroplating in the second opening 1040, such that the width of the second metal layer 22 is smaller than the width of the first metal layer 21. S107, Remove the first sacrificial layer 104; It should be noted that a layer of photoresist material (such as acrylic / epoxy / polyester photopolymerization initiator, etc.) is spin-coated on the second dielectric layer 103 and the first metal layer 21, and a second opening 1040 is formed on the first sacrificial layer 104 formed by the photoresist material by exposure and development. Then, a second metal layer 22 is formed in the second opening 1040 by electroplating (or sputtering, chemical plating). The first sacrificial layer 104 is then removed by using a resist remover (such as acidic or alkaline), exposing the second dielectric layer 103, the first metal layer 21 and the second metal layer 22.

[0054] S108. A second sacrificial layer 105 is formed on the second dielectric layer 103, the first metal layer 21 and the second metal layer 22, and a third opening 1050 is formed on the second sacrificial layer 105, wherein the width of the second opening 1040 is smaller than the width of the third opening 1050. S109. Electroplating a third metal layer 23 within the third opening 1050, such that the width of the second metal layer 22 is smaller than the width of the third metal layer 23. S110, Remove the second sacrificial layer 105 to form a sidewall groove 25 between the first metal layer 21, the second metal layer 22 and the third metal layer 23.

[0055] It should be noted that a layer of photoresist material (such as acrylic / epoxy / polyester photopolymerization initiator, etc.) is spin-coated on the second dielectric layer 103, the first metal layer 21 and the second metal layer 22, and a third opening 1050 is formed on the second sacrificial layer 105 formed by the photoresist material by exposure and development. Then, a third metal layer 23 is formed in the third opening 1050 by electroplating (or sputtering, chemical plating). The second sacrificial layer 105 is then removed by using a resist remover (such as acidic or alkaline) to expose the pad 20 with sidewall grooves 25.

[0056] like Figure 9 and Figure 10 As shown, the above-described fabrication method utilizes a combination of mature semiconductor manufacturing processes, including dielectric layer, sacrificial layer, and electroplating. Through three opening and three electroplating steps, the precise forming of the first metal layer 21, the second metal layer 22, and the third metal layer 23 is achieved. Crucially, the width of the second opening 1040 is designed to be smaller than the width of the first opening 1030 and the third opening 1050. This directly determines that the width of the second metal layer 22 is smaller than the width of the first metal layer 21 and the third metal layer 23, thereby forming sidewall grooves 25 between the first metal layer 21, the second metal layer 22, and the third metal layer 23. This process design is fully compatible with existing wafer-level packaging lines, requiring no additional special equipment or materials, resulting in low cost, a wide process window, and ease of mass production.

[0057] Specifically, in the step of forming the first opening 1030 on the second dielectric layer 103, the size of the first opening 1030 determines the planar size and position of the first metal layer 21. In the step of forming the second opening 1040 on the first sacrificial layer 104, the size of the second opening 1040 determines the planar size and position of the second metal layer 22. In the step of forming the third opening 1050 on the second sacrificial layer 105, the size of the third opening 1050 determines the planar size and position of the third metal layer 23. Since the width of the second opening 1040 is smaller than the width of the first opening 1030 and the width of the third opening 1050, the width of the second metal layer 22 is naturally smaller than the width of the first metal layer 21 and the width of the third metal layer 23. When the first sacrificial layer 104 is removed, the sidewall of the second metal layer 22 is recessed inward relative to the sidewall of the first metal layer 21. When the second sacrificial layer 105 is removed, the sidewall of the second metal layer 22 is recessed inward relative to the sidewall of the third metal layer 23, forming a sidewall groove 25 between the first metal layer 21, the second metal layer 22 and the third metal layer 23.

[0058] like Figure 10As shown, in the embodiment of forming the recess 27, after the third metal layer 23 is formed, a third sacrificial layer 107 can be applied to the surface of the second dielectric layer 103 and the pad 20 away from the substrate 10, forming a fifth opening 1070 in the third sacrificial layer 107. The recess 27 is then formed on the surface of the third metal layer 23 by an etching process, and the third sacrificial layer 107 is removed. The depth and shape of the recess 27 can be precisely controlled by etching process parameters.

[0059] like Figure 11 As shown, in the embodiment for forming solder balls 90, after the recess 27 is formed, a fourth sacrificial layer 108 is applied to the second dielectric layer 103 and the surface of the pad 20 away from the substrate 10. A sixth opening 1080 is formed in the fourth sacrificial layer 108, and then a metal layer 1081 is formed by electroplating in the sixth opening 1080. The fourth sacrificial layer 108 is then removed, and solder balls 90 are formed by formic acid reflow. The material of solder balls 90 can be SnAg, SnAgCu, Sn-Bi, or Sn-Ag-Cu. Subsequently, the carrier 00 is separated by UV or laser irradiation on the back side of the carrier 00. The preparation processes of the first and second surfaces of the substrate 10 are the same and are omitted in the figures, and will not be described again here. Finally, using laser cutting technology, the edge of substrate 10 is circumferentially cut or edge-cut to remove part of the surface of substrate 10, forming a cutting surface 109 on the sidewall of substrate 10 to expose the carrier 00 at the bottom of substrate 10. Then, the second chip 11 is mounted and the bottom is filled to form a filler adhesive 70. Then, a molding process is performed to protect substrate 10 and the second chip 11 with a molding layer 80. Finally, a cutting process is performed to cut it into individual products, completing the process.

[0060] In summary, the chip packaging structure fabrication method provided in this application uses all key process steps (dielectric layer formation, photolithography, electroplating, etching, and resist removal) as mature processes in the semiconductor packaging field. It does not require the introduction of new equipment or materials, has low cost, good process stability, and is suitable for mass production.

[0061] The above description is merely a specific embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0062] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this application will not describe the various possible combinations separately. Furthermore, the various embodiments of this application can be combined with each other, and as long as they do not violate the spirit of this application, they should also be considered as the content disclosed in this application.

Claims

1. A chip packaging structure, characterized in that, The device includes a substrate with conductive pillars, a first dielectric layer disposed on the substrate, a wiring layer embedded in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and pads disposed on the second dielectric layer. The conductive pillars are electrically connected to the pads through the wiring layer. The pads include a first metal layer stacked on top of each other, a second metal layer disposed on the side of the first metal layer away from the substrate, and a third metal layer disposed on the side of the second metal layer away from the substrate. The width of each second metal layer is smaller than the width of the first metal layer and the width of the third metal layer, so that a sidewall groove is formed between the first metal layer, the second metal layer, and the third metal layer. A protrusion is provided on the surface of the third metal layer facing the first metal layer, and the protrusion is at least partially located within the sidewall groove.

2. The chip packaging structure according to claim 1, characterized in that, The protrusion includes a vertical section that extends in a direction perpendicular to the surface of the third metal layer. The end of the vertical section is in contact with or has a predetermined gap with the surface of the first metal layer facing the third metal layer.

3. The chip packaging structure according to claim 1, characterized in that, The protrusion includes a vertical section and a horizontal section. The vertical section extends in a direction perpendicular to the surface of the third metal layer, and the horizontal section bends from the end of the vertical section and extends to the outside of the sidewall groove.

4. The chip packaging structure according to claim 1, characterized in that, It also includes solder balls, wherein the surface of the pad away from the substrate has a recess, the solder balls are disposed on the side of the pad away from the substrate, and the solder balls at least partially fill the recess.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that, The substrate has a first surface and a second surface opposite to each other, and the first surface and the second surface of the substrate are each provided with the first dielectric layer, the wiring layer, the second dielectric layer and the pad.

6. The chip packaging structure according to claim 5, characterized in that, It also includes a first substrate disposed on one side of the second surface of the substrate, the first substrate being soldered to the pads on the second surface of the substrate, so that a first chip disposed on the first substrate is electrically connected to a second chip disposed on the pads on the first surface of the substrate.

7. The chip packaging structure according to claim 5, characterized in that, It also includes a third substrate and a fourth substrate disposed on opposite sides of the substrate, wherein the third substrate and the fourth substrate are respectively soldered to the pads on the first surface and the second surface of the substrate, so that the third chip disposed on the third substrate and the fourth chip disposed on the fourth substrate are electrically connected. The substrate includes two substrates, which are respectively disposed on the left and right sides of the third chip and the fourth chip. The two substrates have a first groove and a second groove respectively on the side close to the third chip and the fourth chip. The first groove and the second groove have a preset distance to form a connection. The chip packaging structure also includes a fifth chip, and the two ends of the fifth chip are respectively soldered to the connection of the two substrates.

8. The chip packaging structure according to claim 7, characterized in that, The fifth chip is disposed on the surface of the connecting portion facing the fourth substrate. The vertical projection of the fourth chip on the fourth substrate is located within the vertical projection range of the fifth chip on the fourth substrate. A coating layer is disposed between the fifth chip and the fourth substrate, and the coating layer covers the fourth chip.

9. The chip packaging structure according to any one of claims 1 to 4, characterized in that, The substrate has a cut surface at its edge, which is exposed to the sidewall of the substrate.

10. A method for fabricating a chip packaging structure, characterized in that, The method for preparing the chip packaging structure according to any one of claims 1 to 9 includes: Provide a substrate with conductive pillars; A first dielectric layer is formed on the substrate, and a wiring pattern is formed on the first dielectric layer, wherein the bottom of the wiring pattern exposes the conductive pillars; A wiring layer is formed by electroplating within the wiring pattern; A second dielectric layer is formed on the first dielectric layer and the wiring layer, and a first opening is formed on the second dielectric layer, the bottom of the first opening exposing the wiring layer; A first metal layer is formed by electroplating within the first opening; A first sacrificial layer is formed on the second dielectric layer and the first metal layer, and a second opening is formed on the first sacrificial layer, wherein the width of the second opening is smaller than the width of the first opening; A second metal layer is electroplated within the second opening, such that the width of the second metal layer is smaller than the width of the first metal layer; Remove the first sacrificial layer; A second sacrificial layer is formed on the second dielectric layer, the first metal layer, and the second metal layer, and a third opening is formed on the second sacrificial layer, wherein the width of the second opening is smaller than the width of the third opening; A third metal layer is electroplated within the third opening, such that the width of the second metal layer is smaller than the width of the third metal layer. Remove the second sacrificial layer to form a sidewall groove between the first metal layer, the second metal layer, and the third metal layer.

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