Semiconductor thin film growth regulation, universal layer stack structure and wafer coupling-free stacking method

Abstract

The application discloses a semiconductor thin film growth regulation and control, a universal layer stack structure and a wafer non-coupling stacking method, and belongs to the technical field of semiconductors. The application comprises three core systems of time-sharing double electric field thin film growth, matrix three-dimensional layer stacking and wafer non-coupling stacking. The thin film uniformity and the crystal quality are improved through time-sharing orthogonal double electric fields, the unit independent addressing is realized through the matrix gating array formed by etching the horizontal and vertical electrode layers, and the wafer non-coupling integration is realized through pure molecular force lamination, so that the inherent defects of the traditional coupling stacking are completely solved. The application has strong universality and can be widely applied to the manufacturing of all kinds of semiconductor products.

Description

Technical Field

[0001] This invention belongs to the fields of semiconductor thin film preparation, three-dimensional integrated circuit physical layer architecture, and wafer-level three-dimensional integration technology, specifically involving time-division dual-electric field semiconductor thin film growth technology, matrix-type three-dimensional stacked structure, and wafer-level uncoupled free stacking method. This invention can be widely applied to the manufacturing and integration of all types of semiconductor products, including logic chips, microprocessors, power semiconductors, optoelectronic devices, sensors, memory chips, and PN junction functional devices. Background Technology

[0002] Semiconductor thin films are the fundamental functional carriers of various semiconductor devices. Current thin film fabrication processes mainly rely on single conditions such as temperature, gas pressure, and gas / liquid phase composition to control the growth state, making it difficult to simultaneously achieve crystal orientation, film uniformity, and defect control. Some technologies attempt to introduce a single electric field to assist growth, but this can only improve the deposition rate or crystal orientation, failing to solve the problem of poor planar uniformity in large-area thin films. Simultaneous multi-electric field technology suffers from defects such as mutual interference of field strengths and significant eddy current effects, making independent control impossible. In the field of three-dimensional stacked architecture, existing structures generally suffer from problems such as severe physical and electrical coupling between units, mutual interference in addressing, and inflexible configuration of hardware resources, making it impossible to adapt to semiconductor devices with different functions across different categories. In the field of 3D stacking technology, the current mainstream solutions are all coupled stacking, with representative technologies including TSV conductive vias, metal bumps, copper-copper hybrid bonding, and fused bonding. This type of solution achieves signal communication by setting vertical electrical interconnect structures between wafers, but it has inherent drawbacks such as stress concentration, thermal mismatch, interlayer crosstalk, limited stacking layers, and low process yield. At the same time, existing coupled stacking architectures are covered by a large number of domestic and foreign patents, limiting the space for technological expansion. Summary of the Invention

[0003] This invention comprises three core technology systems, which can be implemented individually or combined and applied synergistically: time-division dual-electric field semiconductor thin film growth technology, universal matrix three-dimensional stacked structure, and wafer uncoupled free stacking method. 3.1 Time-division dual-field semiconductor thin film growth technology During the growth of semiconductor thin films, two sets of functionally independent, non-overlapping orthogonal electric fields are applied sequentially: Nucleation stage: Apply a high-frequency alternating electric field in a planar direction to regulate the uniform distribution of precursors on the substrate surface; Epitaxial growth stage: Stop applying the planar high-frequency AC electric field and instead apply a vertical DC electric field to guide the precursor to migrate in an oriented manner and control the crystal growth orientation. This technology is not limited by temperature, film formation system, or material type, and is applicable to all semiconductor film formation processes; for non-polar covalent semiconductor materials, the electric field modulation step can be omitted to form a film directly. 3.2 General Matrix-Based Three-Dimensional Layered Stack Structure It is composed of multiple functional units arranged periodically along the vertical direction; each functional unit includes at least a first electrode layer, a functional film layer, and a second electrode layer. The first electrode layer is a conductive material, which is etched to form a first set of equally spaced parallel electrode lines; the second electrode layer is a conductive material, which is etched to form a second set of equally spaced parallel electrode lines; the two sets of electrode lines intersect each other orthogonally to form a matrix-type gating array, and the functional film layer region corresponding to the intersection point is a physically isolated independent functional unit, realizing individual addressing of each independent region. This architecture includes two equivalent forms: Fully independent layer structure: Insulating isolation layers are set between adjacent functional units, and each electrode layer is independent and electrically isolated from each other; Layer reuse structure: adjacent functional units share a single electrode layer, omitting the insulation isolation layer between units. 3.3 Wafer Uncoupled Free Stacking Method Mechanical integration is achieved by combining at least two wafers with completed semiconductor functional layers through surface activation, precise alignment, and low-pressure interface bonding. Adjacent wafers are mechanically bonded together by molecular forces only, without any cross-wafer electrical coupling structures, and each wafer is completely electrically independent; the number of stacked layers is not limited by stress, process, or yield. Attached Figure Description Figure 1 Schematic diagram of the time-division dual-electric-field thin film growth sequence Figure 2 Hierarchical structure diagram of a single functional unit Figure 3 Comparison diagram of fully independent layer structure and layer reuse structure Figure 4 Schematic diagram of a wafer-decoupled stacked structure Note: There are no conductive vias, metal bumps, bonding layers or any other cross-wafer electrical coupling structures between any two adjacent wafers, and each wafer is completely electrically independent. Beneficial effects Comprehensive improvement in thin film performance: Through time-division orthogonal dual electric field control, high uniformity and high crystal integrity of large-area thin films are achieved simultaneously, reducing the defect rate; Universal and standardized architecture: The matrix-style stacked structure has physically isolated and independently addressed units, which can be adapted to all semiconductor devices across categories. It has a simple structure and high integration. Complete breakthrough in stacking bottlenecks: Decoupled stacking completely solves the problems of stress concentration, thermal mismatch, and interlayer crosstalk in traditional coupled stacking, enabling unlimited stacking with simple process and high yield; Comprehensive protection coverage: The three major technology systems are independent yet combinable, covering the entire industry chain from material preparation to device structure and wafer integration. Detailed Implementation Example 1: Fabrication of Time-Division Dual-Field Semiconductor Thin Films A planar high-frequency AC electric field of 1kHz to 10MHz is applied during the nucleation stage of thin film growth using a vapor deposition process to regulate the uniform distribution of the precursor. After nucleation, the planar electric field is stopped, and a vertical DC electric field of 100V / cm to 10kV / cm is applied to guide the directional growth of the crystal, resulting in a semiconductor thin film with high uniformity and low defects. Example 2: Fabrication of a Fully Independent Layer Matrix Three-Dimensional Stacked Structure A first conductive electrode layer is sequentially deposited on a substrate, and a first set of parallel electrode lines is formed by photolithography and etching. A functional film layer is then deposited. A second conductive electrode layer is then deposited, and a second set of parallel electrode lines orthogonal to the first set are formed by photolithography and etching, thus forming a single functional unit. The above steps are repeated to deposit an insulating isolation layer between adjacent functional units, and the layers are stacked to form a three-dimensional stacked device with a fully independent layer structure. Example 3: Fabrication of a Layered Reuse Matrix Three-Dimensional Stacked Structure A first conductive electrode layer is sequentially deposited on a substrate, and parallel lateral electrode lines are formed by photolithography and etching. A first functional film layer is deposited. A common electrode layer is deposited, and parallel vertical electrode lines are formed by photolithography and etching. A second functional film layer is deposited. A third conductive electrode layer is deposited, and parallel lateral electrode lines are formed by photolithography and etching. The common electrode layer also serves as the second electrode of the first functional film layer and the first electrode of the second functional film layer. The inter-unit insulating isolation layer is omitted, forming a three-dimensional stacked device with a layer reuse structure. Example 4: Wafer-free free stacking integration Argon ion surface activation treatment is performed on the bonding surfaces of the two wafers to be stacked. The activated wafers are then precisely aligned at the nanometer level within a 1×10⁻ 5 A uniform pressure of 0.1~1MPa is applied under vacuum to mechanically bond the wafers through molecular forces; the bonded wafers are then electrically independent.

Claims

1. A method for preparing a semiconductor thin film, characterized in that: A high-frequency alternating electric field in a planar direction is applied during the nucleation stage of semiconductor thin film growth. After nucleation, the planar electric field is stopped and a direct current electric field in a vertical direction is applied. The two electric fields do not overlap in duration.

2. A three-dimensional semiconductor stacked structure, characterized in that: It consists of multiple functional units arranged periodically along the vertical direction; A single functional unit includes at least a first electrode layer, a functional film layer, and a second electrode layer; The first electrode layer is etched to form a first set of parallel electrode lines, and the second electrode layer is etched to form a second set of parallel electrode lines; Two sets of electrode lines orthogonally intersect to form a matrix gating array, which divides the functional film layer into multiple physically isolated independent regions, enabling individual addressing of each independent region.

3. A wafer stacking structure, characterized in that: It includes at least two wafers with completed functional layer fabrication. Adjacent wafers are mechanically connected through surface activation, precise alignment, and low-pressure bonding. No cross-wafer electrical coupling structure is set between the wafers, and each wafer is completely electrically independent.

4. A wafer decoupled stacking method, characterized in that: The bonding surfaces of at least two wafers to be stacked are surface activated, and after precise alignment, they are mechanically bonded under low pressure through molecular forces. After bonding, there is no inter-wafer electrical connection between the wafers.

5. The preparation method according to claim 1, characterized in that: It is applicable to various film formation systems including liquid phase, gas phase, epitaxy, and atomic layer deposition; the electric field modulation step can be omitted for non-polar covalent semiconductor materials.

6. The stacked structure according to claim 2, characterized in that: The functional unit includes a fully independent layer structure (with an insulating isolation layer between adjacent units) and a layer reuse structure (adjacent units share a single electrode layer).

7. The stacked structure according to claim 2, characterized in that: The first and second electrode layers are made of conductive materials, and the electrode lines can be formed by photolithography, ion etching, or other physical / chemical methods.

8. The wafer stacking structure according to claim 3, characterized in that: The trans-wafer electrical coupling structure includes, but is not limited to, conductive vias, metal bumps, metal bonding layers, fused bonding layers, and hybrid bonding layers.

9. The wafer stacking structure according to claim 3, characterized in that: A non-conductive interface layer may be provided on the bonding surface of adjacent wafers; the wafer contains the three-dimensional stacked structure as described in claim 2, and the functional film layer is prepared by the method described in claim 1.

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