A mesa glass passivation chip and a manufacturing method thereof

Abstract

The application discloses a mesa glass passivation chip and a manufacturing method thereof, and belongs to the technical field of semiconductor manufacturing. The manufacturing method of the mesa glass passivation chip comprises the following steps: performing a doping treatment on a single crystal silicon wafer to obtain a doped silicon wafer; performing a groove etching treatment on the doped silicon wafer to obtain a plurality of pretreatment chips containing grooves; processing the side edges of the pretreatment chips to form a stepped structure on the side edges of the pretreatment chips, wherein the stepped structure is a transition structure between the mesa of the pretreatment chip and the groove; manufacturing a glass passivation layer in the groove; and performing a surface metallization treatment on the pretreatment chip to obtain the mesa glass passivation chip. Since the side edges of the chip form the stepped structure, the stepped structure serves as the transition structure between the mesa of the chip and the groove, and is not located in the effective area of the PN junction of the chip, so that even if the transition structure has the problems of glass loss, incomplete glass filling or slight damage caused by collision, the reliability of the mesa glass passivation chip will not be affected.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, specifically to a mesa glass passivated chip and its fabrication method. Background Technology

[0002] Currently, the manufacturing of mesa glass passivated chips typically involves multiple photolithography and etching processes on the silicon wafer surface to form PN junction units, followed by filling the trenches with glass to achieve passivation. Traditional glass passivation processes include electrophoresis, photoresist glass methods, and blade scraping. Chips manufactured using the electrophoresis method, such as... Figure 1 As shown; chips manufactured using the photoresist glass method, such as Figure 2 As shown; chips manufactured using the scraping method, such as Figure 3 As shown. Both electrophoresis and photoresist glass passivation of the chip result in a thick glass layer at the junction of the chip mesa and the trench. This glass layer can protrude above the chip mesa, and may even cover the chip's soldering window, affecting the solder joint area. Specifically, the solder joint area (200mm) needs to be smaller than the soldering window area. Figure 4 As shown, this leads to a decrease in the chip's current carrying capacity. Furthermore, solder joint 200 will be misaligned and press against the glass passivation layer, resulting in excessive packaging stress, thus affecting the chip's lifespan and reliability. When using the scraping method for chip passivation, if only one layer of glass powder is coated inside the trench and then sintered, the glass powder will shrink in volume after sintering. Therefore, the glass layer at the interface between the chip mesa and the trench may be incomplete, such as... Figure 5 As shown, this can damage the chip in subsequent processes or packaging, resulting in poor chip reliability. To avoid the loss of the glass layer at the junction of the chip mesa and the trench, it is usually necessary to perform two glass coatings and two sintering processes, which undoubtedly increases the complexity of the process.

[0003] Therefore, improving the reliability of passivated chips on the mesa is an urgent problem to be solved. Summary of the Invention

[0004] The main technical problem solved by this invention is to improve the reliability of the passivated chip on the tabletop glass.

[0005] According to a first aspect, one embodiment provides a method for fabricating a mesa glass passivation chip, the method comprising: Doping is performed on single-crystal silicon wafers to obtain doped silicon wafers; The doped silicon wafer is subjected to trench etching to obtain multiple pre-processed chips containing trenches; The side of the preprocessing chip is processed to form a stepped structure on the side of the preprocessing chip. The stepped structure is a transition structure between the mesa and the trench of the preprocessing chip. A glass passivation layer is formed within the trench; Surface metallization is performed on the pre-processed chip to obtain a mesa glass passivated chip.

[0006] In one embodiment, the step of forming a glass passivation layer within the trench includes: A glass slurry is coated onto the grooves and the stepped structure, and then sintered to obtain a glass passivation layer covering the grooves and the stepped structure.

[0007] In one embodiment, only one glass passivation layer is fabricated, and the stepped structure is not located in the effective region of the PN junction of the mesa glass passivation chip.

[0008] In one embodiment, processing the side of the preprocessed chip includes: Laser ablation is performed on the sides of the pre-processed chip.

[0009] In one embodiment, the doping process of the single-crystal silicon wafer to obtain a doped silicon wafer includes: The top surface of the single-crystal silicon wafer is doped to form a first-type semiconductor layer on the top surface; The bottom surface of the single-crystal silicon wafer is doped to form a heavily doped type II semiconductor layer, thereby obtaining a doped silicon wafer.

[0010] In one embodiment, the trench etching process performed on the doped silicon wafer to obtain a plurality of pre-processed chips containing trenches includes: The doped silicon wafer is subjected to a single photolithography process, so that the areas on the doped silicon wafer that do not require trenches are covered with photoresist for protection. The doped silicon wafer is subjected to trench etching to obtain multiple pre-processed chips containing trenches.

[0011] In one embodiment, processing the sides of the preprocessing chip to form a stepped structure includes: Laser ablation is performed on the region at the junction with the trench on the first type of semiconductor layer according to preset laser ablation parameters to obtain an ablated chip; wherein, the preset laser ablation parameters include one or more of the following: laser type, laser wavelength, laser pulse width, laser frequency, laser power, laser scanning speed, spot diameter, and ablation depth. The ablated chip is cleaned with a pre-set mixed acid to obtain the stepped structure.

[0012] In one embodiment, the stepped structure includes a single-step structure or a multi-step structure; the depth of the stepped structure is between 5μm and 20μm, and the width is between 3μm and 10μm.

[0013] In one embodiment, applying the glass paste to the groove and the stepped structure includes: applying the glass paste to the groove and the stepped structure by screen printing.

[0014] According to a second aspect, one embodiment provides a mesa glass passivation chip, comprising: Substrate; A first type semiconductor layer is stacked on the substrate; A heavily doped type II semiconductor layer is stacked on the lower layer of the substrate; The first type of semiconductor layer has a trench on its side, and a stepped structure is provided at the junction of the first type of semiconductor layer and the trench. Both the first type semiconductor layer and the heavily doped second type semiconductor layer are covered with a metallization layer.

[0015] According to the above embodiment, a mesa glass passivated chip and its fabrication method have a stepped structure formed on the side of the pre-processed chip. This stepped structure serves as a transition structure between the mesa and the trench of the pre-processed chip and is not located within the effective region of the chip's PN junction. Furthermore, the boundary between the stepped structure and the chip mesa is also not located within the effective region of the chip's PN junction. Therefore, even if the transition structure and its boundary with the chip mesa have issues such as missing glass, incomplete glass filling, or minor damage caused by impact, the reliability of the mesa glass passivated chip will not be affected. In other words, when there are issues such as missing glass, incomplete glass filling, or minor damage caused by impact in the boundary region between the mesa and the trench of the pre-processed chip, the stepped structure, as a transition structure, can prevent these defects from affecting the mesa glass passivated chip, thereby improving the reliability of the mesa glass passivated chip. Attached Figure Description

[0016] Figure 1 A schematic diagram of a chip manufactured using the electrophoresis method; Figure 2 A schematic diagram of a chip manufactured using the photoresist glass method; Figure 3 A schematic diagram of a chip manufactured using the blade scraping method; Figure 4 This is a schematic diagram of the chip welding structure; Figure 5 This is a magnified view of a portion of the glass at the junction of the chip mesa and the trench after shrinkage. Figure 6 This is a flowchart illustrating a method for fabricating a passivated chip on a mesa in this embodiment. Figure 7 This is a schematic diagram of the structure of the doped silicon wafer provided in this embodiment; Figure 8 This is a schematic diagram of the preprocessing chip including trenches provided in this embodiment; Figure 9 This is a schematic diagram of the preprocessing chip with a stepped structure provided in this embodiment; Figure 10 This is a partially enlarged schematic diagram of the stepped structure provided in this embodiment; Figure 11 This is a schematic diagram of the structure of the preprocessing chip including the glass passivation layer provided in this embodiment; Figure 12 This is a schematic diagram of the structure of the mesa glass passivation chip including the metallization layer provided in this embodiment; Figure 13 This is a partially enlarged schematic diagram of the mesa glass passivation chip containing a metallization layer provided in this embodiment.

[0017] Figure label: 100 Single crystal silicon wafer, 110 Type I semiconductor layer, 120 Heavy doped Type II semiconductor layer, 130 Trench, 140 Step structure, 150 Metallization layer, 160 Glass passivation layer. Solder joint 200; Substrate 300. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the invention. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present invention are not shown or described in the specification. This is to avoid obscuring the core parts of the invention with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0019] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0020] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this invention, unless otherwise specified, include both direct and indirect connections (linkages).

[0021] Currently, the manufacturing of mesa glass passivated chips typically involves multiple photolithography and etching processes on the silicon wafer surface to form PN junction units, followed by filling the trenches with glass to achieve passivation. Traditional glass passivation processes include electrophoresis, photoresist glass methods, and blade scraping. Chips manufactured using the electrophoresis method, such as... Figure 1 As shown; chips manufactured using the photoresist glass method, such as Figure 2 As shown; chips manufactured using the scraping method, such as Figure 3 As shown. Both electrophoresis and photoresist glass passivation of the chip result in a thick glass layer at the junction of the chip mesa and the trench. This glass layer often protrudes above the chip mesa, sometimes even covering the chip's soldering window, affecting the solder joint area. Specifically, the solder joint area (200mm) needs to be smaller than the soldering window area. Figure 4 As shown, this leads to a decrease in the chip's current carrying capacity. Furthermore, solder joint 200 will be misaligned and press against the glass passivation layer, resulting in excessive packaging stress, thus affecting the chip's lifespan and reliability. When using the scraping method for chip passivation, if only one layer of glass powder is coated inside the trench and then sintered, the glass powder will shrink in volume after sintering. Therefore, the glass layer at the interface between the chip mesa and the trench may be incomplete, such as... Figure 5 As shown, this can damage the chip in subsequent processes or packaging, resulting in poor chip reliability. To avoid missing glass layers at the junction of the chip mesa and trench, two glass coatings and two sintering processes are usually required, which undoubtedly increases the complexity of the process. In addition, when using the scraping method for chip passivation, multiple photolithography processes are required, making the process more complicated and the production cycle longer. Moreover, the protrusions or depressions of the glass layer can directly affect the flatness of the chip soldering window.

[0022] Therefore, improving the reliability of passivated chips on the mesa is an urgent problem to be solved.

[0023] Based on the aforementioned technical problems, this application proposes a method for fabricating a mesa glass passivation chip. A pre-processed chip is obtained by doping and trench etching a single-crystal silicon wafer 100. The sides of the pre-processed chip are then processed to form a stepped structure 140. A glass passivation layer 160 is then fabricated within the trench 130, and surface metallization is performed on the pre-processed chip to obtain the mesa glass passivation chip. Since the stepped structure 140 is formed on the sides of the pre-processed chip, and this stepped structure 140 serves as a transition structure between the mesa of the pre-processed chip and the trench 130, and is not located within the effective PN junction region of the chip, and the boundary area between the stepped structure 140 and the chip mesa is also not within the effective PN junction region of the chip, even if the transition structure and its boundary area with the chip mesa have glass defects, incomplete glass filling, or minor damage caused by collisions, it will not affect the reliability of the mesa glass passivation chip. In other words, when there are glass defects, incomplete glass filling, or minor damage caused by collisions in the interface area between the mesa and the trench 130 of the pre-processed chip, the stepped structure 140, as a transition structure, can prevent these defects from affecting the mesa glass passivation chip, thereby improving the reliability of the mesa glass passivation chip.

[0024] Please refer to Figure 6 , Figure 6 This is a schematic flowchart illustrating a method for fabricating a passivated chip with a mesa provided in this embodiment. Figure 6 As shown, the method includes: Step S101: Perform doping treatment on the single crystal silicon wafer 100 to obtain a doped silicon wafer.

[0025] It should be noted that the monocrystalline silicon wafer 100 can be a P-type monocrystalline silicon wafer, and the resistivity of the P-type monocrystalline silicon wafer can be between 0.0433 Ω•cm and 0.2580 Ω•cm, for example, the resistivity can be 0.0453 Ω•cm, 0.0986 Ω•cm, or 0.1980 Ω•cm. The monocrystalline silicon wafer 100 can also be an N-type monocrystalline silicon wafer, and the resistivity of the N-type monocrystalline silicon wafer can also be between 0.0433 Ω•cm and 0.2580 Ω•cm, for example, the resistivity can be 0.0453 Ω•cm, 0.0986 Ω•cm, or 0.1980 Ω•cm.

[0026] In some embodiments, please refer to Figure 7 A single-crystal silicon wafer 100 is doped to obtain a doped silicon wafer, comprising: The top surface of the single-crystal silicon wafer 100 is doped to form a first-type semiconductor layer 110 on the top surface; The bottom surface of the single-crystal silicon wafer 100 is doped to form a heavily doped type II semiconductor layer 120, thereby obtaining a doped silicon wafer.

[0027] It should be noted that when the single-crystal silicon wafer 100 is a P-type single-crystal silicon wafer, the first type semiconductor layer 110 can be an N-type semiconductor layer, and the heavily doped second type semiconductor layer 120 can be a P+ type semiconductor layer; when the single-crystal silicon wafer 100 is an N-type single-crystal silicon wafer, the first type semiconductor layer 110 can be a P-type semiconductor layer, and the heavily doped second type semiconductor layer 120 can be an N+ type semiconductor layer. This embodiment uses a P-type single-crystal silicon wafer 100 as an example for illustration.

[0028] In practical applications, the process of doping the top surface of a single-crystal silicon wafer 100 to form a first-type semiconductor layer 110 can be as follows: phosphorus diffusion is performed on the top surface of a P-type single-crystal silicon wafer using a phosphorus oxychloride diffusion process. Specifically, after cleaning the single-crystal silicon wafer 100, it is dried and placed in a diffusion furnace. At a preset furnace temperature, a phosphorus source is doped into the P-type single-crystal silicon wafer, thereby forming an N-type semiconductor layer. It should be noted that the preset furnace temperature is between 1100℃ and 1200℃. This phosphorus oxychloride diffusion process is an existing diffusion process and will not be described in detail here.

[0029] In practical applications, the process of doping the bottom surface of a single-crystal silicon wafer 100 to form a heavily doped type II semiconductor layer 120 can be as follows: A latex boron source is coated onto the bottom surface of a P-type single-crystal silicon wafer using a centrifugal spin coating method. Then, the latex boron source is sequentially doped into the bottom surface of the P-type single-crystal silicon wafer under first and second pre-diffusion conditions, thereby forming a P+ type semiconductor layer on the bottom surface of the P-type single-crystal silicon wafer. It should be noted that the first pre-diffusion conditions include: a first pre-diffusion temperature between 1100℃ and 1200℃, and a first pre-diffusion duration of 3 hours. The second pre-diffusion conditions include: a second pre-diffusion temperature between 1220℃ and 1250℃, and a second pre-diffusion duration of 20 hours. This centrifugal spin coating method is an existing method and will not be described in detail here.

[0030] Step S102: Perform trench etching on the doped silicon wafer to obtain multiple pre-processed chips containing trenches 130.

[0031] It should be noted that this application uses trench 130 to divide multiple pre-processing chips on a doped silicon wafer. In other words, trench 130 is the dividing line of each pre-processing chip.

[0032] In some embodiments, please refer to Figure 8 The doped silicon wafer is subjected to trench etching to obtain multiple pre-processed chips containing trenches 130, including: A single photolithography process is performed on the doped silicon wafer to cover the areas on the doped silicon wafer where trenches 130 do not need to be made with photoresist for protection; the doped silicon wafer is then subjected to trench etching to obtain multiple pre-processed chips containing trenches 130.

[0033] It should be noted that the depth of the trench 130 can be between 70μm and 90μm. For example, the depth of the trench 130 can be 70μm, 79μm, 85μm, or 90μm.

[0034] In practical applications, the process of performing a single photolithography process on a doped silicon wafer can be as follows: a negative photoresist is coated on the top and bottom surfaces of the doped silicon wafer, and it is placed in an oven and baked under the first preset baking conditions. Then, a photolithography mask is symmetrically placed on both sides of the wafer and exposed to a preset light intensity for a preset time. The exposed silicon wafer is then rinsed with a developing and rinsing solution and finally placed in an oven and baked under the second preset baking conditions to obtain the photolithographic silicon wafer.

[0035] It should be noted that the first preset baking conditions include: a first preset baking temperature between 90℃ and 100℃; the second preset baking conditions include: a second preset baking temperature between 120℃ and 140℃, and a second preset baking time between 30 mins and 60 mins; the preset light intensity is 100 × 100 μW / cm². 2 The preset time is between 3s and 12s. It should be noted that the developing and rinsing solution is an existing rinsing solution, which will not be described in detail here.

[0036] In practical applications, the process of trench etching on doped silicon wafers can be as follows: using a preset mixed acid at a preset etching temperature to etch the areas of the silicon wafer without photoresist protection after photolithography, thereby obtaining multiple pre-processed chips containing trenches 130.

[0037] It should be noted that the preset mixed acid can be obtained by mixing hydrofluoric acid, nitric acid and glacial acetic acid in a ratio of 5:3:3, or by mixing in other ratios; the preset etching temperature is between -10℃ and 0℃, and the etching time is between 5 mins and 15 mins.

[0038] It should be noted that this application uses a single photolithography-development process to perform trench etching on the doped silicon wafer, which can form a 160mil×160mil PN junction unit on the NP surface. In other words, this application can form a PN junction unit in a single photolithography process, which is more efficient and simpler than processes that require multiple photolithography steps to form a PN junction unit.

[0039] Step S103: Process the side of the preprocessing chip to form a stepped structure 140 on the side of the preprocessing chip. The stepped structure 140 is a transition structure between the mesa and the trench 130 of the preprocessing chip.

[0040] In some embodiments, processing the sides of the preprocessed chip includes: laser ablation of the sides of the preprocessed chip.

[0041] It should be noted that, in addition to laser ablation of the sides of the preprocessed chip, wet etching or dry etching can also be performed on the sides of the preprocessed chip. This application does not impose any limitations on this.

[0042] In practical applications, the process of processing the sides of the pre-processed chip can be as follows: at the junction of the trench 130 and the pre-processed chip mesa, a stepped structure 140 with a preset width and depth is formed by laser ablation. This stepped structure 140 does not involve the effective region of the PN junction and only serves as a transition structure. It should be noted that the effective region of the PN junction is the PN junction interface region and its current extension region exposed on the chip surface by mechanical or chemical means.

[0043] In some embodiments, please refer to Figure 9 and Figure 10 The preprocessing chip's sides are processed to form a stepped structure 140, including: Laser ablation is performed on the region at the junction with the trench 130 on the first semiconductor layer 110 according to preset laser ablation parameters to obtain an ablated chip; wherein, the preset laser ablation parameters include one or more of the following: laser type, laser wavelength, laser pulse width, laser frequency, laser power, laser scanning speed, spot diameter, and ablation depth; the ablated chip is then cleaned with a preset mixed acid to obtain a stepped structure 140.

[0044] In practical applications, the process of laser ablation of the area at the junction with the trench 130 on the first semiconductor layer 110 according to the preset laser ablation parameters can be as follows: the pre-processed chip with completed trench etching is fixed on a high-precision laser processing platform, and a laser scanning path is set on the inner or outer side of the edge of the trench 130. At the same time, an optical microscope or coaxial vision system is aligned with the edge of the trench 130. After setting the laser ablation parameters, the scanning ablation is started. That is, the area at the junction with the trench 130 is laser ablated on the first semiconductor layer 110 according to the set laser scanning path and laser ablation parameters, so that a stepped structure 140 is formed on the side of the pre-processed chip.

[0045] It should be noted that the stepped structure 140 can be continuous or discontinuous. Since the stepped structure 140 is not part of the effective PN junction region of the preprocessing chip, when there are glass gaps, incomplete glass filling, or minor damage caused by collisions in the boundary area between the mesa and the trench 130 of the preprocessing chip, the effective PN junction region of the chip will not be damaged. This improves the reliability of the mesa glass passivation chip.

[0046] In practical applications, different shapes of stepped structures 140 can be achieved by adjusting the laser scanning path. For example, the stepped structure 140 can be an arc-shaped stepped structure or a wave-shaped stepped structure. This application does not impose any limitations on this.

[0047] In practical applications, the process of removing impurities from the ablated chip using a preset mixed acid can be as follows: the ablated chip is cleaned with a preset mixed acid at a preset temperature to remove residues and damaged layers from the chip surface.

[0048] It should be noted that the preset mixed acid can be obtained by mixing hydrofluoric acid, nitric acid and glacial acetic acid in a ratio of 5:3:3, or by mixing in other ratios. The preset temperature can be between -10℃ and 0℃.

[0049] In practical applications, after obtaining the stepped structure 140, the pre-treated chip needs to be soaked in dilute hydrofluoric acid. Then, the pre-treated chip is cleaned in the following order: deionized water rinsing - SC1 cleaning solution rinsing - deionized water rinsing - SC2 cleaning solution rinsing - deionized water rinsing. Finally, the chip is spun dry to obtain a clean pre-treated chip.

[0050] It should be noted that dilute hydrofluoric acid can be obtained by mixing hydrofluoric acid and deionized water in a 1:10 ratio, or by mixing in other ratios. The temperature of both SC1 and SC2 cleaning solutions should be between 70℃ and 80℃. The cleaning time for the chip with SC1 and SC2 cleaning solutions can be 10 minutes, or other times, such as 15 minutes. It should be noted that SC1 and SC2 cleaning solutions are existing cleaning solutions and will not be described in detail here.

[0051] It should be noted that the laser types include infrared lasers or ultraviolet lasers.

[0052] In practical applications, when using infrared lasers to ablate the area at the junction of the first semiconductor layer 110 and the trench 130, the laser wavelength is 1064 nm; the laser pulse width is less than 100 ns; the laser frequency is between 20 kHz and 100 kHz, which ensures the efficiency and accuracy of laser ablation; the laser power is between 1 W and 5 W; the laser scanning speed is between 100 mm / s and 500 mm / s; the spot diameter is less than 10 μm; and the ablation depth is between 8 μm and 12 μm. It should be noted that after using infrared lasers to ablate the sides of the pre-processed chip, the weld heat-affected zone generated at the junction of the first semiconductor layer 110 and the trench 130 is relatively small. In other words, the heat effect of infrared lasers on the weld at the junction of the first semiconductor layer 110 and the trench 130 is minimal.

[0053] In practical applications, when using ultraviolet lasers to ablate the area at the junction of the first semiconductor layer 110 and the trench 130, the laser wavelength is 355nm; the laser pulse width is less than 10ns; the laser frequency is between 50kHz and 200kHz, which ensures the efficiency and precision of the laser ablation; the laser power is between 0.5W and 3W; the laser scanning speed is between 200mm / s and 1000mm / s; the spot diameter is less than 5μm; and the ablation depth is between 5μm and 10μm. It should be noted that after using ultraviolet lasers to ablate the sides of the pre-processed chip, the welding heat-affected zone generated at the junction of the first semiconductor layer 110 and the trench 130 is extremely small. In other words, the welding heat effect of the ultraviolet laser on the junction of the first semiconductor layer 110 and the trench 130 is very small.

[0054] In some embodiments, the stepped structure 140 includes a single-step structure or a multi-step structure; the depth of the stepped structure 140 is between 5μm and 20μm, and the width is between 3μm and 10μm.

[0055] It should be noted that the stepped structure 140 can be a single-level step structure, meaning it can be a single-layer step structure. Since this stepped structure is not located within the effective PN junction area of ​​the chip, any glass defects, incomplete glass filling, or minor damage caused by impact on this step will not affect or damage the mesa glass passivation chip. In other words, this application, by processing the stepped structure 140 on the side of the pre-processed chip, avoids the area corresponding to the stepped structure 140 becoming the effective PN junction area of ​​the chip, thereby reducing the risk of damage to the mesa glass passivation chip.

[0056] It should be noted that the stepped structure 140 can be a multi-level stepped structure, that is, a two-level, three-level, or four-level stepped structure. Since the multi-level stepped structure is not located within the effective region of the chip's PN junction, minor damage caused by glass defects, incomplete glass filling, or collisions on the multi-level steps will not affect or damage the mesa glass passivation chip. In other words, this application avoids the area corresponding to the stepped structure 140 becoming the effective region of the chip's PN junction by processing the stepped structure 140 on the side of the pre-processed chip, thereby reducing the risk of damage to the mesa glass passivation chip. Furthermore, this multi-level stepped structure can disperse the stress applied to the chip by laser scanning, thus providing a certain degree of protection for the chip.

[0057] It should be noted that the depth of the stepped structure can be any value between 5μm and 20μm. For example, the depth of the stepped structure 140 can be 5μm, 10μm, 16μm, or 20μm. The width of the stepped structure 140 can be any value between 3μm and 10μm. For example, the width of the stepped structure 140 can be 3μm, 6μm, 8μm, or 10μm. This application does not impose any limitations on this.

[0058] Step S104: Form a glass passivation layer 160 in the trench 130.

[0059] In some embodiments, please refer to Figure 11 A glass passivation layer 160 is formed within the trench 130, comprising: Glass slurry is coated onto the trench 130 and the stepped structure 140 and sintered to obtain a glass passivation layer 160 covering the trench 130 and the stepped structure 140.

[0060] In practical applications, the process of fabricating the glass passivation layer 160 within the trench 130 can be as follows: a glass paste is coated onto the trench 130 and the stepped structure 140 using screen printing; the glass paste is baked at a third preset baking temperature for 30 minutes to evaporate the diethylene glycol monobutyl ether in the glass paste; then, it is pre-fired at a fourth preset baking temperature for 45 minutes to decompose the ethyl cellulose in the glass paste; finally, the glass powder on the pre-treated chip surface is wiped with a lint-free paper, and the glass powder on the trench 130 and the stepped structure 140 is sintered into a glass layer at a preset sintering temperature to obtain the glass passivation layer 160 covering the trench 130 and the stepped structure 140.

[0061] It should be noted that the third preset baking temperature can be 145℃, the fourth preset baking temperature can be 500℃, and the preset sintering temperature can be 820℃.

[0062] It should be noted that the glass paste used is an existing glass paste, and the screen printing process is an existing process, which will not be described in detail here.

[0063] It should be noted that this application achieves glass passivation by performing a single glass coating and sintering process on the trench 130 and the stepped structure 140. In other words, this application can achieve efficient passivation of the glass slurry with very few process steps. The glass passivation layer 160 formed after passivation is lower than the mesa of the pre-processed chip, thus not affecting the flatness of the chip's soldering window or the chip's soldering quality. Furthermore, the glass layer within the trench 130 is fully filled, preventing the formation of weak areas and ensuring that the chip will not be damaged in subsequent processes or packaging, thereby improving the chip's packaging quality.

[0064] In some embodiments, only one glass passivation layer 160 is fabricated, and the stepped structure 140 is not located in the effective region of the PN junction of the mesa glass passivation chip.

[0065] It should be noted that since the stepped structure 140 serves as a transition structure between the chip mesa and the trench 130, and neither the area where the stepped structure 140 is located nor the boundary area between the stepped structure 140 and the chip mesa is an effective PN junction area of ​​the chip, even if there are glass defects, incomplete glass filling, or minor damage caused by collisions in the boundary area between the pre-processed chip mesa and the trench 130, the chip will not be damaged. Furthermore, since the glass powder at the boundary area between the stepped structure 140 and the trench 130 has not been scraped or wiped, the glass layer at the boundary area after sintering is very full. In other words, this application only needs to fabricate one glass passivation layer 160 to achieve efficient passivation of the glass slurry, reducing processes and saving costs.

[0066] Step S105: Perform surface metallization on the pre-processed chip to obtain a mesa glass passivated chip.

[0067] It should be noted that surface metallization on the preprocessing chip involves metallizing both the top and bottom surfaces of the chip.

[0068] It should be noted that the surface metallization of the chip can be achieved by chemical plating, sputtering, vapor deposition or electroplating.

[0069] In practical applications, the process of surface metallization on the pre-processed chip can be as follows: the pre-processed chip is immersed in a pre-set mixed acid for 20-30 seconds to remove the surface oxide layer; then, surface metallization is performed on the pre-processed chip by chemical plating and nickel sintering. Specifically, the top and bottom surfaces of each pre-processed chip are sequentially plated with nickel (nickel plating temperature between 90℃ and 100℃, nickel plating time between 20s and 40s) - nickel sintering (nickel sintering temperature between 520℃ and 535℃, nickel sintering time between 40s and 60s) - nickel oxide removal (nickel oxide removal time is 10mins) - nickel plating (nickel plating temperature between 90℃ and 100℃, nickel plating time between 20s and 40s) - nickel sintering (nickel sintering temperature between 520℃ and 535℃, nickel sintering time between 40s and 60s) - nickel oxide removal (nickel oxide removal time between 20s and 40s) - nickel plating (nickel plating temperature between 90℃ and 100℃, nickel plating time between 30s and 50s), ultimately forming a mesa glass passivated chip.

[0070] It should be noted that the pre-mixed acid can be obtained by mixing hydrofluoric acid and hydrochloric acid in a 1:10 ratio, or by mixing them in other ratios. The temperature of the hot nitric acid is between 90℃ and 100℃.

[0071] It should be noted that nickel plating includes electroless nickel plating and electroplating. This application uses electroless nickel plating as an example for illustration. Electroless nickel plating mainly uses an autocatalytic reaction to reduce and deposit nickel ions, forming a nickel-phosphorus alloy coating. After nickel plating is completed, the deposited nickel powder can be instantly heated to a molten state using a laser and shaped, thereby achieving nickel sintering. After nickel sintering is completed, hot nitric acid can be used to remove the nickel oxide generated during the sintering process, thereby removing impurities from the chip.

[0072] In practical applications, in addition to plating nickel on the top and bottom surfaces of the pre-processed chip, this application can also plate multiple layers of metal on the top and bottom surfaces of the pre-processed chip. For example, a Ti layer can be plated on the top and bottom surfaces of the pre-processed chip, followed by a Ni layer, and finally an Ag layer, thereby achieving multi-layer metal protection and improving the reliability of chip soldering.

[0073] This embodiment provides a method for fabricating a mesa glass passivated chip. The method includes: doping a single-crystal silicon wafer to obtain a doped silicon wafer; performing trench etching on the doped silicon wafer to obtain multiple pre-processed chips containing trenches; processing the sides of the pre-processed chips to form a stepped structure, the stepped structure serving as a transition structure between the mesa and the trench of the pre-processed chip; fabricating a glass passivation layer within the trench; and performing surface metallization on the pre-processed chips to obtain a mesa glass passivated chip. Because the chip's sides have a stepped structure, which serves as a transition structure between the chip's mesa and the trench, and is not located within the effective region of the chip's PN junction, and the boundary area between the stepped structure and the chip's mesa is also not within the effective region of the chip's PN junction, even if the transition structure and its boundary area with the chip's mesa have glass defects, incomplete glass filling, or minor damage caused by collisions, it will not affect the reliability of the mesa glass passivated chip. In other words, when there are glass defects, incomplete glass filling, or minor damage caused by collisions in the interface area between the mesa and the trench of the pre-processed chip, the stepped structure, as a transition structure, can prevent these defects from affecting the mesa glass passivation chip, thereby improving the reliability of the mesa glass passivation chip.

[0074] Please refer to Figure 12 and Figure 13 The passivation chip for the tabletop glass includes: Substrate 300; A first type semiconductor layer 110 is stacked on the substrate 300; A heavily doped type II semiconductor layer 120 is stacked on the lower layer of the substrate 300; A trench 130 is provided on the side of the first type semiconductor layer 110, and a stepped structure 140 is provided at the junction of the first type semiconductor layer 110 and the trench 130. Both the first type semiconductor layer 110 and the heavily doped second type semiconductor layer 120 are covered with a metallization layer 150.

[0075] It should be noted that the trench 130 and the stepped structure 140 are covered with a glass passivation layer 160.

[0076] It should be noted that substrate 300 is part of single-crystal silicon wafer 100.

[0077] This embodiment provides a mesa glass passivation chip, which includes: a substrate; a first type semiconductor layer stacked on the upper layer of the substrate; a heavily doped second type semiconductor layer stacked on the lower layer of the substrate; trenches are formed on the sides of the first type semiconductor layer, and a stepped structure is formed at the boundary between the first type semiconductor layer and the trenches; both the first type semiconductor layer and the heavily doped second type semiconductor layer are covered with a metallization layer. Because the stepped structure is formed on the sides of the chip, this stepped structure serves as a transition structure between the mesa and the trenches of the chip, and is not located within the effective region of the chip's PN junction. Furthermore, the boundary between the stepped structure and the chip mesa is also not located within the effective region of the chip's PN junction. Therefore, even if the transition structure and its boundary with the chip mesa have glass defects, incomplete glass filling, or minor damage caused by impact, it will not affect the reliability of the mesa glass passivation chip. In other words, when there are glass defects, incomplete glass filling, or minor damage caused by collisions in the interface area between the mesa and the trench of the pre-processed chip, the stepped structure, as a transition structure, can prevent these defects from affecting the mesa glass passivation chip, thereby improving the reliability of the mesa glass passivation chip.

[0078] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0079] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environments and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document. Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the fundamental principles of the invention.

Claims

1. A method for fabricating a passivated chip with a mesa glass surface, characterized in that, The method includes: Doping is performed on single-crystal silicon wafers to obtain doped silicon wafers; The doped silicon wafer is subjected to trench etching to obtain multiple pre-processed chips containing trenches; The side of the preprocessing chip is processed to form a stepped structure on the side of the preprocessing chip. The stepped structure is a transition structure between the mesa and the trench of the preprocessing chip. A glass passivation layer is formed within the trench; Surface metallization is performed on the pre-processed chip to obtain a mesa glass passivated chip.

2. The method as described in claim 1, characterized in that, The step of forming a glass passivation layer in the trench includes: A glass slurry is coated onto the grooves and the stepped structure, and then sintered to obtain a glass passivation layer covering the grooves and the stepped structure.

3. The method as described in claim 2, characterized in that, Only one glass passivation layer is fabricated, and the stepped structure is not located in the effective region of the PN junction of the mesa glass passivation chip.

4. The method as described in claim 2, characterized in that, The processing of the side edges of the preprocessed chip includes: Laser ablation is performed on the sides of the pre-processed chip.

5. The method as described in claim 4, characterized in that, The process of doping a single-crystal silicon wafer to obtain a doped silicon wafer includes: The top surface of the single-crystal silicon wafer is doped to form a first-type semiconductor layer on the top surface; The bottom surface of the single-crystal silicon wafer is doped to form a heavily doped type II semiconductor layer, thereby obtaining a doped silicon wafer.

6. The method as described in claim 3, characterized in that, The trench etching process performed on the doped silicon wafer to obtain multiple pre-processed chips containing trenches includes: The doped silicon wafer is subjected to a single photolithography process, so that the areas on the doped silicon wafer that do not require trenches are covered with photoresist for protection. The doped silicon wafer is subjected to trench etching to obtain multiple pre-processed chips containing trenches.

7. The method as described in claim 5, characterized in that, The step of processing the side of the preprocessing chip to form a stepped structure on the side includes: Laser ablation is performed on the region at the junction with the trench on the first type of semiconductor layer according to preset laser ablation parameters to obtain an ablated chip; wherein, the preset laser ablation parameters include one or more of the following: laser type, laser wavelength, laser pulse width, laser frequency, laser power, laser scanning speed, spot diameter, and ablation depth. The ablated chip is cleaned with a pre-set mixed acid to obtain the stepped structure.

8. The method according to any one of claims 1 to 7, characterized in that, The stepped structure includes a single-step structure or a multi-step structure; the depth of the stepped structure is between 5μm and 20μm, and the width is between 3μm and 10μm.

9. The method as described in claim 2, characterized in that, The step of coating the groove and the stepped structure with glass paste includes: coating the groove and the stepped structure with glass paste by screen printing.

10. A tabletop glass passivated chip, characterized in that, include: Substrate; A first type semiconductor layer is stacked on the substrate; A heavily doped type II semiconductor layer is stacked on the lower layer of the substrate; The first type of semiconductor layer has a trench on its side, and a stepped structure is provided at the junction of the first type of semiconductor layer and the trench. Both the first type semiconductor layer and the heavily doped second type semiconductor layer are covered with a metallization layer.

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