Command scheduling method, apparatus, device, and storage medium

Abstract

The present application relates to the technical field of storage, and discloses a command scheduling method, device, equipment and storage medium, which are used for solving the problem that high-priority commands cause large response time delay fluctuation because of waiting for low-priority commands to be executed in the existing command scheduling scheme based on priority. Specifically disclosed are: a plurality of command queues including a first command queue and a second command queue are established; the scheduling priority of the first command queue is higher than that of the second command queue, and the first command queue is configured to be completed before a preset deadline; when the first command queue receives a to-be-scheduled command, a countdown of the preset deadline for the to-be-scheduled command is started; if the countdown is not greater than a preset threshold, the to-be-scheduled command is not completed, and a target command being executed in the second command queue is in a preemptible state, the target command is suspended, the to-be-scheduled command is executed, and after the execution of the to-be-scheduled command is completed, the execution of the target command is resumed, so as to meet the demand of an application scenario with strict requirements on response time delay.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a command scheduling method, apparatus, device, and storage medium. Background Technology

[0002] Currently, priority-based command queue scheduling is commonly used in SSD (Solid State Drive) command scheduling. This scheme establishes multiple command queues in the SSD controller, assigns different scheduling priorities to each command queue, and selects commands from each command queue in order according to the scheduling priorities.

[0003] Although the above scheme can schedule commands based on scheduling priority, in the scheduling process of multiple command queues, the response latency of high-priority commands is limited by the execution time of the currently executing low-priority commands: when the execution time of low-priority commands is long, even if higher-priority commands arrive, they must wait for the current command to finish executing, resulting in large fluctuations in the response latency of high-priority commands, which is difficult to meet the application scenarios with strict requirements for response latency. Summary of the Invention

[0004] The main objective of this invention is to provide a command scheduling method, apparatus, device, and storage medium, which aims to solve the problem that existing multi-command queue scheduling schemes based on scheduling priorities suffer from large fluctuations in response latency of high-priority commands, making it difficult to meet strict response latency requirements, because the response latency of high-priority commands is limited by the execution time of currently executing low-priority commands.

[0005] In a first aspect, embodiments of this disclosure provide a command scheduling method, including: Multiple command queues are established; the multiple command queues include a first command queue and a second command queue; wherein, the scheduling priority of the first command queue is higher than that of the second command queue, and the commands in the first command queue are configured to be completed before a preset deadline; When the first command queue receives a command to be scheduled, a countdown to the preset deadline for the command to be scheduled is started. If the countdown is not greater than a preset threshold, the scheduled command is not completed, and the target command being executed in the second command queue is in a preemptible state, then the target command is suspended, the scheduled command is executed, and the execution of the target command is resumed after the scheduled command is completed; wherein, the preemptible state indicates that the target command can be paused while maintaining the current execution progress.

[0006] Secondly, embodiments of this disclosure provide a command scheduling apparatus, the apparatus comprising: A creation module is used to establish multiple command queues; the multiple command queues include a first command queue and a second command queue; wherein, the scheduling priority of the first command queue is higher than that of the second command queue, and the commands in the first command queue are configured to be completed before a preset deadline; The timing module is used to start a countdown for a preset deadline for the scheduled command when the first command queue receives a scheduled command. The scheduling module is configured to suspend the target command, execute the scheduled command, and resume the execution of the target command if the countdown is not greater than a preset threshold, the scheduled command is not completed, and the target command being executed in the second command queue is in a preemptible state; wherein, the preemptible state indicates that the target command can be paused while maintaining its current execution progress.

[0007] Thirdly, embodiments of this disclosure provide a storage controller, characterized in that it includes at least an arbitrator, a storage medium controller, and a hardware state machine; wherein the arbitrator is used to schedule commands among command queues according to priority; the storage medium controller is used to issue read commands, write commands, or erase commands to a non-volatile storage medium according to the scheduling result of the arbitrator; the hardware state machine is used to query the current stage register reported by the storage medium controller to determine the preemptible state of the currently executing command; wherein the preemptible state indicates that the command can be suspended while maintaining the current execution progress; the arbitrator, the storage medium controller, and the hardware state machine are configured to collaboratively implement the steps of the method described in the first aspect above.

[0008] Fourthly, embodiments of this disclosure provide a storage device, characterized in that it includes a storage controller as described in the third aspect above, and a non-volatile storage medium.

[0009] Fifthly, embodiments of this disclosure provide a computer-readable storage medium for storing computer-executable instructions that, when executed by a processor, implement the steps of the method described in the first aspect.

[0010] In a sixth aspect, embodiments of this disclosure provide a computer program product, the computer program product including a computer program, which, when executed by a processor, implements the steps of the method described in the first aspect above.

[0011] The at least one technical solution provided by the embodiments of the present invention can achieve the following technical effects: In this embodiment of the invention, firstly, multiple command queues are established, including a first command queue and a second command queue. The scheduling priority of the first command queue is higher than that of the second command queue, and the commands in the first command queue are configured to be completed before a preset deadline. When the first command queue receives a command to be scheduled, a countdown to the preset deadline for the command to be scheduled is started. If the countdown is not greater than a preset threshold, the command to be scheduled is not completed, and the target command being executed in the second command queue is in a preemptible state, then the target command is suspended, the command to be scheduled is executed, and the target command is resumed after the command to be scheduled is completed. The preemptible state indicates that the target command can be paused while maintaining its current execution progress.

[0012] This invention configures a preset deadline for a first command queue with higher scheduling priority, and starts countdown monitoring when the first command queue receives a command to be scheduled. When the countdown is not greater than the preset threshold and the command to be scheduled has not been completed, it actively determines whether the target command being executed in the second command queue is in a preemptible state. If the target command is in a preemptible state, it is suspended and the command to be scheduled is executed instead. This mechanism replaces the passive approach of existing solutions where high-priority commands must wait for low-priority commands to complete, so that the execution of high-priority commands is no longer constrained by the execution time of low-priority commands. This effectively overcomes the technical defect of large fluctuations in response latency of high-priority commands, thus meeting the needs of application scenarios with strict requirements for response latency. Attached Figure Description

[0013] Figure 1 This is one of the flowcharts illustrating the command scheduling method provided in an embodiment of the present invention; Figure 2 A second flowchart illustrating the command scheduling method provided in an embodiment of the present invention; Figure 3 A schematic diagram of the state machine for determining preemptible points and suspending / resumpting normal commands, provided for embodiments of the present invention; Figure 4 This is a schematic diagram of the "Command Type - Preemptible Attribute" configuration table and decision process provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the application identifier distribution and "application-priority" mapping table structure provided in an embodiment of the present invention; Figure 6 A schematic diagram illustrating the composition of firmware layer reserved resources provided in an embodiment of the present invention; Figure 7 A schematic diagram illustrating the data write path for emergency service write commands to fall into the low-latency NAND gate area, as provided in this embodiment of the invention. Figure 8A schematic diagram of the overall architecture of multi-priority queue (Queue) and weighted round-robin (WRR) scheduling provided in an embodiment of the present invention; Figure 9 A schematic diagram of the module composition of the command scheduling device 900 provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of the present invention. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0015] The technical solutions provided by the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0016] Please see Figure 1 , Figure 1 This is one of the flowcharts illustrating the command scheduling method provided in this embodiment of the invention, applied to an SSD device, such as... Figure 1 As shown, the method includes the following steps: Step 102: Establish multiple command queues; the multiple command queues include a first command queue and a second command queue; wherein, the scheduling priority of the first command queue is higher than that of the second command queue, and the commands in the first command queue are configured to be completed before a preset deadline.

[0017] Step 104: When the first command queue receives a command to be scheduled, start a countdown for the preset deadline of the command to be scheduled.

[0018] Step 106: If the countdown is not greater than the preset threshold, the scheduled command is not completed, and the target command being executed in the second command queue is in a preemptible state, then suspend the target command, execute the scheduled command, and resume the execution of the target command after the scheduled command is completed; wherein, the preemptible state indicates that the target command can be suspended while maintaining the current execution progress.

[0019] In this embodiment of the invention, firstly, multiple command queues can be established, and the scheduling priorities of different command queues can be different. These multiple command queues may include a first command queue and a second command queue, wherein the scheduling priority of the first command queue is higher than that of the second command queue, and the commands in the first command queue are configured to be completed before a preset deadline.

[0020] In one example, the multiple command queues may also include a third command queue, wherein the scheduling priority of the third command queue is higher than that of the second command queue but lower than that of the first command queue.

[0021] For example, a host and an SSD device can establish multiple SQs (Submission Queues) and CQs (Completion Queues) via the NVMe (Non-Volatile Memory Express) protocol. The host can use NVMe Admin commands to create multiple SQs / CQs sequentially and assign priority levels to each queue. For instance, four queues can be created: Q0 corresponds to the first command queue, such as UrgentQueue, with the highest priority; commands in Q0 must complete within a preset deadline (e.g., 5ms); Q1 corresponds to the third command queue, such as HighQueue, with a priority between the first and second command queues, including commands from specific transactions or applications; Q2 and Q3 correspond to the second command queue, such as NormalQueue, with normal priority; commands in Q2 and Q3 are used for handling regular I / O (Input / Output). The queue priorities are determined by the host and the SSD device through the NVMe protocol's queue priority negotiation mechanism during queue creation.

[0022] An arbiter can be installed in the controller inside the SSD device. The arbiter can be used to schedule commands between command queues. In each arbitration cycle, the arbiter checks whether each queue is non-empty in descending order of priority: Q0 takes priority, if Q0 is not empty, the command at the head of Q0 is executed; if Q0 is empty, Q1 is checked, if Q1 is not empty, the command at the head of Q1 is executed; if both Q0 and Q1 are empty, then Q2 and Q3 are scheduled in a round-robin fashion according to WRR (Weighted Round Robin).

[0023] In one example, when no commands are available in the first or third command queue, multiple queues in the second command queue can be scheduled using a weighted round-robin (WRR) approach. The WRR weights can be determined through negotiation between the host and the device or dynamically adjusted by firmware policies. For example, the WRR weight of Q2 can be set to 8, and the WRR weight of Q3 to 4. When both Q0 and Q1 are empty, the arbitrator performs a WRR round-robin between Q2 and Q3 with a weight ratio of 8:4. That is, in consecutive scheduling rounds, the ratio of the number of times Q2 and Q3 are selected for execution is 8:4 (i.e., 2:1), thereby achieving fair sharing of scheduling resources among the queues in the second command queue according to their weights. Through the WRR scheduling mechanism, it can be ensured that when no high-priority commands are available, each normal queue can fairly obtain processing time, and the arbitration resources will not be occupied for a long time due to a sudden surge of commands in one queue.

[0024] In this embodiment of the invention, after the SSD device establishes multiple command queues, the first command queue can receive commands to be scheduled. When the first command queue receives a command to be scheduled, a countdown to a preset deadline for that command can be started. For example, the queuing timestamp of the command to be scheduled can be denoted as T_enter, and the preset deadline can be denoted as T_deadline, for example, T_deadline=5ms.

[0025] For example, such as Figure 2 As shown, in practical applications, when a command is enqueued in the first command queue, that command can be bound to a countdown timer with a corresponding preset deadline. For example... Figure 2 As shown on the timeline, if the scheduled command has been completed and returned to the Completion Queue normally before T_enter+T_deadline, the deadline is met, the process ends normally, and the countdown timer is automatically cleared when the command is completed. If the countdown is not greater than the preset threshold, that is, the current time has reached T_enter+T_deadline, but the scheduled command has not yet been completed, a deadline timeout event is triggered, and the subsequent preemption process begins. Figure 2 The countdown is represented by a progress bar. The deadline is met when Cmd_u completes before the countdown exceeds the preset threshold.

[0026] In this embodiment of the invention, if the countdown is not greater than a preset threshold, the scheduled command is not completed, and the target command being executed in the second command queue is in a preemptible state, then the target command is suspended, the scheduled command is executed, and the execution of the target command is resumed after the scheduled command is completed. The preemptible state indicates that the target command can be paused while maintaining its current execution progress. The preset threshold can be determined based on the blocking delay of the device's backend command processing, or it can be set to zero. Considering the backend processing delay between triggering preemption and the actual completion of the scheduled command, setting the preset threshold to a value greater than zero allows the preemption action to be triggered earlier, reserving processing time for the execution of the scheduled command; setting the preset threshold to zero triggers preemption when the countdown reaches zero.

[0027] For example, such as Figure 2 and Figure 3 As shown, in practical applications, within each arbitration cycle, if the arbitrator finds a pending command in the first command queue with a countdown timer that has reached zero and the pending command has not yet been completed, while the command currently being served is from the second command queue, then it can preemptively determine the currently executing command from the second command queue. The core criterion for the preemptible state can be whether the command from the second command queue has been sent to the NAND (Not AND) medium and whether physical programming has begun. If it has not been sent to the NAND medium or physical programming has not begun, it is in a preemptible state; if it has been sent to the NAND medium and physical programming has begun, it is not preemptible and must wait until the next preemptible point, i.e., the current command is completed or the interruptible stage boundary is reached. For write commands, the page boundary can be the interruptible stage boundary, meaning that preemption is allowed when the current page write operation is completed and the next page write operation has not begun. The above core criteria are general criteria. These general criteria can be further refined into preemptible phases and suspend positions for read commands, write commands, and erase commands. The specific refinement methods will be detailed in the following description in conjunction with the command type and the two-dimensional configuration table of NAND execution phases.

[0028] Furthermore, a preemptible point can also be defined as: the second command queue command has been mapped through the FTL (Flash Translation Layer) but has not yet been sent to the NAND medium. One typical scenario for this definition of a preemptible point is: the FTL has completed the mapping from logical address to physical address (i.e., LBA (Logical Block Address) → PBA (Physical Block Address)), and the allocated mapping relationships and FTL entries are all ready, but the NAND controller has not yet received the instruction. Therefore, the command is in a state of "preparation is complete but irreversible physical operation has not yet begun." When in this state, it can be safely suspended.

[0029] Figure 2 and Figure 3 In this context, when a preemptible state is determined, a suspension operation can be performed: the target command's state is switched from "executing" to "suspended," and its context is preserved in the suspension table. Combined with... Figure 3 The state machine requires that the LBA→PBA mapping and the allocated FTL entries be preserved during the suspension operation to maintain data consistency after recovery. Preserving the LBA→PBA mapping means that the mapping relationship from logical address to physical address will not be lost due to suspension, and the FTL mapping step does not need to be re-executed after recovery. Preserving the FTL mapping entries means that the occupied address mapping cache resources remain valid and will not be overwritten by other commands. These preservation measures collectively maintain the data consistency of the suspended operation, ensuring seamless continuation from the suspension point during recovery without data errors or duplication of work.

[0030] After suspension, urgent commands, i.e., commands awaiting scheduling in the first command queue, can be sent to the execution path. These urgent commands can be distributed to the NAND media via a dedicated NAND channel and reserved resources. The dedicated NAND channel is not allocated to commands in the second command queue, thus the urgent command does not need to compete for channel resources with commands in the second command queue. After the urgent command completes execution and writes back to the CQ, the context of the target command is restored from the suspension table, and it is placed back into the execution path to continue the subsequent NAND distribution process from the suspension point. Because the complete FTL mapping state is preserved during suspension, the FTL mapping steps do not need to be re-executed after resumption, thus avoiding redundant work. The integrity of the resumption operation relies on the context information preserved during the suspension phase, ensuring that the preemption mechanism obtains a high-priority response without substantially affecting the correctness and execution efficiency of the preempted command.

[0031] like Figure 3As shown in the state machine, the preemptible point judgment and suspension / resumption process can be described by the following state transitions. After the second command queue command is enqueued, it enters the execution state and first performs FTL mapping. After the FTL mapping is completed, it enters the preemptible point judgment state. If NAND has been issued and physical programming has started, the command enters the non-preemptible state and waits for the current command to complete or reach the next preemptible point before returning to the preemptible state. If it is preemptible and no command from the first command queue arrives, it continues to execute until NAND programming begins (at which point it transitions to non-preemptible). If it is preemptible and a command from the first command queue arrives, it enters the suspension state (retaining LBA→PBA mapping, retaining FTL entries, and setting the state to "suspended") and switches to the execution path of the first command queue command. After the first command queue command completes execution through a dedicated channel and reserved resources, the context of the suspended command is restored, and NAND issuance continues from the suspension point until completion. Figure 3 Taking the write command W_n from the second command queue as an example, the state transition is given. The preemptibility point determination for the read command R_n and the erase command E_n from the second command queue is as follows: Figure 4 The command type and stage configuration table are executed.

[0032] The preemption mechanism is the core difference between this solution and existing NVMe WRR scheduling. Existing arbitration retrieves commands one by one from the queue for execution. Once a Normal priority command begins service, even if a higher-priority urgent command arrives, it must wait for the current command to complete. This example breaks the constraint that "already-serviced Normal commands must complete" by defining "preemptible points" and performing suspension operations at these points, allowing urgent commands to receive responses within a preset deadline. Simultaneously, by preserving context information such as LBA→PBA mappings and FTL entries, it ensures that suspension and resumption operations do not compromise data consistency.

[0033] For example, suppose Q3 is currently serving a Normal write command W_n, which has been mapped via FTL but has not yet been sent to the NAND medium. At this time, Q0 enqueues an urgent read command R_u, and a countdown begins. If R_u has not completed before the countdown exceeds a preset threshold, the scheduler determines that W_n is at a preemptible point (FTL mapping completed but NAND not yet sent), switches W_n's state to "suspended," and retains its allocated LBA→PBA mapping and requested FTL entries. Then, R_u is sent through a dedicated NAND channel, with resources from reserved resources. After R_u completes and writes back to CQ, the context of W_n is restored from the suspended list, and the NAND sending process continues. If W_n has already been sent to the NAND medium and physical programming has begun when R_u is enqueued (i.e., in a non-preemptible state), the scheduler marks R_u as "pending preemption" and performs preemption only when W_n completes or reaches the next preemptible point.

[0034] In one example, before suspending the target command, the command type can be identified, including read, write, and erase commands. Then, based on the execution progress and command type of the target command, it can be determined whether the target command is in a preemptible state.

[0035] For example, such as Figure 4 As shown, in practical applications, the master controller can maintain a configuration table of command types and preemptible attributes between the arbitrator and the NAND controller. The determination of preemptible points can be implemented by the master controller's hardware state machine: this hardware state machine is located inside the master controller chip. In each arbitration cycle, it queries the current stage register reported by the NAND controller to obtain the NAND execution stage number (stage 1 / 2 / 3 / 4) of the currently executing second command queue command, and simultaneously identifies the command type (Read / Write / Erase). The hardware state machine uses the command type and stage number as an index to query... Figure 4 The command type and preemptible attribute configuration table shown are used to obtain the preemptible flag (yes / no) and the corresponding suspend gear information, and the results are output to the scheduling decision-maker. This hardware implementation allows preemptible determination to be completed at the hardware level without relying on firmware software queries, thereby controlling the determination latency to the nanosecond level and avoiding the extra latency introduced by software queries that could cause emergency commands to miss the preset deadline.

[0036] like Figure 4 As shown in the configuration table, this table can be organized along two dimensions: command type and NAND execution stage. The command type dimension is divided into three categories: Read commands, Write commands, and Erase commands. The NAND execution stage dimension can be divided into four stages: Stage 1 is the preparation stage, Stage 2 is before NAND is issued, Stage 3 is after NAND has been issued, and Stage 4 is during physical programming. Each cell in the configuration table records the preemptibility attribute and suspend position of the command type in that stage.

[0037] When the target command is a read command, the determination of the preemptible state is related to the NAND execution phase in which the read command is executed. (Combined with...) Figure 4In the configuration table, read commands are marked as preemptible in both Phase 1 (preparation phase) and Phase 2 (before NAND is issued), allowing them to be suspended at any time before entering the NAND channel. Read commands are also marked as preemptible in Phase 3 (after NAND has been issued). At this stage, the read command has entered the NAND channel but the read data has not yet returned. The read context can be suspended, and the NAND channel can be released for urgent commands. The suspended read context includes the selected Page number, Plane number, Channel number, and Lun number. When the read command enters Phase 4 (during physical programming, i.e., physical reading in progress), the configuration table marks it as non-preemptible. At this time, the current Page is being read. Although the data has not yet returned, a forced interruption will result in incomplete data being returned to the upper layer. Therefore, the channel must be released only after the current Page has been read.

[0038] In one example, when the target command is a write command, it can be determined that the target command is in a preemptible state if the target command has not performed a write operation, or if the target command has completed the write operation of the current page and has not started the write operation of the next page.

[0039] For example, combining Figure 4 The configuration table for write commands can be divided into three levels for preemption determination. Level W1 (corresponding to stage 2, i.e., before NAND is issued): The configuration table is marked as preemptible. At this time, the FTL mapping is completed but has not yet been issued to NAND, and no write operation has been performed. It can be suspended immediately, and the operation method is to cancel the FTL mapping status but retain the mapping relationship. Level W2 (corresponding to stage 3, i.e., after NAND is issued): The configuration table is marked as preemptible. At this time, it has been issued to NAND but SLC (Single-Level Cell) programming has not yet started, and no write operation has been performed. The NAND channel occupation can be canceled and the command suspended, retaining the pages that have been issued but have not started programming. Level W3 (corresponding to stage 4, i.e. during physical programming): The configuration table is marked as preemptible. At this time, SLC programming has started, and page programming can be interrupted in units of "pages". When the write operation to the current page is completed and the write operation to the next page has not yet begun, the page is at a page boundary. This allows subsequent page programming to be aborted at the page boundary, while successfully programmed pages are preserved. The emergency command can then be completed, and subsequent page programming can be resumed from the breakpoint. The W3 level design utilizes the characteristics of NAND page programming, namely that a page is the smallest addressable unit in NAND programming. Once page programming is completed, the data has been reliably written to the NAND medium. Therefore, aborting at the page boundary will not result in the loss of written data.

[0040] In one example, when the target command is an erase command, it can be determined that the target command is in a preemptible state if the erase operation is not performed.

[0041] Combination Figure 4 The configuration table specifies that erase commands are executed in blocks and cannot be interrupted. The configuration table is marked as preemptible only when the erase command is in Phase 1 (erasure preparation phase). At this time, the bad block table has been updated, but the erase pulse has not yet been applied, and the erase operation has not been performed. Preemption is allowed; the erase preparation can be cancelled, the block can be marked as "pending erase," and it can be returned to the erase queue. Once the erase pulse has been applied (Phase 2 and later), the configuration table is marked as non-preemptible, and the system must wait for the erase to complete before switching to emergency commands. The reason for non-preemption after the erase pulse is applied is that the erase operation releases charge from all NAND cells in the entire block. Once the pulse is applied, the physical process is irreversible; a forced interruption will result in incomplete erasure of some cells within the block, leading to unreliable data.

[0042] As can be seen from the above, read commands can be preempted in stages 1 / 2 / 3, but not in stage 4 (waiting for data return); write commands can be preempted in stages 1 / 2 / 3 / 4, corresponding to stage 2-position W1 (cancel FTL mapping state but retain), stage 3-position W2 (cancel NAND channel occupation, retain already issued pages), and stage 4-position W3 (page boundary aborts current page programming, retains successfully issued pages); erase commands can only be preempted in stage 1 (erase preparation, can be undone), and not in stages 2 / 3 / 4 (pulse has been applied or waiting for block completion).

[0043] For example, such as Figure 4 As shown in the decision process, the arbitrator can perform the following decision steps in each arbitration cycle: First, retrieve the target command (W_n / R_n / E_n) currently being executed from the second command queue. Second, identify its command type (Read, Write, or Erase). Third, query the current stage register reported by the NAND controller from the hardware state machine to obtain the current stage number (1 / 2 / 3 / 4) of the command. Fourth, query the command type and stage number as an index. Figure 4The configuration table is used to obtain the preemptibility flag (yes / no) and the corresponding suspension level (read channel suspension, W1, W2, W3, or erase preparation cancellation). The fifth step is to determine if a command has arrived in the first command queue. If it has arrived and the preemptibility flag is "yes," then the corresponding suspension level is executed: the Read command suspends the read context and releases the NAND channel; Write W1 cancels the FTL mapping state but retains the mapping relationship, and does not send it to NAND; Write W2 cancels NAND channel occupation, retaining pages that have been sent but not yet programmed; Write W3 aborts the current page programming at the page boundary, retaining pages that have been successfully programmed; Erase cancels erase preparation, and the block is returned to the erase queue. The sixth step is to switch to emergency command execution after suspension is complete. Emergency commands are sent via a dedicated channel and the first resource (reserved resource). Step 7: After the emergency command is completed, resume the execution of commands in the second command queue according to the corresponding gear: Read restores the read context and re-occupies the channel; Write W1 restores the FTL mapping state and continues NAND delivery; Write W2 restores channel occupation and continues programming for pages that have not yet started programming; Write W3 continues programming from the next unprogrammed page; Erase re-enters erase preparation and is placed back at the head of the erase queue.

[0044] In one example, by configuring preemptible attributes separately for read, write, and erase commands, preemption decisions can be deeply matched to the physical execution characteristics of NAND. Combined with... Figure 4 The three core matching relationships are: First, erase is uninterruptible, corresponding to the erase command being marked as non-preemptible after the pulse is applied, with the hardware state machine directly returning the "non-preemptible" flag, avoiding data unreliability caused by erasing unfinished NAND media; Second, page programming is interruptible, corresponding to the write command being allowed to abort at the page boundary during the SLC programming initiation phase, supporting preemption while preserving successfully programmed pages, without affecting the integrity of written data; Third, read channels can be suspended, corresponding to the read command being allowed to suspend the read context and release the channel during the phase where the channel is occupied but data has not returned, allowing urgent commands to immediately occupy the released channel resources without waiting for the current read command to complete. These three matching relationships demonstrate the core advantage of this example's fine-grained preemption design at the command type level. Preemption decisions are no longer based solely on whether a command enters the NAND, but rather on determining the preemptible phase and suspension method based on the different physical execution characteristics of each command type on the NAND media, thereby maximizing the preemption opportunity for urgent commands while maintaining data consistency and NAND reliability. Figure 4 The preemptible / non-preemptible flags and suspend positions (W1 / W2 / W3, etc.) in the configuration table are exemplary configurations, and can actually be adjusted by the firmware according to the NAND process and controller.

[0045] In one example, in addition to the preemption mechanism described above, priority elevation based on application identity can also be supported. Specifically, after establishing multiple command queues, when a command to be processed is received in the second command queue, the application identifier of the command to be processed can be obtained. The application identifier can be an identifier carried by the command to be processed or a pre-registered identifier. Then, the target scheduling priority corresponding to the application identifier can be determined according to a pre-determined mapping relationship. This pre-determined mapping relationship is the mapping relationship between application identifiers and scheduling priorities. If the target scheduling priority is higher than the scheduling priority of the second command queue, the command to be processed can be added to the third command queue. After being added to the third command queue, the scheduling time occupied by the command to be processed is still deducted from the preset scheduling time limit corresponding to the second command queue.

[0046] For example, such as Figure 5 As shown, multiple applications can run on the host side. For example, App_A is an AI large-model inference service, which is latency-sensitive; App_B is offline data analysis, which is not latency-sensitive. Both App_A and App_B use the second command queue by default, such as Q2. The host can issue the application identifier of the command to the device in either of the following ways: First, write the App ID (Application Identifier) ​​into the 2-byte reserved field of the NVMe command. This App ID is transmitted to the device side along with the reserved field of the command. Second, pre-register the mapping table entry from App ID to priority using a separate Admin command, for example, registering App ID=0xA1 corresponding to the priority of the third command queue. Figure 5 As shown, the device firmware maintains a mapping table between application identifiers and priorities. This mapping table can contain four fields: App ID, application name, default queue, and promoted priority. For example, App ID 0xA1 corresponds to AI large model inference, default queue is Q2, and promoted priority is the priority corresponding to the third command queue (High level); App ID 0xB2 corresponds to offline data analysis, default queue is Q2, and promoted priority remains the priority corresponding to the second command queue (Normal level); App ID 0xC3 corresponds to database critical path, default queue is Q2, and promoted priority is the priority corresponding to the third command queue (High level); App ID 0xD4 corresponds to background backup, default queue is Q3, and promoted priority remains the priority corresponding to the second command queue (Normal level).

[0047] The scheduling decision-maker can query the mapping table during each arbitration cycle and perform the following judgment: If the App ID carried by the command is in the mapping table and the promoted priority corresponding to that App ID in the mapping table is higher than the default priority of the queue where the command is located, then the command can be temporarily added to a higher priority queue for scheduling. Figure 5 As shown, when the second command queue receives a command from App ID=0xA1, the scheduling decision-maker queries the mapping table to determine that the promoted priority (High level) corresponding to 0xA1 is higher than the default priority (Normal level) of Q2. The command is then temporarily added to the third command queue (Q1) for scheduling, and the scheduling order is based on the higher priority corresponding to the third command queue. When a command from App ID=0xB2 is received, since the promoted priority equals the default priority, it is processed according to the priority and WRR weights corresponding to the second command queue. Through this mapping table, AI large-scale model inference commands can obtain high-priority responses without exclusively occupying the queue, and without affecting the throughput of offline analysis services.

[0048] It is important to emphasize that after an application's priority is increased, when a command is temporarily added to a higher-priority queue for scheduling, it can still be included in the WRR fairness statistics according to the WRR weight of its original queue. This means that although the command receives a higher priority response in the scheduling order, when calculating the WRR scheduling time of the second command queue, the scheduling time it occupies is still deducted from the preset scheduling time quota corresponding to the original queue, not from the quota of the third command queue. This mechanism ensures that the application-aware priority increase does not violate the WRR fairness among the queues in the second command queue.

[0049] Furthermore, the aforementioned application-identity-based priority enhancement is linked to the underlying hardware resources of the SSD device. When a command is promoted to the third command queue due to its application identifier, it can utilize the hardware resources reserved for high-priority commands during subsequent execution. These hardware resources can include data storage block resources, low-latency cache resources, address mapping cache resources, and dedicated command execution channels from the first set of resources. This ensures that the effect of priority enhancement at the scheduling layer is realized through underlying resource guarantees, truly translating into a reduction in command latency and preventing situations where high-priority tasks are scheduled but resources are still occupied by ordinary tasks. This deep coupling design between software scheduling and hardware resource allocation means that priority enhancement is not merely an adjustment of scheduling strategies, but also achieves end-to-end latency benefits through resource-level collaborative guarantees.

[0050] In one example, multiple command queues may include the aforementioned third command queue. After establishing multiple command queues, idle resources can be further divided into first resources and second resources, and at least one command execution channel can be configured for use by the first and third command queues. The idle resources may include at least one of the following: data storage block resources, low-latency cache resources, and address mapping cache resources. The first resource can be configured to provide resources for commands in the first and third command queues. The second resource can be configured to provide resources for commands in the first, second, and third command queues. When the available capacity of the first resource falls below a preset capacity threshold, a resource reclamation operation can be triggered to replenish the available capacity of the first resource.

[0051] Combination Figure 6 As shown, in this example, the SSD device dynamically reserves resources for high-priority tasks during firmware initialization or runtime. Figure 6 As shown, the four types of resources can all be divided into a dual-resource method of "secondary resource (such as Normal pool) + primary resource (such as Reserved pool)". The Reserved pool (i.e., the primary resource) can only allow commands from the first command queue and the third command queue to apply for resources. Normal commands will not consume the Reserved pool even if resources are exhausted.

[0052] Specifically, data storage block resources (NAND Free Blocks) can be proportionally divided into a first resource and a second resource. The division can be as follows: Free_Pool_Normal (second resource, i.e., the Normal resource pool) capacity = 70% of total Free Blocks, used by commands in all queues; Free_Pool_Reserved (first resource, i.e., the Reserved resource pool) capacity = 30% of total Free Blocks, which can be used only by commands in the first and third command queues. The 70% and 30% ratios mentioned above are merely exemplary values ​​and can be adjusted by the firmware according to device specifications.

[0053] For low-latency cache resources (SLC Cache), their reserved quota (e.g., 4GB) can be divided into a first resource and a second resource. The first resource (Reserved quota, 4GB) is only allowed to be used by commands in the first and third command queues; the second resource (Normal quota) is available for commands in all queues. 4GB is an example value, and the actual value can be adjusted by the firmware according to the device specifications.

[0054] For address mapping cache resources (FTL mapping table cache), its reserved entries (e.g., 1024 entries) are divided into a first resource and a second resource. The first resource (Reserved entries, 1024 entries) is only allowed to be used by commands in the first and third command queues; the second resource (Normal entries) is available for commands in all queues. 1024 entries is an example value and can be adjusted by the firmware according to device specifications.

[0055] For command execution channel resources (NAND channels), such as Figure 6 As shown, the four channels are labeled Ch0, Ch1, Ch2, and Ch3, respectively. At least one channel (e.g., Ch3) is configured as a dedicated channel for use by the first and third command queues. This dedicated channel does not participate in the scheduling of the second command queue, ensuring that commands in the first and third command queues do not compete with commands in the second command queue for the same channel. The remaining channels (Ch0, Ch1, Ch2) serve as shared channels for use by commands in all queues.

[0056] The four types of resources described above can all be organized using the aforementioned dual-resource allocation method. When a command in the first or third command queue needs to request resources, they are allocated from the first resource queue first; when a command in the second command queue needs to request resources, they are allocated from the second resource queue. Even if a command in the second command queue exhausts its own second resource, it will not consume resources from the first resource queue.

[0057] For example, such as Figure 6 As shown, taking data storage block resources as an example, when the available capacity of the first resource (Free_Pool_Reserved) is lower than the corresponding preset capacity threshold (e.g., the resource pool level is below 10%), the firmware triggers a resource reclamation operation. This resource reclamation operation can be executed asynchronously by the firmware in a low-priority background task, without blocking the execution path of commands in the first command queue. Figure 6As shown, resource reclamation operations can include: accelerating background GC (Garbage Collection) and reclaiming ordinary write buffers in the SLC Cache. Specifically, accelerating background GC means increasing the execution frequency and processing priority of GC tasks, so that more invalid data blocks are reclaimed as Free Blocks; reclaiming ordinary write buffers in the SLC Cache means triggering the SLC→TLC (Triple-Level Cell) folding operation, migrating ordinary data residing in the SLC Cache to the TLC / QLC (Quad-Level Cell) area, and releasing SLCBlocks. The Free Blocks obtained by the above two reclamation methods are added to the first resource (Free_Pool_Reserved), so that the available capacity of the first resource is restored to above the preset capacity threshold, such as... Figure 6 The process of "reclaimed Free Blocks being added to the Reserved pool" and "Reserved pool level rising" is illustrated in the diagram. Similarly, for low-latency cache resources and address-mapped cache resources, when the available amount of their respective first resources falls below the corresponding preset capacity threshold, the corresponding resource reclamation operation is also triggered.

[0058] Through the aforementioned resource reservation mechanism, when a command arrives in the first command queue, even if the second resource corresponding to the second command queue is exhausted, the command in the first command queue can still request resources from the first resource and be directly sent to the NAND medium through a dedicated channel. This reduces the waiting latency caused by insufficient resources, enabling the priority increase of the scheduling layer to be linked with the underlying resource guarantee, truly translating into a reduction in command latency. For example, when an emergency command is scheduled in advance due to the preemption mechanism, if Free_Pool_Normal (the second resource) is exhausted at this time, the emergency command can still request a Free Block from Free_Pool_Reserved (the first resource) and be directly sent through the Ch3 dedicated channel. It does not compete for resources with commands in the second command queue throughout the process, thereby reducing the risk of timeouts caused by resource blockage and making the completion latency of the emergency command tend to approach the preset deadline.

[0059] In the resource reservation mechanism described above, the first resource (Reserved quota) of the low-latency cache resource (SLC Cache) is reserved for high-priority commands with dedicated fast write space. When the urgent command is a write command, this example further restricts its data write path to this low-latency storage area to significantly reduce physical programming latency and make it easier to meet the preset deadline.

[0060] In one example, the command to be scheduled is a write command. Executing this command writes the data to be written to a low-latency storage area. The completion time of a single-page write operation in this low-latency storage area is less than a preset time threshold. When executing this command, the hot / cold data grading process can be skipped, and the data written by the command is marked after execution. If the current load is below a preset load threshold, the marked data is migrated to a designated storage area without blocking the execution of commands in the first command queue. The completion time of a single-page write operation in this designated storage area is not less than the preset time threshold. The hot / cold data grading process allocates data to different storage areas based on data access frequency.

[0061] For example, such as Figure 7 As shown, when preemption is triggered and the urgent command is a write command, the firmware can limit the data write path for this write command to a low-latency storage region. A low-latency storage region can be a NAND region where the completion time of a single-page write operation (page programming) is less than a preset time threshold, such as an SLC cache region. Each SLC (Single-Level Cell) storage cell stores only 1 bit of data, and its page programming time is on the order of tens of microseconds. In contrast, the completion time of a single-page write operation in a designated storage region (such as a TLC / QLC region) is not less than a preset time threshold; that is, for TLC (each storage cell stores 3 bits of data) and QLC (each storage cell stores 4 bits of data), the multi-page programming time is on the order of milliseconds. Therefore, the page programming latency of a low-latency storage region is significantly lower than that of a designated storage region. The microsecond and millisecond levels mentioned above are illustrative examples; actual values ​​may depend on the NAND process and controller implementation.

[0062] like Figure 7 As shown, the regular write path involves the following steps: FTL mapping, allocation of TLC / QLC region physical blocks, TLC / QLC multi-page programming (single page programming time is on the order of milliseconds; if the data volume is large, such as 4MB, multiple page programmings are required, and the total time is usually long), and subsequent participation in background GC migration. The emergency write path is independent of and decoupled from the regular write path. The specific steps of an emergency write are as follows: The first step is to allocate a free SLC block from the first resource of the low-latency cache (SLC Cache Reserved quota, e.g., 4GB), with sufficient capacity to hold the data to be written. The second step is to directly write the data for the urgent write command into this SLC block. For example... Figure 7As illustrated in the latency comparison diagram, since SLC single-page programming time is in the tens of microseconds range, while TLC / QLC multi-page programming time is in the milliseconds range, the physical programming latency of the emergency path is significantly lower than that of the regular path, and the preset deadline (e.g., 5ms) is more easily met. For example, for an emergency write command W_u of about 4MB (such as critical checkpoint data generated by AI large model inference), if the regular TLC path is followed, multiple TLC page programming operations are required, with a total time exceeding milliseconds; if the SLC emergency path is followed, the SLC single-page programming time is in the tens of microseconds range, and 4MB of data can be completed within hundreds of microseconds.

[0063] The third step, as Figure 7 As shown, when the available capacity of the low-latency storage area (SLC Cache reserved quota) is insufficient, a space reclamation operation is triggered. The space reclamation operation includes: accelerating the SLC→TLC folding operation, that is, folding and migrating ordinary data residing in the SLC Cache to the TLC / QLC area, releasing SLC blocks; and releasing ordinary SLC write buffers. The reclaimed SLC blocks are added to the first resource (Reserved quota) of the low-latency cache resources, instead of waiting for the regular reclamation process.

[0064] The fourth step involves skipping the hot / cold data tiering process when executing pending scheduling commands. The hot / cold data tiering process allocates data to different storage areas based on data access frequency—that is, hot data (high-frequency access data) is allocated to low-latency areas, and cold data (low-frequency access data) is allocated to high-density areas. For example... Figure 7 As shown, emergency write commands do not enter the TLC / QLC write queue, but instead directly enter the write path of the SLC Cache reserved quota, decoupling them from the regular hot and cold data hierarchical write process.

[0065] Fifth, after executing the scheduled command, the metadata of the data written by that command is marked as "residing in a low-latency storage area, awaiting migration." After marking, the data still resides in the low-latency storage area and can be accessed normally by read commands, without being mistakenly judged as "data unavailable." Sixth, if the current system load is lower than a preset load threshold (e.g., during a low-load period, or when the available capacity of the data storage block resources in the first resource is lower than a preset capacity threshold), the background garbage collection (GC) asynchronously migrates the marked data to a designated storage area (such as a TLC / QLC area). Figure 7 As shown, the migration process takes place in a background path independent of the emergency command execution path, without blocking the execution of subsequent emergency commands in the first command queue. After the migration is complete, the occupied SLC blocks in the low-latency storage area are released, returning them to the first resource of the low-latency cache for use by subsequent emergency commands.

[0066] Furthermore, the path for urgent data to fall into the low-latency storage area (i.e., the "urgent write path") works in conjunction with the asynchronous migration of background GC to the TLC / QLC area to ensure data persistence. Although urgent data only undergoes SLC single-page programming during writing (SLC is non-volatile storage, and the data has been reliably written), it is ultimately migrated by the background GC to high-density storage areas such as TLC / QLC for long-term storage during low-load periods. Before the migration is complete, the data is always readable in the SLC area; after the migration is complete, the data is persistently stored in the TLC / QLC area. This collaborative design ensures that the urgent write path achieves low latency advantages without sacrificing data persistence; that is, data is not interpreted as abandoning long-term reliable storage simply because it "only falls into SLC." Through this path, the physical programming latency of urgent write commands is significantly reduced compared to the TLC / QLC path. Even if executed immediately after preemption, it is easier to meet the preset deadline requirements, making the completion latency of urgent commands tend to be close to the preset deadline and reducing the risk of urgent command timeout.

[0067] In one example, such as Figure 8 The diagram shows the overall architecture. Figure 8 In this setup, multiple applications run on the host side, including App_A (AI inference service), App_B (offline analytics service), and App_General (general application). The host communicates with the SSD device via the NVMeSQ / CQ interface and issues the application identifier (App ID) to the device through a reserved field or a separate Admin command.

[0068] On the SSD device controller side Figure 8 The following core components are demonstrated. The Queue Arbiter manages a four-level command queue: Q0 corresponds to the first command queue, with the highest priority and bound to a preset deadline (e.g., 5ms) for monitoring; Q1 corresponds to the third command queue, carrying high-value application commands promoted from the App ID (e.g., App_A is promoted to the priority corresponding to Q1); Q2 and Q3 correspond to the second command queue, with Q2 having a WRR weight of 8 and Q3 having a WRR weight of 4. When both Q0 and Q1 are empty, they are round-robin scheduled according to the WRR weights of 8:4. The queues are arranged in descending order of priority, with Q0 having the highest priority and Q3 the lowest.

[0069] The scheduling decision-maker receives scheduling requests from the Queue arbitrator and queries the mapping table from App ID to priority to decide whether to temporarily add the command to a higher priority queue. When a command exists in the first command queue, the scheduling decision-maker prioritizes processing commands from the first command queue; when neither the first nor the third command queue exists, the scheduling decision-maker processes each queue in the second command queue in a round-robin fashion according to WRR.

[0070] The firmware layer resource management module demonstrates a dual-resource allocation method for four resource categories. For NAND Free Blocks, it is divided into Free_Pool_Normal (secondary resource, accounting for 70% of the total Free Blocks) and Free_Pool_Reserved (primary resource, accounting for 30% of the total Free Blocks, available only for commands in the first and third command queues). For SLCCache, it is divided into Normal quota (secondary resource) and Reserved quota (primary resource, 4GB, available only for commands in the first and third command queues). For FTL mapping table cache, it is divided into Normal entries (secondary resource) and Reserved entries (primary resource, 1024 entries, available only for commands in the first and third command queues). For NAND channels, Ch0, Ch1, and Ch2 are shared channels, while Ch3 is configured as a dedicated channel for the first and third command queues.

[0071] The controller contains a "Command Type - Preemptible Attribute" configuration table and an emergency write path (falling into the low-latency NAND region). The command type and preemptible attribute configuration table is configured in two dimensions according to three command types: read, write, and erase, and the NAND execution stages (stages 1 to 4). Details are available in [link to documentation]. Figure 4 Expanding on this, the emergency write path restricts the data for write commands in the first command queue to fall into the low-latency NAND region; its detailed path is detailed in [the relevant section]. Figure 7 It unfolds in the middle.

[0072] Figure 8 The diagram illustrates an overall architecture: from the host-side application identifier issuance, to the device-side queue arbitration and scheduling decision (including application-aware priority enhancement), to the firmware layer's dual-resource reservation for four types of resources, and then to the master control side configuring preemptible attributes and low-latency disk write paths for urgent data according to command type. All components work together to ensure that when a command arrives in the first command queue, preemption is triggered by deadline monitoring. At the preemptible point, the second command queue command is suspended, and the urgent command is executed via a dedicated channel and the first resource. If the urgent command is a write command, it follows a low-latency NAND disk write path, ultimately ensuring that the completion latency of the urgent command approaches the preset deadline, reducing the risk of urgent command timeout.

[0073] In this embodiment of the invention, firstly, multiple command queues are established, including a first command queue and a second command queue. The scheduling priority of the first command queue is higher than that of the second command queue, and the commands in the first command queue are configured to be completed before a preset deadline. When the first command queue receives a command to be scheduled, a countdown to the preset deadline for the command to be scheduled is started. If the countdown is not greater than a preset threshold, the command to be scheduled is not completed, and the target command being executed in the second command queue is in a preemptible state, then the target command is suspended, the command to be scheduled is executed, and the target command is resumed after the command to be scheduled is completed. The preemptible state indicates that the target command can be paused while maintaining its current execution progress.

[0074] This invention configures a preset deadline for a first command queue with higher scheduling priority, and starts countdown monitoring when the first command queue receives a command to be scheduled. When the countdown is not greater than the preset threshold and the command to be scheduled has not been completed, it actively determines whether the target command being executed in the second command queue is in a preemptible state. If the target command is in a preemptible state, it is suspended and the command to be scheduled is executed instead. This mechanism replaces the passive approach of existing solutions where high-priority commands must wait for low-priority commands to complete, so that the execution of high-priority commands is no longer constrained by the execution time of low-priority commands. This effectively overcomes the technical defect of large fluctuations in response latency of high-priority commands, thus meeting the needs of application scenarios with strict requirements for response latency.

[0075] Figure 9 The command scheduling device 900 shown can achieve Figure 1 The method of the embodiment is used to achieve the same technical effect. The command scheduling device 900 is applied to an SSD device and includes: A creation module 901 is used to establish multiple command queues; the multiple command queues include a first command queue and a second command queue; wherein, the scheduling priority of the first command queue is higher than that of the second command queue, and the commands in the first command queue are configured to be completed before a preset deadline; The timing module 902 is used to start a countdown for a preset deadline for the scheduled command when the first command queue receives a scheduled command. The scheduling module 903 is used to suspend the target command, execute the scheduled command, and resume the execution of the target command if the countdown is not greater than a preset threshold, the scheduled command is not completed, and the target command being executed in the second command queue is in a preemptible state; wherein, the preemptible state indicates that the target command can be paused while maintaining the current execution progress.

[0076] Optionally, the command scheduling device 900 may further include other functional modules for implementing any of the method embodiments described above, such as a module for identifying command types and determining preemptible states, a module for priority promotion based on application identifiers, a module for resource allocation and reclamation, and a module for writing write command data to a low-latency storage area. The specific processing flow of each of the above functional modules has been described in [the document / document / etc.]. Figure 1 The method embodiments shown are described in detail and will not be repeated here.

[0077] The functional modules in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0078] It should be noted that if the modules in the embodiments of this application are implemented in the form of software functional units, they can be stored in a computer-readable storage medium and executed by a processor to achieve the corresponding functions. The specific processing flow executed by each module in this virtual device has been described in detail in the foregoing method embodiments. This device embodiment only describes the logical connection relationship between modules. For the specific program execution flow, please refer to the foregoing method embodiments.

[0079] Figure 10 This is a schematic diagram of the structure of a storage device provided in one embodiment of the present invention. Please refer to it. Figure 10 At the hardware level, the storage device includes a storage controller and non-volatile storage media. In one software implementation, the storage controller includes a processor and optionally an internal bus, network interface, and memory. The memory may include main memory, such as high-speed random-access memory (RAM), or non-volatile memory, such as at least one disk drive. Of course, the storage device may also include other hardware required for other business operations.

[0080] The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 10 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0081] Memory is used to store programs. Specifically, programs may include program code, which includes computer operation instructions. Memory may include main memory and non-volatile memory, and provides instructions and data to the processor.

[0082] The processor reads the corresponding computer program from non-volatile memory into main memory and then executes it, forming a command scheduler at the logical level. This command scheduler operates in the memory controller and schedules read, write, and erase operations on the non-volatile storage medium. The processor executes the program stored in memory and specifically performs the following operations: Multiple command queues are established; the multiple command queues include a first command queue and a second command queue; wherein, the scheduling priority of the first command queue is higher than that of the second command queue, and the commands in the first command queue are configured to be completed before a preset deadline; When the first command queue receives a command to be scheduled, a countdown to the preset deadline for the command to be scheduled is started. If the countdown is not greater than a preset threshold, the scheduled command is not completed, and the target command being executed in the second command queue is in a preemptible state, then the target command is suspended, the scheduled command is executed, and the execution of the target command is resumed after the scheduled command is completed; wherein, the preemptible state indicates that the target command can be paused while maintaining the current execution progress.

[0083] The above is as described in the present invention. Figure 1The command scheduling method disclosed in the embodiments described above can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in one or more embodiments of the present invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in one or more embodiments of the present invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0084] This storage device can also perform... Figure 1 The command scheduling method described herein will not be elaborated further here.

[0085] This invention also provides a storage controller configured to implement Figure 1 The method of the illustrated embodiment. Specifically, the storage controller includes at least an arbitrator, a storage medium controller, and a hardware state machine. The arbitrator is used to schedule commands according to priority among the command queues. The storage medium controller is used to issue read commands, write commands, or erase commands to the non-volatile storage medium based on the scheduling result of the arbitrator. The hardware state machine is used to query the current stage register reported by the storage medium controller to determine the preemptible state of the currently executing command. The specific operation of the storage controller can be referred to the above description. Figure 1 The command scheduling method of the illustrated embodiment will not be described in detail here.

[0086] This invention also provides a computer-readable storage medium that stores one or more programs, the programs including instructions that, when executed by a portable electronic device including multiple applications, enable the portable electronic device to perform... Figure 1 The method of the illustrated embodiment will not be described in detail here.

[0087] This invention also provides a computer program product stored in a storage medium and executed by at least one processor to implement... Figure 1 The method of the illustrated embodiment will not be described in detail here.

[0088] Of course, in addition to the software implementation, the storage device of the present invention does not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0089] In summary, the above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of the present invention should be included within the scope of protection of one or more embodiments of the present invention.

[0090] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a storage device. Specifically, storage devices include, but are not limited to, cSSD (Client Solid State Drive), eSSD (Enterprise Solid State Drive), UFS (Universal Flash Storage), solid-state drives, embedded storage devices, memory cards, or any combination of these devices.

[0091] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined in this embodiment of the invention, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0092] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] The various embodiments in this invention are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

Claims

1. A command scheduling method, characterized in that, include: Multiple command queues are established; the multiple command queues include a first command queue, a second command queue, and a third command queue; wherein, the scheduling priority of the first command queue is higher than that of the second command queue, the scheduling priority of the third command queue is higher than that of the second command queue but lower than that of the first command queue, and the commands in the first command queue are configured to be completed before a preset deadline; When the first command queue receives a command to be scheduled, a countdown to the preset deadline for the command to be scheduled is started. If the countdown is not greater than a preset threshold, the scheduled command is not completed, and the target command being executed in the second command queue is in a preemptible state, then the target command is suspended, the scheduled command is executed, and the execution of the target command is resumed after the scheduled command is completed; wherein, the preemptible state indicates that the target command can be paused while maintaining its current execution progress; when the second command queue receives a command to be processed, the application identifier of the command to be processed is obtained; according to a predetermined mapping relationship, the target scheduling priority corresponding to the application identifier is determined; if the target scheduling priority is higher than the scheduling priority of the second command queue, the command to be processed is added to the third command queue; wherein, after being added to the third command queue, the scheduling time occupied by the command to be processed is still deducted from the preset scheduling time quota corresponding to the second command queue; the predetermined mapping relationship is the mapping relationship between the application identifier and the scheduling priority.

2. The method according to claim 1, characterized in that, Before suspending the target command, the method further includes: Identify the command type of the target command; wherein, the command type includes read commands, write commands, and erase commands; Based on the execution progress and command type of the target command, determine whether the target command is in a preemptible state.

3. The method according to claim 2, characterized in that, Determining whether the target command is in a preemptible state based on its execution progress and command type includes: When the target command is a read command, if the target command does not return the read data, it is determined that the target command is in a preemptible state; When the target command is a write command, if the target command does not perform a write operation, or if the target command completes the write operation of the current page but does not start the write operation of the next page, the target command is determined to be in a preemptible state. When the target command is an erase command, if the erase operation is not performed on the target command, the target command is determined to be in a preemptible state.

4. The method according to claim 1, characterized in that, The plurality of command queues also includes a third command queue, the scheduling priority of which is higher than that of the second command queue and lower than that of the first command queue; After establishing multiple command queues, the method further includes: The idle resources are divided into a first resource and a second resource, and at least one command execution channel is configured for use by the first command queue and the third command queue; wherein the idle resources include at least one of the following: data storage block resources, low-latency cache resources, and address mapping cache resources; the first resource is configured to provide resources for commands in the first command queue and the third command queue; the second resource is configured to provide resources for commands in the first command queue, the second command queue, and the third command queue. When the available capacity of the first resource is lower than a preset capacity threshold, a resource reclamation operation is triggered to replenish the available capacity of the first resource.

5. The method according to claim 1, characterized in that, The command to be scheduled is a write command, and executing the command to be scheduled includes: The data to be written in the scheduled command is written to a low-latency storage area; wherein the completion time of a single page write operation in the low-latency storage area is less than a preset time threshold. When executing the scheduled command, the hot and cold data classification process is skipped. After the scheduled command is executed, the data written by the scheduled command is marked. If the current load is lower than a preset load threshold, the marked data is migrated to a designated storage area, and the migration does not block the execution of commands in the first command queue. The completion time of a single page write operation in the designated storage area is not less than the preset time threshold. The hot and cold data classification process is a process of allocating data to different storage areas according to the data access frequency.

6. A command scheduling device, characterized in that, include: A creation module is used to establish multiple command queues; the multiple command queues include a first command queue, a second command queue, and a third command queue; wherein, the scheduling priority of the first command queue is higher than that of the second command queue, the scheduling priority of the third command queue is higher than that of the second command queue but lower than that of the first command queue, and the commands in the first command queue are configured to be completed before a preset deadline; The timing module is used to start a countdown for a preset deadline for the scheduled command when the first command queue receives a scheduled command. The scheduling module is configured to: suspend the target command and execute the scheduled command if the countdown is not greater than a preset threshold, the scheduled command is not completed, and the target command being executed in the second command queue is in a preemptible state; and resume the execution of the target command after the scheduled command is completed. The preemptible state indicates that the target command can be paused while maintaining its current execution progress. When the second command queue receives a pending command, the module obtains the application identifier of the pending command; determines the target scheduling priority corresponding to the application identifier based on a pre-determined mapping relationship; and, if the target scheduling priority is higher than the scheduling priority of the second command queue, adds the pending command to the third command queue. After adding the command to the third command queue, the scheduling time occupied by the pending command is still deducted from the preset scheduling time limit corresponding to the second command queue. The pre-determined mapping relationship is a mapping relationship between the application identifier and the scheduling priority.

7. A storage controller, characterized in that, The method includes at least an arbitrator, a storage medium controller, and a hardware state machine; wherein the arbitrator is used to schedule commands among command queues according to priority; the storage medium controller is used to issue read commands, write commands, or erase commands to the non-volatile storage medium based on the scheduling result of the arbitrator; the hardware state machine is used to query the current stage register reported by the storage medium controller to determine the preemptible state of the currently executing command; wherein the preemptible state indicates that the command can be suspended while maintaining the current execution progress; the arbitrator, the storage medium controller, and the hardware state machine are configured to collaboratively implement the steps of the method as described in any one of claims 1 to 5.

8. A storage device, characterized in that, Includes the storage controller as described in claim 7, and a non-volatile storage medium.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store computer-executable instructions that, when executed by a processor, implement the steps of the method described in any one of claims 1 to 5.

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